From bfcc9945b2eae6fd4364226ad93597925f3d79c0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 10:28:19 +0000 Subject: [PATCH] add full core variant including 4k sram of ls180 --- experiments9/build_full_4ksram.sh | 12 +- .../full_core_4_4ksram_libresoc.v | 205108 +++++++++++++++ .../full_core_4_4ksram_litex_ls180.v | 5899 + 3 files changed, 211018 insertions(+), 1 deletion(-) create mode 100644 experiments9/non_generated/full_core_4_4ksram_libresoc.v create mode 100644 experiments9/non_generated/full_core_4_4ksram_litex_ls180.v diff --git a/experiments9/build_full_4ksram.sh b/experiments9/build_full_4ksram.sh index d2c7a81..b82447d 100755 --- a/experiments9/build_full_4ksram.sh +++ b/experiments9/build_full_4ksram.sh @@ -20,7 +20,17 @@ make clean rm *.vst *.ap # copies over a "full" core -cp non_generated/full_core_4_4ksram_ls180.il ls180.il +#cp non_generated/full_core_4_4ksram_ls180.il ls180.il +cp non_generated/ls180.v ls180.v +cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v +cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v +touch mem.init +touch mem_1.init +touch mem_2.init +touch mem_3.init +touch mem_4.init +touch mem_5.init + # make the vst from ilang make vst diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v new file mode 100644 index 0000000..253cbf5 --- /dev/null +++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v @@ -0,0 +1,205108 @@ +/* Generated by Yosys 0.9+4052 (git sha1 a58571d0, clang 9.0.1-12 -fPIC -Os) */ + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" *) +(* generator = "nMigen" *) +module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_sel, ALU_dec19_in2_sel, ALU_dec19_cr_in, ALU_dec19_cr_out, ALU_dec19_ldst_len, ALU_dec19_rc_sel, ALU_dec19_cry_in, ALU_dec19_inv_a, ALU_dec19_inv_out, ALU_dec19_cry_out, ALU_dec19_is_32b, ALU_dec19_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec19_cr_in; + reg [2:0] ALU_dec19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec19_cr_out; + reg [2:0] ALU_dec19_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec19_cry_in; + reg [1:0] ALU_dec19_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec19_cry_out; + reg ALU_dec19_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] ALU_dec19_function_unit; + reg [13:0] ALU_dec19_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec19_in1_sel; + reg [2:0] ALU_dec19_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec19_in2_sel; + reg [3:0] ALU_dec19_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] ALU_dec19_internal_op; + reg [6:0] ALU_dec19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec19_inv_a; + reg ALU_dec19_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec19_inv_out; + reg ALU_dec19_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec19_is_32b; + reg ALU_dec19_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec19_ldst_len; + reg [3:0] ALU_dec19_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec19_rc_sel; + reg [1:0] ALU_dec19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec19_sgn; + reg ALU_dec19_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + always @* begin + if (\initial ) begin end + ALU_dec19_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_internal_op = 7'h24; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + ALU_dec19_cry_in = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" *) +(* generator = "nMigen" *) +module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_sel, ALU_dec31_in2_sel, ALU_dec31_cr_in, ALU_dec31_cr_out, ALU_dec31_ldst_len, ALU_dec31_rc_sel, ALU_dec31_cry_in, ALU_dec31_inv_a, ALU_dec31_inv_out, ALU_dec31_cry_out, ALU_dec31_is_32b, ALU_dec31_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_cr_in; + reg [2:0] ALU_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_cr_out; + reg [2:0] ALU_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_cry_in; + reg [1:0] ALU_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_cry_out; + reg ALU_dec31_cry_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] ALU_dec31_dec_sub0_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] ALU_dec31_dec_sub10_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] ALU_dec31_dec_sub22_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] ALU_dec31_dec_sub26_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] ALU_dec31_dec_sub8_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] ALU_dec31_function_unit; + reg [13:0] ALU_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_in1_sel; + reg [2:0] ALU_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_in2_sel; + reg [3:0] ALU_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] ALU_dec31_internal_op; + reg [6:0] ALU_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_inv_a; + reg ALU_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_inv_out; + reg ALU_dec31_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_is_32b; + reg ALU_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_ldst_len; + reg [3:0] ALU_dec31_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_rc_sel; + reg [1:0] ALU_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_sgn; + reg ALU_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + ALU_dec31_dec_sub0 ALU_dec31_dec_sub0 ( + .ALU_dec31_dec_sub0_cr_in(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in), + .ALU_dec31_dec_sub0_cr_out(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out), + .ALU_dec31_dec_sub0_cry_in(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in), + .ALU_dec31_dec_sub0_cry_out(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out), + .ALU_dec31_dec_sub0_function_unit(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit), + .ALU_dec31_dec_sub0_in1_sel(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel), + .ALU_dec31_dec_sub0_in2_sel(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel), + .ALU_dec31_dec_sub0_internal_op(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op), + .ALU_dec31_dec_sub0_inv_a(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a), + .ALU_dec31_dec_sub0_inv_out(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out), + .ALU_dec31_dec_sub0_is_32b(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b), + .ALU_dec31_dec_sub0_ldst_len(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len), + .ALU_dec31_dec_sub0_rc_sel(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel), + .ALU_dec31_dec_sub0_sgn(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn), + .opcode_in(ALU_dec31_dec_sub0_opcode_in) + ); + ALU_dec31_dec_sub10 ALU_dec31_dec_sub10 ( + .ALU_dec31_dec_sub10_cr_in(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in), + .ALU_dec31_dec_sub10_cr_out(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out), + .ALU_dec31_dec_sub10_cry_in(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in), + .ALU_dec31_dec_sub10_cry_out(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out), + .ALU_dec31_dec_sub10_function_unit(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit), + .ALU_dec31_dec_sub10_in1_sel(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel), + .ALU_dec31_dec_sub10_in2_sel(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel), + .ALU_dec31_dec_sub10_internal_op(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op), + .ALU_dec31_dec_sub10_inv_a(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a), + .ALU_dec31_dec_sub10_inv_out(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out), + .ALU_dec31_dec_sub10_is_32b(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b), + .ALU_dec31_dec_sub10_ldst_len(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len), + .ALU_dec31_dec_sub10_rc_sel(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel), + .ALU_dec31_dec_sub10_sgn(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn), + .opcode_in(ALU_dec31_dec_sub10_opcode_in) + ); + ALU_dec31_dec_sub22 ALU_dec31_dec_sub22 ( + .ALU_dec31_dec_sub22_cr_in(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in), + .ALU_dec31_dec_sub22_cr_out(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out), + .ALU_dec31_dec_sub22_cry_in(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in), + .ALU_dec31_dec_sub22_cry_out(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out), + .ALU_dec31_dec_sub22_function_unit(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit), + .ALU_dec31_dec_sub22_in1_sel(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel), + .ALU_dec31_dec_sub22_in2_sel(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel), + .ALU_dec31_dec_sub22_internal_op(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op), + .ALU_dec31_dec_sub22_inv_a(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a), + .ALU_dec31_dec_sub22_inv_out(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out), + .ALU_dec31_dec_sub22_is_32b(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b), + .ALU_dec31_dec_sub22_ldst_len(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len), + .ALU_dec31_dec_sub22_rc_sel(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel), + .ALU_dec31_dec_sub22_sgn(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn), + .opcode_in(ALU_dec31_dec_sub22_opcode_in) + ); + ALU_dec31_dec_sub26 ALU_dec31_dec_sub26 ( + .ALU_dec31_dec_sub26_cr_in(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in), + .ALU_dec31_dec_sub26_cr_out(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out), + .ALU_dec31_dec_sub26_cry_in(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in), + .ALU_dec31_dec_sub26_cry_out(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out), + .ALU_dec31_dec_sub26_function_unit(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit), + .ALU_dec31_dec_sub26_in1_sel(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel), + .ALU_dec31_dec_sub26_in2_sel(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel), + .ALU_dec31_dec_sub26_internal_op(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op), + .ALU_dec31_dec_sub26_inv_a(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a), + .ALU_dec31_dec_sub26_inv_out(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out), + .ALU_dec31_dec_sub26_is_32b(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b), + .ALU_dec31_dec_sub26_ldst_len(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len), + .ALU_dec31_dec_sub26_rc_sel(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel), + .ALU_dec31_dec_sub26_sgn(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn), + .opcode_in(ALU_dec31_dec_sub26_opcode_in) + ); + ALU_dec31_dec_sub8 ALU_dec31_dec_sub8 ( + .ALU_dec31_dec_sub8_cr_in(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in), + .ALU_dec31_dec_sub8_cr_out(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out), + .ALU_dec31_dec_sub8_cry_in(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in), + .ALU_dec31_dec_sub8_cry_out(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out), + .ALU_dec31_dec_sub8_function_unit(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit), + .ALU_dec31_dec_sub8_in1_sel(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel), + .ALU_dec31_dec_sub8_in2_sel(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel), + .ALU_dec31_dec_sub8_internal_op(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op), + .ALU_dec31_dec_sub8_inv_a(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a), + .ALU_dec31_dec_sub8_inv_out(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out), + .ALU_dec31_dec_sub8_is_32b(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b), + .ALU_dec31_dec_sub8_ldst_len(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len), + .ALU_dec31_dec_sub8_rc_sel(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel), + .ALU_dec31_dec_sub8_sgn(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn), + .opcode_in(ALU_dec31_dec_sub8_opcode_in) + ); + always @* begin + if (\initial ) begin end + ALU_dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_in2_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_in2_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_in2_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_in2_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_in2_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_cr_in = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_cr_in = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_cr_in = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_cr_in = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_cr_in = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_cr_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_cr_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_cr_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_cr_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_cr_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_ldst_len = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_ldst_len = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_ldst_len = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_ldst_len = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_ldst_len = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_rc_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_rc_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_rc_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_rc_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_rc_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_cry_in = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_cry_in = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_cry_in = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_cry_in = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_cry_in = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_inv_a = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_inv_a = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_inv_a = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_inv_a = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_inv_a = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_inv_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_inv_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_inv_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_inv_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_inv_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_cry_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_cry_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_cry_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_cry_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_cry_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_is_32b = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_is_32b = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_is_32b = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_is_32b = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_is_32b = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_sgn = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_sgn = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_sgn = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_sgn = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_sgn = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_function_unit = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_function_unit = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_function_unit = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_function_unit = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_function_unit = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_internal_op = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_internal_op = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_internal_op = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_internal_op = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_internal_op = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + ALU_dec31_in1_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_in1_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + ALU_dec31_in1_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_in1_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_in1_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel; + endcase + end + assign ALU_dec31_dec_sub8_opcode_in = opcode_in; + assign ALU_dec31_dec_sub22_opcode_in = opcode_in; + assign ALU_dec31_dec_sub26_opcode_in = opcode_in; + assign ALU_dec31_dec_sub0_opcode_in = opcode_in; + assign ALU_dec31_dec_sub10_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" *) +(* generator = "nMigen" *) +module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_internal_op, ALU_dec31_dec_sub0_in1_sel, ALU_dec31_dec_sub0_in2_sel, ALU_dec31_dec_sub0_cr_in, ALU_dec31_dec_sub0_cr_out, ALU_dec31_dec_sub0_ldst_len, ALU_dec31_dec_sub0_rc_sel, ALU_dec31_dec_sub0_cry_in, ALU_dec31_dec_sub0_inv_a, ALU_dec31_dec_sub0_inv_out, ALU_dec31_dec_sub0_cry_out, ALU_dec31_dec_sub0_is_32b, ALU_dec31_dec_sub0_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub0_cr_in; + reg [2:0] ALU_dec31_dec_sub0_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub0_cr_out; + reg [2:0] ALU_dec31_dec_sub0_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub0_cry_in; + reg [1:0] ALU_dec31_dec_sub0_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub0_cry_out; + reg ALU_dec31_dec_sub0_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] ALU_dec31_dec_sub0_function_unit; + reg [13:0] ALU_dec31_dec_sub0_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub0_in1_sel; + reg [2:0] ALU_dec31_dec_sub0_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub0_in2_sel; + reg [3:0] ALU_dec31_dec_sub0_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] ALU_dec31_dec_sub0_internal_op; + reg [6:0] ALU_dec31_dec_sub0_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub0_inv_a; + reg ALU_dec31_dec_sub0_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub0_inv_out; + reg ALU_dec31_dec_sub0_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub0_is_32b; + reg ALU_dec31_dec_sub0_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub0_ldst_len; + reg [3:0] ALU_dec31_dec_sub0_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub0_rc_sel; + reg [1:0] ALU_dec31_dec_sub0_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub0_sgn; + reg ALU_dec31_dec_sub0_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_inv_a = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_internal_op = 7'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_internal_op = 7'h0c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_internal_op = 7'h0a; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_cr_out = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub0_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub0_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub0_cry_in = 2'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" *) +(* generator = "nMigen" *) +module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub10_internal_op, ALU_dec31_dec_sub10_in1_sel, ALU_dec31_dec_sub10_in2_sel, ALU_dec31_dec_sub10_cr_in, ALU_dec31_dec_sub10_cr_out, ALU_dec31_dec_sub10_ldst_len, ALU_dec31_dec_sub10_rc_sel, ALU_dec31_dec_sub10_cry_in, ALU_dec31_dec_sub10_inv_a, ALU_dec31_dec_sub10_inv_out, ALU_dec31_dec_sub10_cry_out, ALU_dec31_dec_sub10_is_32b, ALU_dec31_dec_sub10_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub10_cr_in; + reg [2:0] ALU_dec31_dec_sub10_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub10_cr_out; + reg [2:0] ALU_dec31_dec_sub10_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub10_cry_in; + reg [1:0] ALU_dec31_dec_sub10_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub10_cry_out; + reg ALU_dec31_dec_sub10_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] ALU_dec31_dec_sub10_function_unit; + reg [13:0] ALU_dec31_dec_sub10_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub10_in1_sel; + reg [2:0] ALU_dec31_dec_sub10_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub10_in2_sel; + reg [3:0] ALU_dec31_dec_sub10_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] ALU_dec31_dec_sub10_internal_op; + reg [6:0] ALU_dec31_dec_sub10_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub10_inv_a; + reg ALU_dec31_dec_sub10_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub10_inv_out; + reg ALU_dec31_dec_sub10_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub10_is_32b; + reg ALU_dec31_dec_sub10_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub10_ldst_len; + reg [3:0] ALU_dec31_dec_sub10_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub10_rc_sel; + reg [1:0] ALU_dec31_dec_sub10_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub10_sgn; + reg ALU_dec31_dec_sub10_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_cry_out = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_internal_op = 7'h02; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_in2_sel = 4'h9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_in2_sel = 4'h9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + ALU_dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub10_cry_in = 2'h2; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" *) +(* generator = "nMigen" *) +module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub22_internal_op, ALU_dec31_dec_sub22_in1_sel, ALU_dec31_dec_sub22_in2_sel, ALU_dec31_dec_sub22_cr_in, ALU_dec31_dec_sub22_cr_out, ALU_dec31_dec_sub22_ldst_len, ALU_dec31_dec_sub22_rc_sel, ALU_dec31_dec_sub22_cry_in, ALU_dec31_dec_sub22_inv_a, ALU_dec31_dec_sub22_inv_out, ALU_dec31_dec_sub22_cry_out, ALU_dec31_dec_sub22_is_32b, ALU_dec31_dec_sub22_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub22_cr_in; + reg [2:0] ALU_dec31_dec_sub22_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub22_cr_out; + reg [2:0] ALU_dec31_dec_sub22_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub22_cry_in; + reg [1:0] ALU_dec31_dec_sub22_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub22_cry_out; + reg ALU_dec31_dec_sub22_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] ALU_dec31_dec_sub22_function_unit; + reg [13:0] ALU_dec31_dec_sub22_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub22_in1_sel; + reg [2:0] ALU_dec31_dec_sub22_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub22_in2_sel; + reg [3:0] ALU_dec31_dec_sub22_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] ALU_dec31_dec_sub22_internal_op; + reg [6:0] ALU_dec31_dec_sub22_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub22_inv_a; + reg ALU_dec31_dec_sub22_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub22_inv_out; + reg ALU_dec31_dec_sub22_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub22_is_32b; + reg ALU_dec31_dec_sub22_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub22_ldst_len; + reg [3:0] ALU_dec31_dec_sub22_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub22_rc_sel; + reg [1:0] ALU_dec31_dec_sub22_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub22_sgn; + reg ALU_dec31_dec_sub22_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_internal_op = 7'h21; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_internal_op = 7'h01; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + ALU_dec31_dec_sub22_cry_in = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" *) +(* generator = "nMigen" *) +module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub26_internal_op, ALU_dec31_dec_sub26_in1_sel, ALU_dec31_dec_sub26_in2_sel, ALU_dec31_dec_sub26_cr_in, ALU_dec31_dec_sub26_cr_out, ALU_dec31_dec_sub26_ldst_len, ALU_dec31_dec_sub26_rc_sel, ALU_dec31_dec_sub26_cry_in, ALU_dec31_dec_sub26_inv_a, ALU_dec31_dec_sub26_inv_out, ALU_dec31_dec_sub26_cry_out, ALU_dec31_dec_sub26_is_32b, ALU_dec31_dec_sub26_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub26_cr_in; + reg [2:0] ALU_dec31_dec_sub26_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub26_cr_out; + reg [2:0] ALU_dec31_dec_sub26_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub26_cry_in; + reg [1:0] ALU_dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub26_cry_out; + reg ALU_dec31_dec_sub26_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] ALU_dec31_dec_sub26_function_unit; + reg [13:0] ALU_dec31_dec_sub26_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub26_in1_sel; + reg [2:0] ALU_dec31_dec_sub26_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub26_in2_sel; + reg [3:0] ALU_dec31_dec_sub26_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] ALU_dec31_dec_sub26_internal_op; + reg [6:0] ALU_dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub26_inv_a; + reg ALU_dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub26_inv_out; + reg ALU_dec31_dec_sub26_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub26_is_32b; + reg ALU_dec31_dec_sub26_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub26_ldst_len; + reg [3:0] ALU_dec31_dec_sub26_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub26_rc_sel; + reg [1:0] ALU_dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub26_sgn; + reg ALU_dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_internal_op = 7'h1f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_internal_op = 7'h1f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_internal_op = 7'h1f; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_in1_sel = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + ALU_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + ALU_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + ALU_dec31_dec_sub26_cry_in = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" *) +(* generator = "nMigen" *) +module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_internal_op, ALU_dec31_dec_sub8_in1_sel, ALU_dec31_dec_sub8_in2_sel, ALU_dec31_dec_sub8_cr_in, ALU_dec31_dec_sub8_cr_out, ALU_dec31_dec_sub8_ldst_len, ALU_dec31_dec_sub8_rc_sel, ALU_dec31_dec_sub8_cry_in, ALU_dec31_dec_sub8_inv_a, ALU_dec31_dec_sub8_inv_out, ALU_dec31_dec_sub8_cry_out, ALU_dec31_dec_sub8_is_32b, ALU_dec31_dec_sub8_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub8_cr_in; + reg [2:0] ALU_dec31_dec_sub8_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub8_cr_out; + reg [2:0] ALU_dec31_dec_sub8_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub8_cry_in; + reg [1:0] ALU_dec31_dec_sub8_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub8_cry_out; + reg ALU_dec31_dec_sub8_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] ALU_dec31_dec_sub8_function_unit; + reg [13:0] ALU_dec31_dec_sub8_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_dec31_dec_sub8_in1_sel; + reg [2:0] ALU_dec31_dec_sub8_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub8_in2_sel; + reg [3:0] ALU_dec31_dec_sub8_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] ALU_dec31_dec_sub8_internal_op; + reg [6:0] ALU_dec31_dec_sub8_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub8_inv_a; + reg ALU_dec31_dec_sub8_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub8_inv_out; + reg ALU_dec31_dec_sub8_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub8_is_32b; + reg ALU_dec31_dec_sub8_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_dec31_dec_sub8_ldst_len; + reg [3:0] ALU_dec31_dec_sub8_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub8_rc_sel; + reg [1:0] ALU_dec31_dec_sub8_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_dec31_dec_sub8_sgn; + reg ALU_dec31_dec_sub8_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_inv_a = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_cry_out = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_internal_op = 7'h02; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_in2_sel = 4'h9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_in2_sel = 4'h9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + ALU_dec31_dec_sub8_cry_in = 2'h2; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" *) +(* generator = "nMigen" *) +module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH_dec19_in2_sel, BRANCH_dec19_cr_in, BRANCH_dec19_cr_out, BRANCH_dec19_rc_sel, BRANCH_dec19_is_32b, BRANCH_dec19_lk, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] BRANCH_dec19_cr_in; + reg [2:0] BRANCH_dec19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] BRANCH_dec19_cr_out; + reg [2:0] BRANCH_dec19_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] BRANCH_dec19_function_unit; + reg [13:0] BRANCH_dec19_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] BRANCH_dec19_in2_sel; + reg [3:0] BRANCH_dec19_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] BRANCH_dec19_internal_op; + reg [6:0] BRANCH_dec19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output BRANCH_dec19_is_32b; + reg BRANCH_dec19_is_32b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output BRANCH_dec19_lk; + reg BRANCH_dec19_lk; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] BRANCH_dec19_rc_sel; + reg [1:0] BRANCH_dec19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + always @* begin + if (\initial ) begin end + BRANCH_dec19_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + BRANCH_dec19_function_unit = 14'h0020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + BRANCH_dec19_function_unit = 14'h0020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + BRANCH_dec19_function_unit = 14'h0020; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_dec19_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + BRANCH_dec19_internal_op = 7'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + BRANCH_dec19_internal_op = 7'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + BRANCH_dec19_internal_op = 7'h08; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_dec19_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + BRANCH_dec19_in2_sel = 4'hc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + BRANCH_dec19_in2_sel = 4'hc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + BRANCH_dec19_in2_sel = 4'hc; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_dec19_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + BRANCH_dec19_cr_in = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + BRANCH_dec19_cr_in = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + BRANCH_dec19_cr_in = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_dec19_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + BRANCH_dec19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + BRANCH_dec19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + BRANCH_dec19_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_dec19_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + BRANCH_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + BRANCH_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + BRANCH_dec19_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_dec19_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + BRANCH_dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + BRANCH_dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + BRANCH_dec19_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_dec19_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + BRANCH_dec19_lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + BRANCH_dec19_lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + BRANCH_dec19_lk = 1'h1; + endcase + end + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec19" *) +(* generator = "nMigen" *) +module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR_dec19_cr_out, CR_dec19_rc_sel, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec19_cr_in; + reg [2:0] CR_dec19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec19_cr_out; + reg [2:0] CR_dec19_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] CR_dec19_function_unit; + reg [13:0] CR_dec19_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] CR_dec19_internal_op; + reg [6:0] CR_dec19_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] CR_dec19_rc_sel; + reg [1:0] CR_dec19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + always @* begin + if (\initial ) begin end + CR_dec19_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + CR_dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + CR_dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + CR_dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + CR_dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + CR_dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + CR_dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + CR_dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + CR_dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + CR_dec19_function_unit = 14'h0040; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec19_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + CR_dec19_internal_op = 7'h2a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + CR_dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + CR_dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + CR_dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + CR_dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + CR_dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + CR_dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + CR_dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + CR_dec19_internal_op = 7'h45; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec19_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + CR_dec19_cr_in = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + CR_dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + CR_dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + CR_dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + CR_dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + CR_dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + CR_dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + CR_dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + CR_dec19_cr_in = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec19_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + CR_dec19_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + CR_dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + CR_dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + CR_dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + CR_dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + CR_dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + CR_dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + CR_dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + CR_dec19_cr_out = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec19_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + CR_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + CR_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + CR_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + CR_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + CR_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + CR_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + CR_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + CR_dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + CR_dec19_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31" *) +(* generator = "nMigen" *) +module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR_dec31_cr_out, CR_dec31_rc_sel, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_cr_in; + reg [2:0] CR_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_cr_out; + reg [2:0] CR_dec31_cr_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] CR_dec31_dec_sub0_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] CR_dec31_dec_sub15_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] CR_dec31_dec_sub16_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] CR_dec31_dec_sub19_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] CR_dec31_function_unit; + reg [13:0] CR_dec31_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] CR_dec31_internal_op; + reg [6:0] CR_dec31_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_rc_sel; + reg [1:0] CR_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + CR_dec31_dec_sub0 CR_dec31_dec_sub0 ( + .CR_dec31_dec_sub0_cr_in(CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in), + .CR_dec31_dec_sub0_cr_out(CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out), + .CR_dec31_dec_sub0_function_unit(CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit), + .CR_dec31_dec_sub0_internal_op(CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op), + .CR_dec31_dec_sub0_rc_sel(CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel), + .opcode_in(CR_dec31_dec_sub0_opcode_in) + ); + CR_dec31_dec_sub15 CR_dec31_dec_sub15 ( + .CR_dec31_dec_sub15_cr_in(CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in), + .CR_dec31_dec_sub15_cr_out(CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out), + .CR_dec31_dec_sub15_function_unit(CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit), + .CR_dec31_dec_sub15_internal_op(CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op), + .CR_dec31_dec_sub15_rc_sel(CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel), + .opcode_in(CR_dec31_dec_sub15_opcode_in) + ); + CR_dec31_dec_sub16 CR_dec31_dec_sub16 ( + .CR_dec31_dec_sub16_cr_in(CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in), + .CR_dec31_dec_sub16_cr_out(CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out), + .CR_dec31_dec_sub16_function_unit(CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit), + .CR_dec31_dec_sub16_internal_op(CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op), + .CR_dec31_dec_sub16_rc_sel(CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel), + .opcode_in(CR_dec31_dec_sub16_opcode_in) + ); + CR_dec31_dec_sub19 CR_dec31_dec_sub19 ( + .CR_dec31_dec_sub19_cr_in(CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in), + .CR_dec31_dec_sub19_cr_out(CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out), + .CR_dec31_dec_sub19_function_unit(CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit), + .CR_dec31_dec_sub19_internal_op(CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op), + .CR_dec31_dec_sub19_rc_sel(CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel), + .opcode_in(CR_dec31_dec_sub19_opcode_in) + ); + always @* begin + if (\initial ) begin end + CR_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_rc_sel = CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_rc_sel = CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_rc_sel = CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_rc_sel = CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_function_unit = CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_function_unit = CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_function_unit = CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_function_unit = CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_internal_op = CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_internal_op = CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_internal_op = CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_internal_op = CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_cr_in = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_cr_in = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_cr_in = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_cr_in = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_cr_out = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_cr_out = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_cr_out = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_cr_out = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out; + endcase + end + assign CR_dec31_dec_sub16_opcode_in = opcode_in; + assign CR_dec31_dec_sub15_opcode_in = opcode_in; + assign CR_dec31_dec_sub19_opcode_in = opcode_in; + assign CR_dec31_dec_sub0_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" *) +(* generator = "nMigen" *) +module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_internal_op, CR_dec31_dec_sub0_cr_in, CR_dec31_dec_sub0_cr_out, CR_dec31_dec_sub0_rc_sel, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_dec_sub0_cr_in; + reg [2:0] CR_dec31_dec_sub0_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_dec_sub0_cr_out; + reg [2:0] CR_dec31_dec_sub0_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] CR_dec31_dec_sub0_function_unit; + reg [13:0] CR_dec31_dec_sub0_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] CR_dec31_dec_sub0_internal_op; + reg [6:0] CR_dec31_dec_sub0_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_dec_sub0_rc_sel; + reg [1:0] CR_dec31_dec_sub0_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub0_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub0_function_unit = 14'h0040; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub0_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub0_internal_op = 7'h3b; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub0_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub0_cr_in = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub0_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub0_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub0_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub0_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" *) +(* generator = "nMigen" *) +module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_internal_op, CR_dec31_dec_sub15_cr_in, CR_dec31_dec_sub15_cr_out, CR_dec31_dec_sub15_rc_sel, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_dec_sub15_cr_in; + reg [2:0] CR_dec31_dec_sub15_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_dec_sub15_cr_out; + reg [2:0] CR_dec31_dec_sub15_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] CR_dec31_dec_sub15_function_unit; + reg [13:0] CR_dec31_dec_sub15_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] CR_dec31_dec_sub15_internal_op; + reg [6:0] CR_dec31_dec_sub15_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_dec_sub15_rc_sel; + reg [1:0] CR_dec31_dec_sub15_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + CR_dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + CR_dec31_dec_sub15_function_unit = 14'h0040; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + CR_dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + CR_dec31_dec_sub15_internal_op = 7'h23; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + CR_dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + CR_dec31_dec_sub15_cr_in = 3'h5; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + CR_dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + CR_dec31_dec_sub15_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + CR_dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + CR_dec31_dec_sub15_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" *) +(* generator = "nMigen" *) +module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_internal_op, CR_dec31_dec_sub16_cr_in, CR_dec31_dec_sub16_cr_out, CR_dec31_dec_sub16_rc_sel, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_dec_sub16_cr_in; + reg [2:0] CR_dec31_dec_sub16_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_dec_sub16_cr_out; + reg [2:0] CR_dec31_dec_sub16_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] CR_dec31_dec_sub16_function_unit; + reg [13:0] CR_dec31_dec_sub16_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] CR_dec31_dec_sub16_internal_op; + reg [6:0] CR_dec31_dec_sub16_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_dec_sub16_rc_sel; + reg [1:0] CR_dec31_dec_sub16_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub16_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub16_function_unit = 14'h0040; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub16_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub16_internal_op = 7'h30; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub16_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub16_cr_in = 3'h6; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub16_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub16_cr_out = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub16_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + CR_dec31_dec_sub16_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" *) +(* generator = "nMigen" *) +module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_internal_op, CR_dec31_dec_sub19_cr_in, CR_dec31_dec_sub19_cr_out, CR_dec31_dec_sub19_rc_sel, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_dec_sub19_cr_in; + reg [2:0] CR_dec31_dec_sub19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_dec31_dec_sub19_cr_out; + reg [2:0] CR_dec31_dec_sub19_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] CR_dec31_dec_sub19_function_unit; + reg [13:0] CR_dec31_dec_sub19_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] CR_dec31_dec_sub19_internal_op; + reg [6:0] CR_dec31_dec_sub19_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_dec_sub19_rc_sel; + reg [1:0] CR_dec31_dec_sub19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub19_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub19_function_unit = 14'h0040; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub19_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub19_internal_op = 7'h2d; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub19_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub19_cr_in = 3'h6; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub19_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub19_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub19_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + CR_dec31_dec_sub19_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" *) +(* generator = "nMigen" *) +module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_sel, DIV_dec31_in2_sel, DIV_dec31_cr_in, DIV_dec31_cr_out, DIV_dec31_ldst_len, DIV_dec31_rc_sel, DIV_dec31_cry_in, DIV_dec31_inv_a, DIV_dec31_inv_out, DIV_dec31_cry_out, DIV_dec31_is_32b, DIV_dec31_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_cr_in; + reg [2:0] DIV_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_cr_out; + reg [2:0] DIV_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_cry_in; + reg [1:0] DIV_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_cry_out; + reg DIV_dec31_cry_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] DIV_dec31_dec_sub11_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] DIV_dec31_dec_sub9_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] DIV_dec31_function_unit; + reg [13:0] DIV_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_in1_sel; + reg [2:0] DIV_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] DIV_dec31_in2_sel; + reg [3:0] DIV_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] DIV_dec31_internal_op; + reg [6:0] DIV_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_inv_a; + reg DIV_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_inv_out; + reg DIV_dec31_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_is_32b; + reg DIV_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] DIV_dec31_ldst_len; + reg [3:0] DIV_dec31_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_rc_sel; + reg [1:0] DIV_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_sgn; + reg DIV_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + DIV_dec31_dec_sub11 DIV_dec31_dec_sub11 ( + .DIV_dec31_dec_sub11_cr_in(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in), + .DIV_dec31_dec_sub11_cr_out(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out), + .DIV_dec31_dec_sub11_cry_in(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in), + .DIV_dec31_dec_sub11_cry_out(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out), + .DIV_dec31_dec_sub11_function_unit(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit), + .DIV_dec31_dec_sub11_in1_sel(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel), + .DIV_dec31_dec_sub11_in2_sel(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel), + .DIV_dec31_dec_sub11_internal_op(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op), + .DIV_dec31_dec_sub11_inv_a(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a), + .DIV_dec31_dec_sub11_inv_out(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out), + .DIV_dec31_dec_sub11_is_32b(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b), + .DIV_dec31_dec_sub11_ldst_len(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len), + .DIV_dec31_dec_sub11_rc_sel(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel), + .DIV_dec31_dec_sub11_sgn(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn), + .opcode_in(DIV_dec31_dec_sub11_opcode_in) + ); + DIV_dec31_dec_sub9 DIV_dec31_dec_sub9 ( + .DIV_dec31_dec_sub9_cr_in(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in), + .DIV_dec31_dec_sub9_cr_out(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out), + .DIV_dec31_dec_sub9_cry_in(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in), + .DIV_dec31_dec_sub9_cry_out(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out), + .DIV_dec31_dec_sub9_function_unit(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit), + .DIV_dec31_dec_sub9_in1_sel(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel), + .DIV_dec31_dec_sub9_in2_sel(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel), + .DIV_dec31_dec_sub9_internal_op(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op), + .DIV_dec31_dec_sub9_inv_a(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a), + .DIV_dec31_dec_sub9_inv_out(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out), + .DIV_dec31_dec_sub9_is_32b(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b), + .DIV_dec31_dec_sub9_ldst_len(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len), + .DIV_dec31_dec_sub9_rc_sel(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel), + .DIV_dec31_dec_sub9_sgn(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn), + .opcode_in(DIV_dec31_dec_sub9_opcode_in) + ); + always @* begin + if (\initial ) begin end + DIV_dec31_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_ldst_len = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_ldst_len = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_rc_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_rc_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_cry_in = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_cry_in = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_inv_a = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_inv_a = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_inv_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_inv_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_cry_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_cry_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_is_32b = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_is_32b = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_sgn = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_sgn = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_function_unit = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_function_unit = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_internal_op = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_internal_op = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_in1_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_in1_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_in2_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_in2_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_cr_in = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_cr_in = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + DIV_dec31_cr_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + DIV_dec31_cr_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out; + endcase + end + assign DIV_dec31_dec_sub11_opcode_in = opcode_in; + assign DIV_dec31_dec_sub9_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" *) +(* generator = "nMigen" *) +module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub11_internal_op, DIV_dec31_dec_sub11_in1_sel, DIV_dec31_dec_sub11_in2_sel, DIV_dec31_dec_sub11_cr_in, DIV_dec31_dec_sub11_cr_out, DIV_dec31_dec_sub11_ldst_len, DIV_dec31_dec_sub11_rc_sel, DIV_dec31_dec_sub11_cry_in, DIV_dec31_dec_sub11_inv_a, DIV_dec31_dec_sub11_inv_out, DIV_dec31_dec_sub11_cry_out, DIV_dec31_dec_sub11_is_32b, DIV_dec31_dec_sub11_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_dec_sub11_cr_in; + reg [2:0] DIV_dec31_dec_sub11_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_dec_sub11_cr_out; + reg [2:0] DIV_dec31_dec_sub11_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_dec_sub11_cry_in; + reg [1:0] DIV_dec31_dec_sub11_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub11_cry_out; + reg DIV_dec31_dec_sub11_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] DIV_dec31_dec_sub11_function_unit; + reg [13:0] DIV_dec31_dec_sub11_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_dec_sub11_in1_sel; + reg [2:0] DIV_dec31_dec_sub11_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] DIV_dec31_dec_sub11_in2_sel; + reg [3:0] DIV_dec31_dec_sub11_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] DIV_dec31_dec_sub11_internal_op; + reg [6:0] DIV_dec31_dec_sub11_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub11_inv_a; + reg DIV_dec31_dec_sub11_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub11_inv_out; + reg DIV_dec31_dec_sub11_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub11_is_32b; + reg DIV_dec31_dec_sub11_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] DIV_dec31_dec_sub11_ldst_len; + reg [3:0] DIV_dec31_dec_sub11_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_dec_sub11_rc_sel; + reg [1:0] DIV_dec31_dec_sub11_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub11_sgn; + reg DIV_dec31_dec_sub11_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_function_unit = 14'h0200; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_is_32b = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_sgn = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_internal_op = 7'h2f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_internal_op = 7'h2f; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub11_cry_in = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" *) +(* generator = "nMigen" *) +module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_internal_op, DIV_dec31_dec_sub9_in1_sel, DIV_dec31_dec_sub9_in2_sel, DIV_dec31_dec_sub9_cr_in, DIV_dec31_dec_sub9_cr_out, DIV_dec31_dec_sub9_ldst_len, DIV_dec31_dec_sub9_rc_sel, DIV_dec31_dec_sub9_cry_in, DIV_dec31_dec_sub9_inv_a, DIV_dec31_dec_sub9_inv_out, DIV_dec31_dec_sub9_cry_out, DIV_dec31_dec_sub9_is_32b, DIV_dec31_dec_sub9_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_dec_sub9_cr_in; + reg [2:0] DIV_dec31_dec_sub9_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_dec_sub9_cr_out; + reg [2:0] DIV_dec31_dec_sub9_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_dec_sub9_cry_in; + reg [1:0] DIV_dec31_dec_sub9_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub9_cry_out; + reg DIV_dec31_dec_sub9_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] DIV_dec31_dec_sub9_function_unit; + reg [13:0] DIV_dec31_dec_sub9_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_dec31_dec_sub9_in1_sel; + reg [2:0] DIV_dec31_dec_sub9_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] DIV_dec31_dec_sub9_in2_sel; + reg [3:0] DIV_dec31_dec_sub9_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] DIV_dec31_dec_sub9_internal_op; + reg [6:0] DIV_dec31_dec_sub9_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub9_inv_a; + reg DIV_dec31_dec_sub9_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub9_inv_out; + reg DIV_dec31_dec_sub9_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub9_is_32b; + reg DIV_dec31_dec_sub9_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] DIV_dec31_dec_sub9_ldst_len; + reg [3:0] DIV_dec31_dec_sub9_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_dec_sub9_rc_sel; + reg [1:0] DIV_dec31_dec_sub9_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_dec31_dec_sub9_sgn; + reg DIV_dec31_dec_sub9_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_function_unit = 14'h0200; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_sgn = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_internal_op = 7'h2f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_internal_op = 7'h2f; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + DIV_dec31_dec_sub9_cry_in = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" *) +(* generator = "nMigen" *) +module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_in1_sel, LDST_dec31_in2_sel, LDST_dec31_cr_in, LDST_dec31_cr_out, LDST_dec31_ldst_len, LDST_dec31_upd, LDST_dec31_rc_sel, LDST_dec31_br, LDST_dec31_sgn_ext, LDST_dec31_is_32b, LDST_dec31_sgn, opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_br; + reg LDST_dec31_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_cr_in; + reg [2:0] LDST_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_cr_out; + reg [2:0] LDST_dec31_cr_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LDST_dec31_dec_sub20_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LDST_dec31_dec_sub21_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LDST_dec31_dec_sub22_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LDST_dec31_dec_sub23_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LDST_dec31_function_unit; + reg [13:0] LDST_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_in1_sel; + reg [2:0] LDST_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_in2_sel; + reg [3:0] LDST_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LDST_dec31_internal_op; + reg [6:0] LDST_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_is_32b; + reg LDST_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_ldst_len; + reg [3:0] LDST_dec31_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_rc_sel; + reg [1:0] LDST_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_sgn; + reg LDST_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_sgn_ext; + reg LDST_dec31_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_upd; + reg [1:0] LDST_dec31_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + LDST_dec31_dec_sub20 LDST_dec31_dec_sub20 ( + .LDST_dec31_dec_sub20_br(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br), + .LDST_dec31_dec_sub20_cr_in(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in), + .LDST_dec31_dec_sub20_cr_out(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out), + .LDST_dec31_dec_sub20_function_unit(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit), + .LDST_dec31_dec_sub20_in1_sel(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel), + .LDST_dec31_dec_sub20_in2_sel(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel), + .LDST_dec31_dec_sub20_internal_op(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op), + .LDST_dec31_dec_sub20_is_32b(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b), + .LDST_dec31_dec_sub20_ldst_len(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len), + .LDST_dec31_dec_sub20_rc_sel(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel), + .LDST_dec31_dec_sub20_sgn(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn), + .LDST_dec31_dec_sub20_sgn_ext(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext), + .LDST_dec31_dec_sub20_upd(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd), + .opcode_in(LDST_dec31_dec_sub20_opcode_in) + ); + LDST_dec31_dec_sub21 LDST_dec31_dec_sub21 ( + .LDST_dec31_dec_sub21_br(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br), + .LDST_dec31_dec_sub21_cr_in(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in), + .LDST_dec31_dec_sub21_cr_out(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out), + .LDST_dec31_dec_sub21_function_unit(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit), + .LDST_dec31_dec_sub21_in1_sel(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel), + .LDST_dec31_dec_sub21_in2_sel(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel), + .LDST_dec31_dec_sub21_internal_op(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op), + .LDST_dec31_dec_sub21_is_32b(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b), + .LDST_dec31_dec_sub21_ldst_len(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len), + .LDST_dec31_dec_sub21_rc_sel(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel), + .LDST_dec31_dec_sub21_sgn(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn), + .LDST_dec31_dec_sub21_sgn_ext(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext), + .LDST_dec31_dec_sub21_upd(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd), + .opcode_in(LDST_dec31_dec_sub21_opcode_in) + ); + LDST_dec31_dec_sub22 LDST_dec31_dec_sub22 ( + .LDST_dec31_dec_sub22_br(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br), + .LDST_dec31_dec_sub22_cr_in(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in), + .LDST_dec31_dec_sub22_cr_out(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out), + .LDST_dec31_dec_sub22_function_unit(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit), + .LDST_dec31_dec_sub22_in1_sel(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel), + .LDST_dec31_dec_sub22_in2_sel(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel), + .LDST_dec31_dec_sub22_internal_op(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op), + .LDST_dec31_dec_sub22_is_32b(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b), + .LDST_dec31_dec_sub22_ldst_len(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len), + .LDST_dec31_dec_sub22_rc_sel(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel), + .LDST_dec31_dec_sub22_sgn(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn), + .LDST_dec31_dec_sub22_sgn_ext(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext), + .LDST_dec31_dec_sub22_upd(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd), + .opcode_in(LDST_dec31_dec_sub22_opcode_in) + ); + LDST_dec31_dec_sub23 LDST_dec31_dec_sub23 ( + .LDST_dec31_dec_sub23_br(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br), + .LDST_dec31_dec_sub23_cr_in(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in), + .LDST_dec31_dec_sub23_cr_out(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out), + .LDST_dec31_dec_sub23_function_unit(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit), + .LDST_dec31_dec_sub23_in1_sel(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel), + .LDST_dec31_dec_sub23_in2_sel(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel), + .LDST_dec31_dec_sub23_internal_op(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op), + .LDST_dec31_dec_sub23_is_32b(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b), + .LDST_dec31_dec_sub23_ldst_len(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len), + .LDST_dec31_dec_sub23_rc_sel(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel), + .LDST_dec31_dec_sub23_sgn(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn), + .LDST_dec31_dec_sub23_sgn_ext(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext), + .LDST_dec31_dec_sub23_upd(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd), + .opcode_in(LDST_dec31_dec_sub23_opcode_in) + ); + always @* begin + if (\initial ) begin end + LDST_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_cr_in = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_cr_in = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_cr_in = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_cr_in = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_cr_out = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_cr_out = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_cr_out = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_cr_out = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_ldst_len = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_ldst_len = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_ldst_len = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_ldst_len = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_upd = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_upd = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_upd = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_upd = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_rc_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_rc_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_rc_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_rc_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_br = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_br = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_br = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_br = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_sgn_ext = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_sgn_ext = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_sgn_ext = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_sgn_ext = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_is_32b = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_is_32b = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_is_32b = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_is_32b = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_sgn = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_sgn = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_sgn = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_sgn = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_function_unit = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_function_unit = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_function_unit = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_function_unit = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_internal_op = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_internal_op = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_internal_op = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_internal_op = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_in1_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_in1_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_in1_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_in1_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_in2_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_in2_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_in2_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + LDST_dec31_in2_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel; + endcase + end + assign LDST_dec31_dec_sub23_opcode_in = opcode_in; + assign LDST_dec31_dec_sub21_opcode_in = opcode_in; + assign LDST_dec31_dec_sub20_opcode_in = opcode_in; + assign LDST_dec31_dec_sub22_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" *) +(* generator = "nMigen" *) +module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_sub20_internal_op, LDST_dec31_dec_sub20_in1_sel, LDST_dec31_dec_sub20_in2_sel, LDST_dec31_dec_sub20_cr_in, LDST_dec31_dec_sub20_cr_out, LDST_dec31_dec_sub20_ldst_len, LDST_dec31_dec_sub20_upd, LDST_dec31_dec_sub20_rc_sel, LDST_dec31_dec_sub20_br, LDST_dec31_dec_sub20_sgn_ext, LDST_dec31_dec_sub20_is_32b, LDST_dec31_dec_sub20_sgn, opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub20_br; + reg LDST_dec31_dec_sub20_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub20_cr_in; + reg [2:0] LDST_dec31_dec_sub20_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub20_cr_out; + reg [2:0] LDST_dec31_dec_sub20_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LDST_dec31_dec_sub20_function_unit; + reg [13:0] LDST_dec31_dec_sub20_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub20_in1_sel; + reg [2:0] LDST_dec31_dec_sub20_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_dec_sub20_in2_sel; + reg [3:0] LDST_dec31_dec_sub20_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LDST_dec31_dec_sub20_internal_op; + reg [6:0] LDST_dec31_dec_sub20_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub20_is_32b; + reg LDST_dec31_dec_sub20_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_dec_sub20_ldst_len; + reg [3:0] LDST_dec31_dec_sub20_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub20_rc_sel; + reg [1:0] LDST_dec31_dec_sub20_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub20_sgn; + reg LDST_dec31_dec_sub20_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub20_sgn_ext; + reg LDST_dec31_dec_sub20_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub20_upd; + reg [1:0] LDST_dec31_dec_sub20_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_br = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_ldst_len = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" *) +(* generator = "nMigen" *) +module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_sub21_internal_op, LDST_dec31_dec_sub21_in1_sel, LDST_dec31_dec_sub21_in2_sel, LDST_dec31_dec_sub21_cr_in, LDST_dec31_dec_sub21_cr_out, LDST_dec31_dec_sub21_ldst_len, LDST_dec31_dec_sub21_upd, LDST_dec31_dec_sub21_rc_sel, LDST_dec31_dec_sub21_br, LDST_dec31_dec_sub21_sgn_ext, LDST_dec31_dec_sub21_is_32b, LDST_dec31_dec_sub21_sgn, opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub21_br; + reg LDST_dec31_dec_sub21_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub21_cr_in; + reg [2:0] LDST_dec31_dec_sub21_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub21_cr_out; + reg [2:0] LDST_dec31_dec_sub21_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LDST_dec31_dec_sub21_function_unit; + reg [13:0] LDST_dec31_dec_sub21_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub21_in1_sel; + reg [2:0] LDST_dec31_dec_sub21_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_dec_sub21_in2_sel; + reg [3:0] LDST_dec31_dec_sub21_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LDST_dec31_dec_sub21_internal_op; + reg [6:0] LDST_dec31_dec_sub21_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub21_is_32b; + reg LDST_dec31_dec_sub21_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_dec_sub21_ldst_len; + reg [3:0] LDST_dec31_dec_sub21_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub21_rc_sel; + reg [1:0] LDST_dec31_dec_sub21_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub21_sgn; + reg LDST_dec31_dec_sub21_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub21_sgn_ext; + reg LDST_dec31_dec_sub21_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub21_upd; + reg [1:0] LDST_dec31_dec_sub21_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_upd = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" *) +(* generator = "nMigen" *) +module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_sub22_internal_op, LDST_dec31_dec_sub22_in1_sel, LDST_dec31_dec_sub22_in2_sel, LDST_dec31_dec_sub22_cr_in, LDST_dec31_dec_sub22_cr_out, LDST_dec31_dec_sub22_ldst_len, LDST_dec31_dec_sub22_upd, LDST_dec31_dec_sub22_rc_sel, LDST_dec31_dec_sub22_br, LDST_dec31_dec_sub22_sgn_ext, LDST_dec31_dec_sub22_is_32b, LDST_dec31_dec_sub22_sgn, opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub22_br; + reg LDST_dec31_dec_sub22_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub22_cr_in; + reg [2:0] LDST_dec31_dec_sub22_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub22_cr_out; + reg [2:0] LDST_dec31_dec_sub22_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LDST_dec31_dec_sub22_function_unit; + reg [13:0] LDST_dec31_dec_sub22_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub22_in1_sel; + reg [2:0] LDST_dec31_dec_sub22_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_dec_sub22_in2_sel; + reg [3:0] LDST_dec31_dec_sub22_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LDST_dec31_dec_sub22_internal_op; + reg [6:0] LDST_dec31_dec_sub22_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub22_is_32b; + reg LDST_dec31_dec_sub22_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_dec_sub22_ldst_len; + reg [3:0] LDST_dec31_dec_sub22_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub22_rc_sel; + reg [1:0] LDST_dec31_dec_sub22_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub22_sgn; + reg LDST_dec31_dec_sub22_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub22_sgn_ext; + reg LDST_dec31_dec_sub22_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub22_upd; + reg [1:0] LDST_dec31_dec_sub22_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + LDST_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LDST_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + LDST_dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LDST_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + LDST_dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + LDST_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub22_rc_sel = 2'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" *) +(* generator = "nMigen" *) +module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_sub23_internal_op, LDST_dec31_dec_sub23_in1_sel, LDST_dec31_dec_sub23_in2_sel, LDST_dec31_dec_sub23_cr_in, LDST_dec31_dec_sub23_cr_out, LDST_dec31_dec_sub23_ldst_len, LDST_dec31_dec_sub23_upd, LDST_dec31_dec_sub23_rc_sel, LDST_dec31_dec_sub23_br, LDST_dec31_dec_sub23_sgn_ext, LDST_dec31_dec_sub23_is_32b, LDST_dec31_dec_sub23_sgn, opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub23_br; + reg LDST_dec31_dec_sub23_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub23_cr_in; + reg [2:0] LDST_dec31_dec_sub23_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub23_cr_out; + reg [2:0] LDST_dec31_dec_sub23_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LDST_dec31_dec_sub23_function_unit; + reg [13:0] LDST_dec31_dec_sub23_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec31_dec_sub23_in1_sel; + reg [2:0] LDST_dec31_dec_sub23_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_dec_sub23_in2_sel; + reg [3:0] LDST_dec31_dec_sub23_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LDST_dec31_dec_sub23_internal_op; + reg [6:0] LDST_dec31_dec_sub23_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub23_is_32b; + reg LDST_dec31_dec_sub23_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec31_dec_sub23_ldst_len; + reg [3:0] LDST_dec31_dec_sub23_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub23_rc_sel; + reg [1:0] LDST_dec31_dec_sub23_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub23_sgn; + reg LDST_dec31_dec_sub23_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec31_dec_sub23_sgn_ext; + reg LDST_dec31_dec_sub23_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub23_upd; + reg [1:0] LDST_dec31_dec_sub23_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LDST_dec31_dec_sub23_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" *) +(* generator = "nMigen" *) +module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_in1_sel, LDST_dec58_in2_sel, LDST_dec58_cr_in, LDST_dec58_cr_out, LDST_dec58_ldst_len, LDST_dec58_upd, LDST_dec58_rc_sel, LDST_dec58_br, LDST_dec58_sgn_ext, LDST_dec58_is_32b, LDST_dec58_sgn, opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec58_br; + reg LDST_dec58_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec58_cr_in; + reg [2:0] LDST_dec58_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec58_cr_out; + reg [2:0] LDST_dec58_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LDST_dec58_function_unit; + reg [13:0] LDST_dec58_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec58_in1_sel; + reg [2:0] LDST_dec58_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec58_in2_sel; + reg [3:0] LDST_dec58_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LDST_dec58_internal_op; + reg [6:0] LDST_dec58_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec58_is_32b; + reg LDST_dec58_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec58_ldst_len; + reg [3:0] LDST_dec58_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec58_rc_sel; + reg [1:0] LDST_dec58_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec58_sgn; + reg LDST_dec58_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec58_sgn_ext; + reg LDST_dec58_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec58_upd; + reg [1:0] LDST_dec58_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [1:0] opcode_switch; + always @* begin + if (\initial ) begin end + LDST_dec58_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_sgn_ext = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_internal_op = 7'h25; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_in2_sel = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_in2_sel = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_in2_sel = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec58_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec58_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + LDST_dec58_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[1:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" *) +(* generator = "nMigen" *) +module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_in1_sel, LDST_dec62_in2_sel, LDST_dec62_cr_in, LDST_dec62_cr_out, LDST_dec62_ldst_len, LDST_dec62_upd, LDST_dec62_rc_sel, LDST_dec62_br, LDST_dec62_sgn_ext, LDST_dec62_is_32b, LDST_dec62_sgn, opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec62_br; + reg LDST_dec62_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec62_cr_in; + reg [2:0] LDST_dec62_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec62_cr_out; + reg [2:0] LDST_dec62_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LDST_dec62_function_unit; + reg [13:0] LDST_dec62_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_dec62_in1_sel; + reg [2:0] LDST_dec62_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec62_in2_sel; + reg [3:0] LDST_dec62_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LDST_dec62_internal_op; + reg [6:0] LDST_dec62_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec62_is_32b; + reg LDST_dec62_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_dec62_ldst_len; + reg [3:0] LDST_dec62_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec62_rc_sel; + reg [1:0] LDST_dec62_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec62_sgn; + reg LDST_dec62_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_dec62_sgn_ext; + reg LDST_dec62_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec62_upd; + reg [1:0] LDST_dec62_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [1:0] opcode_switch; + always @* begin + if (\initial ) begin end + LDST_dec62_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_in2_sel = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_in2_sel = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_ldst_len = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_upd = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + LDST_dec62_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + LDST_dec62_rc_sel = 2'h0; + endcase + end + assign opcode_switch = opcode_in[1:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" *) +(* generator = "nMigen" *) +module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOGICAL_dec31_in1_sel, LOGICAL_dec31_in2_sel, LOGICAL_dec31_cr_in, LOGICAL_dec31_cr_out, LOGICAL_dec31_ldst_len, LOGICAL_dec31_rc_sel, LOGICAL_dec31_cry_in, LOGICAL_dec31_inv_a, LOGICAL_dec31_inv_out, LOGICAL_dec31_cry_out, LOGICAL_dec31_is_32b, LOGICAL_dec31_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_cr_in; + reg [2:0] LOGICAL_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_cr_out; + reg [2:0] LOGICAL_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_cry_in; + reg [1:0] LOGICAL_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_cry_out; + reg LOGICAL_dec31_cry_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LOGICAL_dec31_dec_sub26_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LOGICAL_dec31_dec_sub28_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LOGICAL_dec31_function_unit; + reg [13:0] LOGICAL_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_in1_sel; + reg [2:0] LOGICAL_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LOGICAL_dec31_in2_sel; + reg [3:0] LOGICAL_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LOGICAL_dec31_internal_op; + reg [6:0] LOGICAL_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_inv_a; + reg LOGICAL_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_inv_out; + reg LOGICAL_dec31_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_is_32b; + reg LOGICAL_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LOGICAL_dec31_ldst_len; + reg [3:0] LOGICAL_dec31_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_rc_sel; + reg [1:0] LOGICAL_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_sgn; + reg LOGICAL_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + LOGICAL_dec31_dec_sub26 LOGICAL_dec31_dec_sub26 ( + .LOGICAL_dec31_dec_sub26_cr_in(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in), + .LOGICAL_dec31_dec_sub26_cr_out(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out), + .LOGICAL_dec31_dec_sub26_cry_in(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in), + .LOGICAL_dec31_dec_sub26_cry_out(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out), + .LOGICAL_dec31_dec_sub26_function_unit(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit), + .LOGICAL_dec31_dec_sub26_in1_sel(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel), + .LOGICAL_dec31_dec_sub26_in2_sel(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel), + .LOGICAL_dec31_dec_sub26_internal_op(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op), + .LOGICAL_dec31_dec_sub26_inv_a(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a), + .LOGICAL_dec31_dec_sub26_inv_out(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out), + .LOGICAL_dec31_dec_sub26_is_32b(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b), + .LOGICAL_dec31_dec_sub26_ldst_len(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len), + .LOGICAL_dec31_dec_sub26_rc_sel(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel), + .LOGICAL_dec31_dec_sub26_sgn(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn), + .opcode_in(LOGICAL_dec31_dec_sub26_opcode_in) + ); + LOGICAL_dec31_dec_sub28 LOGICAL_dec31_dec_sub28 ( + .LOGICAL_dec31_dec_sub28_cr_in(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in), + .LOGICAL_dec31_dec_sub28_cr_out(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out), + .LOGICAL_dec31_dec_sub28_cry_in(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in), + .LOGICAL_dec31_dec_sub28_cry_out(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out), + .LOGICAL_dec31_dec_sub28_function_unit(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit), + .LOGICAL_dec31_dec_sub28_in1_sel(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel), + .LOGICAL_dec31_dec_sub28_in2_sel(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel), + .LOGICAL_dec31_dec_sub28_internal_op(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op), + .LOGICAL_dec31_dec_sub28_inv_a(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a), + .LOGICAL_dec31_dec_sub28_inv_out(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out), + .LOGICAL_dec31_dec_sub28_is_32b(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b), + .LOGICAL_dec31_dec_sub28_ldst_len(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len), + .LOGICAL_dec31_dec_sub28_rc_sel(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel), + .LOGICAL_dec31_dec_sub28_sgn(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn), + .opcode_in(LOGICAL_dec31_dec_sub28_opcode_in) + ); + always @* begin + if (\initial ) begin end + LOGICAL_dec31_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_ldst_len = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_ldst_len = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_rc_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_rc_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_cry_in = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_cry_in = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_inv_a = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_inv_a = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_inv_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_inv_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_cry_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_cry_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_is_32b = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_is_32b = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_sgn = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_sgn = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_function_unit = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_function_unit = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_internal_op = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_internal_op = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_in1_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_in1_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_in2_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_in2_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_cr_in = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_cr_in = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + LOGICAL_dec31_cr_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + LOGICAL_dec31_cr_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out; + endcase + end + assign LOGICAL_dec31_dec_sub26_opcode_in = opcode_in; + assign LOGICAL_dec31_dec_sub28_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" *) +(* generator = "nMigen" *) +module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_dec31_dec_sub26_internal_op, LOGICAL_dec31_dec_sub26_in1_sel, LOGICAL_dec31_dec_sub26_in2_sel, LOGICAL_dec31_dec_sub26_cr_in, LOGICAL_dec31_dec_sub26_cr_out, LOGICAL_dec31_dec_sub26_ldst_len, LOGICAL_dec31_dec_sub26_rc_sel, LOGICAL_dec31_dec_sub26_cry_in, LOGICAL_dec31_dec_sub26_inv_a, LOGICAL_dec31_dec_sub26_inv_out, LOGICAL_dec31_dec_sub26_cry_out, LOGICAL_dec31_dec_sub26_is_32b, LOGICAL_dec31_dec_sub26_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_dec_sub26_cr_in; + reg [2:0] LOGICAL_dec31_dec_sub26_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_dec_sub26_cr_out; + reg [2:0] LOGICAL_dec31_dec_sub26_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_dec_sub26_cry_in; + reg [1:0] LOGICAL_dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub26_cry_out; + reg LOGICAL_dec31_dec_sub26_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LOGICAL_dec31_dec_sub26_function_unit; + reg [13:0] LOGICAL_dec31_dec_sub26_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_dec_sub26_in1_sel; + reg [2:0] LOGICAL_dec31_dec_sub26_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LOGICAL_dec31_dec_sub26_in2_sel; + reg [3:0] LOGICAL_dec31_dec_sub26_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LOGICAL_dec31_dec_sub26_internal_op; + reg [6:0] LOGICAL_dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub26_inv_a; + reg LOGICAL_dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub26_inv_out; + reg LOGICAL_dec31_dec_sub26_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub26_is_32b; + reg LOGICAL_dec31_dec_sub26_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LOGICAL_dec31_dec_sub26_ldst_len; + reg [3:0] LOGICAL_dec31_dec_sub26_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_dec_sub26_rc_sel; + reg [1:0] LOGICAL_dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub26_sgn; + reg LOGICAL_dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_internal_op = 7'h36; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_internal_op = 7'h36; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_internal_op = 7'h36; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_internal_op = 7'h37; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_internal_op = 7'h37; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" *) +(* generator = "nMigen" *) +module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_dec31_dec_sub28_internal_op, LOGICAL_dec31_dec_sub28_in1_sel, LOGICAL_dec31_dec_sub28_in2_sel, LOGICAL_dec31_dec_sub28_cr_in, LOGICAL_dec31_dec_sub28_cr_out, LOGICAL_dec31_dec_sub28_ldst_len, LOGICAL_dec31_dec_sub28_rc_sel, LOGICAL_dec31_dec_sub28_cry_in, LOGICAL_dec31_dec_sub28_inv_a, LOGICAL_dec31_dec_sub28_inv_out, LOGICAL_dec31_dec_sub28_cry_out, LOGICAL_dec31_dec_sub28_is_32b, LOGICAL_dec31_dec_sub28_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_dec_sub28_cr_in; + reg [2:0] LOGICAL_dec31_dec_sub28_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_dec_sub28_cr_out; + reg [2:0] LOGICAL_dec31_dec_sub28_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_dec_sub28_cry_in; + reg [1:0] LOGICAL_dec31_dec_sub28_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub28_cry_out; + reg LOGICAL_dec31_dec_sub28_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LOGICAL_dec31_dec_sub28_function_unit; + reg [13:0] LOGICAL_dec31_dec_sub28_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_dec31_dec_sub28_in1_sel; + reg [2:0] LOGICAL_dec31_dec_sub28_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LOGICAL_dec31_dec_sub28_in2_sel; + reg [3:0] LOGICAL_dec31_dec_sub28_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LOGICAL_dec31_dec_sub28_internal_op; + reg [6:0] LOGICAL_dec31_dec_sub28_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub28_inv_a; + reg LOGICAL_dec31_dec_sub28_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub28_inv_out; + reg LOGICAL_dec31_dec_sub28_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub28_is_32b; + reg LOGICAL_dec31_dec_sub28_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LOGICAL_dec31_dec_sub28_ldst_len; + reg [3:0] LOGICAL_dec31_dec_sub28_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_dec_sub28_rc_sel; + reg [1:0] LOGICAL_dec31_dec_sub28_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_dec31_dec_sub28_sgn; + reg LOGICAL_dec31_dec_sub28_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_inv_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_inv_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_inv_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_internal_op = 7'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_internal_op = 7'h0b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_internal_op = 7'h43; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_internal_op = 7'h43; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" *) +(* generator = "nMigen" *) +module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_sel, MUL_dec31_cr_in, MUL_dec31_cr_out, MUL_dec31_rc_sel, MUL_dec31_is_32b, MUL_dec31_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] MUL_dec31_cr_in; + reg [2:0] MUL_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] MUL_dec31_cr_out; + reg [2:0] MUL_dec31_cr_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] MUL_dec31_dec_sub11_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] MUL_dec31_dec_sub9_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] MUL_dec31_function_unit; + reg [13:0] MUL_dec31_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] MUL_dec31_in2_sel; + reg [3:0] MUL_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] MUL_dec31_internal_op; + reg [6:0] MUL_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output MUL_dec31_is_32b; + reg MUL_dec31_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] MUL_dec31_rc_sel; + reg [1:0] MUL_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output MUL_dec31_sgn; + reg MUL_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + MUL_dec31_dec_sub11 MUL_dec31_dec_sub11 ( + .MUL_dec31_dec_sub11_cr_in(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in), + .MUL_dec31_dec_sub11_cr_out(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out), + .MUL_dec31_dec_sub11_function_unit(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit), + .MUL_dec31_dec_sub11_in2_sel(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel), + .MUL_dec31_dec_sub11_internal_op(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op), + .MUL_dec31_dec_sub11_is_32b(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b), + .MUL_dec31_dec_sub11_rc_sel(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel), + .MUL_dec31_dec_sub11_sgn(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn), + .opcode_in(MUL_dec31_dec_sub11_opcode_in) + ); + MUL_dec31_dec_sub9 MUL_dec31_dec_sub9 ( + .MUL_dec31_dec_sub9_cr_in(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in), + .MUL_dec31_dec_sub9_cr_out(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out), + .MUL_dec31_dec_sub9_function_unit(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit), + .MUL_dec31_dec_sub9_in2_sel(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel), + .MUL_dec31_dec_sub9_internal_op(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op), + .MUL_dec31_dec_sub9_is_32b(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b), + .MUL_dec31_dec_sub9_rc_sel(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel), + .MUL_dec31_dec_sub9_sgn(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn), + .opcode_in(MUL_dec31_dec_sub9_opcode_in) + ); + always @* begin + if (\initial ) begin end + MUL_dec31_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + MUL_dec31_is_32b = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + MUL_dec31_is_32b = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + MUL_dec31_sgn = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + MUL_dec31_sgn = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + MUL_dec31_function_unit = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + MUL_dec31_function_unit = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + MUL_dec31_internal_op = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + MUL_dec31_internal_op = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + MUL_dec31_in2_sel = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + MUL_dec31_in2_sel = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + MUL_dec31_cr_in = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + MUL_dec31_cr_in = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + MUL_dec31_cr_out = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + MUL_dec31_cr_out = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + MUL_dec31_rc_sel = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + MUL_dec31_rc_sel = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel; + endcase + end + assign MUL_dec31_dec_sub11_opcode_in = opcode_in; + assign MUL_dec31_dec_sub9_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" *) +(* generator = "nMigen" *) +module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub11_internal_op, MUL_dec31_dec_sub11_in2_sel, MUL_dec31_dec_sub11_cr_in, MUL_dec31_dec_sub11_cr_out, MUL_dec31_dec_sub11_rc_sel, MUL_dec31_dec_sub11_is_32b, MUL_dec31_dec_sub11_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] MUL_dec31_dec_sub11_cr_in; + reg [2:0] MUL_dec31_dec_sub11_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] MUL_dec31_dec_sub11_cr_out; + reg [2:0] MUL_dec31_dec_sub11_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] MUL_dec31_dec_sub11_function_unit; + reg [13:0] MUL_dec31_dec_sub11_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] MUL_dec31_dec_sub11_in2_sel; + reg [3:0] MUL_dec31_dec_sub11_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] MUL_dec31_dec_sub11_internal_op; + reg [6:0] MUL_dec31_dec_sub11_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output MUL_dec31_dec_sub11_is_32b; + reg MUL_dec31_dec_sub11_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] MUL_dec31_dec_sub11_rc_sel; + reg [1:0] MUL_dec31_dec_sub11_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output MUL_dec31_dec_sub11_sgn; + reg MUL_dec31_dec_sub11_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub11_function_unit = 14'h0100; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub11_internal_op = 7'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub11_internal_op = 7'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub11_internal_op = 7'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub11_internal_op = 7'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub11_internal_op = 7'h32; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub11_internal_op = 7'h32; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub11_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub11_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub11_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub11_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub11_is_32b = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub11_sgn = 1'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" *) +(* generator = "nMigen" *) +module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_internal_op, MUL_dec31_dec_sub9_in2_sel, MUL_dec31_dec_sub9_cr_in, MUL_dec31_dec_sub9_cr_out, MUL_dec31_dec_sub9_rc_sel, MUL_dec31_dec_sub9_is_32b, MUL_dec31_dec_sub9_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] MUL_dec31_dec_sub9_cr_in; + reg [2:0] MUL_dec31_dec_sub9_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] MUL_dec31_dec_sub9_cr_out; + reg [2:0] MUL_dec31_dec_sub9_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] MUL_dec31_dec_sub9_function_unit; + reg [13:0] MUL_dec31_dec_sub9_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] MUL_dec31_dec_sub9_in2_sel; + reg [3:0] MUL_dec31_dec_sub9_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] MUL_dec31_dec_sub9_internal_op; + reg [6:0] MUL_dec31_dec_sub9_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output MUL_dec31_dec_sub9_is_32b; + reg MUL_dec31_dec_sub9_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] MUL_dec31_dec_sub9_rc_sel; + reg [1:0] MUL_dec31_dec_sub9_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output MUL_dec31_dec_sub9_sgn; + reg MUL_dec31_dec_sub9_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub9_function_unit = 14'h0100; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub9_internal_op = 7'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub9_internal_op = 7'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub9_internal_op = 7'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub9_internal_op = 7'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub9_internal_op = 7'h32; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub9_internal_op = 7'h32; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub9_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub9_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub9_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub9_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub9_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + MUL_dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + MUL_dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + MUL_dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + MUL_dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + MUL_dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + MUL_dec31_dec_sub9_sgn = 1'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" *) +(* generator = "nMigen" *) +module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_op, SHIFT_ROT_dec30_in2_sel, SHIFT_ROT_dec30_cr_in, SHIFT_ROT_dec30_cr_out, SHIFT_ROT_dec30_rc_sel, SHIFT_ROT_dec30_cry_in, SHIFT_ROT_dec30_inv_a, SHIFT_ROT_dec30_cry_out, SHIFT_ROT_dec30_is_32b, SHIFT_ROT_dec30_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec30_cr_in; + reg [2:0] SHIFT_ROT_dec30_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec30_cr_out; + reg [2:0] SHIFT_ROT_dec30_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec30_cry_in; + reg [1:0] SHIFT_ROT_dec30_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec30_cry_out; + reg SHIFT_ROT_dec30_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SHIFT_ROT_dec30_function_unit; + reg [13:0] SHIFT_ROT_dec30_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] SHIFT_ROT_dec30_in2_sel; + reg [3:0] SHIFT_ROT_dec30_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SHIFT_ROT_dec30_internal_op; + reg [6:0] SHIFT_ROT_dec30_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec30_inv_a; + reg SHIFT_ROT_dec30_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec30_is_32b; + reg SHIFT_ROT_dec30_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec30_rc_sel; + reg [1:0] SHIFT_ROT_dec30_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec30_sgn; + reg SHIFT_ROT_dec30_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [3:0] opcode_switch; + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_internal_op = 7'h39; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_internal_op = 7'h39; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_internal_op = 7'h3a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_internal_op = 7'h3a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_internal_op = 7'h39; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_internal_op = 7'h3a; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + SHIFT_ROT_dec30_cry_out = 1'h0; + endcase + end + assign opcode_switch = opcode_in[4:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" *) +(* generator = "nMigen" *) +module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_op, SHIFT_ROT_dec31_in2_sel, SHIFT_ROT_dec31_cr_in, SHIFT_ROT_dec31_cr_out, SHIFT_ROT_dec31_rc_sel, SHIFT_ROT_dec31_cry_in, SHIFT_ROT_dec31_inv_a, SHIFT_ROT_dec31_cry_out, SHIFT_ROT_dec31_is_32b, SHIFT_ROT_dec31_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec31_cr_in; + reg [2:0] SHIFT_ROT_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec31_cr_out; + reg [2:0] SHIFT_ROT_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_cry_in; + reg [1:0] SHIFT_ROT_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_cry_out; + reg SHIFT_ROT_dec31_cry_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] SHIFT_ROT_dec31_dec_sub24_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] SHIFT_ROT_dec31_dec_sub26_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] SHIFT_ROT_dec31_dec_sub27_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SHIFT_ROT_dec31_function_unit; + reg [13:0] SHIFT_ROT_dec31_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] SHIFT_ROT_dec31_in2_sel; + reg [3:0] SHIFT_ROT_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SHIFT_ROT_dec31_internal_op; + reg [6:0] SHIFT_ROT_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_inv_a; + reg SHIFT_ROT_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_is_32b; + reg SHIFT_ROT_dec31_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_rc_sel; + reg [1:0] SHIFT_ROT_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_sgn; + reg SHIFT_ROT_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + SHIFT_ROT_dec31_dec_sub24 SHIFT_ROT_dec31_dec_sub24 ( + .SHIFT_ROT_dec31_dec_sub24_cr_in(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in), + .SHIFT_ROT_dec31_dec_sub24_cr_out(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out), + .SHIFT_ROT_dec31_dec_sub24_cry_in(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in), + .SHIFT_ROT_dec31_dec_sub24_cry_out(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out), + .SHIFT_ROT_dec31_dec_sub24_function_unit(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit), + .SHIFT_ROT_dec31_dec_sub24_in2_sel(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel), + .SHIFT_ROT_dec31_dec_sub24_internal_op(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op), + .SHIFT_ROT_dec31_dec_sub24_inv_a(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a), + .SHIFT_ROT_dec31_dec_sub24_is_32b(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b), + .SHIFT_ROT_dec31_dec_sub24_rc_sel(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel), + .SHIFT_ROT_dec31_dec_sub24_sgn(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn), + .opcode_in(SHIFT_ROT_dec31_dec_sub24_opcode_in) + ); + SHIFT_ROT_dec31_dec_sub26 SHIFT_ROT_dec31_dec_sub26 ( + .SHIFT_ROT_dec31_dec_sub26_cr_in(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in), + .SHIFT_ROT_dec31_dec_sub26_cr_out(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out), + .SHIFT_ROT_dec31_dec_sub26_cry_in(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in), + .SHIFT_ROT_dec31_dec_sub26_cry_out(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out), + .SHIFT_ROT_dec31_dec_sub26_function_unit(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit), + .SHIFT_ROT_dec31_dec_sub26_in2_sel(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel), + .SHIFT_ROT_dec31_dec_sub26_internal_op(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op), + .SHIFT_ROT_dec31_dec_sub26_inv_a(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a), + .SHIFT_ROT_dec31_dec_sub26_is_32b(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b), + .SHIFT_ROT_dec31_dec_sub26_rc_sel(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel), + .SHIFT_ROT_dec31_dec_sub26_sgn(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn), + .opcode_in(SHIFT_ROT_dec31_dec_sub26_opcode_in) + ); + SHIFT_ROT_dec31_dec_sub27 SHIFT_ROT_dec31_dec_sub27 ( + .SHIFT_ROT_dec31_dec_sub27_cr_in(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in), + .SHIFT_ROT_dec31_dec_sub27_cr_out(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out), + .SHIFT_ROT_dec31_dec_sub27_cry_in(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in), + .SHIFT_ROT_dec31_dec_sub27_cry_out(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out), + .SHIFT_ROT_dec31_dec_sub27_function_unit(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit), + .SHIFT_ROT_dec31_dec_sub27_in2_sel(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel), + .SHIFT_ROT_dec31_dec_sub27_internal_op(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op), + .SHIFT_ROT_dec31_dec_sub27_inv_a(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a), + .SHIFT_ROT_dec31_dec_sub27_is_32b(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b), + .SHIFT_ROT_dec31_dec_sub27_rc_sel(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel), + .SHIFT_ROT_dec31_dec_sub27_sgn(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn), + .opcode_in(SHIFT_ROT_dec31_dec_sub27_opcode_in) + ); + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out; + endcase + end + assign SHIFT_ROT_dec31_dec_sub24_opcode_in = opcode_in; + assign SHIFT_ROT_dec31_dec_sub27_opcode_in = opcode_in; + assign SHIFT_ROT_dec31_dec_sub26_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" *) +(* generator = "nMigen" *) +module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ROT_dec31_dec_sub24_internal_op, SHIFT_ROT_dec31_dec_sub24_in2_sel, SHIFT_ROT_dec31_dec_sub24_cr_in, SHIFT_ROT_dec31_dec_sub24_cr_out, SHIFT_ROT_dec31_dec_sub24_rc_sel, SHIFT_ROT_dec31_dec_sub24_cry_in, SHIFT_ROT_dec31_dec_sub24_inv_a, SHIFT_ROT_dec31_dec_sub24_cry_out, SHIFT_ROT_dec31_dec_sub24_is_32b, SHIFT_ROT_dec31_dec_sub24_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec31_dec_sub24_cr_in; + reg [2:0] SHIFT_ROT_dec31_dec_sub24_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec31_dec_sub24_cr_out; + reg [2:0] SHIFT_ROT_dec31_dec_sub24_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub24_cry_in; + reg [1:0] SHIFT_ROT_dec31_dec_sub24_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub24_cry_out; + reg SHIFT_ROT_dec31_dec_sub24_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SHIFT_ROT_dec31_dec_sub24_function_unit; + reg [13:0] SHIFT_ROT_dec31_dec_sub24_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] SHIFT_ROT_dec31_dec_sub24_in2_sel; + reg [3:0] SHIFT_ROT_dec31_dec_sub24_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SHIFT_ROT_dec31_dec_sub24_internal_op; + reg [6:0] SHIFT_ROT_dec31_dec_sub24_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub24_inv_a; + reg SHIFT_ROT_dec31_dec_sub24_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub24_is_32b; + reg SHIFT_ROT_dec31_dec_sub24_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub24_rc_sel; + reg [1:0] SHIFT_ROT_dec31_dec_sub24_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub24_sgn; + reg SHIFT_ROT_dec31_dec_sub24_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'hb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" *) +(* generator = "nMigen" *) +module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ROT_dec31_dec_sub26_internal_op, SHIFT_ROT_dec31_dec_sub26_in2_sel, SHIFT_ROT_dec31_dec_sub26_cr_in, SHIFT_ROT_dec31_dec_sub26_cr_out, SHIFT_ROT_dec31_dec_sub26_rc_sel, SHIFT_ROT_dec31_dec_sub26_cry_in, SHIFT_ROT_dec31_dec_sub26_inv_a, SHIFT_ROT_dec31_dec_sub26_cry_out, SHIFT_ROT_dec31_dec_sub26_is_32b, SHIFT_ROT_dec31_dec_sub26_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec31_dec_sub26_cr_in; + reg [2:0] SHIFT_ROT_dec31_dec_sub26_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec31_dec_sub26_cr_out; + reg [2:0] SHIFT_ROT_dec31_dec_sub26_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub26_cry_in; + reg [1:0] SHIFT_ROT_dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub26_cry_out; + reg SHIFT_ROT_dec31_dec_sub26_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SHIFT_ROT_dec31_dec_sub26_function_unit; + reg [13:0] SHIFT_ROT_dec31_dec_sub26_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] SHIFT_ROT_dec31_dec_sub26_in2_sel; + reg [3:0] SHIFT_ROT_dec31_dec_sub26_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SHIFT_ROT_dec31_dec_sub26_internal_op; + reg [6:0] SHIFT_ROT_dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub26_inv_a; + reg SHIFT_ROT_dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub26_is_32b; + reg SHIFT_ROT_dec31_dec_sub26_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub26_rc_sel; + reg [1:0] SHIFT_ROT_dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub26_sgn; + reg SHIFT_ROT_dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_sgn = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h20; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h3d; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'ha; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" *) +(* generator = "nMigen" *) +module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ROT_dec31_dec_sub27_internal_op, SHIFT_ROT_dec31_dec_sub27_in2_sel, SHIFT_ROT_dec31_dec_sub27_cr_in, SHIFT_ROT_dec31_dec_sub27_cr_out, SHIFT_ROT_dec31_dec_sub27_rc_sel, SHIFT_ROT_dec31_dec_sub27_cry_in, SHIFT_ROT_dec31_dec_sub27_inv_a, SHIFT_ROT_dec31_dec_sub27_cry_out, SHIFT_ROT_dec31_dec_sub27_is_32b, SHIFT_ROT_dec31_dec_sub27_sgn, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec31_dec_sub27_cr_in; + reg [2:0] SHIFT_ROT_dec31_dec_sub27_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_dec31_dec_sub27_cr_out; + reg [2:0] SHIFT_ROT_dec31_dec_sub27_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub27_cry_in; + reg [1:0] SHIFT_ROT_dec31_dec_sub27_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub27_cry_out; + reg SHIFT_ROT_dec31_dec_sub27_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SHIFT_ROT_dec31_dec_sub27_function_unit; + reg [13:0] SHIFT_ROT_dec31_dec_sub27_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] SHIFT_ROT_dec31_dec_sub27_in2_sel; + reg [3:0] SHIFT_ROT_dec31_dec_sub27_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SHIFT_ROT_dec31_dec_sub27_internal_op; + reg [6:0] SHIFT_ROT_dec31_dec_sub27_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub27_inv_a; + reg SHIFT_ROT_dec31_dec_sub27_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub27_is_32b; + reg SHIFT_ROT_dec31_dec_sub27_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub27_rc_sel; + reg [1:0] SHIFT_ROT_dec31_dec_sub27_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_dec31_dec_sub27_sgn; + reg SHIFT_ROT_dec31_dec_sub27_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h20; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3d; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" *) +(* generator = "nMigen" *) +module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in, SPR_dec31_cr_out, SPR_dec31_rc_sel, SPR_dec31_is_32b, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SPR_dec31_cr_in; + reg [2:0] SPR_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SPR_dec31_cr_out; + reg [2:0] SPR_dec31_cr_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] SPR_dec31_dec_sub19_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SPR_dec31_function_unit; + reg [13:0] SPR_dec31_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SPR_dec31_internal_op; + reg [6:0] SPR_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SPR_dec31_is_32b; + reg SPR_dec31_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SPR_dec31_rc_sel; + reg [1:0] SPR_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + SPR_dec31_dec_sub19 SPR_dec31_dec_sub19 ( + .SPR_dec31_dec_sub19_cr_in(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in), + .SPR_dec31_dec_sub19_cr_out(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out), + .SPR_dec31_dec_sub19_function_unit(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit), + .SPR_dec31_dec_sub19_internal_op(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op), + .SPR_dec31_dec_sub19_is_32b(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b), + .SPR_dec31_dec_sub19_rc_sel(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel), + .opcode_in(SPR_dec31_dec_sub19_opcode_in) + ); + always @* begin + if (\initial ) begin end + SPR_dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + SPR_dec31_function_unit = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + SPR_dec31_internal_op = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + SPR_dec31_cr_in = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + SPR_dec31_cr_out = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + SPR_dec31_rc_sel = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + SPR_dec31_is_32b = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b; + endcase + end + assign SPR_dec31_dec_sub19_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" *) +(* generator = "nMigen" *) +module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub19_internal_op, SPR_dec31_dec_sub19_cr_in, SPR_dec31_dec_sub19_cr_out, SPR_dec31_dec_sub19_rc_sel, SPR_dec31_dec_sub19_is_32b, opcode_in); + reg \initial = 0; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SPR_dec31_dec_sub19_cr_in; + reg [2:0] SPR_dec31_dec_sub19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SPR_dec31_dec_sub19_cr_out; + reg [2:0] SPR_dec31_dec_sub19_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SPR_dec31_dec_sub19_function_unit; + reg [13:0] SPR_dec31_dec_sub19_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SPR_dec31_dec_sub19_internal_op; + reg [6:0] SPR_dec31_dec_sub19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SPR_dec31_dec_sub19_is_32b; + reg SPR_dec31_dec_sub19_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SPR_dec31_dec_sub19_rc_sel; + reg [1:0] SPR_dec31_dec_sub19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + SPR_dec31_dec_sub19_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + SPR_dec31_dec_sub19_function_unit = 14'h0400; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + SPR_dec31_dec_sub19_function_unit = 14'h0400; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_dec_sub19_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + SPR_dec31_dec_sub19_internal_op = 7'h2e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + SPR_dec31_dec_sub19_internal_op = 7'h31; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_dec_sub19_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + SPR_dec31_dec_sub19_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + SPR_dec31_dec_sub19_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_dec_sub19_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + SPR_dec31_dec_sub19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + SPR_dec31_dec_sub19_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_dec_sub19_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + SPR_dec31_dec_sub19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + SPR_dec31_dec_sub19_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + SPR_dec31_dec_sub19_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + SPR_dec31_dec_sub19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + SPR_dec31_dec_sub19_is_32b = 1'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.adr_l" *) +(* generator = "nMigen" *) +module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_adr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_adr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_adr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_adr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_adr; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_adr; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_adr; + assign \$15 = q_adr | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_adr; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_adr; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_adr; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_adr = \$15 ; + assign qn_adr = \$13 ; + assign q_adr = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.adrok_l" *) +(* generator = "nMigen" *) +module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_acked, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_addr_acked; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_addr_acked; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + output qn_addr_acked; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_addr_acked; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_addr_acked; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_addr_acked; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_addr_acked; + assign \$15 = q_addr_acked | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_addr_acked; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_addr_acked; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_addr_acked; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_addr_acked = \$15 ; + assign qn_addr_acked = \$13 ; + assign q_addr_acked = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0" *) +(* generator = "nMigen" *) +module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, xer_ov_ok, dest4_o, xer_so_ok, dest5_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [3:0] \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [3:0] \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [3:0] \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [3:0] \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$117 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$119 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [4:0] \$125 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [4:0] \$127 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$129 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$131 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$133 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$135 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$137 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [4:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [4:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [4:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [4:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [3:0] \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [4:0] \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [3:0] \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [4:0] \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [4:0] \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [3:0] \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$89 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$91 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$93 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [1:0] \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] alu_alu0_alu_op__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \alu_alu0_alu_op__data_len$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_alu0_alu_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_alu0_alu_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_alu0_alu_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_alu0_alu_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__imm_data__ok$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] alu_alu0_alu_op__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \alu_alu0_alu_op__input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_alu0_alu_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_alu0_alu_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_alu0_alu_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_alu0_alu_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__invert_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__invert_out$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__output_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_alu0_alu_op__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_alu0_alu_op__zero_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] alu_alu0_cr_a; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_alu0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_alu0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_alu0_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_alu0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_alu0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_alu0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_alu0_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] alu_alu0_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \alu_alu0_xer_ca$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] alu_alu0_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire alu_alu0_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \alu_alu0_xer_so$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [4:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [3:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [3:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [3:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [4:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [4:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [4:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] data_r1__cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] \data_r1__cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] data_r2__xer_ca = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] \data_r2__xer_ca$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r2__xer_ca_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r2__xer_ca_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] data_r3__xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] \data_r3__xer_ov$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__xer_ov_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r4__xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r4__xer_so$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r4__xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r4__xer_so_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] dest2_o; + reg [3:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest3_o; + reg [1:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest4_o; + reg [1:0] dest4_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output dest5_o; + reg dest5_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] oper_i_alu_alu0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_alu0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_alu0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_alu_alu0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_alu0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_alu0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [4:0] prev_wr_go = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [4:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [4:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [4:0] req_l_r_req = 5'h1f; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [4:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [4:0] req_l_s_req = 5'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [4:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [3:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [4:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input src3_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [1:0] src4_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [3:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [3:0] src_l_r_src = 4'hf; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [3:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [3:0] src_l_s_src = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [3:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] src_or_imm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] \src_or_imm$88 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg src_r2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [1:0] src_r3 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [1:0] \src_r3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire src_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire \src_sel$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + assign \$5 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ; + assign \$99 = alu_alu0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$101 = alu_alu0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$103 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$105 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_alu0_alu_op__zero_a; + assign \$107 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_alu0_alu_op__imm_data__ok; + assign \$109 = \$103 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 2'h3, \$107 , \$105 }; + assign \$111 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + assign \$113 = \$109 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$111 ; + assign \$115 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$117 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ; + assign \$119 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$121 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$123 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$125 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$115 , \$117 , \$119 , \$121 , \$123 }; + assign \$127 = \$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$129 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$131 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$133 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$135 = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$137 = cu_wr__go_i[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$15 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ; + assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$19 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ; + assign \$21 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$27 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ; + assign \$24 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; + assign \$31 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; + assign \$33 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$35 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ; + assign \$3 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_alu0_n_ready_i; + assign \$41 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ; + assign \$43 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$45 = \$43 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$47 = \$41 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ; + assign \$49 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$51 = \$49 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_alu0_n_ready_i; + assign \$53 = \$51 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_alu0_n_valid_o; + assign \$55 = \$53 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$57 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$59 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$61 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$63 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$65 = alu_alu0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$67 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$69 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$71 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$73 = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$75 = xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$77 = xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$79 = xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$81 = alu_alu0_alu_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[0]; + assign \$83 = alu_alu0_alu_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) 64'h0000000000000000 : src1_i; + assign \$86 = alu_alu0_alu_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1]; + assign \$8 = \$6 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$89 = alu_alu0_alu_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_alu0_alu_op__imm_data__data : src2_i; + assign \$91 = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r0; + assign \$93 = \src_sel$85 ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) \src_or_imm$88 : src_r1; + assign \$95 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$97 = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r3 <= \src_r3$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r4__xer_so <= \data_r4__xer_so$next ; + always @(posedge coresync_clk) + data_r4__xer_so_ok <= \data_r4__xer_so_ok$next ; + always @(posedge coresync_clk) + data_r3__xer_ov <= \data_r3__xer_ov$next ; + always @(posedge coresync_clk) + data_r3__xer_ov_ok <= \data_r3__xer_ov_ok$next ; + always @(posedge coresync_clk) + data_r2__xer_ca <= \data_r2__xer_ca$next ; + always @(posedge coresync_clk) + data_r2__xer_ca_ok <= \data_r2__xer_ca_ok$next ; + always @(posedge coresync_clk) + data_r1__cr_a <= \data_r1__cr_a$next ; + always @(posedge coresync_clk) + data_r1__cr_a_ok <= \data_r1__cr_a_ok$next ; + always @(posedge coresync_clk) + data_r0__o <= \data_r0__o$next ; + always @(posedge coresync_clk) + data_r0__o_ok <= \data_r0__o_ok$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__insn_type <= \alu_alu0_alu_op__insn_type$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__fn_unit <= \alu_alu0_alu_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__imm_data__data <= \alu_alu0_alu_op__imm_data__data$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__imm_data__ok <= \alu_alu0_alu_op__imm_data__ok$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__rc__rc <= \alu_alu0_alu_op__rc__rc$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__rc__ok <= \alu_alu0_alu_op__rc__ok$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__oe__oe <= \alu_alu0_alu_op__oe__oe$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__oe__ok <= \alu_alu0_alu_op__oe__ok$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__invert_in <= \alu_alu0_alu_op__invert_in$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__zero_a <= \alu_alu0_alu_op__zero_a$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__invert_out <= \alu_alu0_alu_op__invert_out$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__write_cr0 <= \alu_alu0_alu_op__write_cr0$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__input_carry <= \alu_alu0_alu_op__input_carry$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__output_carry <= \alu_alu0_alu_op__output_carry$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__is_32bit <= \alu_alu0_alu_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__is_signed <= \alu_alu0_alu_op__is_signed$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__data_len <= \alu_alu0_alu_op__data_len$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__insn <= \alu_alu0_alu_op__insn$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_alu0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$11 ; + alu_alu0 alu_alu0 ( + .alu_op__data_len(alu_alu0_alu_op__data_len), + .alu_op__fn_unit(alu_alu0_alu_op__fn_unit), + .alu_op__imm_data__data(alu_alu0_alu_op__imm_data__data), + .alu_op__imm_data__ok(alu_alu0_alu_op__imm_data__ok), + .alu_op__input_carry(alu_alu0_alu_op__input_carry), + .alu_op__insn(alu_alu0_alu_op__insn), + .alu_op__insn_type(alu_alu0_alu_op__insn_type), + .alu_op__invert_in(alu_alu0_alu_op__invert_in), + .alu_op__invert_out(alu_alu0_alu_op__invert_out), + .alu_op__is_32bit(alu_alu0_alu_op__is_32bit), + .alu_op__is_signed(alu_alu0_alu_op__is_signed), + .alu_op__oe__oe(alu_alu0_alu_op__oe__oe), + .alu_op__oe__ok(alu_alu0_alu_op__oe__ok), + .alu_op__output_carry(alu_alu0_alu_op__output_carry), + .alu_op__rc__ok(alu_alu0_alu_op__rc__ok), + .alu_op__rc__rc(alu_alu0_alu_op__rc__rc), + .alu_op__write_cr0(alu_alu0_alu_op__write_cr0), + .alu_op__zero_a(alu_alu0_alu_op__zero_a), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(alu_alu0_cr_a), + .cr_a_ok(cr_a_ok), + .n_ready_i(alu_alu0_n_ready_i), + .n_valid_o(alu_alu0_n_valid_o), + .o(alu_alu0_o), + .o_ok(o_ok), + .p_ready_o(alu_alu0_p_ready_o), + .p_valid_i(alu_alu0_p_valid_i), + .ra(alu_alu0_ra), + .rb(alu_alu0_rb), + .xer_ca(alu_alu0_xer_ca), + .\xer_ca$2 (\alu_alu0_xer_ca$2 ), + .xer_ca_ok(xer_ca_ok), + .xer_ov(alu_alu0_xer_ov), + .xer_ov_ok(xer_ov_ok), + .xer_so(alu_alu0_xer_so), + .\xer_so$1 (\alu_alu0_xer_so$1 ), + .xer_so_ok(xer_so_ok) + ); + alu_l alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + alui_l alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + opc_l opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + req_l req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + rok_l rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + rst_l rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + src_l src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$55 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$65 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 4'hf; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$67 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 5'h00; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$69 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 5'h1f; + endcase + end + always @* begin + if (\initial ) begin end + \alu_alu0_alu_op__insn_type$next = alu_alu0_alu_op__insn_type; + \alu_alu0_alu_op__fn_unit$next = alu_alu0_alu_op__fn_unit; + \alu_alu0_alu_op__imm_data__data$next = alu_alu0_alu_op__imm_data__data; + \alu_alu0_alu_op__imm_data__ok$next = alu_alu0_alu_op__imm_data__ok; + \alu_alu0_alu_op__rc__rc$next = alu_alu0_alu_op__rc__rc; + \alu_alu0_alu_op__rc__ok$next = alu_alu0_alu_op__rc__ok; + \alu_alu0_alu_op__oe__oe$next = alu_alu0_alu_op__oe__oe; + \alu_alu0_alu_op__oe__ok$next = alu_alu0_alu_op__oe__ok; + \alu_alu0_alu_op__invert_in$next = alu_alu0_alu_op__invert_in; + \alu_alu0_alu_op__zero_a$next = alu_alu0_alu_op__zero_a; + \alu_alu0_alu_op__invert_out$next = alu_alu0_alu_op__invert_out; + \alu_alu0_alu_op__write_cr0$next = alu_alu0_alu_op__write_cr0; + \alu_alu0_alu_op__input_carry$next = alu_alu0_alu_op__input_carry; + \alu_alu0_alu_op__output_carry$next = alu_alu0_alu_op__output_carry; + \alu_alu0_alu_op__is_32bit$next = alu_alu0_alu_op__is_32bit; + \alu_alu0_alu_op__is_signed$next = alu_alu0_alu_op__is_signed; + \alu_alu0_alu_op__data_len$next = alu_alu0_alu_op__data_len; + \alu_alu0_alu_op__insn$next = alu_alu0_alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_alu0_alu_op__insn$next , \alu_alu0_alu_op__data_len$next , \alu_alu0_alu_op__is_signed$next , \alu_alu0_alu_op__is_32bit$next , \alu_alu0_alu_op__output_carry$next , \alu_alu0_alu_op__input_carry$next , \alu_alu0_alu_op__write_cr0$next , \alu_alu0_alu_op__invert_out$next , \alu_alu0_alu_op__zero_a$next , \alu_alu0_alu_op__invert_in$next , \alu_alu0_alu_op__oe__ok$next , \alu_alu0_alu_op__oe__oe$next , \alu_alu0_alu_op__rc__ok$next , \alu_alu0_alu_op__rc__rc$next , \alu_alu0_alu_op__imm_data__ok$next , \alu_alu0_alu_op__imm_data__data$next , \alu_alu0_alu_op__fn_unit$next , \alu_alu0_alu_op__insn_type$next } = { oper_i_alu_alu0__insn, oper_i_alu_alu0__data_len, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__insn_type }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \alu_alu0_alu_op__imm_data__data$next = 64'h0000000000000000; + \alu_alu0_alu_op__imm_data__ok$next = 1'h0; + \alu_alu0_alu_op__rc__rc$next = 1'h0; + \alu_alu0_alu_op__rc__ok$next = 1'h0; + \alu_alu0_alu_op__oe__oe$next = 1'h0; + \alu_alu0_alu_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__o$next = data_r0__o; + \data_r0__o_ok$next = data_r0__o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = { o_ok, alu_alu0_o }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__cr_a$next = data_r1__cr_a; + \data_r1__cr_a_ok$next = data_r1__cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = { cr_a_ok, alu_alu0_cr_a }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r2__xer_ca$next = data_r2__xer_ca; + \data_r2__xer_ca_ok$next = data_r2__xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = { xer_ca_ok, alu_alu0_xer_ca }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r2__xer_ca_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r3__xer_ov$next = data_r3__xer_ov; + \data_r3__xer_ov_ok$next = data_r3__xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r3__xer_ov_ok$next , \data_r3__xer_ov$next } = { xer_ov_ok, alu_alu0_xer_ov }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r3__xer_ov_ok$next , \data_r3__xer_ov$next } = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r3__xer_ov_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r4__xer_so$next = data_r4__xer_so; + \data_r4__xer_so_ok$next = data_r4__xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r4__xer_so_ok$next , \data_r4__xer_so$next } = { xer_so_ok, alu_alu0_xer_so }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r4__xer_so_ok$next , \data_r4__xer_so$next } = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r4__xer_so_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_sel) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src_or_imm; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (\src_sel$85 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = \src_or_imm$88 ; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r3$next = src_r3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[3]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r3$next = src4_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$99 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$101 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$129 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__o; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$131 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__cr_a; + endcase + end + always @* begin + if (\initial ) begin end + dest3_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$133 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest3_o = data_r2__xer_ca; + endcase + end + always @* begin + if (\initial ) begin end + dest4_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$135 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest4_o = data_r3__xer_ov; + endcase + end + always @* begin + if (\initial ) begin end + dest5_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$137 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest5_o = data_r4__xer_so; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$21 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 5'h00; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$127 ; + assign cu_rd__rel_o = \$113 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_alu0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_alu0_p_valid_i = alui_l_q_alui; + assign \alu_alu0_xer_ca$2 = \$97 ; + assign \alu_alu0_xer_so$1 = \$95 ; + assign alu_alu0_rb = \$93 ; + assign alu_alu0_ra = \$91 ; + assign \src_or_imm$88 = \$89 ; + assign \src_sel$85 = \$86 ; + assign src_or_imm = \$83 ; + assign src_sel = \$81 ; + assign cu_wrmask_o = { \$79 , \$77 , \$75 , \$73 , \$71 }; + assign reset_r = \$63 ; + assign reset_w = \$61 ; + assign rst_r = \$59 ; + assign reset = \$57 ; + assign wr_any = \$37 ; + assign cu_done_o = \$31 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$19 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_alu0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$15 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0" *) +(* generator = "nMigen" *) +module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, cr_a, xer_ca, xer_ov, xer_so, ra, rb, \xer_so$1 , \xer_ca$2 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \alu_op__data_len$70 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \alu_op__fn_unit$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \alu_op__imm_data__data$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__imm_data__ok$57 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \alu_op__input_carry$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \alu_op__insn$71 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \alu_op__insn_type$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__invert_in$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__invert_out$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__is_32bit$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__is_signed$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__oe__oe$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__oe__ok$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__output_carry$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__rc__ok$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__rc__rc$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__write_cr0$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__zero_a$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$53 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] pipe1_alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \pipe1_alu_op__data_len$20 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe1_alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe1_alu_op__fn_unit$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe1_alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe1_alu_op__imm_data__data$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__imm_data__ok$7 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] pipe1_alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \pipe1_alu_op__input_carry$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe1_alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe1_alu_op__insn$21 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe1_alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe1_alu_op__insn_type$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__invert_in$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__invert_out$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__is_32bit$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__is_signed$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__oe__oe$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__oe__ok$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__output_carry$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__rc__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__rc__rc$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__write_cr0$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_alu_op__zero_a$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] pipe1_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe1_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe1_muxid$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe1_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe1_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe1_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe1_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] pipe1_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \pipe1_xer_ca$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] pipe1_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \pipe1_xer_so$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] pipe2_alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \pipe2_alu_op__data_len$41 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe2_alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe2_alu_op__fn_unit$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe2_alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe2_alu_op__imm_data__data$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__imm_data__ok$28 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] pipe2_alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \pipe2_alu_op__input_carry$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe2_alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe2_alu_op__insn$42 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe2_alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe2_alu_op__insn_type$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__invert_in$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__invert_out$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__is_32bit$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__is_signed$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__oe__oe$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__oe__ok$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__output_carry$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__rc__ok$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__rc__rc$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__write_cr0$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_alu_op__zero_a$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] pipe2_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \pipe2_cr_a$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_cr_a_ok$46 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe2_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe2_muxid$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe2_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe2_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \pipe2_o$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_o_ok$44 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe2_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe2_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] pipe2_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \pipe2_xer_ca$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_xer_ca_ok$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] pipe2_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \pipe2_xer_ov$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_xer_ov_ok$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_xer_so$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_xer_so_ok$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] \xer_ca$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + n n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + p p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + pipe1 pipe1 ( + .alu_op__data_len(pipe1_alu_op__data_len), + .\alu_op__data_len$18 (\pipe1_alu_op__data_len$20 ), + .alu_op__fn_unit(pipe1_alu_op__fn_unit), + .\alu_op__fn_unit$3 (\pipe1_alu_op__fn_unit$5 ), + .alu_op__imm_data__data(pipe1_alu_op__imm_data__data), + .\alu_op__imm_data__data$4 (\pipe1_alu_op__imm_data__data$6 ), + .alu_op__imm_data__ok(pipe1_alu_op__imm_data__ok), + .\alu_op__imm_data__ok$5 (\pipe1_alu_op__imm_data__ok$7 ), + .alu_op__input_carry(pipe1_alu_op__input_carry), + .\alu_op__input_carry$14 (\pipe1_alu_op__input_carry$16 ), + .alu_op__insn(pipe1_alu_op__insn), + .\alu_op__insn$19 (\pipe1_alu_op__insn$21 ), + .alu_op__insn_type(pipe1_alu_op__insn_type), + .\alu_op__insn_type$2 (\pipe1_alu_op__insn_type$4 ), + .alu_op__invert_in(pipe1_alu_op__invert_in), + .\alu_op__invert_in$10 (\pipe1_alu_op__invert_in$12 ), + .alu_op__invert_out(pipe1_alu_op__invert_out), + .\alu_op__invert_out$12 (\pipe1_alu_op__invert_out$14 ), + .alu_op__is_32bit(pipe1_alu_op__is_32bit), + .\alu_op__is_32bit$16 (\pipe1_alu_op__is_32bit$18 ), + .alu_op__is_signed(pipe1_alu_op__is_signed), + .\alu_op__is_signed$17 (\pipe1_alu_op__is_signed$19 ), + .alu_op__oe__oe(pipe1_alu_op__oe__oe), + .\alu_op__oe__oe$8 (\pipe1_alu_op__oe__oe$10 ), + .alu_op__oe__ok(pipe1_alu_op__oe__ok), + .\alu_op__oe__ok$9 (\pipe1_alu_op__oe__ok$11 ), + .alu_op__output_carry(pipe1_alu_op__output_carry), + .\alu_op__output_carry$15 (\pipe1_alu_op__output_carry$17 ), + .alu_op__rc__ok(pipe1_alu_op__rc__ok), + .\alu_op__rc__ok$7 (\pipe1_alu_op__rc__ok$9 ), + .alu_op__rc__rc(pipe1_alu_op__rc__rc), + .\alu_op__rc__rc$6 (\pipe1_alu_op__rc__rc$8 ), + .alu_op__write_cr0(pipe1_alu_op__write_cr0), + .\alu_op__write_cr0$13 (\pipe1_alu_op__write_cr0$15 ), + .alu_op__zero_a(pipe1_alu_op__zero_a), + .\alu_op__zero_a$11 (\pipe1_alu_op__zero_a$13 ), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(pipe1_cr_a), + .cr_a_ok(pipe1_cr_a_ok), + .muxid(pipe1_muxid), + .\muxid$1 (\pipe1_muxid$3 ), + .n_ready_i(pipe1_n_ready_i), + .n_valid_o(pipe1_n_valid_o), + .o(pipe1_o), + .o_ok(pipe1_o_ok), + .p_ready_o(pipe1_p_ready_o), + .p_valid_i(pipe1_p_valid_i), + .ra(pipe1_ra), + .rb(pipe1_rb), + .xer_ca(pipe1_xer_ca), + .\xer_ca$21 (\pipe1_xer_ca$23 ), + .xer_ca_ok(pipe1_xer_ca_ok), + .xer_ov(pipe1_xer_ov), + .xer_ov_ok(pipe1_xer_ov_ok), + .xer_so(pipe1_xer_so), + .\xer_so$20 (\pipe1_xer_so$22 ), + .xer_so_ok(pipe1_xer_so_ok) + ); + pipe2 pipe2 ( + .alu_op__data_len(pipe2_alu_op__data_len), + .\alu_op__data_len$18 (\pipe2_alu_op__data_len$41 ), + .alu_op__fn_unit(pipe2_alu_op__fn_unit), + .\alu_op__fn_unit$3 (\pipe2_alu_op__fn_unit$26 ), + .alu_op__imm_data__data(pipe2_alu_op__imm_data__data), + .\alu_op__imm_data__data$4 (\pipe2_alu_op__imm_data__data$27 ), + .alu_op__imm_data__ok(pipe2_alu_op__imm_data__ok), + .\alu_op__imm_data__ok$5 (\pipe2_alu_op__imm_data__ok$28 ), + .alu_op__input_carry(pipe2_alu_op__input_carry), + .\alu_op__input_carry$14 (\pipe2_alu_op__input_carry$37 ), + .alu_op__insn(pipe2_alu_op__insn), + .\alu_op__insn$19 (\pipe2_alu_op__insn$42 ), + .alu_op__insn_type(pipe2_alu_op__insn_type), + .\alu_op__insn_type$2 (\pipe2_alu_op__insn_type$25 ), + .alu_op__invert_in(pipe2_alu_op__invert_in), + .\alu_op__invert_in$10 (\pipe2_alu_op__invert_in$33 ), + .alu_op__invert_out(pipe2_alu_op__invert_out), + .\alu_op__invert_out$12 (\pipe2_alu_op__invert_out$35 ), + .alu_op__is_32bit(pipe2_alu_op__is_32bit), + .\alu_op__is_32bit$16 (\pipe2_alu_op__is_32bit$39 ), + .alu_op__is_signed(pipe2_alu_op__is_signed), + .\alu_op__is_signed$17 (\pipe2_alu_op__is_signed$40 ), + .alu_op__oe__oe(pipe2_alu_op__oe__oe), + .\alu_op__oe__oe$8 (\pipe2_alu_op__oe__oe$31 ), + .alu_op__oe__ok(pipe2_alu_op__oe__ok), + .\alu_op__oe__ok$9 (\pipe2_alu_op__oe__ok$32 ), + .alu_op__output_carry(pipe2_alu_op__output_carry), + .\alu_op__output_carry$15 (\pipe2_alu_op__output_carry$38 ), + .alu_op__rc__ok(pipe2_alu_op__rc__ok), + .\alu_op__rc__ok$7 (\pipe2_alu_op__rc__ok$30 ), + .alu_op__rc__rc(pipe2_alu_op__rc__rc), + .\alu_op__rc__rc$6 (\pipe2_alu_op__rc__rc$29 ), + .alu_op__write_cr0(pipe2_alu_op__write_cr0), + .\alu_op__write_cr0$13 (\pipe2_alu_op__write_cr0$36 ), + .alu_op__zero_a(pipe2_alu_op__zero_a), + .\alu_op__zero_a$11 (\pipe2_alu_op__zero_a$34 ), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(pipe2_cr_a), + .\cr_a$22 (\pipe2_cr_a$45 ), + .cr_a_ok(pipe2_cr_a_ok), + .\cr_a_ok$23 (\pipe2_cr_a_ok$46 ), + .muxid(pipe2_muxid), + .\muxid$1 (\pipe2_muxid$24 ), + .n_ready_i(pipe2_n_ready_i), + .n_valid_o(pipe2_n_valid_o), + .o(pipe2_o), + .\o$20 (\pipe2_o$43 ), + .o_ok(pipe2_o_ok), + .\o_ok$21 (\pipe2_o_ok$44 ), + .p_ready_o(pipe2_p_ready_o), + .p_valid_i(pipe2_p_valid_i), + .xer_ca(pipe2_xer_ca), + .\xer_ca$24 (\pipe2_xer_ca$47 ), + .xer_ca_ok(pipe2_xer_ca_ok), + .\xer_ca_ok$25 (\pipe2_xer_ca_ok$48 ), + .xer_ov(pipe2_xer_ov), + .\xer_ov$26 (\pipe2_xer_ov$49 ), + .xer_ov_ok(pipe2_xer_ov_ok), + .\xer_ov_ok$27 (\pipe2_xer_ov_ok$50 ), + .xer_so(pipe2_xer_so), + .\xer_so$28 (\pipe2_xer_so$51 ), + .xer_so_ok(pipe2_xer_so_ok), + .\xer_so_ok$29 (\pipe2_xer_so_ok$52 ) + ); + assign muxid = 2'h0; + assign { xer_so_ok, xer_so } = { \pipe2_xer_so_ok$52 , \pipe2_xer_so$51 }; + assign { xer_ov_ok, xer_ov } = { \pipe2_xer_ov_ok$50 , \pipe2_xer_ov$49 }; + assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$48 , \pipe2_xer_ca$47 }; + assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$46 , \pipe2_cr_a$45 }; + assign { o_ok, o } = { \pipe2_o_ok$44 , \pipe2_o$43 }; + assign { \alu_op__insn$71 , \alu_op__data_len$70 , \alu_op__is_signed$69 , \alu_op__is_32bit$68 , \alu_op__output_carry$67 , \alu_op__input_carry$66 , \alu_op__write_cr0$65 , \alu_op__invert_out$64 , \alu_op__zero_a$63 , \alu_op__invert_in$62 , \alu_op__oe__ok$61 , \alu_op__oe__oe$60 , \alu_op__rc__ok$59 , \alu_op__rc__rc$58 , \alu_op__imm_data__ok$57 , \alu_op__imm_data__data$56 , \alu_op__fn_unit$55 , \alu_op__insn_type$54 } = { \pipe2_alu_op__insn$42 , \pipe2_alu_op__data_len$41 , \pipe2_alu_op__is_signed$40 , \pipe2_alu_op__is_32bit$39 , \pipe2_alu_op__output_carry$38 , \pipe2_alu_op__input_carry$37 , \pipe2_alu_op__write_cr0$36 , \pipe2_alu_op__invert_out$35 , \pipe2_alu_op__zero_a$34 , \pipe2_alu_op__invert_in$33 , \pipe2_alu_op__oe__ok$32 , \pipe2_alu_op__oe__oe$31 , \pipe2_alu_op__rc__ok$30 , \pipe2_alu_op__rc__rc$29 , \pipe2_alu_op__imm_data__ok$28 , \pipe2_alu_op__imm_data__data$27 , \pipe2_alu_op__fn_unit$26 , \pipe2_alu_op__insn_type$25 }; + assign \muxid$53 = \pipe2_muxid$24 ; + assign pipe2_n_ready_i = n_ready_i; + assign n_valid_o = pipe2_n_valid_o; + assign \pipe1_xer_ca$23 = \xer_ca$2 ; + assign \pipe1_xer_so$22 = \xer_so$1 ; + assign pipe1_rb = rb; + assign pipe1_ra = ra; + assign { \pipe1_alu_op__insn$21 , \pipe1_alu_op__data_len$20 , \pipe1_alu_op__is_signed$19 , \pipe1_alu_op__is_32bit$18 , \pipe1_alu_op__output_carry$17 , \pipe1_alu_op__input_carry$16 , \pipe1_alu_op__write_cr0$15 , \pipe1_alu_op__invert_out$14 , \pipe1_alu_op__zero_a$13 , \pipe1_alu_op__invert_in$12 , \pipe1_alu_op__oe__ok$11 , \pipe1_alu_op__oe__oe$10 , \pipe1_alu_op__rc__ok$9 , \pipe1_alu_op__rc__rc$8 , \pipe1_alu_op__imm_data__ok$7 , \pipe1_alu_op__imm_data__data$6 , \pipe1_alu_op__fn_unit$5 , \pipe1_alu_op__insn_type$4 } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign \pipe1_muxid$3 = 2'h0; + assign p_ready_o = pipe1_p_ready_o; + assign pipe1_p_valid_i = p_valid_i; + assign { pipe2_xer_so_ok, pipe2_xer_so } = { pipe1_xer_so_ok, pipe1_xer_so }; + assign { pipe2_xer_ov_ok, pipe2_xer_ov } = { pipe1_xer_ov_ok, pipe1_xer_ov }; + assign { pipe2_xer_ca_ok, pipe2_xer_ca } = { pipe1_xer_ca_ok, pipe1_xer_ca }; + assign { pipe2_cr_a_ok, pipe2_cr_a } = { pipe1_cr_a_ok, pipe1_cr_a }; + assign { pipe2_o_ok, pipe2_o } = { pipe1_o_ok, pipe1_o }; + assign { pipe2_alu_op__insn, pipe2_alu_op__data_len, pipe2_alu_op__is_signed, pipe2_alu_op__is_32bit, pipe2_alu_op__output_carry, pipe2_alu_op__input_carry, pipe2_alu_op__write_cr0, pipe2_alu_op__invert_out, pipe2_alu_op__zero_a, pipe2_alu_op__invert_in, pipe2_alu_op__oe__ok, pipe2_alu_op__oe__oe, pipe2_alu_op__rc__ok, pipe2_alu_op__rc__rc, pipe2_alu_op__imm_data__ok, pipe2_alu_op__imm_data__data, pipe2_alu_op__fn_unit, pipe2_alu_op__insn_type } = { pipe1_alu_op__insn, pipe1_alu_op__data_len, pipe1_alu_op__is_signed, pipe1_alu_op__is_32bit, pipe1_alu_op__output_carry, pipe1_alu_op__input_carry, pipe1_alu_op__write_cr0, pipe1_alu_op__invert_out, pipe1_alu_op__zero_a, pipe1_alu_op__invert_in, pipe1_alu_op__oe__ok, pipe1_alu_op__oe__oe, pipe1_alu_op__rc__ok, pipe1_alu_op__rc__rc, pipe1_alu_op__imm_data__ok, pipe1_alu_op__imm_data__data, pipe1_alu_op__fn_unit, pipe1_alu_op__insn_type }; + assign pipe2_muxid = pipe1_muxid; + assign pipe1_n_ready_i = pipe2_p_ready_o; + assign pipe2_p_valid_i = pipe1_n_valid_o; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0" *) +(* generator = "nMigen" *) +module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_i, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, nia, \fast1$1 , \fast2$2 , cr_a, p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] br_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \br_op__cia$15 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] br_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \br_op__fn_unit$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] br_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \br_op__imm_data__data$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \br_op__imm_data__ok$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] br_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \br_op__insn$18 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] br_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \br_op__insn_type$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \br_op__is_32bit$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \br_op__lk$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \fast1$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \fast2$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$14 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe_br_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe_br_op__cia$4 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe_br_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe_br_op__fn_unit$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe_br_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe_br_op__imm_data__data$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_br_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_br_op__imm_data__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe_br_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe_br_op__insn$7 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe_br_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe_br_op__insn_type$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_br_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_br_op__is_32bit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_br_op__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_br_op__lk$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] pipe_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \pipe_fast1$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \pipe_fast2$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_fast2_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe_muxid$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe_nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_nia_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe_p_valid_i; + \n$18 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$17 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + \pipe$19 pipe ( + .br_op__cia(pipe_br_op__cia), + .\br_op__cia$2 (\pipe_br_op__cia$4 ), + .br_op__fn_unit(pipe_br_op__fn_unit), + .\br_op__fn_unit$4 (\pipe_br_op__fn_unit$6 ), + .br_op__imm_data__data(pipe_br_op__imm_data__data), + .\br_op__imm_data__data$6 (\pipe_br_op__imm_data__data$8 ), + .br_op__imm_data__ok(pipe_br_op__imm_data__ok), + .\br_op__imm_data__ok$7 (\pipe_br_op__imm_data__ok$9 ), + .br_op__insn(pipe_br_op__insn), + .\br_op__insn$5 (\pipe_br_op__insn$7 ), + .br_op__insn_type(pipe_br_op__insn_type), + .\br_op__insn_type$3 (\pipe_br_op__insn_type$5 ), + .br_op__is_32bit(pipe_br_op__is_32bit), + .\br_op__is_32bit$9 (\pipe_br_op__is_32bit$11 ), + .br_op__lk(pipe_br_op__lk), + .\br_op__lk$8 (\pipe_br_op__lk$10 ), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(pipe_cr_a), + .fast1(pipe_fast1), + .\fast1$10 (\pipe_fast1$12 ), + .fast1_ok(pipe_fast1_ok), + .fast2(pipe_fast2), + .\fast2$11 (\pipe_fast2$13 ), + .fast2_ok(pipe_fast2_ok), + .muxid(pipe_muxid), + .\muxid$1 (\pipe_muxid$3 ), + .n_ready_i(pipe_n_ready_i), + .n_valid_o(pipe_n_valid_o), + .nia(pipe_nia), + .nia_ok(pipe_nia_ok), + .p_ready_o(pipe_p_ready_o), + .p_valid_i(pipe_p_valid_i) + ); + assign muxid = 2'h0; + assign { nia_ok, nia } = { pipe_nia_ok, pipe_nia }; + assign { fast2_ok, fast2 } = { pipe_fast2_ok, \pipe_fast2$13 }; + assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$12 }; + assign { \br_op__is_32bit$22 , \br_op__lk$21 , \br_op__imm_data__ok$20 , \br_op__imm_data__data$19 , \br_op__insn$18 , \br_op__fn_unit$17 , \br_op__insn_type$16 , \br_op__cia$15 } = { \pipe_br_op__is_32bit$11 , \pipe_br_op__lk$10 , \pipe_br_op__imm_data__ok$9 , \pipe_br_op__imm_data__data$8 , \pipe_br_op__insn$7 , \pipe_br_op__fn_unit$6 , \pipe_br_op__insn_type$5 , \pipe_br_op__cia$4 }; + assign \muxid$14 = \pipe_muxid$3 ; + assign pipe_n_ready_i = n_ready_i; + assign n_valid_o = pipe_n_valid_o; + assign pipe_cr_a = cr_a; + assign pipe_fast2 = \fast2$2 ; + assign pipe_fast1 = \fast1$1 ; + assign { pipe_br_op__is_32bit, pipe_br_op__lk, pipe_br_op__imm_data__ok, pipe_br_op__imm_data__data, pipe_br_op__insn, pipe_br_op__fn_unit, pipe_br_op__insn_type, pipe_br_op__cia } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; + assign pipe_muxid = 2'h0; + assign p_ready_o = pipe_p_ready_o; + assign pipe_p_valid_i = p_valid_i; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0" *) +(* generator = "nMigen" *) +module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] \cr_a$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_c; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] cr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \cr_op__fn_unit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] cr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \cr_op__insn$12 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] cr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \cr_op__insn_type$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [31:0] full_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [31:0] \full_cr$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output full_cr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$9 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] pipe_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \pipe_cr_a$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] pipe_cr_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] pipe_cr_c; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe_cr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe_cr_op__fn_unit$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe_cr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe_cr_op__insn$6 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe_cr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe_cr_op__insn_type$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [31:0] pipe_full_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [31:0] \pipe_full_cr$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_full_cr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe_muxid$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + \n$6 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$5 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + pipe pipe ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(pipe_cr_a), + .\cr_a$6 (\pipe_cr_a$8 ), + .cr_a_ok(pipe_cr_a_ok), + .cr_b(pipe_cr_b), + .cr_c(pipe_cr_c), + .cr_op__fn_unit(pipe_cr_op__fn_unit), + .\cr_op__fn_unit$3 (\pipe_cr_op__fn_unit$5 ), + .cr_op__insn(pipe_cr_op__insn), + .\cr_op__insn$4 (\pipe_cr_op__insn$6 ), + .cr_op__insn_type(pipe_cr_op__insn_type), + .\cr_op__insn_type$2 (\pipe_cr_op__insn_type$4 ), + .full_cr(pipe_full_cr), + .\full_cr$5 (\pipe_full_cr$7 ), + .full_cr_ok(pipe_full_cr_ok), + .muxid(pipe_muxid), + .\muxid$1 (\pipe_muxid$3 ), + .n_ready_i(pipe_n_ready_i), + .n_valid_o(pipe_n_valid_o), + .o(pipe_o), + .o_ok(pipe_o_ok), + .p_ready_o(pipe_p_ready_o), + .p_valid_i(pipe_p_valid_i), + .ra(pipe_ra), + .rb(pipe_rb) + ); + assign muxid = 2'h0; + assign { cr_a_ok, cr_a } = { pipe_cr_a_ok, \pipe_cr_a$8 }; + assign { full_cr_ok, full_cr } = { pipe_full_cr_ok, \pipe_full_cr$7 }; + assign { o_ok, o } = { pipe_o_ok, pipe_o }; + assign { \cr_op__insn$12 , \cr_op__fn_unit$11 , \cr_op__insn_type$10 } = { \pipe_cr_op__insn$6 , \pipe_cr_op__fn_unit$5 , \pipe_cr_op__insn_type$4 }; + assign \muxid$9 = \pipe_muxid$3 ; + assign pipe_n_ready_i = n_ready_i; + assign n_valid_o = pipe_n_valid_o; + assign pipe_cr_c = cr_c; + assign pipe_cr_b = cr_b; + assign pipe_cr_a = \cr_a$2 ; + assign pipe_full_cr = \full_cr$1 ; + assign pipe_rb = rb; + assign pipe_ra = ra; + assign { pipe_cr_op__insn, pipe_cr_op__fn_unit, pipe_cr_op__insn_type } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; + assign pipe_muxid = 2'h0; + assign p_ready_o = pipe_p_ready_o; + assign pipe_p_valid_i = p_valid_i; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0" *) +(* generator = "nMigen" *) +module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \logical_op__data_len$88 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \logical_op__fn_unit$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \logical_op__imm_data__data$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__imm_data__ok$75 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \logical_op__input_carry$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \logical_op__insn$89 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \logical_op__insn_type$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_in$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_out$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_32bit$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_signed$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__oe$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__ok$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__output_carry$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__ok$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__rc$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__write_cr0$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__zero_a$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$71 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] pipe_end_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_end_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + wire pipe_end_div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + wire pipe_end_dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + wire pipe_end_dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + wire pipe_end_dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + wire pipe_end_divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] pipe_end_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \pipe_end_logical_op__data_len$68 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe_end_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe_end_logical_op__fn_unit$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe_end_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe_end_logical_op__imm_data__data$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__imm_data__ok$55 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] pipe_end_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \pipe_end_logical_op__input_carry$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe_end_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe_end_logical_op__insn$69 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe_end_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe_end_logical_op__insn_type$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__invert_in$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__invert_out$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__is_32bit$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__is_signed$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__oe__oe$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__oe__ok$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__output_carry$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__rc__ok$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__rc__rc$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__write_cr0$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_end_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_end_logical_op__zero_a$61 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe_end_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe_end_muxid$51 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe_end_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe_end_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe_end_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_end_o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe_end_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe_end_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) + wire [63:0] pipe_end_quotient_root; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_end_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_end_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) + wire [191:0] pipe_end_remainder; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] pipe_end_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_end_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire pipe_end_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe_end_xer_so$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_end_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + wire pipe_middle_0_div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + wire \pipe_middle_0_div_by_zero$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + wire pipe_middle_0_dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + wire \pipe_middle_0_dive_abs_ov32$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + wire pipe_middle_0_dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + wire \pipe_middle_0_dive_abs_ov64$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + wire [127:0] pipe_middle_0_dividend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + wire pipe_middle_0_dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + wire \pipe_middle_0_dividend_neg$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + wire pipe_middle_0_divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + wire \pipe_middle_0_divisor_neg$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + wire [63:0] pipe_middle_0_divisor_radicand; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] pipe_middle_0_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \pipe_middle_0_logical_op__data_len$41 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe_middle_0_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe_middle_0_logical_op__fn_unit$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe_middle_0_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe_middle_0_logical_op__imm_data__data$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__imm_data__ok$28 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] pipe_middle_0_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \pipe_middle_0_logical_op__input_carry$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe_middle_0_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe_middle_0_logical_op__insn$42 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe_middle_0_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe_middle_0_logical_op__insn_type$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__invert_in$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__invert_out$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__is_32bit$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__is_signed$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__oe__oe$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__oe__ok$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__output_carry$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__rc__ok$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__rc__rc$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__write_cr0$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_middle_0_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_middle_0_logical_op__zero_a$34 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe_middle_0_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe_middle_0_muxid$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe_middle_0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe_middle_0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + wire [1:0] pipe_middle_0_operation; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe_middle_0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe_middle_0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) + wire [63:0] pipe_middle_0_quotient_root; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_middle_0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \pipe_middle_0_ra$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_middle_0_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \pipe_middle_0_rb$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) + wire [191:0] pipe_middle_0_remainder; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire pipe_middle_0_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \pipe_middle_0_xer_so$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + wire pipe_start_div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + wire pipe_start_dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + wire pipe_start_dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + wire [127:0] pipe_start_dividend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + wire pipe_start_dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + wire pipe_start_divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + wire [63:0] pipe_start_divisor_radicand; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] pipe_start_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \pipe_start_logical_op__data_len$19 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe_start_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe_start_logical_op__fn_unit$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe_start_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe_start_logical_op__imm_data__data$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__imm_data__ok$6 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] pipe_start_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \pipe_start_logical_op__input_carry$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe_start_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe_start_logical_op__insn$20 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe_start_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe_start_logical_op__insn_type$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__invert_in$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__invert_out$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__is_32bit$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__is_signed$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__oe__oe$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__oe__ok$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__output_carry$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__rc__ok$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__rc__rc$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__write_cr0$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_start_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_start_logical_op__zero_a$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe_start_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe_start_muxid$2 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe_start_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe_start_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + wire [1:0] pipe_start_operation; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe_start_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe_start_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_start_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \pipe_start_ra$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_start_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \pipe_start_rb$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire pipe_start_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \pipe_start_xer_so$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + \n$75 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$74 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + pipe_end pipe_end ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(pipe_end_cr_a), + .cr_a_ok(pipe_end_cr_a_ok), + .div_by_zero(pipe_end_div_by_zero), + .dive_abs_ov32(pipe_end_dive_abs_ov32), + .dive_abs_ov64(pipe_end_dive_abs_ov64), + .dividend_neg(pipe_end_dividend_neg), + .divisor_neg(pipe_end_divisor_neg), + .logical_op__data_len(pipe_end_logical_op__data_len), + .\logical_op__data_len$18 (\pipe_end_logical_op__data_len$68 ), + .logical_op__fn_unit(pipe_end_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\pipe_end_logical_op__fn_unit$53 ), + .logical_op__imm_data__data(pipe_end_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\pipe_end_logical_op__imm_data__data$54 ), + .logical_op__imm_data__ok(pipe_end_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\pipe_end_logical_op__imm_data__ok$55 ), + .logical_op__input_carry(pipe_end_logical_op__input_carry), + .\logical_op__input_carry$12 (\pipe_end_logical_op__input_carry$62 ), + .logical_op__insn(pipe_end_logical_op__insn), + .\logical_op__insn$19 (\pipe_end_logical_op__insn$69 ), + .logical_op__insn_type(pipe_end_logical_op__insn_type), + .\logical_op__insn_type$2 (\pipe_end_logical_op__insn_type$52 ), + .logical_op__invert_in(pipe_end_logical_op__invert_in), + .\logical_op__invert_in$10 (\pipe_end_logical_op__invert_in$60 ), + .logical_op__invert_out(pipe_end_logical_op__invert_out), + .\logical_op__invert_out$13 (\pipe_end_logical_op__invert_out$63 ), + .logical_op__is_32bit(pipe_end_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\pipe_end_logical_op__is_32bit$66 ), + .logical_op__is_signed(pipe_end_logical_op__is_signed), + .\logical_op__is_signed$17 (\pipe_end_logical_op__is_signed$67 ), + .logical_op__oe__oe(pipe_end_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\pipe_end_logical_op__oe__oe$58 ), + .logical_op__oe__ok(pipe_end_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\pipe_end_logical_op__oe__ok$59 ), + .logical_op__output_carry(pipe_end_logical_op__output_carry), + .\logical_op__output_carry$15 (\pipe_end_logical_op__output_carry$65 ), + .logical_op__rc__ok(pipe_end_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\pipe_end_logical_op__rc__ok$57 ), + .logical_op__rc__rc(pipe_end_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\pipe_end_logical_op__rc__rc$56 ), + .logical_op__write_cr0(pipe_end_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\pipe_end_logical_op__write_cr0$64 ), + .logical_op__zero_a(pipe_end_logical_op__zero_a), + .\logical_op__zero_a$11 (\pipe_end_logical_op__zero_a$61 ), + .muxid(pipe_end_muxid), + .\muxid$1 (\pipe_end_muxid$51 ), + .n_ready_i(pipe_end_n_ready_i), + .n_valid_o(pipe_end_n_valid_o), + .o(pipe_end_o), + .o_ok(pipe_end_o_ok), + .p_ready_o(pipe_end_p_ready_o), + .p_valid_i(pipe_end_p_valid_i), + .quotient_root(pipe_end_quotient_root), + .ra(pipe_end_ra), + .rb(pipe_end_rb), + .remainder(pipe_end_remainder), + .xer_ov(pipe_end_xer_ov), + .xer_ov_ok(pipe_end_xer_ov_ok), + .xer_so(pipe_end_xer_so), + .\xer_so$20 (\pipe_end_xer_so$70 ), + .xer_so_ok(pipe_end_xer_so_ok) + ); + pipe_middle_0 pipe_middle_0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .div_by_zero(pipe_middle_0_div_by_zero), + .\div_by_zero$27 (\pipe_middle_0_div_by_zero$50 ), + .dive_abs_ov32(pipe_middle_0_dive_abs_ov32), + .\dive_abs_ov32$25 (\pipe_middle_0_dive_abs_ov32$48 ), + .dive_abs_ov64(pipe_middle_0_dive_abs_ov64), + .\dive_abs_ov64$26 (\pipe_middle_0_dive_abs_ov64$49 ), + .dividend(pipe_middle_0_dividend), + .dividend_neg(pipe_middle_0_dividend_neg), + .\dividend_neg$24 (\pipe_middle_0_dividend_neg$47 ), + .divisor_neg(pipe_middle_0_divisor_neg), + .\divisor_neg$23 (\pipe_middle_0_divisor_neg$46 ), + .divisor_radicand(pipe_middle_0_divisor_radicand), + .logical_op__data_len(pipe_middle_0_logical_op__data_len), + .\logical_op__data_len$18 (\pipe_middle_0_logical_op__data_len$41 ), + .logical_op__fn_unit(pipe_middle_0_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\pipe_middle_0_logical_op__fn_unit$26 ), + .logical_op__imm_data__data(pipe_middle_0_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\pipe_middle_0_logical_op__imm_data__data$27 ), + .logical_op__imm_data__ok(pipe_middle_0_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\pipe_middle_0_logical_op__imm_data__ok$28 ), + .logical_op__input_carry(pipe_middle_0_logical_op__input_carry), + .\logical_op__input_carry$12 (\pipe_middle_0_logical_op__input_carry$35 ), + .logical_op__insn(pipe_middle_0_logical_op__insn), + .\logical_op__insn$19 (\pipe_middle_0_logical_op__insn$42 ), + .logical_op__insn_type(pipe_middle_0_logical_op__insn_type), + .\logical_op__insn_type$2 (\pipe_middle_0_logical_op__insn_type$25 ), + .logical_op__invert_in(pipe_middle_0_logical_op__invert_in), + .\logical_op__invert_in$10 (\pipe_middle_0_logical_op__invert_in$33 ), + .logical_op__invert_out(pipe_middle_0_logical_op__invert_out), + .\logical_op__invert_out$13 (\pipe_middle_0_logical_op__invert_out$36 ), + .logical_op__is_32bit(pipe_middle_0_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\pipe_middle_0_logical_op__is_32bit$39 ), + .logical_op__is_signed(pipe_middle_0_logical_op__is_signed), + .\logical_op__is_signed$17 (\pipe_middle_0_logical_op__is_signed$40 ), + .logical_op__oe__oe(pipe_middle_0_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\pipe_middle_0_logical_op__oe__oe$31 ), + .logical_op__oe__ok(pipe_middle_0_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\pipe_middle_0_logical_op__oe__ok$32 ), + .logical_op__output_carry(pipe_middle_0_logical_op__output_carry), + .\logical_op__output_carry$15 (\pipe_middle_0_logical_op__output_carry$38 ), + .logical_op__rc__ok(pipe_middle_0_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\pipe_middle_0_logical_op__rc__ok$30 ), + .logical_op__rc__rc(pipe_middle_0_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\pipe_middle_0_logical_op__rc__rc$29 ), + .logical_op__write_cr0(pipe_middle_0_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\pipe_middle_0_logical_op__write_cr0$37 ), + .logical_op__zero_a(pipe_middle_0_logical_op__zero_a), + .\logical_op__zero_a$11 (\pipe_middle_0_logical_op__zero_a$34 ), + .muxid(pipe_middle_0_muxid), + .\muxid$1 (\pipe_middle_0_muxid$24 ), + .n_ready_i(pipe_middle_0_n_ready_i), + .n_valid_o(pipe_middle_0_n_valid_o), + .operation(pipe_middle_0_operation), + .p_ready_o(pipe_middle_0_p_ready_o), + .p_valid_i(pipe_middle_0_p_valid_i), + .quotient_root(pipe_middle_0_quotient_root), + .ra(pipe_middle_0_ra), + .\ra$20 (\pipe_middle_0_ra$43 ), + .rb(pipe_middle_0_rb), + .\rb$21 (\pipe_middle_0_rb$44 ), + .remainder(pipe_middle_0_remainder), + .xer_so(pipe_middle_0_xer_so), + .\xer_so$22 (\pipe_middle_0_xer_so$45 ) + ); + pipe_start pipe_start ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .div_by_zero(pipe_start_div_by_zero), + .dive_abs_ov32(pipe_start_dive_abs_ov32), + .dive_abs_ov64(pipe_start_dive_abs_ov64), + .dividend(pipe_start_dividend), + .dividend_neg(pipe_start_dividend_neg), + .divisor_neg(pipe_start_divisor_neg), + .divisor_radicand(pipe_start_divisor_radicand), + .logical_op__data_len(pipe_start_logical_op__data_len), + .\logical_op__data_len$18 (\pipe_start_logical_op__data_len$19 ), + .logical_op__fn_unit(pipe_start_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\pipe_start_logical_op__fn_unit$4 ), + .logical_op__imm_data__data(pipe_start_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\pipe_start_logical_op__imm_data__data$5 ), + .logical_op__imm_data__ok(pipe_start_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\pipe_start_logical_op__imm_data__ok$6 ), + .logical_op__input_carry(pipe_start_logical_op__input_carry), + .\logical_op__input_carry$12 (\pipe_start_logical_op__input_carry$13 ), + .logical_op__insn(pipe_start_logical_op__insn), + .\logical_op__insn$19 (\pipe_start_logical_op__insn$20 ), + .logical_op__insn_type(pipe_start_logical_op__insn_type), + .\logical_op__insn_type$2 (\pipe_start_logical_op__insn_type$3 ), + .logical_op__invert_in(pipe_start_logical_op__invert_in), + .\logical_op__invert_in$10 (\pipe_start_logical_op__invert_in$11 ), + .logical_op__invert_out(pipe_start_logical_op__invert_out), + .\logical_op__invert_out$13 (\pipe_start_logical_op__invert_out$14 ), + .logical_op__is_32bit(pipe_start_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\pipe_start_logical_op__is_32bit$17 ), + .logical_op__is_signed(pipe_start_logical_op__is_signed), + .\logical_op__is_signed$17 (\pipe_start_logical_op__is_signed$18 ), + .logical_op__oe__oe(pipe_start_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\pipe_start_logical_op__oe__oe$9 ), + .logical_op__oe__ok(pipe_start_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\pipe_start_logical_op__oe__ok$10 ), + .logical_op__output_carry(pipe_start_logical_op__output_carry), + .\logical_op__output_carry$15 (\pipe_start_logical_op__output_carry$16 ), + .logical_op__rc__ok(pipe_start_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\pipe_start_logical_op__rc__ok$8 ), + .logical_op__rc__rc(pipe_start_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\pipe_start_logical_op__rc__rc$7 ), + .logical_op__write_cr0(pipe_start_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\pipe_start_logical_op__write_cr0$15 ), + .logical_op__zero_a(pipe_start_logical_op__zero_a), + .\logical_op__zero_a$11 (\pipe_start_logical_op__zero_a$12 ), + .muxid(pipe_start_muxid), + .\muxid$1 (\pipe_start_muxid$2 ), + .n_ready_i(pipe_start_n_ready_i), + .n_valid_o(pipe_start_n_valid_o), + .operation(pipe_start_operation), + .p_ready_o(pipe_start_p_ready_o), + .p_valid_i(pipe_start_p_valid_i), + .ra(pipe_start_ra), + .\ra$20 (\pipe_start_ra$21 ), + .rb(pipe_start_rb), + .\rb$21 (\pipe_start_rb$22 ), + .xer_so(pipe_start_xer_so), + .\xer_so$22 (\pipe_start_xer_so$23 ) + ); + assign muxid = 2'h0; + assign { xer_so_ok, xer_so } = { pipe_end_xer_so_ok, \pipe_end_xer_so$70 }; + assign { xer_ov_ok, xer_ov } = { pipe_end_xer_ov_ok, pipe_end_xer_ov }; + assign { cr_a_ok, cr_a } = { pipe_end_cr_a_ok, pipe_end_cr_a }; + assign { o_ok, o } = { pipe_end_o_ok, pipe_end_o }; + assign { \logical_op__insn$89 , \logical_op__data_len$88 , \logical_op__is_signed$87 , \logical_op__is_32bit$86 , \logical_op__output_carry$85 , \logical_op__write_cr0$84 , \logical_op__invert_out$83 , \logical_op__input_carry$82 , \logical_op__zero_a$81 , \logical_op__invert_in$80 , \logical_op__oe__ok$79 , \logical_op__oe__oe$78 , \logical_op__rc__ok$77 , \logical_op__rc__rc$76 , \logical_op__imm_data__ok$75 , \logical_op__imm_data__data$74 , \logical_op__fn_unit$73 , \logical_op__insn_type$72 } = { \pipe_end_logical_op__insn$69 , \pipe_end_logical_op__data_len$68 , \pipe_end_logical_op__is_signed$67 , \pipe_end_logical_op__is_32bit$66 , \pipe_end_logical_op__output_carry$65 , \pipe_end_logical_op__write_cr0$64 , \pipe_end_logical_op__invert_out$63 , \pipe_end_logical_op__input_carry$62 , \pipe_end_logical_op__zero_a$61 , \pipe_end_logical_op__invert_in$60 , \pipe_end_logical_op__oe__ok$59 , \pipe_end_logical_op__oe__oe$58 , \pipe_end_logical_op__rc__ok$57 , \pipe_end_logical_op__rc__rc$56 , \pipe_end_logical_op__imm_data__ok$55 , \pipe_end_logical_op__imm_data__data$54 , \pipe_end_logical_op__fn_unit$53 , \pipe_end_logical_op__insn_type$52 }; + assign \muxid$71 = \pipe_end_muxid$51 ; + assign pipe_end_n_ready_i = n_ready_i; + assign n_valid_o = pipe_end_n_valid_o; + assign \pipe_start_xer_so$23 = \xer_so$1 ; + assign \pipe_start_rb$22 = rb; + assign \pipe_start_ra$21 = ra; + assign { \pipe_start_logical_op__insn$20 , \pipe_start_logical_op__data_len$19 , \pipe_start_logical_op__is_signed$18 , \pipe_start_logical_op__is_32bit$17 , \pipe_start_logical_op__output_carry$16 , \pipe_start_logical_op__write_cr0$15 , \pipe_start_logical_op__invert_out$14 , \pipe_start_logical_op__input_carry$13 , \pipe_start_logical_op__zero_a$12 , \pipe_start_logical_op__invert_in$11 , \pipe_start_logical_op__oe__ok$10 , \pipe_start_logical_op__oe__oe$9 , \pipe_start_logical_op__rc__ok$8 , \pipe_start_logical_op__rc__rc$7 , \pipe_start_logical_op__imm_data__ok$6 , \pipe_start_logical_op__imm_data__data$5 , \pipe_start_logical_op__fn_unit$4 , \pipe_start_logical_op__insn_type$3 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \pipe_start_muxid$2 = 2'h0; + assign p_ready_o = pipe_start_p_ready_o; + assign pipe_start_p_valid_i = p_valid_i; + assign pipe_end_remainder = pipe_middle_0_remainder; + assign pipe_end_quotient_root = pipe_middle_0_quotient_root; + assign pipe_end_div_by_zero = \pipe_middle_0_div_by_zero$50 ; + assign pipe_end_dive_abs_ov64 = \pipe_middle_0_dive_abs_ov64$49 ; + assign pipe_end_dive_abs_ov32 = \pipe_middle_0_dive_abs_ov32$48 ; + assign pipe_end_dividend_neg = \pipe_middle_0_dividend_neg$47 ; + assign pipe_end_divisor_neg = \pipe_middle_0_divisor_neg$46 ; + assign pipe_end_xer_so = \pipe_middle_0_xer_so$45 ; + assign pipe_end_rb = \pipe_middle_0_rb$44 ; + assign pipe_end_ra = \pipe_middle_0_ra$43 ; + assign { pipe_end_logical_op__insn, pipe_end_logical_op__data_len, pipe_end_logical_op__is_signed, pipe_end_logical_op__is_32bit, pipe_end_logical_op__output_carry, pipe_end_logical_op__write_cr0, pipe_end_logical_op__invert_out, pipe_end_logical_op__input_carry, pipe_end_logical_op__zero_a, pipe_end_logical_op__invert_in, pipe_end_logical_op__oe__ok, pipe_end_logical_op__oe__oe, pipe_end_logical_op__rc__ok, pipe_end_logical_op__rc__rc, pipe_end_logical_op__imm_data__ok, pipe_end_logical_op__imm_data__data, pipe_end_logical_op__fn_unit, pipe_end_logical_op__insn_type } = { \pipe_middle_0_logical_op__insn$42 , \pipe_middle_0_logical_op__data_len$41 , \pipe_middle_0_logical_op__is_signed$40 , \pipe_middle_0_logical_op__is_32bit$39 , \pipe_middle_0_logical_op__output_carry$38 , \pipe_middle_0_logical_op__write_cr0$37 , \pipe_middle_0_logical_op__invert_out$36 , \pipe_middle_0_logical_op__input_carry$35 , \pipe_middle_0_logical_op__zero_a$34 , \pipe_middle_0_logical_op__invert_in$33 , \pipe_middle_0_logical_op__oe__ok$32 , \pipe_middle_0_logical_op__oe__oe$31 , \pipe_middle_0_logical_op__rc__ok$30 , \pipe_middle_0_logical_op__rc__rc$29 , \pipe_middle_0_logical_op__imm_data__ok$28 , \pipe_middle_0_logical_op__imm_data__data$27 , \pipe_middle_0_logical_op__fn_unit$26 , \pipe_middle_0_logical_op__insn_type$25 }; + assign pipe_end_muxid = \pipe_middle_0_muxid$24 ; + assign pipe_middle_0_n_ready_i = pipe_end_p_ready_o; + assign pipe_end_p_valid_i = pipe_middle_0_n_valid_o; + assign pipe_middle_0_operation = pipe_start_operation; + assign pipe_middle_0_divisor_radicand = pipe_start_divisor_radicand; + assign pipe_middle_0_dividend = pipe_start_dividend; + assign pipe_middle_0_div_by_zero = pipe_start_div_by_zero; + assign pipe_middle_0_dive_abs_ov64 = pipe_start_dive_abs_ov64; + assign pipe_middle_0_dive_abs_ov32 = pipe_start_dive_abs_ov32; + assign pipe_middle_0_dividend_neg = pipe_start_dividend_neg; + assign pipe_middle_0_divisor_neg = pipe_start_divisor_neg; + assign pipe_middle_0_xer_so = pipe_start_xer_so; + assign pipe_middle_0_rb = pipe_start_rb; + assign pipe_middle_0_ra = pipe_start_ra; + assign { pipe_middle_0_logical_op__insn, pipe_middle_0_logical_op__data_len, pipe_middle_0_logical_op__is_signed, pipe_middle_0_logical_op__is_32bit, pipe_middle_0_logical_op__output_carry, pipe_middle_0_logical_op__write_cr0, pipe_middle_0_logical_op__invert_out, pipe_middle_0_logical_op__input_carry, pipe_middle_0_logical_op__zero_a, pipe_middle_0_logical_op__invert_in, pipe_middle_0_logical_op__oe__ok, pipe_middle_0_logical_op__oe__oe, pipe_middle_0_logical_op__rc__ok, pipe_middle_0_logical_op__rc__rc, pipe_middle_0_logical_op__imm_data__ok, pipe_middle_0_logical_op__imm_data__data, pipe_middle_0_logical_op__fn_unit, pipe_middle_0_logical_op__insn_type } = { pipe_start_logical_op__insn, pipe_start_logical_op__data_len, pipe_start_logical_op__is_signed, pipe_start_logical_op__is_32bit, pipe_start_logical_op__output_carry, pipe_start_logical_op__write_cr0, pipe_start_logical_op__invert_out, pipe_start_logical_op__input_carry, pipe_start_logical_op__zero_a, pipe_start_logical_op__invert_in, pipe_start_logical_op__oe__ok, pipe_start_logical_op__oe__oe, pipe_start_logical_op__rc__ok, pipe_start_logical_op__rc__rc, pipe_start_logical_op__imm_data__ok, pipe_start_logical_op__imm_data__data, pipe_start_logical_op__fn_unit, pipe_start_logical_op__insn_type }; + assign pipe_middle_0_muxid = pipe_start_muxid; + assign pipe_start_n_ready_i = pipe_middle_0_p_ready_o; + assign pipe_middle_0_p_valid_i = pipe_start_n_valid_o; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_l" *) +(* generator = "nMigen" *) +module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_l" *) +(* generator = "nMigen" *) +module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alu; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu; + assign \$15 = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alu = \$15 ; + assign qn_alu = \$13 ; + assign q_alu = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0" *) +(* generator = "nMigen" *) +module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \logical_op__data_len$61 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \logical_op__fn_unit$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \logical_op__imm_data__data$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__imm_data__ok$48 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \logical_op__input_carry$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \logical_op__insn$62 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \logical_op__insn_type$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_in$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_out$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_32bit$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_signed$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__oe$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__ok$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__output_carry$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__ok$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__rc$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__write_cr0$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__zero_a$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] logical_pipe1_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire logical_pipe1_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] logical_pipe1_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \logical_pipe1_logical_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] logical_pipe1_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \logical_pipe1_logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] logical_pipe1_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \logical_pipe1_logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] logical_pipe1_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \logical_pipe1_logical_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] logical_pipe1_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \logical_pipe1_logical_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] logical_pipe1_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \logical_pipe1_logical_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe1_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe1_logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] logical_pipe1_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \logical_pipe1_muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire logical_pipe1_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire logical_pipe1_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] logical_pipe1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire logical_pipe1_o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire logical_pipe1_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire logical_pipe1_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] logical_pipe1_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] logical_pipe1_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire logical_pipe1_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \logical_pipe1_xer_so$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire logical_pipe1_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] logical_pipe2_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \logical_pipe2_cr_a$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire logical_pipe2_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \logical_pipe2_cr_a_ok$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] logical_pipe2_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \logical_pipe2_logical_op__data_len$38 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] logical_pipe2_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \logical_pipe2_logical_op__fn_unit$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] logical_pipe2_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \logical_pipe2_logical_op__imm_data__data$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__imm_data__ok$25 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] logical_pipe2_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \logical_pipe2_logical_op__input_carry$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] logical_pipe2_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \logical_pipe2_logical_op__insn$39 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] logical_pipe2_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \logical_pipe2_logical_op__insn_type$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__invert_in$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__invert_out$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__is_32bit$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__is_signed$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__oe__oe$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__oe__ok$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__output_carry$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__rc__ok$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__rc__rc$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__write_cr0$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire logical_pipe2_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_pipe2_logical_op__zero_a$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] logical_pipe2_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \logical_pipe2_muxid$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire logical_pipe2_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire logical_pipe2_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] logical_pipe2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \logical_pipe2_o$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire logical_pipe2_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \logical_pipe2_o_ok$41 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire logical_pipe2_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire logical_pipe2_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire logical_pipe2_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire logical_pipe2_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$44 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + logical_pipe1 logical_pipe1 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(logical_pipe1_cr_a), + .cr_a_ok(logical_pipe1_cr_a_ok), + .logical_op__data_len(logical_pipe1_logical_op__data_len), + .\logical_op__data_len$18 (\logical_pipe1_logical_op__data_len$18 ), + .logical_op__fn_unit(logical_pipe1_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\logical_pipe1_logical_op__fn_unit$3 ), + .logical_op__imm_data__data(logical_pipe1_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\logical_pipe1_logical_op__imm_data__data$4 ), + .logical_op__imm_data__ok(logical_pipe1_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\logical_pipe1_logical_op__imm_data__ok$5 ), + .logical_op__input_carry(logical_pipe1_logical_op__input_carry), + .\logical_op__input_carry$12 (\logical_pipe1_logical_op__input_carry$12 ), + .logical_op__insn(logical_pipe1_logical_op__insn), + .\logical_op__insn$19 (\logical_pipe1_logical_op__insn$19 ), + .logical_op__insn_type(logical_pipe1_logical_op__insn_type), + .\logical_op__insn_type$2 (\logical_pipe1_logical_op__insn_type$2 ), + .logical_op__invert_in(logical_pipe1_logical_op__invert_in), + .\logical_op__invert_in$10 (\logical_pipe1_logical_op__invert_in$10 ), + .logical_op__invert_out(logical_pipe1_logical_op__invert_out), + .\logical_op__invert_out$13 (\logical_pipe1_logical_op__invert_out$13 ), + .logical_op__is_32bit(logical_pipe1_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\logical_pipe1_logical_op__is_32bit$16 ), + .logical_op__is_signed(logical_pipe1_logical_op__is_signed), + .\logical_op__is_signed$17 (\logical_pipe1_logical_op__is_signed$17 ), + .logical_op__oe__oe(logical_pipe1_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\logical_pipe1_logical_op__oe__oe$8 ), + .logical_op__oe__ok(logical_pipe1_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\logical_pipe1_logical_op__oe__ok$9 ), + .logical_op__output_carry(logical_pipe1_logical_op__output_carry), + .\logical_op__output_carry$15 (\logical_pipe1_logical_op__output_carry$15 ), + .logical_op__rc__ok(logical_pipe1_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\logical_pipe1_logical_op__rc__ok$7 ), + .logical_op__rc__rc(logical_pipe1_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\logical_pipe1_logical_op__rc__rc$6 ), + .logical_op__write_cr0(logical_pipe1_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\logical_pipe1_logical_op__write_cr0$14 ), + .logical_op__zero_a(logical_pipe1_logical_op__zero_a), + .\logical_op__zero_a$11 (\logical_pipe1_logical_op__zero_a$11 ), + .muxid(logical_pipe1_muxid), + .\muxid$1 (\logical_pipe1_muxid$1 ), + .n_ready_i(logical_pipe1_n_ready_i), + .n_valid_o(logical_pipe1_n_valid_o), + .o(logical_pipe1_o), + .o_ok(logical_pipe1_o_ok), + .p_ready_o(logical_pipe1_p_ready_o), + .p_valid_i(logical_pipe1_p_valid_i), + .ra(logical_pipe1_ra), + .rb(logical_pipe1_rb), + .xer_so(logical_pipe1_xer_so), + .\xer_so$20 (\logical_pipe1_xer_so$20 ), + .xer_so_ok(logical_pipe1_xer_so_ok) + ); + logical_pipe2 logical_pipe2 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(logical_pipe2_cr_a), + .\cr_a$22 (\logical_pipe2_cr_a$42 ), + .cr_a_ok(logical_pipe2_cr_a_ok), + .\cr_a_ok$23 (\logical_pipe2_cr_a_ok$43 ), + .logical_op__data_len(logical_pipe2_logical_op__data_len), + .\logical_op__data_len$18 (\logical_pipe2_logical_op__data_len$38 ), + .logical_op__fn_unit(logical_pipe2_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\logical_pipe2_logical_op__fn_unit$23 ), + .logical_op__imm_data__data(logical_pipe2_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\logical_pipe2_logical_op__imm_data__data$24 ), + .logical_op__imm_data__ok(logical_pipe2_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\logical_pipe2_logical_op__imm_data__ok$25 ), + .logical_op__input_carry(logical_pipe2_logical_op__input_carry), + .\logical_op__input_carry$12 (\logical_pipe2_logical_op__input_carry$32 ), + .logical_op__insn(logical_pipe2_logical_op__insn), + .\logical_op__insn$19 (\logical_pipe2_logical_op__insn$39 ), + .logical_op__insn_type(logical_pipe2_logical_op__insn_type), + .\logical_op__insn_type$2 (\logical_pipe2_logical_op__insn_type$22 ), + .logical_op__invert_in(logical_pipe2_logical_op__invert_in), + .\logical_op__invert_in$10 (\logical_pipe2_logical_op__invert_in$30 ), + .logical_op__invert_out(logical_pipe2_logical_op__invert_out), + .\logical_op__invert_out$13 (\logical_pipe2_logical_op__invert_out$33 ), + .logical_op__is_32bit(logical_pipe2_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\logical_pipe2_logical_op__is_32bit$36 ), + .logical_op__is_signed(logical_pipe2_logical_op__is_signed), + .\logical_op__is_signed$17 (\logical_pipe2_logical_op__is_signed$37 ), + .logical_op__oe__oe(logical_pipe2_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\logical_pipe2_logical_op__oe__oe$28 ), + .logical_op__oe__ok(logical_pipe2_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\logical_pipe2_logical_op__oe__ok$29 ), + .logical_op__output_carry(logical_pipe2_logical_op__output_carry), + .\logical_op__output_carry$15 (\logical_pipe2_logical_op__output_carry$35 ), + .logical_op__rc__ok(logical_pipe2_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\logical_pipe2_logical_op__rc__ok$27 ), + .logical_op__rc__rc(logical_pipe2_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\logical_pipe2_logical_op__rc__rc$26 ), + .logical_op__write_cr0(logical_pipe2_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\logical_pipe2_logical_op__write_cr0$34 ), + .logical_op__zero_a(logical_pipe2_logical_op__zero_a), + .\logical_op__zero_a$11 (\logical_pipe2_logical_op__zero_a$31 ), + .muxid(logical_pipe2_muxid), + .\muxid$1 (\logical_pipe2_muxid$21 ), + .n_ready_i(logical_pipe2_n_ready_i), + .n_valid_o(logical_pipe2_n_valid_o), + .o(logical_pipe2_o), + .\o$20 (\logical_pipe2_o$40 ), + .o_ok(logical_pipe2_o_ok), + .\o_ok$21 (\logical_pipe2_o_ok$41 ), + .p_ready_o(logical_pipe2_p_ready_o), + .p_valid_i(logical_pipe2_p_valid_i), + .xer_so(logical_pipe2_xer_so), + .xer_so_ok(logical_pipe2_xer_so_ok) + ); + \n$47 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$46 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + assign muxid = 2'h0; + assign { cr_a_ok, cr_a } = { \logical_pipe2_cr_a_ok$43 , \logical_pipe2_cr_a$42 }; + assign { o_ok, o } = { \logical_pipe2_o_ok$41 , \logical_pipe2_o$40 }; + assign { \logical_op__insn$62 , \logical_op__data_len$61 , \logical_op__is_signed$60 , \logical_op__is_32bit$59 , \logical_op__output_carry$58 , \logical_op__write_cr0$57 , \logical_op__invert_out$56 , \logical_op__input_carry$55 , \logical_op__zero_a$54 , \logical_op__invert_in$53 , \logical_op__oe__ok$52 , \logical_op__oe__oe$51 , \logical_op__rc__ok$50 , \logical_op__rc__rc$49 , \logical_op__imm_data__ok$48 , \logical_op__imm_data__data$47 , \logical_op__fn_unit$46 , \logical_op__insn_type$45 } = { \logical_pipe2_logical_op__insn$39 , \logical_pipe2_logical_op__data_len$38 , \logical_pipe2_logical_op__is_signed$37 , \logical_pipe2_logical_op__is_32bit$36 , \logical_pipe2_logical_op__output_carry$35 , \logical_pipe2_logical_op__write_cr0$34 , \logical_pipe2_logical_op__invert_out$33 , \logical_pipe2_logical_op__input_carry$32 , \logical_pipe2_logical_op__zero_a$31 , \logical_pipe2_logical_op__invert_in$30 , \logical_pipe2_logical_op__oe__ok$29 , \logical_pipe2_logical_op__oe__oe$28 , \logical_pipe2_logical_op__rc__ok$27 , \logical_pipe2_logical_op__rc__rc$26 , \logical_pipe2_logical_op__imm_data__ok$25 , \logical_pipe2_logical_op__imm_data__data$24 , \logical_pipe2_logical_op__fn_unit$23 , \logical_pipe2_logical_op__insn_type$22 }; + assign \muxid$44 = \logical_pipe2_muxid$21 ; + assign logical_pipe2_n_ready_i = n_ready_i; + assign n_valid_o = logical_pipe2_n_valid_o; + assign \logical_pipe1_xer_so$20 = xer_so; + assign logical_pipe1_rb = rb; + assign logical_pipe1_ra = ra; + assign { \logical_pipe1_logical_op__insn$19 , \logical_pipe1_logical_op__data_len$18 , \logical_pipe1_logical_op__is_signed$17 , \logical_pipe1_logical_op__is_32bit$16 , \logical_pipe1_logical_op__output_carry$15 , \logical_pipe1_logical_op__write_cr0$14 , \logical_pipe1_logical_op__invert_out$13 , \logical_pipe1_logical_op__input_carry$12 , \logical_pipe1_logical_op__zero_a$11 , \logical_pipe1_logical_op__invert_in$10 , \logical_pipe1_logical_op__oe__ok$9 , \logical_pipe1_logical_op__oe__oe$8 , \logical_pipe1_logical_op__rc__ok$7 , \logical_pipe1_logical_op__rc__rc$6 , \logical_pipe1_logical_op__imm_data__ok$5 , \logical_pipe1_logical_op__imm_data__data$4 , \logical_pipe1_logical_op__fn_unit$3 , \logical_pipe1_logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \logical_pipe1_muxid$1 = 2'h0; + assign p_ready_o = logical_pipe1_p_ready_o; + assign logical_pipe1_p_valid_i = p_valid_i; + assign { logical_pipe2_xer_so_ok, logical_pipe2_xer_so } = { logical_pipe1_xer_so_ok, logical_pipe1_xer_so }; + assign { logical_pipe2_cr_a_ok, logical_pipe2_cr_a } = { logical_pipe1_cr_a_ok, logical_pipe1_cr_a }; + assign { logical_pipe2_o_ok, logical_pipe2_o } = { logical_pipe1_o_ok, logical_pipe1_o }; + assign { logical_pipe2_logical_op__insn, logical_pipe2_logical_op__data_len, logical_pipe2_logical_op__is_signed, logical_pipe2_logical_op__is_32bit, logical_pipe2_logical_op__output_carry, logical_pipe2_logical_op__write_cr0, logical_pipe2_logical_op__invert_out, logical_pipe2_logical_op__input_carry, logical_pipe2_logical_op__zero_a, logical_pipe2_logical_op__invert_in, logical_pipe2_logical_op__oe__ok, logical_pipe2_logical_op__oe__oe, logical_pipe2_logical_op__rc__ok, logical_pipe2_logical_op__rc__rc, logical_pipe2_logical_op__imm_data__ok, logical_pipe2_logical_op__imm_data__data, logical_pipe2_logical_op__fn_unit, logical_pipe2_logical_op__insn_type } = { logical_pipe1_logical_op__insn, logical_pipe1_logical_op__data_len, logical_pipe1_logical_op__is_signed, logical_pipe1_logical_op__is_32bit, logical_pipe1_logical_op__output_carry, logical_pipe1_logical_op__write_cr0, logical_pipe1_logical_op__invert_out, logical_pipe1_logical_op__input_carry, logical_pipe1_logical_op__zero_a, logical_pipe1_logical_op__invert_in, logical_pipe1_logical_op__oe__ok, logical_pipe1_logical_op__oe__oe, logical_pipe1_logical_op__rc__ok, logical_pipe1_logical_op__rc__rc, logical_pipe1_logical_op__imm_data__ok, logical_pipe1_logical_op__imm_data__data, logical_pipe1_logical_op__fn_unit, logical_pipe1_logical_op__insn_type }; + assign logical_pipe2_muxid = logical_pipe1_muxid; + assign logical_pipe1_n_ready_i = logical_pipe2_p_ready_o; + assign logical_pipe2_p_valid_i = logical_pipe1_n_valid_o; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0" *) +(* generator = "nMigen" *) +module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul_op__fn_unit$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul_op__imm_data__data$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__imm_data__ok$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul_op__insn$61 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul_op__insn_type$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__is_32bit$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__is_signed$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__oe__oe$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__oe__ok$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__rc__ok$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__rc__rc$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__write_cr0$58 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] mul_pipe1_mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul_pipe1_mul_op__fn_unit$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] mul_pipe1_mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul_pipe1_mul_op__imm_data__data$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe1_mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe1_mul_op__imm_data__ok$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] mul_pipe1_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul_pipe1_mul_op__insn$14 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] mul_pipe1_mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul_pipe1_mul_op__insn_type$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe1_mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe1_mul_op__is_32bit$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe1_mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe1_mul_op__is_signed$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe1_mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe1_mul_op__oe__oe$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe1_mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe1_mul_op__oe__ok$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe1_mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe1_mul_op__rc__ok$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe1_mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe1_mul_op__rc__rc$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe1_mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe1_mul_op__write_cr0$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] mul_pipe1_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \mul_pipe1_muxid$2 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire mul_pipe1_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire mul_pipe1_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + wire mul_pipe1_neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + wire mul_pipe1_neg_res32; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire mul_pipe1_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire mul_pipe1_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] mul_pipe1_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \mul_pipe1_ra$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] mul_pipe1_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \mul_pipe1_rb$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire mul_pipe1_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \mul_pipe1_xer_so$17 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] mul_pipe2_mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul_pipe2_mul_op__fn_unit$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] mul_pipe2_mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul_pipe2_mul_op__imm_data__data$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe2_mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe2_mul_op__imm_data__ok$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] mul_pipe2_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul_pipe2_mul_op__insn$30 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] mul_pipe2_mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul_pipe2_mul_op__insn_type$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe2_mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe2_mul_op__is_32bit$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe2_mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe2_mul_op__is_signed$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe2_mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe2_mul_op__oe__oe$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe2_mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe2_mul_op__oe__ok$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe2_mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe2_mul_op__rc__ok$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe2_mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe2_mul_op__rc__rc$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe2_mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe2_mul_op__write_cr0$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] mul_pipe2_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \mul_pipe2_muxid$18 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire mul_pipe2_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire mul_pipe2_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + wire mul_pipe2_neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + wire \mul_pipe2_neg_res$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + wire mul_pipe2_neg_res32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + wire \mul_pipe2_neg_res32$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [128:0] mul_pipe2_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire mul_pipe2_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire mul_pipe2_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] mul_pipe2_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] mul_pipe2_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire mul_pipe2_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \mul_pipe2_xer_so$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] mul_pipe3_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire mul_pipe3_cr_a_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] mul_pipe3_mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul_pipe3_mul_op__fn_unit$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] mul_pipe3_mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul_pipe3_mul_op__imm_data__data$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe3_mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe3_mul_op__imm_data__ok$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] mul_pipe3_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul_pipe3_mul_op__insn$46 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] mul_pipe3_mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul_pipe3_mul_op__insn_type$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe3_mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe3_mul_op__is_32bit$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe3_mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe3_mul_op__is_signed$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe3_mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe3_mul_op__oe__oe$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe3_mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe3_mul_op__oe__ok$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe3_mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe3_mul_op__rc__ok$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe3_mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe3_mul_op__rc__rc$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul_pipe3_mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_pipe3_mul_op__write_cr0$43 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] mul_pipe3_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \mul_pipe3_muxid$34 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire mul_pipe3_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire mul_pipe3_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + wire mul_pipe3_neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + wire mul_pipe3_neg_res32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [128:0] mul_pipe3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \mul_pipe3_o$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire mul_pipe3_o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire mul_pipe3_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire mul_pipe3_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] mul_pipe3_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire mul_pipe3_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire mul_pipe3_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \mul_pipe3_xer_so$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire mul_pipe3_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$49 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + mul_pipe1 mul_pipe1 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .mul_op__fn_unit(mul_pipe1_mul_op__fn_unit), + .\mul_op__fn_unit$3 (\mul_pipe1_mul_op__fn_unit$4 ), + .mul_op__imm_data__data(mul_pipe1_mul_op__imm_data__data), + .\mul_op__imm_data__data$4 (\mul_pipe1_mul_op__imm_data__data$5 ), + .mul_op__imm_data__ok(mul_pipe1_mul_op__imm_data__ok), + .\mul_op__imm_data__ok$5 (\mul_pipe1_mul_op__imm_data__ok$6 ), + .mul_op__insn(mul_pipe1_mul_op__insn), + .\mul_op__insn$13 (\mul_pipe1_mul_op__insn$14 ), + .mul_op__insn_type(mul_pipe1_mul_op__insn_type), + .\mul_op__insn_type$2 (\mul_pipe1_mul_op__insn_type$3 ), + .mul_op__is_32bit(mul_pipe1_mul_op__is_32bit), + .\mul_op__is_32bit$11 (\mul_pipe1_mul_op__is_32bit$12 ), + .mul_op__is_signed(mul_pipe1_mul_op__is_signed), + .\mul_op__is_signed$12 (\mul_pipe1_mul_op__is_signed$13 ), + .mul_op__oe__oe(mul_pipe1_mul_op__oe__oe), + .\mul_op__oe__oe$8 (\mul_pipe1_mul_op__oe__oe$9 ), + .mul_op__oe__ok(mul_pipe1_mul_op__oe__ok), + .\mul_op__oe__ok$9 (\mul_pipe1_mul_op__oe__ok$10 ), + .mul_op__rc__ok(mul_pipe1_mul_op__rc__ok), + .\mul_op__rc__ok$7 (\mul_pipe1_mul_op__rc__ok$8 ), + .mul_op__rc__rc(mul_pipe1_mul_op__rc__rc), + .\mul_op__rc__rc$6 (\mul_pipe1_mul_op__rc__rc$7 ), + .mul_op__write_cr0(mul_pipe1_mul_op__write_cr0), + .\mul_op__write_cr0$10 (\mul_pipe1_mul_op__write_cr0$11 ), + .muxid(mul_pipe1_muxid), + .\muxid$1 (\mul_pipe1_muxid$2 ), + .n_ready_i(mul_pipe1_n_ready_i), + .n_valid_o(mul_pipe1_n_valid_o), + .neg_res(mul_pipe1_neg_res), + .neg_res32(mul_pipe1_neg_res32), + .p_ready_o(mul_pipe1_p_ready_o), + .p_valid_i(mul_pipe1_p_valid_i), + .ra(mul_pipe1_ra), + .\ra$14 (\mul_pipe1_ra$15 ), + .rb(mul_pipe1_rb), + .\rb$15 (\mul_pipe1_rb$16 ), + .xer_so(mul_pipe1_xer_so), + .\xer_so$16 (\mul_pipe1_xer_so$17 ) + ); + mul_pipe2 mul_pipe2 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .mul_op__fn_unit(mul_pipe2_mul_op__fn_unit), + .\mul_op__fn_unit$3 (\mul_pipe2_mul_op__fn_unit$20 ), + .mul_op__imm_data__data(mul_pipe2_mul_op__imm_data__data), + .\mul_op__imm_data__data$4 (\mul_pipe2_mul_op__imm_data__data$21 ), + .mul_op__imm_data__ok(mul_pipe2_mul_op__imm_data__ok), + .\mul_op__imm_data__ok$5 (\mul_pipe2_mul_op__imm_data__ok$22 ), + .mul_op__insn(mul_pipe2_mul_op__insn), + .\mul_op__insn$13 (\mul_pipe2_mul_op__insn$30 ), + .mul_op__insn_type(mul_pipe2_mul_op__insn_type), + .\mul_op__insn_type$2 (\mul_pipe2_mul_op__insn_type$19 ), + .mul_op__is_32bit(mul_pipe2_mul_op__is_32bit), + .\mul_op__is_32bit$11 (\mul_pipe2_mul_op__is_32bit$28 ), + .mul_op__is_signed(mul_pipe2_mul_op__is_signed), + .\mul_op__is_signed$12 (\mul_pipe2_mul_op__is_signed$29 ), + .mul_op__oe__oe(mul_pipe2_mul_op__oe__oe), + .\mul_op__oe__oe$8 (\mul_pipe2_mul_op__oe__oe$25 ), + .mul_op__oe__ok(mul_pipe2_mul_op__oe__ok), + .\mul_op__oe__ok$9 (\mul_pipe2_mul_op__oe__ok$26 ), + .mul_op__rc__ok(mul_pipe2_mul_op__rc__ok), + .\mul_op__rc__ok$7 (\mul_pipe2_mul_op__rc__ok$24 ), + .mul_op__rc__rc(mul_pipe2_mul_op__rc__rc), + .\mul_op__rc__rc$6 (\mul_pipe2_mul_op__rc__rc$23 ), + .mul_op__write_cr0(mul_pipe2_mul_op__write_cr0), + .\mul_op__write_cr0$10 (\mul_pipe2_mul_op__write_cr0$27 ), + .muxid(mul_pipe2_muxid), + .\muxid$1 (\mul_pipe2_muxid$18 ), + .n_ready_i(mul_pipe2_n_ready_i), + .n_valid_o(mul_pipe2_n_valid_o), + .neg_res(mul_pipe2_neg_res), + .\neg_res$15 (\mul_pipe2_neg_res$32 ), + .neg_res32(mul_pipe2_neg_res32), + .\neg_res32$16 (\mul_pipe2_neg_res32$33 ), + .o(mul_pipe2_o), + .p_ready_o(mul_pipe2_p_ready_o), + .p_valid_i(mul_pipe2_p_valid_i), + .ra(mul_pipe2_ra), + .rb(mul_pipe2_rb), + .xer_so(mul_pipe2_xer_so), + .\xer_so$14 (\mul_pipe2_xer_so$31 ) + ); + mul_pipe3 mul_pipe3 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(mul_pipe3_cr_a), + .cr_a_ok(mul_pipe3_cr_a_ok), + .mul_op__fn_unit(mul_pipe3_mul_op__fn_unit), + .\mul_op__fn_unit$3 (\mul_pipe3_mul_op__fn_unit$36 ), + .mul_op__imm_data__data(mul_pipe3_mul_op__imm_data__data), + .\mul_op__imm_data__data$4 (\mul_pipe3_mul_op__imm_data__data$37 ), + .mul_op__imm_data__ok(mul_pipe3_mul_op__imm_data__ok), + .\mul_op__imm_data__ok$5 (\mul_pipe3_mul_op__imm_data__ok$38 ), + .mul_op__insn(mul_pipe3_mul_op__insn), + .\mul_op__insn$13 (\mul_pipe3_mul_op__insn$46 ), + .mul_op__insn_type(mul_pipe3_mul_op__insn_type), + .\mul_op__insn_type$2 (\mul_pipe3_mul_op__insn_type$35 ), + .mul_op__is_32bit(mul_pipe3_mul_op__is_32bit), + .\mul_op__is_32bit$11 (\mul_pipe3_mul_op__is_32bit$44 ), + .mul_op__is_signed(mul_pipe3_mul_op__is_signed), + .\mul_op__is_signed$12 (\mul_pipe3_mul_op__is_signed$45 ), + .mul_op__oe__oe(mul_pipe3_mul_op__oe__oe), + .\mul_op__oe__oe$8 (\mul_pipe3_mul_op__oe__oe$41 ), + .mul_op__oe__ok(mul_pipe3_mul_op__oe__ok), + .\mul_op__oe__ok$9 (\mul_pipe3_mul_op__oe__ok$42 ), + .mul_op__rc__ok(mul_pipe3_mul_op__rc__ok), + .\mul_op__rc__ok$7 (\mul_pipe3_mul_op__rc__ok$40 ), + .mul_op__rc__rc(mul_pipe3_mul_op__rc__rc), + .\mul_op__rc__rc$6 (\mul_pipe3_mul_op__rc__rc$39 ), + .mul_op__write_cr0(mul_pipe3_mul_op__write_cr0), + .\mul_op__write_cr0$10 (\mul_pipe3_mul_op__write_cr0$43 ), + .muxid(mul_pipe3_muxid), + .\muxid$1 (\mul_pipe3_muxid$34 ), + .n_ready_i(mul_pipe3_n_ready_i), + .n_valid_o(mul_pipe3_n_valid_o), + .neg_res(mul_pipe3_neg_res), + .neg_res32(mul_pipe3_neg_res32), + .o(mul_pipe3_o), + .\o$14 (\mul_pipe3_o$47 ), + .o_ok(mul_pipe3_o_ok), + .p_ready_o(mul_pipe3_p_ready_o), + .p_valid_i(mul_pipe3_p_valid_i), + .xer_ov(mul_pipe3_xer_ov), + .xer_ov_ok(mul_pipe3_xer_ov_ok), + .xer_so(mul_pipe3_xer_so), + .\xer_so$15 (\mul_pipe3_xer_so$48 ), + .xer_so_ok(mul_pipe3_xer_so_ok) + ); + \n$92 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$91 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + assign muxid = 2'h0; + assign { xer_so_ok, xer_so } = { mul_pipe3_xer_so_ok, \mul_pipe3_xer_so$48 }; + assign { xer_ov_ok, xer_ov } = { mul_pipe3_xer_ov_ok, mul_pipe3_xer_ov }; + assign { cr_a_ok, cr_a } = { mul_pipe3_cr_a_ok, mul_pipe3_cr_a }; + assign { o_ok, o } = { mul_pipe3_o_ok, \mul_pipe3_o$47 }; + assign { \mul_op__insn$61 , \mul_op__is_signed$60 , \mul_op__is_32bit$59 , \mul_op__write_cr0$58 , \mul_op__oe__ok$57 , \mul_op__oe__oe$56 , \mul_op__rc__ok$55 , \mul_op__rc__rc$54 , \mul_op__imm_data__ok$53 , \mul_op__imm_data__data$52 , \mul_op__fn_unit$51 , \mul_op__insn_type$50 } = { \mul_pipe3_mul_op__insn$46 , \mul_pipe3_mul_op__is_signed$45 , \mul_pipe3_mul_op__is_32bit$44 , \mul_pipe3_mul_op__write_cr0$43 , \mul_pipe3_mul_op__oe__ok$42 , \mul_pipe3_mul_op__oe__oe$41 , \mul_pipe3_mul_op__rc__ok$40 , \mul_pipe3_mul_op__rc__rc$39 , \mul_pipe3_mul_op__imm_data__ok$38 , \mul_pipe3_mul_op__imm_data__data$37 , \mul_pipe3_mul_op__fn_unit$36 , \mul_pipe3_mul_op__insn_type$35 }; + assign \muxid$49 = \mul_pipe3_muxid$34 ; + assign mul_pipe3_n_ready_i = n_ready_i; + assign n_valid_o = mul_pipe3_n_valid_o; + assign \mul_pipe1_xer_so$17 = \xer_so$1 ; + assign \mul_pipe1_rb$16 = rb; + assign \mul_pipe1_ra$15 = ra; + assign { \mul_pipe1_mul_op__insn$14 , \mul_pipe1_mul_op__is_signed$13 , \mul_pipe1_mul_op__is_32bit$12 , \mul_pipe1_mul_op__write_cr0$11 , \mul_pipe1_mul_op__oe__ok$10 , \mul_pipe1_mul_op__oe__oe$9 , \mul_pipe1_mul_op__rc__ok$8 , \mul_pipe1_mul_op__rc__rc$7 , \mul_pipe1_mul_op__imm_data__ok$6 , \mul_pipe1_mul_op__imm_data__data$5 , \mul_pipe1_mul_op__fn_unit$4 , \mul_pipe1_mul_op__insn_type$3 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \mul_pipe1_muxid$2 = 2'h0; + assign p_ready_o = mul_pipe1_p_ready_o; + assign mul_pipe1_p_valid_i = p_valid_i; + assign mul_pipe3_neg_res32 = \mul_pipe2_neg_res32$33 ; + assign mul_pipe3_neg_res = \mul_pipe2_neg_res$32 ; + assign mul_pipe3_xer_so = \mul_pipe2_xer_so$31 ; + assign mul_pipe3_o = mul_pipe2_o; + assign { mul_pipe3_mul_op__insn, mul_pipe3_mul_op__is_signed, mul_pipe3_mul_op__is_32bit, mul_pipe3_mul_op__write_cr0, mul_pipe3_mul_op__oe__ok, mul_pipe3_mul_op__oe__oe, mul_pipe3_mul_op__rc__ok, mul_pipe3_mul_op__rc__rc, mul_pipe3_mul_op__imm_data__ok, mul_pipe3_mul_op__imm_data__data, mul_pipe3_mul_op__fn_unit, mul_pipe3_mul_op__insn_type } = { \mul_pipe2_mul_op__insn$30 , \mul_pipe2_mul_op__is_signed$29 , \mul_pipe2_mul_op__is_32bit$28 , \mul_pipe2_mul_op__write_cr0$27 , \mul_pipe2_mul_op__oe__ok$26 , \mul_pipe2_mul_op__oe__oe$25 , \mul_pipe2_mul_op__rc__ok$24 , \mul_pipe2_mul_op__rc__rc$23 , \mul_pipe2_mul_op__imm_data__ok$22 , \mul_pipe2_mul_op__imm_data__data$21 , \mul_pipe2_mul_op__fn_unit$20 , \mul_pipe2_mul_op__insn_type$19 }; + assign mul_pipe3_muxid = \mul_pipe2_muxid$18 ; + assign mul_pipe2_n_ready_i = mul_pipe3_p_ready_o; + assign mul_pipe3_p_valid_i = mul_pipe2_n_valid_o; + assign mul_pipe2_neg_res32 = mul_pipe1_neg_res32; + assign mul_pipe2_neg_res = mul_pipe1_neg_res; + assign mul_pipe2_xer_so = mul_pipe1_xer_so; + assign mul_pipe2_rb = mul_pipe1_rb; + assign mul_pipe2_ra = mul_pipe1_ra; + assign { mul_pipe2_mul_op__insn, mul_pipe2_mul_op__is_signed, mul_pipe2_mul_op__is_32bit, mul_pipe2_mul_op__write_cr0, mul_pipe2_mul_op__oe__ok, mul_pipe2_mul_op__oe__oe, mul_pipe2_mul_op__rc__ok, mul_pipe2_mul_op__rc__rc, mul_pipe2_mul_op__imm_data__ok, mul_pipe2_mul_op__imm_data__data, mul_pipe2_mul_op__fn_unit, mul_pipe2_mul_op__insn_type } = { mul_pipe1_mul_op__insn, mul_pipe1_mul_op__is_signed, mul_pipe1_mul_op__is_32bit, mul_pipe1_mul_op__write_cr0, mul_pipe1_mul_op__oe__ok, mul_pipe1_mul_op__oe__oe, mul_pipe1_mul_op__rc__ok, mul_pipe1_mul_op__rc__rc, mul_pipe1_mul_op__imm_data__ok, mul_pipe1_mul_op__imm_data__data, mul_pipe1_mul_op__fn_unit, mul_pipe1_mul_op__insn_type }; + assign mul_pipe2_muxid = mul_pipe1_muxid; + assign mul_pipe1_n_ready_i = mul_pipe2_p_ready_o; + assign mul_pipe2_p_valid_i = mul_pipe1_n_valid_o; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *) +(* generator = "nMigen" *) +module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$46 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] pipe1_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe1_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe1_muxid$2 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe1_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe1_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe1_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe1_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_rc; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe1_sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe1_sr_op__fn_unit$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe1_sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe1_sr_op__imm_data__data$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__imm_data__ok$6 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] pipe1_sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \pipe1_sr_op__input_carry$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__input_cr$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe1_sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe1_sr_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe1_sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe1_sr_op__insn_type$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__invert_in$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__is_32bit$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__is_signed$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__oe__oe$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__oe__ok$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__output_carry$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__output_cr$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__rc__ok$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__rc__rc$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_sr_op__write_cr0$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] pipe1_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \pipe1_xer_ca$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \pipe1_xer_so$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe1_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] pipe2_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \pipe2_cr_a$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_cr_a_ok$43 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe2_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe2_muxid$22 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe2_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe2_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \pipe2_o$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_o_ok$41 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe2_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe2_p_valid_i; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe2_sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe2_sr_op__fn_unit$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe2_sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe2_sr_op__imm_data__data$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__imm_data__ok$26 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] pipe2_sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \pipe2_sr_op__input_carry$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__input_cr$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe2_sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe2_sr_op__insn$39 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe2_sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe2_sr_op__insn_type$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__invert_in$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__is_32bit$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__is_signed$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__oe__oe$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__oe__ok$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__output_carry$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__output_cr$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__rc__ok$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__rc__rc$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_sr_op__write_cr0$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] pipe2_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \pipe2_xer_ca$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe2_xer_ca_ok$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rc; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \sr_op__fn_unit$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \sr_op__imm_data__data$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__imm_data__ok$50 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \sr_op__input_carry$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__input_cr$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \sr_op__insn$63 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \sr_op__insn_type$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__invert_in$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__is_32bit$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__is_signed$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__oe__oe$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__oe__ok$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__output_carry$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__output_cr$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__rc__ok$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__rc__rc$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__write_cr0$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] \xer_ca$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + \n$109 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$108 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + \pipe1$110 pipe1 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(pipe1_cr_a), + .cr_a_ok(pipe1_cr_a_ok), + .muxid(pipe1_muxid), + .\muxid$1 (\pipe1_muxid$2 ), + .n_ready_i(pipe1_n_ready_i), + .n_valid_o(pipe1_n_valid_o), + .o(pipe1_o), + .o_ok(pipe1_o_ok), + .p_ready_o(pipe1_p_ready_o), + .p_valid_i(pipe1_p_valid_i), + .ra(pipe1_ra), + .rb(pipe1_rb), + .rc(pipe1_rc), + .sr_op__fn_unit(pipe1_sr_op__fn_unit), + .\sr_op__fn_unit$3 (\pipe1_sr_op__fn_unit$4 ), + .sr_op__imm_data__data(pipe1_sr_op__imm_data__data), + .\sr_op__imm_data__data$4 (\pipe1_sr_op__imm_data__data$5 ), + .sr_op__imm_data__ok(pipe1_sr_op__imm_data__ok), + .\sr_op__imm_data__ok$5 (\pipe1_sr_op__imm_data__ok$6 ), + .sr_op__input_carry(pipe1_sr_op__input_carry), + .\sr_op__input_carry$12 (\pipe1_sr_op__input_carry$13 ), + .sr_op__input_cr(pipe1_sr_op__input_cr), + .\sr_op__input_cr$14 (\pipe1_sr_op__input_cr$15 ), + .sr_op__insn(pipe1_sr_op__insn), + .\sr_op__insn$18 (\pipe1_sr_op__insn$19 ), + .sr_op__insn_type(pipe1_sr_op__insn_type), + .\sr_op__insn_type$2 (\pipe1_sr_op__insn_type$3 ), + .sr_op__invert_in(pipe1_sr_op__invert_in), + .\sr_op__invert_in$11 (\pipe1_sr_op__invert_in$12 ), + .sr_op__is_32bit(pipe1_sr_op__is_32bit), + .\sr_op__is_32bit$16 (\pipe1_sr_op__is_32bit$17 ), + .sr_op__is_signed(pipe1_sr_op__is_signed), + .\sr_op__is_signed$17 (\pipe1_sr_op__is_signed$18 ), + .sr_op__oe__oe(pipe1_sr_op__oe__oe), + .\sr_op__oe__oe$8 (\pipe1_sr_op__oe__oe$9 ), + .sr_op__oe__ok(pipe1_sr_op__oe__ok), + .\sr_op__oe__ok$9 (\pipe1_sr_op__oe__ok$10 ), + .sr_op__output_carry(pipe1_sr_op__output_carry), + .\sr_op__output_carry$13 (\pipe1_sr_op__output_carry$14 ), + .sr_op__output_cr(pipe1_sr_op__output_cr), + .\sr_op__output_cr$15 (\pipe1_sr_op__output_cr$16 ), + .sr_op__rc__ok(pipe1_sr_op__rc__ok), + .\sr_op__rc__ok$7 (\pipe1_sr_op__rc__ok$8 ), + .sr_op__rc__rc(pipe1_sr_op__rc__rc), + .\sr_op__rc__rc$6 (\pipe1_sr_op__rc__rc$7 ), + .sr_op__write_cr0(pipe1_sr_op__write_cr0), + .\sr_op__write_cr0$10 (\pipe1_sr_op__write_cr0$11 ), + .xer_ca(pipe1_xer_ca), + .\xer_ca$20 (\pipe1_xer_ca$21 ), + .xer_ca_ok(pipe1_xer_ca_ok), + .xer_so(pipe1_xer_so), + .\xer_so$19 (\pipe1_xer_so$20 ), + .xer_so_ok(pipe1_xer_so_ok) + ); + \pipe2$115 pipe2 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(pipe2_cr_a), + .\cr_a$21 (\pipe2_cr_a$42 ), + .cr_a_ok(pipe2_cr_a_ok), + .\cr_a_ok$22 (\pipe2_cr_a_ok$43 ), + .muxid(pipe2_muxid), + .\muxid$1 (\pipe2_muxid$22 ), + .n_ready_i(pipe2_n_ready_i), + .n_valid_o(pipe2_n_valid_o), + .o(pipe2_o), + .\o$19 (\pipe2_o$40 ), + .o_ok(pipe2_o_ok), + .\o_ok$20 (\pipe2_o_ok$41 ), + .p_ready_o(pipe2_p_ready_o), + .p_valid_i(pipe2_p_valid_i), + .sr_op__fn_unit(pipe2_sr_op__fn_unit), + .\sr_op__fn_unit$3 (\pipe2_sr_op__fn_unit$24 ), + .sr_op__imm_data__data(pipe2_sr_op__imm_data__data), + .\sr_op__imm_data__data$4 (\pipe2_sr_op__imm_data__data$25 ), + .sr_op__imm_data__ok(pipe2_sr_op__imm_data__ok), + .\sr_op__imm_data__ok$5 (\pipe2_sr_op__imm_data__ok$26 ), + .sr_op__input_carry(pipe2_sr_op__input_carry), + .\sr_op__input_carry$12 (\pipe2_sr_op__input_carry$33 ), + .sr_op__input_cr(pipe2_sr_op__input_cr), + .\sr_op__input_cr$14 (\pipe2_sr_op__input_cr$35 ), + .sr_op__insn(pipe2_sr_op__insn), + .\sr_op__insn$18 (\pipe2_sr_op__insn$39 ), + .sr_op__insn_type(pipe2_sr_op__insn_type), + .\sr_op__insn_type$2 (\pipe2_sr_op__insn_type$23 ), + .sr_op__invert_in(pipe2_sr_op__invert_in), + .\sr_op__invert_in$11 (\pipe2_sr_op__invert_in$32 ), + .sr_op__is_32bit(pipe2_sr_op__is_32bit), + .\sr_op__is_32bit$16 (\pipe2_sr_op__is_32bit$37 ), + .sr_op__is_signed(pipe2_sr_op__is_signed), + .\sr_op__is_signed$17 (\pipe2_sr_op__is_signed$38 ), + .sr_op__oe__oe(pipe2_sr_op__oe__oe), + .\sr_op__oe__oe$8 (\pipe2_sr_op__oe__oe$29 ), + .sr_op__oe__ok(pipe2_sr_op__oe__ok), + .\sr_op__oe__ok$9 (\pipe2_sr_op__oe__ok$30 ), + .sr_op__output_carry(pipe2_sr_op__output_carry), + .\sr_op__output_carry$13 (\pipe2_sr_op__output_carry$34 ), + .sr_op__output_cr(pipe2_sr_op__output_cr), + .\sr_op__output_cr$15 (\pipe2_sr_op__output_cr$36 ), + .sr_op__rc__ok(pipe2_sr_op__rc__ok), + .\sr_op__rc__ok$7 (\pipe2_sr_op__rc__ok$28 ), + .sr_op__rc__rc(pipe2_sr_op__rc__rc), + .\sr_op__rc__rc$6 (\pipe2_sr_op__rc__rc$27 ), + .sr_op__write_cr0(pipe2_sr_op__write_cr0), + .\sr_op__write_cr0$10 (\pipe2_sr_op__write_cr0$31 ), + .xer_ca(pipe2_xer_ca), + .\xer_ca$23 (\pipe2_xer_ca$44 ), + .xer_ca_ok(pipe2_xer_ca_ok), + .\xer_ca_ok$24 (\pipe2_xer_ca_ok$45 ), + .xer_so(pipe2_xer_so), + .xer_so_ok(pipe2_xer_so_ok) + ); + assign muxid = 2'h0; + assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$45 , \pipe2_xer_ca$44 }; + assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$43 , \pipe2_cr_a$42 }; + assign { o_ok, o } = { \pipe2_o_ok$41 , \pipe2_o$40 }; + assign { \sr_op__insn$63 , \sr_op__is_signed$62 , \sr_op__is_32bit$61 , \sr_op__output_cr$60 , \sr_op__input_cr$59 , \sr_op__output_carry$58 , \sr_op__input_carry$57 , \sr_op__invert_in$56 , \sr_op__write_cr0$55 , \sr_op__oe__ok$54 , \sr_op__oe__oe$53 , \sr_op__rc__ok$52 , \sr_op__rc__rc$51 , \sr_op__imm_data__ok$50 , \sr_op__imm_data__data$49 , \sr_op__fn_unit$48 , \sr_op__insn_type$47 } = { \pipe2_sr_op__insn$39 , \pipe2_sr_op__is_signed$38 , \pipe2_sr_op__is_32bit$37 , \pipe2_sr_op__output_cr$36 , \pipe2_sr_op__input_cr$35 , \pipe2_sr_op__output_carry$34 , \pipe2_sr_op__input_carry$33 , \pipe2_sr_op__invert_in$32 , \pipe2_sr_op__write_cr0$31 , \pipe2_sr_op__oe__ok$30 , \pipe2_sr_op__oe__oe$29 , \pipe2_sr_op__rc__ok$28 , \pipe2_sr_op__rc__rc$27 , \pipe2_sr_op__imm_data__ok$26 , \pipe2_sr_op__imm_data__data$25 , \pipe2_sr_op__fn_unit$24 , \pipe2_sr_op__insn_type$23 }; + assign \muxid$46 = \pipe2_muxid$22 ; + assign pipe2_n_ready_i = n_ready_i; + assign n_valid_o = pipe2_n_valid_o; + assign \pipe1_xer_ca$21 = \xer_ca$1 ; + assign \pipe1_xer_so$20 = xer_so; + assign pipe1_rc = rc; + assign pipe1_rb = rb; + assign pipe1_ra = ra; + assign { \pipe1_sr_op__insn$19 , \pipe1_sr_op__is_signed$18 , \pipe1_sr_op__is_32bit$17 , \pipe1_sr_op__output_cr$16 , \pipe1_sr_op__input_cr$15 , \pipe1_sr_op__output_carry$14 , \pipe1_sr_op__input_carry$13 , \pipe1_sr_op__invert_in$12 , \pipe1_sr_op__write_cr0$11 , \pipe1_sr_op__oe__ok$10 , \pipe1_sr_op__oe__oe$9 , \pipe1_sr_op__rc__ok$8 , \pipe1_sr_op__rc__rc$7 , \pipe1_sr_op__imm_data__ok$6 , \pipe1_sr_op__imm_data__data$5 , \pipe1_sr_op__fn_unit$4 , \pipe1_sr_op__insn_type$3 } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign \pipe1_muxid$2 = 2'h0; + assign p_ready_o = pipe1_p_ready_o; + assign pipe1_p_valid_i = p_valid_i; + assign { pipe2_xer_ca_ok, pipe2_xer_ca } = { pipe1_xer_ca_ok, pipe1_xer_ca }; + assign { pipe2_xer_so_ok, pipe2_xer_so } = { pipe1_xer_so_ok, pipe1_xer_so }; + assign { pipe2_cr_a_ok, pipe2_cr_a } = { pipe1_cr_a_ok, pipe1_cr_a }; + assign { pipe2_o_ok, pipe2_o } = { pipe1_o_ok, pipe1_o }; + assign { pipe2_sr_op__insn, pipe2_sr_op__is_signed, pipe2_sr_op__is_32bit, pipe2_sr_op__output_cr, pipe2_sr_op__input_cr, pipe2_sr_op__output_carry, pipe2_sr_op__input_carry, pipe2_sr_op__invert_in, pipe2_sr_op__write_cr0, pipe2_sr_op__oe__ok, pipe2_sr_op__oe__oe, pipe2_sr_op__rc__ok, pipe2_sr_op__rc__rc, pipe2_sr_op__imm_data__ok, pipe2_sr_op__imm_data__data, pipe2_sr_op__fn_unit, pipe2_sr_op__insn_type } = { pipe1_sr_op__insn, pipe1_sr_op__is_signed, pipe1_sr_op__is_32bit, pipe1_sr_op__output_cr, pipe1_sr_op__input_cr, pipe1_sr_op__output_carry, pipe1_sr_op__input_carry, pipe1_sr_op__invert_in, pipe1_sr_op__write_cr0, pipe1_sr_op__oe__ok, pipe1_sr_op__oe__oe, pipe1_sr_op__rc__ok, pipe1_sr_op__rc__rc, pipe1_sr_op__imm_data__ok, pipe1_sr_op__imm_data__data, pipe1_sr_op__fn_unit, pipe1_sr_op__insn_type }; + assign pipe2_muxid = pipe1_muxid; + assign pipe1_n_ready_i = pipe2_p_ready_o; + assign pipe2_p_valid_i = pipe1_n_valid_o; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0" *) +(* generator = "nMigen" *) +module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \fast1$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \pipe_fast1$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_fast1_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe_muxid$6 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe_spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \pipe_spr1$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_spr1_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe_spr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe_spr_op__fn_unit$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe_spr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe_spr_op__insn$9 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe_spr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe_spr_op__insn_type$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe_spr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe_spr_op__is_32bit$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] pipe_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \pipe_xer_ca$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] pipe_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \pipe_xer_ov$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire pipe_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \pipe_xer_so$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \spr1$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr1_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] spr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \spr_op__fn_unit$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] spr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \spr_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] spr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \spr_op__insn_type$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input spr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \spr_op__is_32bit$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] \xer_ca$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] \xer_ov$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + \n$63 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$62 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + \pipe$64 pipe ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .fast1(pipe_fast1), + .\fast1$7 (\pipe_fast1$12 ), + .fast1_ok(pipe_fast1_ok), + .muxid(pipe_muxid), + .\muxid$1 (\pipe_muxid$6 ), + .n_ready_i(pipe_n_ready_i), + .n_valid_o(pipe_n_valid_o), + .o(pipe_o), + .o_ok(pipe_o_ok), + .p_ready_o(pipe_p_ready_o), + .p_valid_i(pipe_p_valid_i), + .ra(pipe_ra), + .spr1(pipe_spr1), + .\spr1$6 (\pipe_spr1$11 ), + .spr1_ok(pipe_spr1_ok), + .spr_op__fn_unit(pipe_spr_op__fn_unit), + .\spr_op__fn_unit$3 (\pipe_spr_op__fn_unit$8 ), + .spr_op__insn(pipe_spr_op__insn), + .\spr_op__insn$4 (\pipe_spr_op__insn$9 ), + .spr_op__insn_type(pipe_spr_op__insn_type), + .\spr_op__insn_type$2 (\pipe_spr_op__insn_type$7 ), + .spr_op__is_32bit(pipe_spr_op__is_32bit), + .\spr_op__is_32bit$5 (\pipe_spr_op__is_32bit$10 ), + .xer_ca(pipe_xer_ca), + .\xer_ca$10 (\pipe_xer_ca$15 ), + .xer_ca_ok(pipe_xer_ca_ok), + .xer_ov(pipe_xer_ov), + .\xer_ov$9 (\pipe_xer_ov$14 ), + .xer_ov_ok(pipe_xer_ov_ok), + .xer_so(pipe_xer_so), + .\xer_so$8 (\pipe_xer_so$13 ), + .xer_so_ok(pipe_xer_so_ok) + ); + assign muxid = 2'h0; + assign { xer_ca_ok, xer_ca } = { pipe_xer_ca_ok, \pipe_xer_ca$15 }; + assign { xer_ov_ok, xer_ov } = { pipe_xer_ov_ok, \pipe_xer_ov$14 }; + assign { xer_so_ok, xer_so } = { pipe_xer_so_ok, \pipe_xer_so$13 }; + assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$12 }; + assign { spr1_ok, spr1 } = { pipe_spr1_ok, \pipe_spr1$11 }; + assign { o_ok, o } = { pipe_o_ok, pipe_o }; + assign { \spr_op__is_32bit$20 , \spr_op__insn$19 , \spr_op__fn_unit$18 , \spr_op__insn_type$17 } = { \pipe_spr_op__is_32bit$10 , \pipe_spr_op__insn$9 , \pipe_spr_op__fn_unit$8 , \pipe_spr_op__insn_type$7 }; + assign \muxid$16 = \pipe_muxid$6 ; + assign pipe_n_ready_i = n_ready_i; + assign n_valid_o = pipe_n_valid_o; + assign pipe_xer_ca = \xer_ca$5 ; + assign pipe_xer_ov = \xer_ov$4 ; + assign pipe_xer_so = \xer_so$3 ; + assign pipe_fast1 = \fast1$2 ; + assign pipe_spr1 = \spr1$1 ; + assign pipe_ra = ra; + assign { pipe_spr_op__is_32bit, pipe_spr_op__insn, pipe_spr_op__fn_unit, pipe_spr_op__insn_type } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; + assign pipe_muxid = 2'h0; + assign p_ready_o = pipe_p_ready_o; + assign pipe_p_valid_i = p_valid_i; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0" *) +(* generator = "nMigen" *) +module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, o, fast1, fast2, nia, msr, ra, rb, \fast1$1 , \fast2$2 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \fast1$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \fast2$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output msr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$29 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \pipe1_fast1$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \pipe1_fast2$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe1_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe1_muxid$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe1_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe1_n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe1_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe1_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \pipe1_ra$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe1_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \pipe1_rb$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe1_trap_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe1_trap_op__cia$8 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe1_trap_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe1_trap_op__fn_unit$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe1_trap_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe1_trap_op__insn$6 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe1_trap_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe1_trap_op__insn_type$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe1_trap_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe1_trap_op__is_32bit$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] pipe1_trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \pipe1_trap_op__ldst_exc$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe1_trap_op__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe1_trap_op__msr$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] pipe1_trap_op__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] \pipe1_trap_op__trapaddr$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] pipe1_trap_op__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \pipe1_trap_op__traptype$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe2_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \pipe2_fast1$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe2_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \pipe2_fast2$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe2_msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_msr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] pipe2_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \pipe2_muxid$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire pipe2_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire pipe2_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe2_nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pipe2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pipe2_o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire pipe2_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire pipe2_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe2_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] pipe2_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe2_trap_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe2_trap_op__cia$22 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] pipe2_trap_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \pipe2_trap_op__fn_unit$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] pipe2_trap_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \pipe2_trap_op__insn$20 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] pipe2_trap_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \pipe2_trap_op__insn_type$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire pipe2_trap_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \pipe2_trap_op__is_32bit$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] pipe2_trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \pipe2_trap_op__ldst_exc$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] pipe2_trap_op__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \pipe2_trap_op__msr$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] pipe2_trap_op__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] \pipe2_trap_op__trapaddr$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] pipe2_trap_op__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \pipe2_trap_op__traptype$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] trap_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \trap_op__cia$34 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] trap_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \trap_op__fn_unit$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] trap_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \trap_op__insn$32 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] trap_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \trap_op__insn_type$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input trap_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \trap_op__is_32bit$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \trap_op__ldst_exc$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] trap_op__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \trap_op__msr$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [12:0] trap_op__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] \trap_op__trapaddr$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] trap_op__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \trap_op__traptype$36 ; + \n$31 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$30 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + \pipe1$32 pipe1 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .fast1(pipe1_fast1), + .\fast1$13 (\pipe1_fast1$15 ), + .fast2(pipe1_fast2), + .\fast2$14 (\pipe1_fast2$16 ), + .muxid(pipe1_muxid), + .\muxid$1 (\pipe1_muxid$3 ), + .n_ready_i(pipe1_n_ready_i), + .n_valid_o(pipe1_n_valid_o), + .p_ready_o(pipe1_p_ready_o), + .p_valid_i(pipe1_p_valid_i), + .ra(pipe1_ra), + .\ra$11 (\pipe1_ra$13 ), + .rb(pipe1_rb), + .\rb$12 (\pipe1_rb$14 ), + .trap_op__cia(pipe1_trap_op__cia), + .\trap_op__cia$6 (\pipe1_trap_op__cia$8 ), + .trap_op__fn_unit(pipe1_trap_op__fn_unit), + .\trap_op__fn_unit$3 (\pipe1_trap_op__fn_unit$5 ), + .trap_op__insn(pipe1_trap_op__insn), + .\trap_op__insn$4 (\pipe1_trap_op__insn$6 ), + .trap_op__insn_type(pipe1_trap_op__insn_type), + .\trap_op__insn_type$2 (\pipe1_trap_op__insn_type$4 ), + .trap_op__is_32bit(pipe1_trap_op__is_32bit), + .\trap_op__is_32bit$7 (\pipe1_trap_op__is_32bit$9 ), + .trap_op__ldst_exc(pipe1_trap_op__ldst_exc), + .\trap_op__ldst_exc$10 (\pipe1_trap_op__ldst_exc$12 ), + .trap_op__msr(pipe1_trap_op__msr), + .\trap_op__msr$5 (\pipe1_trap_op__msr$7 ), + .trap_op__trapaddr(pipe1_trap_op__trapaddr), + .\trap_op__trapaddr$9 (\pipe1_trap_op__trapaddr$11 ), + .trap_op__traptype(pipe1_trap_op__traptype), + .\trap_op__traptype$8 (\pipe1_trap_op__traptype$10 ) + ); + \pipe2$35 pipe2 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .fast1(pipe2_fast1), + .\fast1$11 (\pipe2_fast1$27 ), + .fast1_ok(pipe2_fast1_ok), + .fast2(pipe2_fast2), + .\fast2$12 (\pipe2_fast2$28 ), + .fast2_ok(pipe2_fast2_ok), + .msr(pipe2_msr), + .msr_ok(pipe2_msr_ok), + .muxid(pipe2_muxid), + .\muxid$1 (\pipe2_muxid$17 ), + .n_ready_i(pipe2_n_ready_i), + .n_valid_o(pipe2_n_valid_o), + .nia(pipe2_nia), + .nia_ok(pipe2_nia_ok), + .o(pipe2_o), + .o_ok(pipe2_o_ok), + .p_ready_o(pipe2_p_ready_o), + .p_valid_i(pipe2_p_valid_i), + .ra(pipe2_ra), + .rb(pipe2_rb), + .trap_op__cia(pipe2_trap_op__cia), + .\trap_op__cia$6 (\pipe2_trap_op__cia$22 ), + .trap_op__fn_unit(pipe2_trap_op__fn_unit), + .\trap_op__fn_unit$3 (\pipe2_trap_op__fn_unit$19 ), + .trap_op__insn(pipe2_trap_op__insn), + .\trap_op__insn$4 (\pipe2_trap_op__insn$20 ), + .trap_op__insn_type(pipe2_trap_op__insn_type), + .\trap_op__insn_type$2 (\pipe2_trap_op__insn_type$18 ), + .trap_op__is_32bit(pipe2_trap_op__is_32bit), + .\trap_op__is_32bit$7 (\pipe2_trap_op__is_32bit$23 ), + .trap_op__ldst_exc(pipe2_trap_op__ldst_exc), + .\trap_op__ldst_exc$10 (\pipe2_trap_op__ldst_exc$26 ), + .trap_op__msr(pipe2_trap_op__msr), + .\trap_op__msr$5 (\pipe2_trap_op__msr$21 ), + .trap_op__trapaddr(pipe2_trap_op__trapaddr), + .\trap_op__trapaddr$9 (\pipe2_trap_op__trapaddr$25 ), + .trap_op__traptype(pipe2_trap_op__traptype), + .\trap_op__traptype$8 (\pipe2_trap_op__traptype$24 ) + ); + assign muxid = 2'h0; + assign { msr_ok, msr } = { pipe2_msr_ok, pipe2_msr }; + assign { nia_ok, nia } = { pipe2_nia_ok, pipe2_nia }; + assign { fast2_ok, fast2 } = { pipe2_fast2_ok, \pipe2_fast2$28 }; + assign { fast1_ok, fast1 } = { pipe2_fast1_ok, \pipe2_fast1$27 }; + assign { o_ok, o } = { pipe2_o_ok, pipe2_o }; + assign { \trap_op__ldst_exc$38 , \trap_op__trapaddr$37 , \trap_op__traptype$36 , \trap_op__is_32bit$35 , \trap_op__cia$34 , \trap_op__msr$33 , \trap_op__insn$32 , \trap_op__fn_unit$31 , \trap_op__insn_type$30 } = { \pipe2_trap_op__ldst_exc$26 , \pipe2_trap_op__trapaddr$25 , \pipe2_trap_op__traptype$24 , \pipe2_trap_op__is_32bit$23 , \pipe2_trap_op__cia$22 , \pipe2_trap_op__msr$21 , \pipe2_trap_op__insn$20 , \pipe2_trap_op__fn_unit$19 , \pipe2_trap_op__insn_type$18 }; + assign \muxid$29 = \pipe2_muxid$17 ; + assign pipe2_n_ready_i = n_ready_i; + assign n_valid_o = pipe2_n_valid_o; + assign \pipe1_fast2$16 = \fast2$2 ; + assign \pipe1_fast1$15 = \fast1$1 ; + assign \pipe1_rb$14 = rb; + assign \pipe1_ra$13 = ra; + assign { \pipe1_trap_op__ldst_exc$12 , \pipe1_trap_op__trapaddr$11 , \pipe1_trap_op__traptype$10 , \pipe1_trap_op__is_32bit$9 , \pipe1_trap_op__cia$8 , \pipe1_trap_op__msr$7 , \pipe1_trap_op__insn$6 , \pipe1_trap_op__fn_unit$5 , \pipe1_trap_op__insn_type$4 } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; + assign \pipe1_muxid$3 = 2'h0; + assign p_ready_o = pipe1_p_ready_o; + assign pipe1_p_valid_i = p_valid_i; + assign pipe2_fast2 = pipe1_fast2; + assign pipe2_fast1 = pipe1_fast1; + assign pipe2_rb = pipe1_rb; + assign pipe2_ra = pipe1_ra; + assign { pipe2_trap_op__ldst_exc, pipe2_trap_op__trapaddr, pipe2_trap_op__traptype, pipe2_trap_op__is_32bit, pipe2_trap_op__cia, pipe2_trap_op__msr, pipe2_trap_op__insn, pipe2_trap_op__fn_unit, pipe2_trap_op__insn_type } = { pipe1_trap_op__ldst_exc, pipe1_trap_op__trapaddr, pipe1_trap_op__traptype, pipe1_trap_op__is_32bit, pipe1_trap_op__cia, pipe1_trap_op__msr, pipe1_trap_op__insn, pipe1_trap_op__fn_unit, pipe1_trap_op__insn_type }; + assign pipe2_muxid = pipe1_muxid; + assign pipe1_n_ready_i = pipe2_p_ready_o; + assign pipe2_p_valid_i = pipe1_n_valid_o; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alui_l" *) +(* generator = "nMigen" *) +module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alui_l" *) +(* generator = "nMigen" *) +module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alui_l" *) +(* generator = "nMigen" *) +module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alui_l" *) +(* generator = "nMigen" *) +module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alui_l" *) +(* generator = "nMigen" *) +module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alui_l" *) +(* generator = "nMigen" *) +module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alui_l" *) +(* generator = "nMigen" *) +module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alui_l" *) +(* generator = "nMigen" *) +module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alui_l" *) +(* generator = "nMigen" *) +module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_alui; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui; + assign \$15 = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_alui = \$15 ; + assign qn_alui = \$13 ; + assign q_alui = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" *) +(* generator = "nMigen" *) +module bpermd(rb, ra, rs); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *) + wire [7:0] idx_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *) + wire [7:0] idx_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *) + wire [7:0] idx_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *) + wire [7:0] idx_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *) + wire [7:0] idx_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *) + wire [7:0] idx_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *) + wire [7:0] idx_6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *) + wire [7:0] idx_7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" *) + reg [63:0] perm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" *) + output [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_15; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_16; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_17; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_18; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_19; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_20; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_21; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_22; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_23; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_24; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_25; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_26; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_27; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_28; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_29; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_30; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_31; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_33; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_34; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_35; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_36; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_37; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_38; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_39; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_40; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_41; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_42; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_43; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_44; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_45; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_46; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_47; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_48; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_49; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_50; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_51; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_52; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_53; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_54; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_55; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_56; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_57; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_58; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_59; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_60; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_61; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_62; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_63; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *) + wire rb64_9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" *) + input [63:0] rs; + assign \$9 = idx_4 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40; + assign \$11 = idx_5 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40; + assign \$13 = idx_6 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40; + assign \$15 = idx_7 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40; + assign \$1 = idx_0 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40; + assign \$3 = idx_1 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40; + assign \$5 = idx_2 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40; + assign \$7 = idx_3 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40; + always @* begin + if (\initial ) begin end + perm = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) + casez (idx_0) + 8'h00: + perm[0] = rb64_0; + 8'h01: + perm[0] = rb64_1; + 8'h02: + perm[0] = rb64_2; + 8'h03: + perm[0] = rb64_3; + 8'h04: + perm[0] = rb64_4; + 8'h05: + perm[0] = rb64_5; + 8'h06: + perm[0] = rb64_6; + 8'h07: + perm[0] = rb64_7; + 8'h08: + perm[0] = rb64_8; + 8'h09: + perm[0] = rb64_9; + 8'h0a: + perm[0] = rb64_10; + 8'h0b: + perm[0] = rb64_11; + 8'h0c: + perm[0] = rb64_12; + 8'h0d: + perm[0] = rb64_13; + 8'h0e: + perm[0] = rb64_14; + 8'h0f: + perm[0] = rb64_15; + 8'h10: + perm[0] = rb64_16; + 8'h11: + perm[0] = rb64_17; + 8'h12: + perm[0] = rb64_18; + 8'h13: + perm[0] = rb64_19; + 8'h14: + perm[0] = rb64_20; + 8'h15: + perm[0] = rb64_21; + 8'h16: + perm[0] = rb64_22; + 8'h17: + perm[0] = rb64_23; + 8'h18: + perm[0] = rb64_24; + 8'h19: + perm[0] = rb64_25; + 8'h1a: + perm[0] = rb64_26; + 8'h1b: + perm[0] = rb64_27; + 8'h1c: + perm[0] = rb64_28; + 8'h1d: + perm[0] = rb64_29; + 8'h1e: + perm[0] = rb64_30; + 8'h1f: + perm[0] = rb64_31; + 8'h20: + perm[0] = rb64_32; + 8'h21: + perm[0] = rb64_33; + 8'h22: + perm[0] = rb64_34; + 8'h23: + perm[0] = rb64_35; + 8'h24: + perm[0] = rb64_36; + 8'h25: + perm[0] = rb64_37; + 8'h26: + perm[0] = rb64_38; + 8'h27: + perm[0] = rb64_39; + 8'h28: + perm[0] = rb64_40; + 8'h29: + perm[0] = rb64_41; + 8'h2a: + perm[0] = rb64_42; + 8'h2b: + perm[0] = rb64_43; + 8'h2c: + perm[0] = rb64_44; + 8'h2d: + perm[0] = rb64_45; + 8'h2e: + perm[0] = rb64_46; + 8'h2f: + perm[0] = rb64_47; + 8'h30: + perm[0] = rb64_48; + 8'h31: + perm[0] = rb64_49; + 8'h32: + perm[0] = rb64_50; + 8'h33: + perm[0] = rb64_51; + 8'h34: + perm[0] = rb64_52; + 8'h35: + perm[0] = rb64_53; + 8'h36: + perm[0] = rb64_54; + 8'h37: + perm[0] = rb64_55; + 8'h38: + perm[0] = rb64_56; + 8'h39: + perm[0] = rb64_57; + 8'h3a: + perm[0] = rb64_58; + 8'h3b: + perm[0] = rb64_59; + 8'h3c: + perm[0] = rb64_60; + 8'h3d: + perm[0] = rb64_61; + 8'h3e: + perm[0] = rb64_62; + 8'h??: + perm[0] = rb64_63; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) + casez (idx_1) + 8'h00: + perm[1] = rb64_0; + 8'h01: + perm[1] = rb64_1; + 8'h02: + perm[1] = rb64_2; + 8'h03: + perm[1] = rb64_3; + 8'h04: + perm[1] = rb64_4; + 8'h05: + perm[1] = rb64_5; + 8'h06: + perm[1] = rb64_6; + 8'h07: + perm[1] = rb64_7; + 8'h08: + perm[1] = rb64_8; + 8'h09: + perm[1] = rb64_9; + 8'h0a: + perm[1] = rb64_10; + 8'h0b: + perm[1] = rb64_11; + 8'h0c: + perm[1] = rb64_12; + 8'h0d: + perm[1] = rb64_13; + 8'h0e: + perm[1] = rb64_14; + 8'h0f: + perm[1] = rb64_15; + 8'h10: + perm[1] = rb64_16; + 8'h11: + perm[1] = rb64_17; + 8'h12: + perm[1] = rb64_18; + 8'h13: + perm[1] = rb64_19; + 8'h14: + perm[1] = rb64_20; + 8'h15: + perm[1] = rb64_21; + 8'h16: + perm[1] = rb64_22; + 8'h17: + perm[1] = rb64_23; + 8'h18: + perm[1] = rb64_24; + 8'h19: + perm[1] = rb64_25; + 8'h1a: + perm[1] = rb64_26; + 8'h1b: + perm[1] = rb64_27; + 8'h1c: + perm[1] = rb64_28; + 8'h1d: + perm[1] = rb64_29; + 8'h1e: + perm[1] = rb64_30; + 8'h1f: + perm[1] = rb64_31; + 8'h20: + perm[1] = rb64_32; + 8'h21: + perm[1] = rb64_33; + 8'h22: + perm[1] = rb64_34; + 8'h23: + perm[1] = rb64_35; + 8'h24: + perm[1] = rb64_36; + 8'h25: + perm[1] = rb64_37; + 8'h26: + perm[1] = rb64_38; + 8'h27: + perm[1] = rb64_39; + 8'h28: + perm[1] = rb64_40; + 8'h29: + perm[1] = rb64_41; + 8'h2a: + perm[1] = rb64_42; + 8'h2b: + perm[1] = rb64_43; + 8'h2c: + perm[1] = rb64_44; + 8'h2d: + perm[1] = rb64_45; + 8'h2e: + perm[1] = rb64_46; + 8'h2f: + perm[1] = rb64_47; + 8'h30: + perm[1] = rb64_48; + 8'h31: + perm[1] = rb64_49; + 8'h32: + perm[1] = rb64_50; + 8'h33: + perm[1] = rb64_51; + 8'h34: + perm[1] = rb64_52; + 8'h35: + perm[1] = rb64_53; + 8'h36: + perm[1] = rb64_54; + 8'h37: + perm[1] = rb64_55; + 8'h38: + perm[1] = rb64_56; + 8'h39: + perm[1] = rb64_57; + 8'h3a: + perm[1] = rb64_58; + 8'h3b: + perm[1] = rb64_59; + 8'h3c: + perm[1] = rb64_60; + 8'h3d: + perm[1] = rb64_61; + 8'h3e: + perm[1] = rb64_62; + 8'h??: + perm[1] = rb64_63; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + casez (\$5 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) + casez (idx_2) + 8'h00: + perm[2] = rb64_0; + 8'h01: + perm[2] = rb64_1; + 8'h02: + perm[2] = rb64_2; + 8'h03: + perm[2] = rb64_3; + 8'h04: + perm[2] = rb64_4; + 8'h05: + perm[2] = rb64_5; + 8'h06: + perm[2] = rb64_6; + 8'h07: + perm[2] = rb64_7; + 8'h08: + perm[2] = rb64_8; + 8'h09: + perm[2] = rb64_9; + 8'h0a: + perm[2] = rb64_10; + 8'h0b: + perm[2] = rb64_11; + 8'h0c: + perm[2] = rb64_12; + 8'h0d: + perm[2] = rb64_13; + 8'h0e: + perm[2] = rb64_14; + 8'h0f: + perm[2] = rb64_15; + 8'h10: + perm[2] = rb64_16; + 8'h11: + perm[2] = rb64_17; + 8'h12: + perm[2] = rb64_18; + 8'h13: + perm[2] = rb64_19; + 8'h14: + perm[2] = rb64_20; + 8'h15: + perm[2] = rb64_21; + 8'h16: + perm[2] = rb64_22; + 8'h17: + perm[2] = rb64_23; + 8'h18: + perm[2] = rb64_24; + 8'h19: + perm[2] = rb64_25; + 8'h1a: + perm[2] = rb64_26; + 8'h1b: + perm[2] = rb64_27; + 8'h1c: + perm[2] = rb64_28; + 8'h1d: + perm[2] = rb64_29; + 8'h1e: + perm[2] = rb64_30; + 8'h1f: + perm[2] = rb64_31; + 8'h20: + perm[2] = rb64_32; + 8'h21: + perm[2] = rb64_33; + 8'h22: + perm[2] = rb64_34; + 8'h23: + perm[2] = rb64_35; + 8'h24: + perm[2] = rb64_36; + 8'h25: + perm[2] = rb64_37; + 8'h26: + perm[2] = rb64_38; + 8'h27: + perm[2] = rb64_39; + 8'h28: + perm[2] = rb64_40; + 8'h29: + perm[2] = rb64_41; + 8'h2a: + perm[2] = rb64_42; + 8'h2b: + perm[2] = rb64_43; + 8'h2c: + perm[2] = rb64_44; + 8'h2d: + perm[2] = rb64_45; + 8'h2e: + perm[2] = rb64_46; + 8'h2f: + perm[2] = rb64_47; + 8'h30: + perm[2] = rb64_48; + 8'h31: + perm[2] = rb64_49; + 8'h32: + perm[2] = rb64_50; + 8'h33: + perm[2] = rb64_51; + 8'h34: + perm[2] = rb64_52; + 8'h35: + perm[2] = rb64_53; + 8'h36: + perm[2] = rb64_54; + 8'h37: + perm[2] = rb64_55; + 8'h38: + perm[2] = rb64_56; + 8'h39: + perm[2] = rb64_57; + 8'h3a: + perm[2] = rb64_58; + 8'h3b: + perm[2] = rb64_59; + 8'h3c: + perm[2] = rb64_60; + 8'h3d: + perm[2] = rb64_61; + 8'h3e: + perm[2] = rb64_62; + 8'h??: + perm[2] = rb64_63; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + casez (\$7 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) + casez (idx_3) + 8'h00: + perm[3] = rb64_0; + 8'h01: + perm[3] = rb64_1; + 8'h02: + perm[3] = rb64_2; + 8'h03: + perm[3] = rb64_3; + 8'h04: + perm[3] = rb64_4; + 8'h05: + perm[3] = rb64_5; + 8'h06: + perm[3] = rb64_6; + 8'h07: + perm[3] = rb64_7; + 8'h08: + perm[3] = rb64_8; + 8'h09: + perm[3] = rb64_9; + 8'h0a: + perm[3] = rb64_10; + 8'h0b: + perm[3] = rb64_11; + 8'h0c: + perm[3] = rb64_12; + 8'h0d: + perm[3] = rb64_13; + 8'h0e: + perm[3] = rb64_14; + 8'h0f: + perm[3] = rb64_15; + 8'h10: + perm[3] = rb64_16; + 8'h11: + perm[3] = rb64_17; + 8'h12: + perm[3] = rb64_18; + 8'h13: + perm[3] = rb64_19; + 8'h14: + perm[3] = rb64_20; + 8'h15: + perm[3] = rb64_21; + 8'h16: + perm[3] = rb64_22; + 8'h17: + perm[3] = rb64_23; + 8'h18: + perm[3] = rb64_24; + 8'h19: + perm[3] = rb64_25; + 8'h1a: + perm[3] = rb64_26; + 8'h1b: + perm[3] = rb64_27; + 8'h1c: + perm[3] = rb64_28; + 8'h1d: + perm[3] = rb64_29; + 8'h1e: + perm[3] = rb64_30; + 8'h1f: + perm[3] = rb64_31; + 8'h20: + perm[3] = rb64_32; + 8'h21: + perm[3] = rb64_33; + 8'h22: + perm[3] = rb64_34; + 8'h23: + perm[3] = rb64_35; + 8'h24: + perm[3] = rb64_36; + 8'h25: + perm[3] = rb64_37; + 8'h26: + perm[3] = rb64_38; + 8'h27: + perm[3] = rb64_39; + 8'h28: + perm[3] = rb64_40; + 8'h29: + perm[3] = rb64_41; + 8'h2a: + perm[3] = rb64_42; + 8'h2b: + perm[3] = rb64_43; + 8'h2c: + perm[3] = rb64_44; + 8'h2d: + perm[3] = rb64_45; + 8'h2e: + perm[3] = rb64_46; + 8'h2f: + perm[3] = rb64_47; + 8'h30: + perm[3] = rb64_48; + 8'h31: + perm[3] = rb64_49; + 8'h32: + perm[3] = rb64_50; + 8'h33: + perm[3] = rb64_51; + 8'h34: + perm[3] = rb64_52; + 8'h35: + perm[3] = rb64_53; + 8'h36: + perm[3] = rb64_54; + 8'h37: + perm[3] = rb64_55; + 8'h38: + perm[3] = rb64_56; + 8'h39: + perm[3] = rb64_57; + 8'h3a: + perm[3] = rb64_58; + 8'h3b: + perm[3] = rb64_59; + 8'h3c: + perm[3] = rb64_60; + 8'h3d: + perm[3] = rb64_61; + 8'h3e: + perm[3] = rb64_62; + 8'h??: + perm[3] = rb64_63; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) + casez (idx_4) + 8'h00: + perm[4] = rb64_0; + 8'h01: + perm[4] = rb64_1; + 8'h02: + perm[4] = rb64_2; + 8'h03: + perm[4] = rb64_3; + 8'h04: + perm[4] = rb64_4; + 8'h05: + perm[4] = rb64_5; + 8'h06: + perm[4] = rb64_6; + 8'h07: + perm[4] = rb64_7; + 8'h08: + perm[4] = rb64_8; + 8'h09: + perm[4] = rb64_9; + 8'h0a: + perm[4] = rb64_10; + 8'h0b: + perm[4] = rb64_11; + 8'h0c: + perm[4] = rb64_12; + 8'h0d: + perm[4] = rb64_13; + 8'h0e: + perm[4] = rb64_14; + 8'h0f: + perm[4] = rb64_15; + 8'h10: + perm[4] = rb64_16; + 8'h11: + perm[4] = rb64_17; + 8'h12: + perm[4] = rb64_18; + 8'h13: + perm[4] = rb64_19; + 8'h14: + perm[4] = rb64_20; + 8'h15: + perm[4] = rb64_21; + 8'h16: + perm[4] = rb64_22; + 8'h17: + perm[4] = rb64_23; + 8'h18: + perm[4] = rb64_24; + 8'h19: + perm[4] = rb64_25; + 8'h1a: + perm[4] = rb64_26; + 8'h1b: + perm[4] = rb64_27; + 8'h1c: + perm[4] = rb64_28; + 8'h1d: + perm[4] = rb64_29; + 8'h1e: + perm[4] = rb64_30; + 8'h1f: + perm[4] = rb64_31; + 8'h20: + perm[4] = rb64_32; + 8'h21: + perm[4] = rb64_33; + 8'h22: + perm[4] = rb64_34; + 8'h23: + perm[4] = rb64_35; + 8'h24: + perm[4] = rb64_36; + 8'h25: + perm[4] = rb64_37; + 8'h26: + perm[4] = rb64_38; + 8'h27: + perm[4] = rb64_39; + 8'h28: + perm[4] = rb64_40; + 8'h29: + perm[4] = rb64_41; + 8'h2a: + perm[4] = rb64_42; + 8'h2b: + perm[4] = rb64_43; + 8'h2c: + perm[4] = rb64_44; + 8'h2d: + perm[4] = rb64_45; + 8'h2e: + perm[4] = rb64_46; + 8'h2f: + perm[4] = rb64_47; + 8'h30: + perm[4] = rb64_48; + 8'h31: + perm[4] = rb64_49; + 8'h32: + perm[4] = rb64_50; + 8'h33: + perm[4] = rb64_51; + 8'h34: + perm[4] = rb64_52; + 8'h35: + perm[4] = rb64_53; + 8'h36: + perm[4] = rb64_54; + 8'h37: + perm[4] = rb64_55; + 8'h38: + perm[4] = rb64_56; + 8'h39: + perm[4] = rb64_57; + 8'h3a: + perm[4] = rb64_58; + 8'h3b: + perm[4] = rb64_59; + 8'h3c: + perm[4] = rb64_60; + 8'h3d: + perm[4] = rb64_61; + 8'h3e: + perm[4] = rb64_62; + 8'h??: + perm[4] = rb64_63; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + casez (\$11 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) + casez (idx_5) + 8'h00: + perm[5] = rb64_0; + 8'h01: + perm[5] = rb64_1; + 8'h02: + perm[5] = rb64_2; + 8'h03: + perm[5] = rb64_3; + 8'h04: + perm[5] = rb64_4; + 8'h05: + perm[5] = rb64_5; + 8'h06: + perm[5] = rb64_6; + 8'h07: + perm[5] = rb64_7; + 8'h08: + perm[5] = rb64_8; + 8'h09: + perm[5] = rb64_9; + 8'h0a: + perm[5] = rb64_10; + 8'h0b: + perm[5] = rb64_11; + 8'h0c: + perm[5] = rb64_12; + 8'h0d: + perm[5] = rb64_13; + 8'h0e: + perm[5] = rb64_14; + 8'h0f: + perm[5] = rb64_15; + 8'h10: + perm[5] = rb64_16; + 8'h11: + perm[5] = rb64_17; + 8'h12: + perm[5] = rb64_18; + 8'h13: + perm[5] = rb64_19; + 8'h14: + perm[5] = rb64_20; + 8'h15: + perm[5] = rb64_21; + 8'h16: + perm[5] = rb64_22; + 8'h17: + perm[5] = rb64_23; + 8'h18: + perm[5] = rb64_24; + 8'h19: + perm[5] = rb64_25; + 8'h1a: + perm[5] = rb64_26; + 8'h1b: + perm[5] = rb64_27; + 8'h1c: + perm[5] = rb64_28; + 8'h1d: + perm[5] = rb64_29; + 8'h1e: + perm[5] = rb64_30; + 8'h1f: + perm[5] = rb64_31; + 8'h20: + perm[5] = rb64_32; + 8'h21: + perm[5] = rb64_33; + 8'h22: + perm[5] = rb64_34; + 8'h23: + perm[5] = rb64_35; + 8'h24: + perm[5] = rb64_36; + 8'h25: + perm[5] = rb64_37; + 8'h26: + perm[5] = rb64_38; + 8'h27: + perm[5] = rb64_39; + 8'h28: + perm[5] = rb64_40; + 8'h29: + perm[5] = rb64_41; + 8'h2a: + perm[5] = rb64_42; + 8'h2b: + perm[5] = rb64_43; + 8'h2c: + perm[5] = rb64_44; + 8'h2d: + perm[5] = rb64_45; + 8'h2e: + perm[5] = rb64_46; + 8'h2f: + perm[5] = rb64_47; + 8'h30: + perm[5] = rb64_48; + 8'h31: + perm[5] = rb64_49; + 8'h32: + perm[5] = rb64_50; + 8'h33: + perm[5] = rb64_51; + 8'h34: + perm[5] = rb64_52; + 8'h35: + perm[5] = rb64_53; + 8'h36: + perm[5] = rb64_54; + 8'h37: + perm[5] = rb64_55; + 8'h38: + perm[5] = rb64_56; + 8'h39: + perm[5] = rb64_57; + 8'h3a: + perm[5] = rb64_58; + 8'h3b: + perm[5] = rb64_59; + 8'h3c: + perm[5] = rb64_60; + 8'h3d: + perm[5] = rb64_61; + 8'h3e: + perm[5] = rb64_62; + 8'h??: + perm[5] = rb64_63; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) + casez (idx_6) + 8'h00: + perm[6] = rb64_0; + 8'h01: + perm[6] = rb64_1; + 8'h02: + perm[6] = rb64_2; + 8'h03: + perm[6] = rb64_3; + 8'h04: + perm[6] = rb64_4; + 8'h05: + perm[6] = rb64_5; + 8'h06: + perm[6] = rb64_6; + 8'h07: + perm[6] = rb64_7; + 8'h08: + perm[6] = rb64_8; + 8'h09: + perm[6] = rb64_9; + 8'h0a: + perm[6] = rb64_10; + 8'h0b: + perm[6] = rb64_11; + 8'h0c: + perm[6] = rb64_12; + 8'h0d: + perm[6] = rb64_13; + 8'h0e: + perm[6] = rb64_14; + 8'h0f: + perm[6] = rb64_15; + 8'h10: + perm[6] = rb64_16; + 8'h11: + perm[6] = rb64_17; + 8'h12: + perm[6] = rb64_18; + 8'h13: + perm[6] = rb64_19; + 8'h14: + perm[6] = rb64_20; + 8'h15: + perm[6] = rb64_21; + 8'h16: + perm[6] = rb64_22; + 8'h17: + perm[6] = rb64_23; + 8'h18: + perm[6] = rb64_24; + 8'h19: + perm[6] = rb64_25; + 8'h1a: + perm[6] = rb64_26; + 8'h1b: + perm[6] = rb64_27; + 8'h1c: + perm[6] = rb64_28; + 8'h1d: + perm[6] = rb64_29; + 8'h1e: + perm[6] = rb64_30; + 8'h1f: + perm[6] = rb64_31; + 8'h20: + perm[6] = rb64_32; + 8'h21: + perm[6] = rb64_33; + 8'h22: + perm[6] = rb64_34; + 8'h23: + perm[6] = rb64_35; + 8'h24: + perm[6] = rb64_36; + 8'h25: + perm[6] = rb64_37; + 8'h26: + perm[6] = rb64_38; + 8'h27: + perm[6] = rb64_39; + 8'h28: + perm[6] = rb64_40; + 8'h29: + perm[6] = rb64_41; + 8'h2a: + perm[6] = rb64_42; + 8'h2b: + perm[6] = rb64_43; + 8'h2c: + perm[6] = rb64_44; + 8'h2d: + perm[6] = rb64_45; + 8'h2e: + perm[6] = rb64_46; + 8'h2f: + perm[6] = rb64_47; + 8'h30: + perm[6] = rb64_48; + 8'h31: + perm[6] = rb64_49; + 8'h32: + perm[6] = rb64_50; + 8'h33: + perm[6] = rb64_51; + 8'h34: + perm[6] = rb64_52; + 8'h35: + perm[6] = rb64_53; + 8'h36: + perm[6] = rb64_54; + 8'h37: + perm[6] = rb64_55; + 8'h38: + perm[6] = rb64_56; + 8'h39: + perm[6] = rb64_57; + 8'h3a: + perm[6] = rb64_58; + 8'h3b: + perm[6] = rb64_59; + 8'h3c: + perm[6] = rb64_60; + 8'h3d: + perm[6] = rb64_61; + 8'h3e: + perm[6] = rb64_62; + 8'h??: + perm[6] = rb64_63; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) + casez (idx_7) + 8'h00: + perm[7] = rb64_0; + 8'h01: + perm[7] = rb64_1; + 8'h02: + perm[7] = rb64_2; + 8'h03: + perm[7] = rb64_3; + 8'h04: + perm[7] = rb64_4; + 8'h05: + perm[7] = rb64_5; + 8'h06: + perm[7] = rb64_6; + 8'h07: + perm[7] = rb64_7; + 8'h08: + perm[7] = rb64_8; + 8'h09: + perm[7] = rb64_9; + 8'h0a: + perm[7] = rb64_10; + 8'h0b: + perm[7] = rb64_11; + 8'h0c: + perm[7] = rb64_12; + 8'h0d: + perm[7] = rb64_13; + 8'h0e: + perm[7] = rb64_14; + 8'h0f: + perm[7] = rb64_15; + 8'h10: + perm[7] = rb64_16; + 8'h11: + perm[7] = rb64_17; + 8'h12: + perm[7] = rb64_18; + 8'h13: + perm[7] = rb64_19; + 8'h14: + perm[7] = rb64_20; + 8'h15: + perm[7] = rb64_21; + 8'h16: + perm[7] = rb64_22; + 8'h17: + perm[7] = rb64_23; + 8'h18: + perm[7] = rb64_24; + 8'h19: + perm[7] = rb64_25; + 8'h1a: + perm[7] = rb64_26; + 8'h1b: + perm[7] = rb64_27; + 8'h1c: + perm[7] = rb64_28; + 8'h1d: + perm[7] = rb64_29; + 8'h1e: + perm[7] = rb64_30; + 8'h1f: + perm[7] = rb64_31; + 8'h20: + perm[7] = rb64_32; + 8'h21: + perm[7] = rb64_33; + 8'h22: + perm[7] = rb64_34; + 8'h23: + perm[7] = rb64_35; + 8'h24: + perm[7] = rb64_36; + 8'h25: + perm[7] = rb64_37; + 8'h26: + perm[7] = rb64_38; + 8'h27: + perm[7] = rb64_39; + 8'h28: + perm[7] = rb64_40; + 8'h29: + perm[7] = rb64_41; + 8'h2a: + perm[7] = rb64_42; + 8'h2b: + perm[7] = rb64_43; + 8'h2c: + perm[7] = rb64_44; + 8'h2d: + perm[7] = rb64_45; + 8'h2e: + perm[7] = rb64_46; + 8'h2f: + perm[7] = rb64_47; + 8'h30: + perm[7] = rb64_48; + 8'h31: + perm[7] = rb64_49; + 8'h32: + perm[7] = rb64_50; + 8'h33: + perm[7] = rb64_51; + 8'h34: + perm[7] = rb64_52; + 8'h35: + perm[7] = rb64_53; + 8'h36: + perm[7] = rb64_54; + 8'h37: + perm[7] = rb64_55; + 8'h38: + perm[7] = rb64_56; + 8'h39: + perm[7] = rb64_57; + 8'h3a: + perm[7] = rb64_58; + 8'h3b: + perm[7] = rb64_59; + 8'h3c: + perm[7] = rb64_60; + 8'h3d: + perm[7] = rb64_61; + 8'h3e: + perm[7] = rb64_62; + 8'h??: + perm[7] = rb64_63; + endcase + endcase + end + assign ra[7:0] = perm[7:0]; + assign ra[63:8] = 56'h00000000000000; + assign idx_7 = rs[63:56]; + assign idx_6 = rs[55:48]; + assign idx_5 = rs[47:40]; + assign idx_4 = rs[39:32]; + assign idx_3 = rs[31:24]; + assign idx_2 = rs[23:16]; + assign idx_1 = rs[15:8]; + assign idx_0 = rs[7:0]; + assign rb64_63 = rb[0]; + assign rb64_62 = rb[1]; + assign rb64_61 = rb[2]; + assign rb64_60 = rb[3]; + assign rb64_59 = rb[4]; + assign rb64_58 = rb[5]; + assign rb64_57 = rb[6]; + assign rb64_56 = rb[7]; + assign rb64_55 = rb[8]; + assign rb64_54 = rb[9]; + assign rb64_53 = rb[10]; + assign rb64_52 = rb[11]; + assign rb64_51 = rb[12]; + assign rb64_50 = rb[13]; + assign rb64_49 = rb[14]; + assign rb64_48 = rb[15]; + assign rb64_47 = rb[16]; + assign rb64_46 = rb[17]; + assign rb64_45 = rb[18]; + assign rb64_44 = rb[19]; + assign rb64_43 = rb[20]; + assign rb64_42 = rb[21]; + assign rb64_41 = rb[22]; + assign rb64_40 = rb[23]; + assign rb64_39 = rb[24]; + assign rb64_38 = rb[25]; + assign rb64_37 = rb[26]; + assign rb64_36 = rb[27]; + assign rb64_35 = rb[28]; + assign rb64_34 = rb[29]; + assign rb64_33 = rb[30]; + assign rb64_32 = rb[31]; + assign rb64_31 = rb[32]; + assign rb64_30 = rb[33]; + assign rb64_29 = rb[34]; + assign rb64_28 = rb[35]; + assign rb64_27 = rb[36]; + assign rb64_26 = rb[37]; + assign rb64_25 = rb[38]; + assign rb64_24 = rb[39]; + assign rb64_23 = rb[40]; + assign rb64_22 = rb[41]; + assign rb64_21 = rb[42]; + assign rb64_20 = rb[43]; + assign rb64_19 = rb[44]; + assign rb64_18 = rb[45]; + assign rb64_17 = rb[46]; + assign rb64_16 = rb[47]; + assign rb64_15 = rb[48]; + assign rb64_14 = rb[49]; + assign rb64_13 = rb[50]; + assign rb64_12 = rb[51]; + assign rb64_11 = rb[52]; + assign rb64_10 = rb[53]; + assign rb64_9 = rb[54]; + assign rb64_8 = rb[55]; + assign rb64_7 = rb[56]; + assign rb64_6 = rb[57]; + assign rb64_5 = rb[58]; + assign rb64_4 = rb[59]; + assign rb64_3 = rb[60]; + assign rb64_2 = rb[61]; + assign rb64_1 = rb[62]; + assign rb64_0 = rb[63]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0" *) +(* generator = "nMigen" *) +module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src3_i, src1_i, src2_i, fast1_ok, cu_wr__rel_o, cu_wr__go_i, fast2_ok, dest1_o, dest2_o, nia_ok, dest3_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [2:0] \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [2:0] \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [2:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [2:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [2:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [2:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [2:0] \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [2:0] \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [2:0] \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [2:0] \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [2:0] \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [2:0] \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$83 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [3:0] \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_branch0_br_op__cia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_branch0_br_op__cia$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_branch0_br_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_branch0_br_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_branch0_br_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_branch0_br_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_branch0_br_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_branch0_br_op__imm_data__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_branch0_br_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_branch0_br_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_branch0_br_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_branch0_br_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_branch0_br_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_branch0_br_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_branch0_br_op__lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_branch0_br_op__lk$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] alu_branch0_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_branch0_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \alu_branch0_fast1$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_branch0_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \alu_branch0_fast2$2 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_branch0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_branch0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_branch0_nia; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_branch0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_branch0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [2:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [2:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__fast1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__fast1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__fast1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r1__fast2 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r1__fast2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__fast2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__fast2_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r2__nia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r2__nia$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r2__nia_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r2__nia_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest2_o; + reg [63:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest3_o; + reg [63:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_branch0__cia; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_branch0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_branch0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_branch0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_branch0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_branch0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_branch0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_branch0__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [2:0] prev_wr_go = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [2:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [2:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] req_l_r_req = 3'h7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] req_l_s_req = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [2:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [2:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [3:0] src3_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [2:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] src_l_r_src = 3'h7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] src_l_s_src = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] src_or_imm; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [3:0] src_r2 = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [3:0] \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire src_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + assign \$5 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ; + assign \$99 = \$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$97 ; + assign \$101 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$103 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$105 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$107 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$101 , \$103 , \$105 }; + assign \$109 = \$107 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$111 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$113 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$115 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$15 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ; + assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$19 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ; + assign \$21 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$27 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ; + assign \$24 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; + assign \$31 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; + assign \$33 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$35 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ; + assign \$3 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_branch0_n_ready_i; + assign \$41 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ; + assign \$43 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$45 = \$43 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$47 = \$41 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ; + assign \$49 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$51 = \$49 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_branch0_n_ready_i; + assign \$53 = \$51 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_branch0_n_valid_o; + assign \$55 = \$53 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$57 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$59 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$61 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$63 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$65 = alu_branch0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$67 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$69 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$71 = fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$73 = fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$75 = nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$77 = alu_branch0_br_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1]; + assign \$79 = alu_branch0_br_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_branch0_br_op__imm_data__data : src2_i; + assign \$81 = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0; + assign \$83 = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r1; + assign \$85 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$87 = alu_branch0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$8 = \$6 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$89 = alu_branch0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$91 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$93 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_branch0_br_op__imm_data__ok; + assign \$95 = \$91 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 1'h1, \$93 , 1'h1 }; + assign \$97 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r2__nia <= \data_r2__nia$next ; + always @(posedge coresync_clk) + data_r2__nia_ok <= \data_r2__nia_ok$next ; + always @(posedge coresync_clk) + data_r1__fast2 <= \data_r1__fast2$next ; + always @(posedge coresync_clk) + data_r1__fast2_ok <= \data_r1__fast2_ok$next ; + always @(posedge coresync_clk) + data_r0__fast1 <= \data_r0__fast1$next ; + always @(posedge coresync_clk) + data_r0__fast1_ok <= \data_r0__fast1_ok$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__cia <= \alu_branch0_br_op__cia$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__insn_type <= \alu_branch0_br_op__insn_type$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__fn_unit <= \alu_branch0_br_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__insn <= \alu_branch0_br_op__insn$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__imm_data__data <= \alu_branch0_br_op__imm_data__data$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__imm_data__ok <= \alu_branch0_br_op__imm_data__ok$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__lk <= \alu_branch0_br_op__lk$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__is_32bit <= \alu_branch0_br_op__is_32bit$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_branch0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$11 ; + alu_branch0 alu_branch0 ( + .br_op__cia(alu_branch0_br_op__cia), + .br_op__fn_unit(alu_branch0_br_op__fn_unit), + .br_op__imm_data__data(alu_branch0_br_op__imm_data__data), + .br_op__imm_data__ok(alu_branch0_br_op__imm_data__ok), + .br_op__insn(alu_branch0_br_op__insn), + .br_op__insn_type(alu_branch0_br_op__insn_type), + .br_op__is_32bit(alu_branch0_br_op__is_32bit), + .br_op__lk(alu_branch0_br_op__lk), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(alu_branch0_cr_a), + .fast1(alu_branch0_fast1), + .\fast1$1 (\alu_branch0_fast1$1 ), + .fast1_ok(fast1_ok), + .fast2(alu_branch0_fast2), + .\fast2$2 (\alu_branch0_fast2$2 ), + .fast2_ok(fast2_ok), + .n_ready_i(alu_branch0_n_ready_i), + .n_valid_o(alu_branch0_n_valid_o), + .nia(alu_branch0_nia), + .nia_ok(nia_ok), + .p_ready_o(alu_branch0_p_ready_o), + .p_valid_i(alu_branch0_p_valid_i) + ); + \alu_l$29 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + \alui_l$28 alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + \opc_l$24 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \req_l$25 req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + \rok_l$27 rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + \rst_l$26 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$23 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$55 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$65 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$67 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$69 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \alu_branch0_br_op__cia$next = alu_branch0_br_op__cia; + \alu_branch0_br_op__insn_type$next = alu_branch0_br_op__insn_type; + \alu_branch0_br_op__fn_unit$next = alu_branch0_br_op__fn_unit; + \alu_branch0_br_op__insn$next = alu_branch0_br_op__insn; + \alu_branch0_br_op__imm_data__data$next = alu_branch0_br_op__imm_data__data; + \alu_branch0_br_op__imm_data__ok$next = alu_branch0_br_op__imm_data__ok; + \alu_branch0_br_op__lk$next = alu_branch0_br_op__lk; + \alu_branch0_br_op__is_32bit$next = alu_branch0_br_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_branch0_br_op__is_32bit$next , \alu_branch0_br_op__lk$next , \alu_branch0_br_op__imm_data__ok$next , \alu_branch0_br_op__imm_data__data$next , \alu_branch0_br_op__insn$next , \alu_branch0_br_op__fn_unit$next , \alu_branch0_br_op__insn_type$next , \alu_branch0_br_op__cia$next } = { oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__lk, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__insn, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__cia }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \alu_branch0_br_op__imm_data__data$next = 64'h0000000000000000; + \alu_branch0_br_op__imm_data__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__fast1$next = data_r0__fast1; + \data_r0__fast1_ok$next = data_r0__fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__fast1_ok$next , \data_r0__fast1$next } = { fast1_ok, alu_branch0_fast1 }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__fast1_ok$next , \data_r0__fast1$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__fast1_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__fast2$next = data_r1__fast2; + \data_r1__fast2_ok$next = data_r1__fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__fast2_ok$next , \data_r1__fast2$next } = { fast2_ok, alu_branch0_fast2 }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__fast2_ok$next , \data_r1__fast2$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__fast2_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r2__nia$next = data_r2__nia; + \data_r2__nia_ok$next = data_r2__nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r2__nia_ok$next , \data_r2__nia$next } = { nia_ok, alu_branch0_nia }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r2__nia_ok$next , \data_r2__nia$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r2__nia_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[0]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src1_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_sel) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = src_or_imm; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$87 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$89 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$111 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__fast1; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$113 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__fast2; + endcase + end + always @* begin + if (\initial ) begin end + dest3_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$115 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest3_o = data_r2__nia; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$21 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 3'h0; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$109 ; + assign cu_rd__rel_o = \$99 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_branch0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_branch0_p_valid_i = alui_l_q_alui; + assign alu_branch0_cr_a = \$85 ; + assign \alu_branch0_fast2$2 = \$83 ; + assign \alu_branch0_fast1$1 = \$81 ; + assign src_or_imm = \$79 ; + assign src_sel = \$77 ; + assign cu_wrmask_o = { \$75 , \$73 , \$71 }; + assign reset_r = \$63 ; + assign reset_w = \$61 ; + assign rst_r = \$59 ; + assign reset = \$57 ; + assign wr_any = \$37 ; + assign cu_done_o = \$31 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$19 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_branch0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$15 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.busy_l" *) +(* generator = "nMigen" *) +module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_busy; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_busy; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_busy; + assign \$15 = q_busy | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_busy; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_busy; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_busy; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_busy = \$15 ; + assign qn_busy = \$13 ; + assign q_busy = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" *) +(* generator = "nMigen" *) +module clz(lz, sig_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [3:0] \$101 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [3:0] \$107 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [3:0] \$113 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$117 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [3:0] \$119 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [3:0] \$125 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$127 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$129 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [3:0] \$131 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$133 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$135 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [3:0] \$137 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$139 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$141 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [3:0] \$143 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$145 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$147 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [4:0] \$149 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$151 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$153 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [4:0] \$155 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$157 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$159 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [4:0] \$161 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$163 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$165 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [4:0] \$167 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$169 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$171 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [5:0] \$173 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$175 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$177 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [5:0] \$179 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$181 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$183 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [6:0] \$185 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$29 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$35 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$47 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$53 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$65 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$71 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$77 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$83 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$89 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) + wire [2:0] \$95 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_10; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_11; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_12; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_13; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_14; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_15; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_16; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_17; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_18; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_19; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_20; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_21; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_22; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_23; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_24; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_25; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_26; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_27; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_28; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_29; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_30; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_31; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_5; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_8; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *) + reg [1:0] cnt_1_9; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_10; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_12; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_14; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_16; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_18; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_20; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_22; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_24; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_26; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_28; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_30; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [2:0] cnt_2_8; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [3:0] cnt_3_0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [3:0] cnt_3_10; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [3:0] cnt_3_12; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [3:0] cnt_3_14; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [3:0] cnt_3_2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [3:0] cnt_3_4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [3:0] cnt_3_6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [3:0] cnt_3_8; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [4:0] cnt_4_0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [4:0] cnt_4_2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [4:0] cnt_4_4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [4:0] cnt_4_6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [5:0] cnt_5_0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [5:0] cnt_5_2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *) + reg [6:0] cnt_6_0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) + output [6:0] lz; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair10; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair12; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair14; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair16; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair18; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair20; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair22; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair24; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair26; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair28; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair30; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair32; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair34; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair36; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair38; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair40; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair42; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair44; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair46; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair48; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair50; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair52; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair54; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair56; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair58; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair60; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair62; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *) + wire [1:0] pair8; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" *) + input [63:0] sig_in; + assign \$9 = cnt_1_2[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$99 = cnt_2_0[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$101 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_2_0[1:0] }; + assign \$103 = cnt_2_6[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$105 = cnt_2_4[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$107 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_2_4[1:0] }; + assign \$109 = cnt_2_10[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$111 = cnt_2_8[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$113 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_2_8[1:0] }; + assign \$115 = cnt_2_14[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$117 = cnt_2_12[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_2[0] }; + assign \$119 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_2_12[1:0] }; + assign \$121 = cnt_2_18[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$123 = cnt_2_16[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$125 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_2_16[1:0] }; + assign \$127 = cnt_2_22[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$129 = cnt_2_20[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$131 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_2_20[1:0] }; + assign \$133 = cnt_2_26[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$135 = cnt_2_24[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$137 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_2_24[1:0] }; + assign \$13 = cnt_1_5[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$139 = cnt_2_30[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$141 = cnt_2_28[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$143 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_2_28[1:0] }; + assign \$145 = cnt_3_2[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$147 = cnt_3_0[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$149 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_3_0[2:0] }; + assign \$151 = cnt_3_6[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$153 = cnt_3_4[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$155 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_3_4[2:0] }; + assign \$157 = cnt_3_10[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$15 = cnt_1_4[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$159 = cnt_3_8[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$161 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_3_8[2:0] }; + assign \$163 = cnt_3_14[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$165 = cnt_3_12[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$167 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_3_12[2:0] }; + assign \$169 = cnt_4_2[4] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$171 = cnt_4_0[4] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$173 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_4_0[3:0] }; + assign \$175 = cnt_4_6[4] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$177 = cnt_4_4[4] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$17 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_4[0] }; + assign \$179 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_4_4[3:0] }; + assign \$181 = cnt_5_2[5] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$183 = cnt_5_0[5] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$185 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_5_0[4:0] }; + assign \$1 = cnt_1_1[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$19 = cnt_1_7[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$21 = cnt_1_6[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$23 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_6[0] }; + assign \$25 = cnt_1_9[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$27 = cnt_1_8[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$29 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_8[0] }; + assign \$31 = cnt_1_11[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$33 = cnt_1_10[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$35 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_10[0] }; + assign \$37 = cnt_1_13[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$3 = cnt_1_0[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$39 = cnt_1_12[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$41 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_12[0] }; + assign \$43 = cnt_1_15[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$45 = cnt_1_14[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$47 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_14[0] }; + assign \$49 = cnt_1_17[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$51 = cnt_1_16[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$53 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_16[0] }; + assign \$55 = cnt_1_19[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$57 = cnt_1_18[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$5 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_0[0] }; + assign \$59 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_18[0] }; + assign \$61 = cnt_1_21[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$63 = cnt_1_20[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$65 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_20[0] }; + assign \$67 = cnt_1_23[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$69 = cnt_1_22[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$71 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_22[0] }; + assign \$73 = cnt_1_25[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$75 = cnt_1_24[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$77 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_24[0] }; + assign \$7 = cnt_1_3[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$79 = cnt_1_27[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$81 = cnt_1_26[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$83 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_26[0] }; + assign \$85 = cnt_1_29[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$87 = cnt_1_28[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$89 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_28[0] }; + assign \$91 = cnt_1_31[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + assign \$93 = cnt_1_30[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1; + assign \$95 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 1'h1, cnt_1_30[0] }; + assign \$97 = cnt_2_2[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair0) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_0 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_0 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_0 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair10) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_5 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_5 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_5 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair12) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_6 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_6 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_6 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair14) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_7 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_7 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_7 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair16) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_8 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_8 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_8 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair18) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_9 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_9 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_9 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair20) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_10 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_10 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_10 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair22) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_11 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_11 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_11 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair24) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_12 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_12 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_12 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair26) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_13 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_13 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_13 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair28) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_14 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_14 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_14 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair2) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_1 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_1 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_1 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair30) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_15 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_15 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_15 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair32) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_16 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_16 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_16 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair34) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_17 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_17 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_17 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair36) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_18 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_18 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_18 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair38) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_19 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_19 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_19 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair40) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_20 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_20 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_20 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair42) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_21 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_21 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_21 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair44) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_22 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_22 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_22 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair46) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_23 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_23 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_23 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair48) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_24 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_24 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_24 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair4) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_2 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_2 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_2 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair50) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_25 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_25 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_25 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair52) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_26 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_26 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_26 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair54) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_27 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_27 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_27 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair56) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_28 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_28 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_28 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair58) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_29 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_29 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_29 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair60) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_30 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_30 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_30 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair62) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_31 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_31 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_31 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_0 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_0 = \$5 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_0 = { 1'h0, cnt_1_1 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$7 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_2 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_2 = \$11 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_2 = { 1'h0, cnt_1_3 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_4 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_4 = \$17 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_4 = { 1'h0, cnt_1_5 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$21 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_6 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_6 = \$23 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_6 = { 1'h0, cnt_1_7 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_8 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_8 = \$29 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_8 = { 1'h0, cnt_1_9 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$33 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_10 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_10 = \$35 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_10 = { 1'h0, cnt_1_11 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair6) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_3 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_3 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_3 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$37 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$39 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_12 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_12 = \$41 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_12 = { 1'h0, cnt_1_13 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$43 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$45 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_14 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_14 = \$47 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_14 = { 1'h0, cnt_1_15 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$49 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$51 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_16 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_16 = \$53 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_16 = { 1'h0, cnt_1_17 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$55 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$57 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_18 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_18 = \$59 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_18 = { 1'h0, cnt_1_19 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$61 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$63 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_20 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_20 = \$65 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_20 = { 1'h0, cnt_1_21 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$67 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$69 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_22 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_22 = \$71 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_22 = { 1'h0, cnt_1_23 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$73 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$75 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_24 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_24 = \$77 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_24 = { 1'h0, cnt_1_25 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$79 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$81 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_26 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_26 = \$83 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_26 = { 1'h0, cnt_1_27 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$85 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$87 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_28 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_28 = \$89 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_28 = { 1'h0, cnt_1_29 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$91 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$93 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_2_30 = 3'h4; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_2_30 = \$95 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_2_30 = { 1'h0, cnt_1_31 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$97 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$99 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_3_0 = 4'h8; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_3_0 = \$101 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_3_0 = { 1'h0, cnt_2_2 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$103 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$105 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_3_2 = 4'h8; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_3_2 = \$107 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_3_2 = { 1'h0, cnt_2_6 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$109 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$111 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_3_4 = 4'h8; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_3_4 = \$113 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_3_4 = { 1'h0, cnt_2_10 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$115 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$117 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_3_6 = 4'h8; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_3_6 = \$119 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_3_6 = { 1'h0, cnt_2_14 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$121 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$123 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_3_8 = 4'h8; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_3_8 = \$125 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_3_8 = { 1'h0, cnt_2_18 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$127 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$129 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_3_10 = 4'h8; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_3_10 = \$131 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_3_10 = { 1'h0, cnt_2_22 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$133 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$135 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_3_12 = 4'h8; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_3_12 = \$137 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_3_12 = { 1'h0, cnt_2_26 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$139 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$141 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_3_14 = 4'h8; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_3_14 = \$143 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_3_14 = { 1'h0, cnt_2_30 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$145 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$147 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_4_0 = 5'h10; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_4_0 = \$149 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_4_0 = { 1'h0, cnt_3_2 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$151 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$153 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_4_2 = 5'h10; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_4_2 = \$155 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_4_2 = { 1'h0, cnt_3_6 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) + casez (pair8) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ + 2'h0: + cnt_1_4 = 2'h2; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:36" */ + 2'h1: + cnt_1_4 = 2'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:38" */ + default: + cnt_1_4 = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$157 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$159 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_4_4 = 5'h10; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_4_4 = \$161 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_4_4 = { 1'h0, cnt_3_10 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$163 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$165 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_4_6 = 5'h10; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_4_6 = \$167 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_4_6 = { 1'h0, cnt_3_14 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$169 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$171 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_5_0 = 6'h20; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_5_0 = \$173 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_5_0 = { 1'h0, cnt_4_2 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$175 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$177 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_5_2 = 6'h20; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_5_2 = \$179 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_5_2 = { 1'h0, cnt_4_6 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) + casez (\$181 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) + casez (\$183 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ + 1'h1: + cnt_6_0 = 7'h40; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:63" */ + default: + cnt_6_0 = \$185 ; + endcase + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:65" */ + default: + cnt_6_0 = { 1'h0, cnt_5_2 }; + endcase + end + assign lz = cnt_6_0; + assign pair62 = sig_in[63:62]; + assign pair60 = sig_in[61:60]; + assign pair58 = sig_in[59:58]; + assign pair56 = sig_in[57:56]; + assign pair54 = sig_in[55:54]; + assign pair52 = sig_in[53:52]; + assign pair50 = sig_in[51:50]; + assign pair48 = sig_in[49:48]; + assign pair46 = sig_in[47:46]; + assign pair44 = sig_in[45:44]; + assign pair42 = sig_in[43:42]; + assign pair40 = sig_in[41:40]; + assign pair38 = sig_in[39:38]; + assign pair36 = sig_in[37:36]; + assign pair34 = sig_in[35:34]; + assign pair32 = sig_in[33:32]; + assign pair30 = sig_in[31:30]; + assign pair28 = sig_in[29:28]; + assign pair26 = sig_in[27:26]; + assign pair24 = sig_in[25:24]; + assign pair22 = sig_in[23:22]; + assign pair20 = sig_in[21:20]; + assign pair18 = sig_in[19:18]; + assign pair16 = sig_in[17:16]; + assign pair14 = sig_in[15:14]; + assign pair12 = sig_in[13:12]; + assign pair10 = sig_in[11:10]; + assign pair8 = sig_in[9:8]; + assign pair6 = sig_in[7:6]; + assign pair4 = sig_in[5:4]; + assign pair2 = sig_in[3:2]; + assign pair0 = sig_in[1:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core" *) +(* generator = "nMigen" *) +module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fasto1, core_fasto2, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core_msr, core_core_cia, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, \core_core_exc_$signal , \core_core_exc_$signal$3 , \core_core_exc_$signal$4 , \core_core_exc_$signal$5 , \core_core_exc_$signal$6 , \core_core_exc_$signal$7 , \core_core_exc_$signal$8 , \core_core_exc_$signal$9 , core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, raw_insn_i, bigendian_i, sv_a_nz, \wen$10 , \data_i$11 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$12 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1001 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1003 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1006 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1010 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1012 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1019 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1022 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1024 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1027 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1031 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1033 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1037 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1040 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1042 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1045 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1049 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1051 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1059 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1062 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1064 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1067 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1071 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1073 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1079 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1082 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1084 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1087 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1091 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1093 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1099 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1107 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1111 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1126 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1130 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1132 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1141 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1144 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1147 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1149 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1152 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$1155 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [64:0] \$1157 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [63:0] \$1158 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [63:0] \$1160 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$1162 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$1164 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [63:0] \$1166 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) + wire [64:0] \$1168 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [64:0] \$1170 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [64:0] \$1172 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [64:0] \$1174 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$1176 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [6:0] \$1177 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [6:0] \$1179 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$1181 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$1183 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [6:0] \$1185 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [6:0] \$1187 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$1189 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$1191 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$1193 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire \$1195 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire \$1197 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire \$1199 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire \$1201 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire \$1203 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire \$1205 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire \$1207 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire \$1209 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire \$1211 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1213 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$1215 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1218 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1221 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1223 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1226 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [7:0] \$1229 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1231 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$1233 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$1235 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$1237 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$1239 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$1241 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$1243 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1246 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1249 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1251 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1254 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + wire [7:0] \$1257 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + wire [255:0] \$1259 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [255:0] \$1261 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$1263 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$1266 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1269 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1271 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$1274 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + wire [7:0] \$1277 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) + wire [255:0] \$1279 ; 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+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) + wire [7:0] \$823 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) + wire [255:0] \$825 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [255:0] \$827 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [255:0] \$829 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [255:0] \$830 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$832 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$834 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$836 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$838 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + wire \$840 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) + wire [7:0] \$842 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) + wire [255:0] \$844 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [255:0] \$846 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$848 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$850 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$852 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$854 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + wire \$856 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) + wire [7:0] \$858 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) + wire [255:0] \$860 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [255:0] \$862 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$864 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$866 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$868 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$870 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + wire \$872 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [2:0] \$874 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$876 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$878 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$880 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$882 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + wire \$884 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [2:0] \$886 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$888 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$890 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$892 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$894 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + wire \$896 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [2:0] \$898 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$900 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$902 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$904 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$906 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + wire \$908 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [2:0] \$910 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$912 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$914 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$916 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$918 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + wire \$920 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [2:0] \$922 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [2:0] \$924 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [2:0] \$926 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [2:0] \$928 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [2:0] \$930 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) + wire \$932 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$934 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire \$936 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$938 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) + wire \$940 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) + wire \$942 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) + wire [9:0] \$944 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) + wire \$946 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$948 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$950 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$952 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$954 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$956 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$958 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$960 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$962 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$964 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$966 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) + wire \$968 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$970 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$972 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$974 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$980 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) + wire [6:0] \$982 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) + wire \$984 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) + wire \$987 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$991 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$993 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire \$998 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] addr_en; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1000 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1021 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1039 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1061 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1081 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1138 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [6:0] \addr_en$1154 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [7:0] \addr_en$1228 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [255:0] \addr_en$1256 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [255:0] \addr_en$1276 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [255:0] \addr_en$1296 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [255:0] \addr_en$1316 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [255:0] \addr_en$1336 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [255:0] \addr_en$1356 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [1:0] \addr_en$1403 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [1:0] \addr_en$1419 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [1:0] \addr_en$1435 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1469 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1485 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1501 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1517 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire \addr_en$1553 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire \addr_en$1569 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire \addr_en$1585 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire \addr_en$1601 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1646 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1662 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1678 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1694 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [2:0] \addr_en$1710 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire \addr_en$1754 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire \addr_en$1770 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [1:0] \addr_en$1794 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + wire [9:0] \addr_en$1814 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [255:0] addr_en_CR_cr_a_branch0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [255:0] addr_en_CR_cr_a_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [255:0] addr_en_CR_cr_b_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [255:0] addr_en_CR_cr_c_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [7:0] addr_en_CR_full_cr_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [2:0] addr_en_FAST_fast1_branch0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [2:0] addr_en_FAST_fast1_branch0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [2:0] addr_en_FAST_fast1_spr0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [2:0] addr_en_FAST_fast1_trap0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [2:0] addr_en_FAST_fast1_trap0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_alu0_10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_cr0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_cr0_11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_div0_15; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_div0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_ldst0_18; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_ldst0_7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_ldst0_9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_logical0_13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_logical0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_mul0_16; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_mul0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_shiftrot0_17; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_shiftrot0_6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_shiftrot0_8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_spr0_14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_trap0_12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [6:0] addr_en_INT_rabc_trap0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [9:0] addr_en_SPR_spr1_spr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [1:0] addr_en_XER_xer_ca_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [1:0] addr_en_XER_xer_ca_shiftrot0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [1:0] addr_en_XER_xer_ca_spr0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire [2:0] addr_en_XER_xer_ov_spr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire addr_en_XER_xer_so_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire addr_en_XER_xer_so_div0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire addr_en_XER_xer_so_logical0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire addr_en_XER_xer_so_mul0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire addr_en_XER_xer_so_shiftrot0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + wire addr_en_XER_xer_so_spr0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *) + input bigendian_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] cia__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] cia__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + input [63:0] core_core_cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [7:0] core_core_cr_rd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_core_cr_rd_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [7:0] core_core_cr_wr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \core_core_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \core_core_exc_$signal$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \core_core_exc_$signal$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \core_core_exc_$signal$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \core_core_exc_$signal$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \core_core_exc_$signal$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \core_core_exc_$signal$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \core_core_exc_$signal$9 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + input [13:0] core_core_fn_unit; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + input [1:0] core_core_input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + input [31:0] core_core_insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + input [6:0] core_core_insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + input core_core_is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + input [63:0] core_core_msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_core_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_core_oe_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_core_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_core_rc_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + input [12:0] core_core_trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + input [7:0] core_core_traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] core_cr_in1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_cr_in1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] core_cr_in2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] \core_cr_in2$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_cr_in2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input \core_cr_in2_ok$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] core_cr_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] core_ea; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [2:0] core_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [2:0] core_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [2:0] core_fasto1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [2:0] core_fasto2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + input [63:0] core_pc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] core_reg1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_reg1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] core_reg2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_reg2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] core_reg3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_reg3_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [6:0] core_rego; + (* enum_base_type = "SPR" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [9:0] core_spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input core_spr1_ok; + (* enum_base_type = "SPR" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [9:0] core_spro; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) + output core_terminate_o; + reg core_terminate_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) + reg \core_terminate_o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + input [2:0] core_xer_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *) + output corebusy_o; + reg corebusy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) + reg [1:0] counter = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) + reg [1:0] \counter$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] cr_data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [31:0] cr_full_rd__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [7:0] cr_full_rd__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [31:0] cr_full_wr__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [7:0] cr_full_wr__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] cr_src1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [7:0] cr_src1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] cr_src2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [7:0] cr_src2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] cr_src3__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [7:0] cr_src3__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [7:0] cr_wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input cu_ad__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output cu_ad__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input cu_st__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output cu_st__rel_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] \data_i$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [44:0] dbus__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input [63:0] dbus__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [63:0] dbus__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [7:0] dbus__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] dec_ALU_ALU__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_ALU_ALU__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dec_ALU_ALU__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] dec_ALU_ALU__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_ALU_ALU__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_ALU_ALU__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_ALU_ALU__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_ALU_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_ALU_raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire dec_ALU_sv_a_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dec_BRANCH_BRANCH__cia; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_BRANCH_BRANCH__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dec_BRANCH_BRANCH__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_BRANCH_BRANCH__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_BRANCH_BRANCH__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_BRANCH_BRANCH__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_BRANCH_BRANCH__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_BRANCH_BRANCH__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_BRANCH_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_BRANCH_raw_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_CR_CR__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_CR_CR__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_CR_CR__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_CR_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_CR_raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] dec_DIV_DIV__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_DIV_DIV__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dec_DIV_DIV__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] dec_DIV_DIV__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_DIV_DIV__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_DIV_DIV__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_DIV_DIV__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_DIV_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_DIV_raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire dec_DIV_sv_a_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__byte_reverse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] dec_LDST_LDST__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_LDST_LDST__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dec_LDST_LDST__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_LDST_LDST__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_LDST_LDST__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__is_signed; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] dec_LDST_LDST__ldst_mode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__sign_extend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LDST_LDST__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_LDST_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_LDST_raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire dec_LDST_sv_a_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] dec_LOGICAL_LOGICAL__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_LOGICAL_LOGICAL__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dec_LOGICAL_LOGICAL__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] dec_LOGICAL_LOGICAL__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_LOGICAL_LOGICAL__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_LOGICAL_LOGICAL__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_LOGICAL_LOGICAL__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_LOGICAL_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_LOGICAL_raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire dec_LOGICAL_sv_a_nz; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_MUL_MUL__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dec_MUL_MUL__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_MUL_MUL__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_MUL_MUL__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_MUL_MUL__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_MUL_MUL__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_MUL_MUL__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_MUL_MUL__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_MUL_MUL__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_MUL_MUL__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_MUL_MUL__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_MUL_MUL__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_MUL_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_MUL_raw_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_SHIFT_ROT_SHIFT_ROT__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dec_SHIFT_ROT_SHIFT_ROT__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] dec_SHIFT_ROT_SHIFT_ROT__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_SHIFT_ROT_SHIFT_ROT__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_SHIFT_ROT_SHIFT_ROT__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SHIFT_ROT_SHIFT_ROT__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_SHIFT_ROT_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_SHIFT_ROT_raw_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dec_SPR_SPR__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dec_SPR_SPR__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dec_SPR_SPR__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dec_SPR_SPR__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec_SPR_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + wire [31:0] dec_SPR_raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [4:0] dmi__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] dmi__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dmi__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_CR_cr_a_branch0_1 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_CR_cr_a_branch0_1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_CR_cr_a_cr0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_CR_cr_a_cr0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_CR_cr_b_cr0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_CR_cr_b_cr0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_CR_cr_c_cr0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_CR_cr_c_cr0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_CR_full_cr_cr0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_CR_full_cr_cr0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_FAST_fast1_branch0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_FAST_fast1_branch0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_FAST_fast1_branch0_3 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_FAST_fast1_branch0_3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_FAST_fast1_spr0_2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_FAST_fast1_spr0_2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_FAST_fast1_trap0_1 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_FAST_fast1_trap0_1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_FAST_fast1_trap0_4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_FAST_fast1_trap0_4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_alu0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_alu0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_alu0_10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_alu0_10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_cr0_1 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_cr0_1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_cr0_11 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_cr0_11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_div0_15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_div0_15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_div0_4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_div0_4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_ldst0_18 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_ldst0_18$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_ldst0_7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_ldst0_7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_ldst0_9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_ldst0_9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_logical0_13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_logical0_13$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_logical0_3 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_logical0_3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_mul0_16 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_mul0_16$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_mul0_5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_mul0_5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_shiftrot0_17 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_shiftrot0_17$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_shiftrot0_6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_shiftrot0_6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_shiftrot0_8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_shiftrot0_8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_spr0_14 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_spr0_14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_trap0_12 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_trap0_12$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_INT_rabc_trap0_2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_INT_rabc_trap0_2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_SPR_spr1_spr0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_SPR_spr1_spr0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_ca_alu0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_ca_alu0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_ca_shiftrot0_2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_ca_shiftrot0_2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_ca_spr0_1 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_ca_spr0_1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_ov_spr0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_ov_spr0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_so_alu0_0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_so_alu0_0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_so_div0_3 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_so_div0_3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_so_logical0_1 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_so_logical0_1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_so_mul0_4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_so_mul0_4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_so_shiftrot0_5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_so_shiftrot0_5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg dp_XER_xer_so_spr0_2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *) + reg \dp_XER_xer_so_spr0_2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire ea_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_alu0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_branch0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_div0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_ldst0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_logical0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_mul0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_shiftrot0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_spr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire en_trap0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] fast_dest1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] fast_dest1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire fast_dest1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] fast_src1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] fast_src1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire fast_src1__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" *) + wire [9:0] fu_enable; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [31:0] full_rd2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [7:0] full_rd2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [5:0] full_rd__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] full_rd__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_cr_a_ok$122 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_cr_a_ok$123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_cr_a_ok$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_cr_a_ok$125 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_cr_a_ok$126 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire fus_cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + wire \fus_cu_busy_o$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg fus_cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + reg \fus_cu_issue_i$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [3:0] fus_cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [5:0] \fus_cu_rd__go_i$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [3:0] \fus_cu_rd__go_i$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__go_i$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__go_i$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__go_i$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [4:0] \fus_cu_rd__go_i$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__go_i$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [5:0] \fus_cu_rd__go_i$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__go_i$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [3:0] fus_cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [5:0] \fus_cu_rd__rel_o$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [3:0] \fus_cu_rd__rel_o$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__rel_o$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__rel_o$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__rel_o$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [4:0] \fus_cu_rd__rel_o$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__rel_o$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [5:0] \fus_cu_rd__rel_o$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_rd__rel_o$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [3:0] fus_cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [5:0] \fus_cu_rdmaskn_i$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [2:0] \fus_cu_rdmaskn_i$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [3:0] \fus_cu_rdmaskn_i$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [2:0] \fus_cu_rdmaskn_i$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [5:0] \fus_cu_rdmaskn_i$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [2:0] \fus_cu_rdmaskn_i$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [2:0] \fus_cu_rdmaskn_i$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [4:0] \fus_cu_rdmaskn_i$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + reg [2:0] \fus_cu_rdmaskn_i$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [4:0] fus_cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [1:0] \fus_cu_wr__go_i$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [5:0] \fus_cu_wr__go_i$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [3:0] \fus_cu_wr__go_i$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [3:0] \fus_cu_wr__go_i$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_wr__go_i$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [1:0] \fus_cu_wr__go_i$114 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_wr__go_i$149 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_wr__go_i$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [4:0] \fus_cu_wr__go_i$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [4:0] fus_cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [5:0] \fus_cu_wr__rel_o$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [3:0] \fus_cu_wr__rel_o$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [3:0] \fus_cu_wr__rel_o$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_wr__rel_o$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [1:0] \fus_cu_wr__rel_o$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_wr__rel_o$148 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [2:0] \fus_cu_wr__rel_o$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [4:0] \fus_cu_wr__rel_o$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire [1:0] \fus_cu_wr__rel_o$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] fus_dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest1_o$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest1_o$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest1_o$117 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest1_o$118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest1_o$119 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest1_o$120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest1_o$121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest1_o$153 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [31:0] fus_dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [3:0] \fus_dest2_o$127 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [3:0] \fus_dest2_o$128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [3:0] \fus_dest2_o$129 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [3:0] \fus_dest2_o$130 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [3:0] \fus_dest2_o$131 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest2_o$154 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest2_o$156 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest2_o$162 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [3:0] fus_dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [1:0] \fus_dest3_o$134 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [1:0] \fus_dest3_o$135 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [1:0] \fus_dest3_o$139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [1:0] \fus_dest3_o$140 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest3_o$155 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest3_o$157 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest3_o$159 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [1:0] fus_dest4_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire \fus_dest4_o$145 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire \fus_dest4_o$146 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire \fus_dest4_o$147 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest4_o$160 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [1:0] fus_dest5_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire \fus_dest5_o$144 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest5_o$161 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [1:0] fus_dest6_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] fus_ea; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_fast1_ok$150 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_fast1_ok$151 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_fast2_ok$152 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_full_cr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [95:0] fus_ldst_port0_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_ldst_port0_addr_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + wire fus_ldst_port0_addr_ok_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + wire fus_ldst_port0_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + wire [3:0] fus_ldst_port0_data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \fus_ldst_port0_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \fus_ldst_port0_exc_$signal$163 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \fus_ldst_port0_exc_$signal$164 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \fus_ldst_port0_exc_$signal$165 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \fus_ldst_port0_exc_$signal$166 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \fus_ldst_port0_exc_$signal$167 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \fus_ldst_port0_exc_$signal$168 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \fus_ldst_port0_exc_$signal$169 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + wire fus_ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + wire fus_ldst_port0_is_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] fus_ldst_port0_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_ldst_port0_ld_data_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] fus_ldst_port0_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_ldst_port0_st_data_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_msr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_nia_ok$158 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] fus_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_o_ok$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_o_ok$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_o_ok$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_o_ok$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_o_ok$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_o_ok$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_o_ok$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] fus_oper_i_alu_alu0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_alu0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_alu0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] fus_oper_i_alu_alu0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_alu0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_alu0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_alu0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_branch0__cia; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_branch0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_branch0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_branch0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_branch0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_branch0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_branch0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_branch0__lk; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_cr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_cr0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_cr0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] fus_oper_i_alu_div0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_div0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_div0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] fus_oper_i_alu_div0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_div0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_div0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_div0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] fus_oper_i_alu_logical0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_logical0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_logical0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] fus_oper_i_alu_logical0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_logical0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_logical0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_logical0__zero_a; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_mul0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_mul0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_mul0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_mul0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_mul0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_mul0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_mul0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_mul0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_mul0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_mul0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_mul0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_mul0__write_cr0; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_shift_rot0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_shift_rot0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] fus_oper_i_alu_shift_rot0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_shift_rot0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_shift_rot0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_shift_rot0__write_cr0; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_spr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_spr0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_spr0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_spr0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_trap0__cia; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_alu_trap0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_alu_trap0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_alu_trap0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_alu_trap0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] fus_oper_i_alu_trap0__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_alu_trap0__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [12:0] fus_oper_i_alu_trap0__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] fus_oper_i_alu_trap0__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__byte_reverse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] fus_oper_i_ldst_ldst0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] fus_oper_i_ldst_ldst0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] fus_oper_i_ldst_ldst0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] fus_oper_i_ldst_ldst0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] fus_oper_i_ldst_ldst0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__is_signed; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] fus_oper_i_ldst_ldst0__ldst_mode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__sign_extend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg fus_oper_i_ldst_ldst0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_spr1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] fus_src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src1_i$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] fus_src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src2_i$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] fus_src3_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src3_i$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg \fus_src3_i$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg \fus_src3_i$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg \fus_src3_i$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg \fus_src3_i$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [31:0] \fus_src3_i$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [3:0] \fus_src3_i$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src3_i$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src3_i$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg fus_src4_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg \fus_src4_i$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [1:0] \fus_src4_i$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [3:0] \fus_src4_i$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src4_i$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [1:0] fus_src5_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [1:0] \fus_src5_i$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [3:0] \fus_src5_i$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [1:0] fus_src6_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [3:0] \fus_src6_i$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_xer_ca_ok$132 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_xer_ca_ok$133 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_xer_ov_ok$136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_xer_ov_ok$137 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_xer_ov_ok$138 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire fus_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_xer_so_ok$141 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_xer_so_ok$142 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fus_xer_so_ok$143 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [4:0] int_dest1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] int_dest1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire int_dest1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [4:0] int_src1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] int_src1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire int_src1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] issue__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] \issue__addr$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] issue__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] issue__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input issue__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input issue__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" *) + input issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" *) + input ivalid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] msr__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] msr__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_CR_cr_a_branch0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_CR_cr_a_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_CR_cr_b_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_CR_cr_c_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_CR_full_cr_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_FAST_fast1_branch0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_FAST_fast1_branch0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_FAST_fast1_spr0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_FAST_fast1_trap0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_FAST_fast1_trap0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_alu0_10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_cr0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_cr0_11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_div0_15; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_div0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_ldst0_18; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_ldst0_7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_ldst0_9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_logical0_13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_logical0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_mul0_16; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_mul0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_shiftrot0_17; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_shiftrot0_6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_shiftrot0_8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_spr0_14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_trap0_12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_INT_rabc_trap0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_SPR_spr1_spr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_ca_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_ca_shiftrot0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_ca_spr0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_ov_spr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_so_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_so_div0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_so_logical0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_so_mul0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_so_shiftrot0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + wire pick_XER_xer_so_spr0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *) + input [31:0] raw_insn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_CR_cr_a_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_CR_cr_b_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_CR_cr_c_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_CR_full_cr_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_FAST_fast1_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_FAST_fast1_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_INT_rabc_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_INT_rabc_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_INT_rabc_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_SPR_spr1_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_XER_xer_ca_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_XER_xer_ov_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *) + wire rdflag_XER_xer_so_0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_CR_cr_a_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [1:0] rdpick_CR_cr_a_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [1:0] rdpick_CR_cr_a_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_CR_cr_b_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire rdpick_CR_cr_b_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire rdpick_CR_cr_b_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_CR_cr_c_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire rdpick_CR_cr_c_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire rdpick_CR_cr_c_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_CR_full_cr_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire rdpick_CR_full_cr_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire rdpick_CR_full_cr_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_FAST_fast1_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [4:0] rdpick_FAST_fast1_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [4:0] rdpick_FAST_fast1_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_INT_rabc_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [18:0] rdpick_INT_rabc_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [18:0] rdpick_INT_rabc_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_SPR_spr1_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire rdpick_SPR_spr1_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire rdpick_SPR_spr1_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_XER_xer_ca_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [2:0] rdpick_XER_xer_ca_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [2:0] rdpick_XER_xer_ca_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_XER_xer_ov_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire rdpick_XER_xer_ov_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire rdpick_XER_xer_ov_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire rdpick_XER_xer_so_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [5:0] rdpick_XER_xer_so_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [5:0] rdpick_XER_xer_so_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_CR_cr_a_branch0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_CR_cr_a_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_CR_cr_b_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_CR_cr_c_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_CR_full_cr_cr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_FAST_fast1_branch0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_FAST_fast1_branch0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_FAST_fast1_spr0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_FAST_fast1_trap0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_FAST_fast1_trap0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_alu0_10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_cr0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_cr0_11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_div0_15; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_div0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_ldst0_18; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_ldst0_7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_ldst0_9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_logical0_13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_logical0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_mul0_16; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_mul0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_shiftrot0_17; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_shiftrot0_6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_shiftrot0_8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_spr0_14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_trap0_12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_INT_rabc_trap0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_SPR_spr1_spr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_ca_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_ca_shiftrot0_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_ca_spr0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_ov_spr0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_so_alu0_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_so_div0_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_so_logical0_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_so_mul0_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_so_shiftrot0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + wire rp_XER_xer_so_spr0_2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] spr_spr1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] \spr_spr1__addr$175 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] spr_spr1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] spr_spr1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire spr_spr1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire spr_spr1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] state_data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] \state_data_i$174 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [2:0] state_nia_wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] state_wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] sv__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] sv__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *) + input sv_a_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire \sv_a_nz$176 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire \sv_a_nz$177 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire \sv_a_nz$178 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire \sv_a_nz$179 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire \sv_a_nz$180 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + input wb_dcache_en; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] \wen$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire wp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1018 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1036 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1058 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1078 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1098 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1117 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1135 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1151 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1225 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1253 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1273 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1293 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1313 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1333 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1353 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1400 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1416 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1432 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1466 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1482 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1498 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1514 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1550 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1566 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1582 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1598 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1643 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1659 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1675 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1691 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1707 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1751 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1767 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1791 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$1811 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \wp$997 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire wr_pick; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1005 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1026 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1044 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1066 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1086 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1125 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1143 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1217 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1245 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1265 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1285 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1305 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1325 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1345 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1392 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1408 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1424 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1458 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1474 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1490 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1506 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1542 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1558 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1574 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1590 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1632 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1651 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1667 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1683 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1699 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1743 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1759 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1783 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$1803 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + wire \wr_pick$986 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg wr_pick_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1008 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1008$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1029 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1029$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1047 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1047$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1069 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1069$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1089 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1089$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1109 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1109$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1128 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1128$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1146 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1146$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1220 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1220$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1248 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1248$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1268 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1268$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1288 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1288$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1308 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1308$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1328 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1328$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1348 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1348$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1395 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1395$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1411 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1411$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1427 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1427$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1461 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1461$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1477 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1477$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1493 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1493$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1509 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1509$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1545 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1545$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1561 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1561$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1577 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1577$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1593 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1593$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1635 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1635$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1654 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1654$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1670 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1670$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1686 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1686$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1702 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1702$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1746 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1746$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1762 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1762$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1786 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1786$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1806 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1806$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$989 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$989$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire wr_pick_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1009 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1014 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1015 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1016 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1017 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1030 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1035 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1048 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1053 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1054 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1055 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1056 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1057 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1070 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1075 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1076 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1077 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1090 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1095 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1096 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1097 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1110 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1115 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1116 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1129 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1134 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1636 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1641 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$1642 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$976 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$977 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$978 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$979 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$990 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$995 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$996 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_alu0_cr_a_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_alu0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_alu0_xer_ca_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_alu0_xer_ov_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_alu0_xer_so_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_branch0_fast1_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_branch0_fast1_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_branch0_nia_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_cr0_cr_a_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_cr0_full_cr_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_cr0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_div0_cr_a_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_div0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_div0_xer_ov_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_div0_xer_so_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_ldst0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_ldst0_o_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_logical0_cr_a_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_logical0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_mul0_cr_a_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_mul0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_mul0_xer_ov_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_mul0_xer_so_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_shiftrot0_cr_a_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_shiftrot0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_shiftrot0_xer_ca_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_spr0_fast1_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_spr0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_spr0_spr1_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_spr0_xer_ca_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_spr0_xer_ov_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_spr0_xer_so_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_trap0_fast1_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_trap0_fast1_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_trap0_msr_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_trap0_nia_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire wrflag_trap0_o_0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_CR_cr_a_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [5:0] wrpick_CR_cr_a_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [5:0] wrpick_CR_cr_a_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_CR_full_cr_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire wrpick_CR_full_cr_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire wrpick_CR_full_cr_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_FAST_fast1_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [4:0] wrpick_FAST_fast1_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [4:0] wrpick_FAST_fast1_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_INT_o_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [9:0] wrpick_INT_o_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [9:0] wrpick_INT_o_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_SPR_spr1_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire wrpick_SPR_spr1_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire wrpick_SPR_spr1_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_STATE_msr_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire wrpick_STATE_msr_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire wrpick_STATE_msr_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_STATE_nia_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [1:0] wrpick_STATE_nia_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [1:0] wrpick_STATE_nia_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_XER_xer_ca_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [2:0] wrpick_XER_xer_ca_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [2:0] wrpick_XER_xer_ca_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_XER_xer_ov_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [3:0] wrpick_XER_xer_ov_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [3:0] wrpick_XER_xer_ov_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_XER_xer_so_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire [3:0] wrpick_XER_xer_so_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [3:0] wrpick_XER_xer_so_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] xer_data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] \xer_data_i$170 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] \xer_data_i$172 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] xer_src1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] xer_src1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] xer_src2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] xer_src2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] xer_src3__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] xer_src3__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] xer_wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] \xer_wen$171 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] \xer_wen$173 ; + assign \$1001 = \wp$997 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$1003 = \fus_o_ok$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; + assign \$1006 = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1010 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1008 ; + assign \$1012 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1010 ; + assign \$1019 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$1022 = \wp$1018 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$1024 = \fus_o_ok$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$23 ; + assign \$1027 = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1031 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1029 ; + assign \$1033 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1031 ; + assign \$1037 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$1040 = \wp$1036 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$1042 = \fus_o_ok$101 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; + assign \$1045 = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1049 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1047 ; + assign \$1051 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1049 ; + assign \$1059 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$1062 = \wp$1058 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$1064 = \fus_o_ok$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ; + assign \$1067 = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1071 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1069 ; + assign \$1073 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1071 ; + assign \$1079 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$1082 = \wp$1078 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$1084 = \fus_o_ok$107 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ; + assign \$1087 = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1091 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1089 ; + assign \$1093 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1091 ; + assign \$1099 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$1102 = \wp$1098 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$1104 = \fus_o_ok$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ; + assign \$1107 = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1111 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1109 ; + assign \$1113 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1111 ; + assign \$1118 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$1121 = \wp$1117 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$1123 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$38 ; + assign \$1126 = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1130 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1128 ; + assign \$1132 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1130 ; + assign \$1136 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$1139 = \wp$1135 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$1141 = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$38 ; + assign \$1144 = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$1147 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1146 ; + assign \$1149 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1147 ; + assign \$1152 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$1155 = \wp$1151 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_ea : 7'h00; + assign \$1158 = fus_dest1_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$115 ; + assign \$1160 = \fus_dest1_o$117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$118 ; + assign \$1162 = \fus_dest1_o$116 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1160 ; + assign \$1164 = \$1158 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1162 ; + assign \$1166 = \fus_dest1_o$119 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$120 ; + assign \$1168 = { o_ok, fus_o } | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) { ea_ok, fus_ea }; + assign \$1170 = \fus_dest1_o$121 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1168 ; + assign \$1172 = \$1166 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1170 ; + assign \$1174 = \$1164 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1172 ; + assign \$1177 = addr_en | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1000 ; + assign \$1179 = \addr_en$1039 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1061 ; + assign \$1181 = \addr_en$1021 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1179 ; + assign \$1183 = \$1177 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1181 ; + assign \$1185 = \addr_en$1081 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1101 ; + assign \$1187 = \addr_en$1138 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1154 ; + assign \$1189 = \addr_en$1120 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1187 ; + assign \$1191 = \$1185 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1189 ; + assign \$1193 = \$1183 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1191 ; + assign \$1195 = wp | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$997 ; + assign \$1197 = \wp$1036 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1058 ; + assign \$1199 = \wp$1018 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1197 ; + assign \$1201 = \$1195 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1199 ; + assign \$1203 = \wp$1078 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1098 ; + assign \$1205 = \wp$1135 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1151 ; + assign \$1207 = \wp$1117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1205 ; + assign \$1209 = \$1203 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1207 ; + assign \$1211 = \$1201 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1209 ; + assign \$1213 = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ; + assign \$1215 = \fus_cu_wr__rel_o$93 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1]; + assign \$1218 = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_full_cr_en_o; + assign \$1221 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1220 ; + assign \$1223 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1221 ; + assign \$1226 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_full_cr_en_o; + assign \$1229 = \wp$1225 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_core_cr_wr : 8'h00; + assign \$1231 = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; + assign \$1233 = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; + assign \$1235 = \fus_cu_wr__rel_o$93 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1]; + assign \$1237 = \fus_cu_wr__rel_o$99 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[4]; + assign \$1239 = \fus_cu_wr__rel_o$105 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6]; + assign \$1241 = \fus_cu_wr__rel_o$108 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7]; + assign \$1243 = \fus_cu_wr__rel_o$111 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8]; + assign \$1246 = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1249 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1248 ; + assign \$1251 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1249 ; + assign \$1254 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; + assign \$1257 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1259 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1257 ; + assign \$1261 = \wp$1253 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1259 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1263 = \fus_cr_a_ok$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ; + assign \$1266 = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1269 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1268 ; + assign \$1271 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1269 ; + assign \$1274 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; + assign \$1277 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1279 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1277 ; + assign \$1281 = \wp$1273 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1279 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1283 = \fus_cr_a_ok$123 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$23 ; + assign \$1286 = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1289 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1288 ; + assign \$1291 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1289 ; + assign \$1294 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; + assign \$1297 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1299 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1297 ; + assign \$1301 = \wp$1293 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1299 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1303 = \fus_cr_a_ok$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ; + assign \$1306 = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1309 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1308 ; + assign \$1311 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1309 ; + assign \$1314 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; + assign \$1317 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1319 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1317 ; + assign \$1321 = \wp$1313 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1319 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1323 = \fus_cr_a_ok$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ; + assign \$1326 = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1329 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1328 ; + assign \$1331 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1329 ; + assign \$1334 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; + assign \$1337 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1339 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1337 ; + assign \$1341 = \wp$1333 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1339 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1343 = \fus_cr_a_ok$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ; + assign \$1346 = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o; + assign \$1349 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1348 ; + assign \$1351 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1349 ; + assign \$1354 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o; + assign \$1357 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; + assign \$1359 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1357 ; + assign \$1361 = \wp$1353 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1359 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1363 = fus_dest3_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$128 ; + assign \$1365 = \fus_dest2_o$127 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1363 ; + assign \$1367 = \fus_dest2_o$130 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$131 ; + assign \$1369 = \fus_dest2_o$129 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1367 ; + assign \$1371 = \$1365 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1369 ; + assign \$1374 = \addr_en$1276 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1296 ; + assign \$1376 = \addr_en$1256 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1374 ; + assign \$1378 = \addr_en$1336 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1356 ; + assign \$1380 = \addr_en$1316 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1378 ; + assign \$1382 = \$1376 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1380 ; + assign \$1384 = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; + assign \$1386 = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; + assign \$1388 = \fus_cu_wr__rel_o$102 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; + assign \$1390 = \fus_cu_wr__rel_o$111 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8]; + assign \$1393 = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o; + assign \$1396 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1395 ; + assign \$1398 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1396 ; + assign \$1401 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o; + assign \$1404 = \wp$1400 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0; + assign \$1406 = \fus_xer_ca_ok$132 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; + assign \$1409 = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o; + assign \$1412 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1411 ; + assign \$1414 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1412 ; + assign \$1417 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o; + assign \$1420 = \wp$1416 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0; + assign \$1422 = \fus_xer_ca_ok$133 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ; + assign \$1425 = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o; + assign \$1428 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1427 ; + assign \$1430 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1428 ; + assign \$1433 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o; + assign \$1436 = \wp$1432 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0; + assign \$1438 = fus_dest6_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$135 ; + assign \$1440 = \fus_dest3_o$134 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1438 ; + assign \$1443 = \addr_en$1419 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1435 ; + assign \$1445 = \addr_en$1403 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1443 ; + assign \$1442 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1445 ; + assign \$1448 = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; + assign \$1450 = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; + assign \$1452 = \fus_cu_wr__rel_o$102 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; + assign \$1454 = \fus_cu_wr__rel_o$105 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6]; + assign \$1456 = \fus_cu_wr__rel_o$108 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7]; + assign \$1459 = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o; + assign \$1462 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1461 ; + assign \$1464 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1462 ; + assign \$1467 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o; + assign \$1470 = \wp$1466 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0; + assign \$1472 = \fus_xer_ov_ok$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; + assign \$1475 = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o; + assign \$1478 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1477 ; + assign \$1480 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1478 ; + assign \$1483 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o; + assign \$1486 = \wp$1482 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0; + assign \$1488 = \fus_xer_ov_ok$137 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ; + assign \$1491 = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o; + assign \$1494 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1493 ; + assign \$1496 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1494 ; + assign \$1499 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o; + assign \$1502 = \wp$1498 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0; + assign \$1504 = \fus_xer_ov_ok$138 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ; + assign \$1507 = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o; + assign \$1510 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1509 ; + assign \$1512 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1510 ; + assign \$1515 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o; + assign \$1518 = \wp$1514 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0; + assign \$1520 = fus_dest4_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) fus_dest5_o; + assign \$1522 = \fus_dest3_o$139 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$140 ; + assign \$1524 = \$1520 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1522 ; + assign \$1526 = \addr_en$1469 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1485 ; + assign \$1528 = \addr_en$1501 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1517 ; + assign \$1530 = \$1526 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1528 ; + assign \$1532 = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; + assign \$1534 = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; + assign \$1536 = \fus_cu_wr__rel_o$102 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; + assign \$1538 = \fus_cu_wr__rel_o$105 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6]; + assign \$1540 = \fus_cu_wr__rel_o$108 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7]; + assign \$1543 = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o; + assign \$1546 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1545 ; + assign \$1548 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1546 ; + assign \$1551 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o; + assign \$1554 = \wp$1550 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; + assign \$1556 = \fus_xer_so_ok$141 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; + assign \$1559 = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o; + assign \$1562 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1561 ; + assign \$1564 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1562 ; + assign \$1567 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o; + assign \$1570 = \wp$1566 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; + assign \$1572 = \fus_xer_so_ok$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ; + assign \$1575 = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o; + assign \$1578 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1577 ; + assign \$1580 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1578 ; + assign \$1583 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o; + assign \$1586 = \wp$1582 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; + assign \$1588 = \fus_xer_so_ok$143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ; + assign \$1591 = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o; + assign \$1594 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1593 ; + assign \$1596 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1594 ; + assign \$1599 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o; + assign \$1602 = \wp$1598 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; + assign \$1605 = \fus_dest5_o$144 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$145 ; + assign \$1607 = \fus_dest4_o$146 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$147 ; + assign \$1609 = \$1605 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1607 ; + assign \$1604 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1609 ; + assign \$1613 = \addr_en$1553 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1569 ; + assign \$1615 = \addr_en$1585 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1601 ; + assign \$1617 = \$1613 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1615 ; + assign \$1612 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1617 ; + assign \$1620 = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ; + assign \$1622 = \fus_cu_wr__rel_o$148 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2]; + assign \$1624 = \fus_cu_wr__rel_o$96 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; + assign \$1626 = \fus_cu_wr__rel_o$102 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; + assign \$1628 = \fus_cu_wr__rel_o$148 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2]; + assign \$1630 = \fus_cu_wr__rel_o$96 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; + assign \$1633 = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1637 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1635 ; + assign \$1639 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1637 ; + assign \$1644 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; + assign \$1647 = \wp$1643 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0; + assign \$1649 = \fus_fast1_ok$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; + assign \$1652 = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1655 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1654 ; + assign \$1657 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1655 ; + assign \$1660 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; + assign \$1663 = \wp$1659 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0; + assign \$1665 = \fus_fast1_ok$151 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; + assign \$1668 = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1671 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1670 ; + assign \$1673 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1671 ; + assign \$1676 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; + assign \$1679 = \wp$1675 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0; + assign \$1681 = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ; + assign \$1684 = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1687 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1686 ; + assign \$1689 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1687 ; + assign \$1692 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; + assign \$1695 = \wp$1691 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto2 : 3'h0; + assign \$1697 = \fus_fast2_ok$152 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; + assign \$1700 = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o; + assign \$1703 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1702 ; + assign \$1705 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1703 ; + assign \$1708 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o; + assign \$1711 = \wp$1707 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto2 : 3'h0; + assign \$1713 = \fus_dest1_o$153 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$154 ; + assign \$1715 = \fus_dest2_o$156 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$157 ; + assign \$1717 = \fus_dest3_o$155 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1715 ; + assign \$1719 = \$1713 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1717 ; + assign \$1721 = \addr_en$1646 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1662 ; + assign \$1723 = \addr_en$1694 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1710 ; + assign \$1725 = \addr_en$1678 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1723 ; + assign \$1727 = \$1721 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1725 ; + assign \$1729 = \wp$1643 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1659 ; + assign \$1731 = \wp$1691 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1707 ; + assign \$1733 = \wp$1675 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1731 ; + assign \$1735 = \$1729 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1733 ; + assign \$1737 = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ; + assign \$1739 = \fus_cu_wr__rel_o$148 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2]; + assign \$1741 = \fus_cu_wr__rel_o$96 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; + assign \$1744 = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_nia_en_o; + assign \$1747 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1746 ; + assign \$1749 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1747 ; + assign \$1752 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_nia_en_o; + assign \$1755 = \wp$1751 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; + assign \$1757 = \fus_nia_ok$158 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; + assign \$1760 = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_nia_en_o; + assign \$1763 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1762 ; + assign \$1765 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1763 ; + assign \$1768 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_nia_en_o; + assign \$1771 = \wp$1767 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0; + assign \$1773 = \fus_dest3_o$159 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$160 ; + assign \$1776 = \addr_en$1754 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1770 ; + assign \$1775 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \$1776 ; + assign \$1779 = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ; + assign \$1781 = \fus_cu_wr__rel_o$96 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; + assign \$1784 = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_msr_en_o; + assign \$1787 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1786 ; + assign \$1789 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1787 ; + assign \$1792 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_msr_en_o; + assign \$1795 = \wp$1791 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0; + assign \$1797 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) \addr_en$1794 ; + assign \$1799 = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ; + assign \$1801 = \fus_cu_wr__rel_o$102 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; + assign \$1804 = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_SPR_spr1_en_o; + assign \$1807 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1806 ; + assign \$1809 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1807 ; + assign \$1812 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_SPR_spr1_en_o; + assign \$1815 = \wp$1811 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_spro : 10'h000; + assign \$182 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 2'h2; + assign \$181 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$182 ; + assign \$186 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 7'h40; + assign \$185 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$186 ; + assign \$190 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 6'h20; + assign \$189 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$190 ; + assign \$194 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 8'h80; + assign \$193 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$194 ; + assign \$198 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 5'h10; + assign \$197 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$198 ; + assign \$202 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 11'h400; + assign \$201 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$202 ; + assign \$206 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 10'h200; + assign \$205 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$206 ; + assign \$210 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 9'h100; + assign \$209 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$210 ; + assign \$214 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 4'h8; + assign \$213 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$214 ; + assign \$218 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 3'h4; + assign \$217 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$218 ; + assign \$221 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h0; + assign \$224 = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *) 1'h1; + assign \$226 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h0; + assign \$229 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$231 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$233 = \$231 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$235 = \$229 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$233 ; + assign \$237 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$239 = \$235 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$237 ; + assign \$241 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$243 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$245 = \$243 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$247 = \$241 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$245 ; + assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$247 , \$239 , core_reg2_ok, core_reg1_ok }; + assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok }; + assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok }; + assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok }; + assign \$257 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$259 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$261 = \$259 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$263 = \$257 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$261 ; + assign \$265 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$267 = \$263 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$265 ; + assign \$256 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$267 , core_reg2_ok, core_reg1_ok }; + assign \$271 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$273 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$275 = \$273 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$277 = \$271 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$275 ; + assign \$279 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$281 = \$277 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$279 ; + assign \$283 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) core_core_oe_ok; + assign \$285 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$287 = \$285 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$289 = \$283 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$287 ; + assign \$291 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$293 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$295 = \$293 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$297 = \$291 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$295 ; + assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$297 , \$289 , \$281 , core_fast1_ok, core_spr1_ok, core_reg1_ok }; + assign \$301 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$303 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$305 = \$303 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$307 = \$301 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$305 ; + assign \$309 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$311 = \$307 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$309 ; + assign \$300 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$311 , core_reg2_ok, core_reg1_ok }; + assign \$315 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$317 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$319 = \$317 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$321 = \$315 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$319 ; + assign \$323 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$325 = \$321 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$323 ; + assign \$314 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$325 , core_reg2_ok, core_reg1_ok }; + assign \$329 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$331 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$333 = \$331 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$335 = \$329 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$333 ; + assign \$337 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$339 = \$335 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$337 ; + assign \$341 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$343 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$345 = \$343 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$347 = \$341 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$345 ; + assign \$328 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$347 , \$339 , core_reg3_ok, core_reg2_ok, core_reg1_ok }; + assign \$350 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok }; + assign \$352 = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0]; + assign \$354 = \$352 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; + assign \$356 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_alu0_0; + assign \$358 = \$354 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$356 ; + assign \$360 = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$362 = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; + assign \$364 = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; + assign \$366 = \$364 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; + assign \$368 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_cr0_1; + assign \$370 = \$366 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$368 ; + assign \$372 = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$374 = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; + assign \$376 = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3]; + assign \$378 = \$376 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; + assign \$380 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_trap0_2; + assign \$382 = \$378 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$380 ; + assign \$384 = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$386 = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; + assign \$388 = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4]; + assign \$390 = \$388 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; + assign \$392 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_logical0_3; + assign \$394 = \$390 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$392 ; + assign \$396 = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$398 = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; + assign \$400 = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6]; + assign \$402 = \$400 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; + assign \$404 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_div0_4; + assign \$406 = \$402 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$404 ; + assign \$408 = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$410 = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; + assign \$412 = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7]; + assign \$414 = \$412 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; + assign \$416 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_mul0_5; + assign \$418 = \$414 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$416 ; + assign \$420 = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$422 = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; + assign \$424 = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; + assign \$426 = \$424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; + assign \$428 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_6; + assign \$430 = \$426 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$428 ; + assign \$432 = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$434 = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; + assign \$436 = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9]; + assign \$438 = \$436 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0; + assign \$440 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_7; + assign \$442 = \$438 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$440 ; + assign \$444 = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$446 = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00; + assign \$448 = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; + assign \$450 = \$448 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_1; + assign \$452 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_8; + assign \$454 = \$450 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$452 ; + assign \$456 = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$458 = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg3 : 7'h00; + assign \$460 = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9]; + assign \$462 = \$460 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_1; + assign \$464 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_9; + assign \$466 = \$462 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$464 ; + assign \$468 = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$470 = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg3 : 7'h00; + assign \$472 = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0]; + assign \$474 = \$472 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$476 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_alu0_10; + assign \$478 = \$474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$476 ; + assign \$480 = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$482 = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$484 = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; + assign \$486 = \$484 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$488 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_cr0_11; + assign \$490 = \$486 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$488 ; + assign \$492 = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$494 = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$496 = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3]; + assign \$498 = \$496 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$500 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_trap0_12; + assign \$502 = \$498 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$500 ; + assign \$504 = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$506 = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$508 = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4]; + assign \$510 = \$508 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$512 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_logical0_13; + assign \$514 = \$510 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$512 ; + assign \$516 = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$518 = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$520 = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; + assign \$522 = \$520 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$524 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_spr0_14; + assign \$526 = \$522 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$524 ; + assign \$528 = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$530 = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$532 = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6]; + assign \$534 = \$532 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$536 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_div0_15; + assign \$538 = \$534 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$536 ; + assign \$540 = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$542 = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$544 = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7]; + assign \$546 = \$544 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$548 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_mul0_16; + assign \$550 = \$546 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$548 ; + assign \$552 = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$554 = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$556 = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; + assign \$558 = \$556 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$560 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_17; + assign \$562 = \$558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$560 ; + assign \$564 = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$566 = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$568 = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9]; + assign \$570 = \$568 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2; + assign \$572 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_18; + assign \$574 = \$570 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$572 ; + assign \$576 = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o; + assign \$578 = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00; + assign \$581 = addr_en_INT_rabc_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_cr0_1; + assign \$583 = addr_en_INT_rabc_trap0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_3; + assign \$585 = \$581 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$583 ; + assign \$587 = addr_en_INT_rabc_div0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_mul0_5; + assign \$589 = addr_en_INT_rabc_ldst0_7 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_shiftrot0_8; + assign \$591 = addr_en_INT_rabc_shiftrot0_6 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$589 ; + assign \$593 = \$587 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$591 ; + assign \$595 = \$585 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$593 ; + assign \$597 = addr_en_INT_rabc_ldst0_9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_alu0_10; + assign \$599 = addr_en_INT_rabc_trap0_12 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_13; + assign \$601 = addr_en_INT_rabc_cr0_11 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$599 ; + assign \$603 = \$597 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$601 ; + assign \$605 = addr_en_INT_rabc_spr0_14 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_div0_15; + assign \$607 = addr_en_INT_rabc_shiftrot0_17 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_ldst0_18; + assign \$609 = addr_en_INT_rabc_mul0_16 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$607 ; + assign \$611 = \$605 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$609 ; + assign \$613 = \$603 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$611 ; + assign \$615 = \$595 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$613 ; + assign \$617 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 }; + assign \$619 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$621 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$623 = \$621 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$625 = \$619 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$623 ; + assign \$627 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$629 = \$625 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$627 ; + assign \$631 = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0]; + assign \$633 = \$631 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; + assign \$635 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_alu0_0; + assign \$637 = \$633 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$635 ; + assign \$639 = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; + assign \$641 = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; + assign \$643 = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4]; + assign \$645 = \$643 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; + assign \$647 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_logical0_1; + assign \$649 = \$645 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$647 ; + assign \$651 = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; + assign \$653 = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; + assign \$655 = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; + assign \$657 = \$655 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; + assign \$659 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_spr0_2; + assign \$661 = \$657 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$659 ; + assign \$663 = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; + assign \$665 = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; + assign \$667 = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6]; + assign \$669 = \$667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; + assign \$671 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_div0_3; + assign \$673 = \$669 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$671 ; + assign \$675 = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; + assign \$677 = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; + assign \$679 = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7]; + assign \$681 = \$679 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; + assign \$683 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_mul0_4; + assign \$685 = \$681 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$683 ; + assign \$687 = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; + assign \$689 = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; + assign \$691 = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; + assign \$693 = \$691 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0; + assign \$695 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_shiftrot0_5; + assign \$697 = \$693 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$695 ; + assign \$699 = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o; + assign \$701 = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0; + assign \$704 = addr_en_XER_xer_so_logical0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_spr0_2; + assign \$706 = addr_en_XER_xer_so_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$704 ; + assign \$708 = addr_en_XER_xer_so_mul0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_shiftrot0_5; + assign \$710 = addr_en_XER_xer_so_div0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$708 ; + assign \$712 = \$706 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$710 ; + assign \$703 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$712 ; + assign \$715 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$717 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$719 = \$717 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$721 = \$715 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$719 ; + assign \$723 = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0]; + assign \$725 = \$723 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0; + assign \$727 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_alu0_0; + assign \$729 = \$725 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$727 ; + assign \$731 = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o; + assign \$733 = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0; + assign \$735 = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; + assign \$737 = \$735 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0; + assign \$739 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_spr0_1; + assign \$741 = \$737 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$739 ; + assign \$743 = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o; + assign \$745 = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0; + assign \$747 = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8]; + assign \$749 = \$747 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0; + assign \$751 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_shiftrot0_2; + assign \$753 = \$749 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$751 ; + assign \$755 = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o; + assign \$757 = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0; + assign \$760 = addr_en_XER_xer_ca_spr0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_ca_shiftrot0_2; + assign \$762 = addr_en_XER_xer_ca_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$760 ; + assign \$759 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$762 ; + assign \$765 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) core_core_oe_ok; + assign \$767 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$769 = \$767 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$771 = \$765 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$769 ; + assign \$773 = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; + assign \$775 = \$773 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ov_0; + assign \$777 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ov_spr0_0; + assign \$779 = \$775 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$777 ; + assign \$781 = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ov_en_o; + assign \$783 = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 3'h4 : 3'h0; + assign \$785 = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; + assign \$787 = \$785 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_full_cr_0; + assign \$789 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_full_cr_cr0_0; + assign \$791 = \$787 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$789 ; + assign \$793 = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_full_cr_en_o; + assign \$795 = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_core_cr_rd : 8'h00; + assign \$797 = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; + assign \$799 = \$797 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_a_0; + assign \$801 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_a_cr0_0; + assign \$803 = \$799 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$801 ; + assign \$805 = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_a_en_o; + assign \$807 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1; + assign \$809 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$807 ; + assign \$811 = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$809 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$813 = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2]; + assign \$815 = \$813 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_a_0; + assign \$817 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_a_branch0_1; + assign \$819 = \$815 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$817 ; + assign \$821 = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_a_en_o; + assign \$823 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1; + assign \$825 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$823 ; + assign \$827 = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$825 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$830 = addr_en_CR_cr_a_cr0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_CR_cr_a_branch0_1; + assign \$832 = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; + assign \$834 = \$832 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_b_0; + assign \$836 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_b_cr0_0; + assign \$838 = \$834 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$836 ; + assign \$840 = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_b_en_o; + assign \$842 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) core_cr_in2; + assign \$844 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) \$842 ; + assign \$846 = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$844 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$848 = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1]; + assign \$850 = \$848 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_c_0; + assign \$852 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_c_cr0_0; + assign \$854 = \$850 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$852 ; + assign \$856 = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_c_en_o; + assign \$858 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ; + assign \$860 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \$858 ; + assign \$862 = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$860 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$864 = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2]; + assign \$866 = \$864 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0; + assign \$868 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_branch0_0; + assign \$870 = \$866 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$868 ; + assign \$872 = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; + assign \$874 = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0; + assign \$876 = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3]; + assign \$878 = \$876 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0; + assign \$880 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_trap0_1; + assign \$882 = \$878 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$880 ; + assign \$884 = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; + assign \$886 = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0; + assign \$888 = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; + assign \$890 = \$888 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0; + assign \$892 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_spr0_2; + assign \$894 = \$890 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$892 ; + assign \$896 = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; + assign \$898 = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0; + assign \$900 = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2]; + assign \$902 = \$900 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_1; + assign \$904 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_branch0_3; + assign \$906 = \$902 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$904 ; + assign \$908 = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; + assign \$910 = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast2 : 3'h0; + assign \$912 = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3]; + assign \$914 = \$912 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_1; + assign \$916 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_trap0_4; + assign \$918 = \$914 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$916 ; + assign \$920 = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o; + assign \$922 = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast2 : 3'h0; + assign \$924 = addr_en_FAST_fast1_branch0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_1; + assign \$926 = addr_en_FAST_fast1_branch0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_4; + assign \$928 = addr_en_FAST_fast1_spr0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$926 ; + assign \$930 = \$924 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$928 ; + assign \$932 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) { rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 }; + assign \$934 = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5]; + assign \$936 = \$934 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_SPR_spr1_0; + assign \$938 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_SPR_spr1_spr0_0; + assign \$940 = \$936 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$938 ; + assign \$942 = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_SPR_spr1_en_o; + assign \$944 = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_spr1 : 10'h000; + assign \$946 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) rp_SPR_spr1_spr0_0; + assign \$948 = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o; + assign \$950 = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0]; + assign \$952 = \fus_cu_wr__rel_o$93 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1]; + assign \$954 = \fus_cu_wr__rel_o$96 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3]; + assign \$956 = \fus_cu_wr__rel_o$99 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[4]; + assign \$958 = \fus_cu_wr__rel_o$102 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5]; + assign \$960 = \fus_cu_wr__rel_o$105 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6]; + assign \$962 = \fus_cu_wr__rel_o$108 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7]; + assign \$964 = \fus_cu_wr__rel_o$111 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8]; + assign \$966 = \fus_cu_wr__rel_o$113 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[9]; + assign \$968 = \fus_cu_wr__rel_o$113 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[9]; + assign \$970 = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$972 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wr_pick_dly; + assign \$974 = wr_pick & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$972 ; + assign \$980 = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + assign \$982 = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00; + assign \$984 = \fus_o_ok$92 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ; + assign \$987 = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o; + assign \$991 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$989 ; + assign \$993 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$991 ; + assign \$998 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o; + always @(posedge coresync_clk) + \wr_pick_dly$1806 <= \wr_pick_dly$1806$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1786 <= \wr_pick_dly$1786$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1762 <= \wr_pick_dly$1762$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1746 <= \wr_pick_dly$1746$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1702 <= \wr_pick_dly$1702$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1686 <= \wr_pick_dly$1686$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1670 <= \wr_pick_dly$1670$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1654 <= \wr_pick_dly$1654$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1635 <= \wr_pick_dly$1635$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1593 <= \wr_pick_dly$1593$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1577 <= \wr_pick_dly$1577$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1561 <= \wr_pick_dly$1561$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1545 <= \wr_pick_dly$1545$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1509 <= \wr_pick_dly$1509$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1493 <= \wr_pick_dly$1493$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1477 <= \wr_pick_dly$1477$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1461 <= \wr_pick_dly$1461$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1427 <= \wr_pick_dly$1427$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1411 <= \wr_pick_dly$1411$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1395 <= \wr_pick_dly$1395$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1348 <= \wr_pick_dly$1348$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1328 <= \wr_pick_dly$1328$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1308 <= \wr_pick_dly$1308$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1288 <= \wr_pick_dly$1288$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1268 <= \wr_pick_dly$1268$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1248 <= \wr_pick_dly$1248$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1220 <= \wr_pick_dly$1220$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1146 <= \wr_pick_dly$1146$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1128 <= \wr_pick_dly$1128$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1109 <= \wr_pick_dly$1109$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1089 <= \wr_pick_dly$1089$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1069 <= \wr_pick_dly$1069$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1047 <= \wr_pick_dly$1047$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1029 <= \wr_pick_dly$1029$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1008 <= \wr_pick_dly$1008$next ; + always @(posedge coresync_clk) + \wr_pick_dly$989 <= \wr_pick_dly$989$next ; + always @(posedge coresync_clk) + wr_pick_dly <= \wr_pick_dly$next ; + always @(posedge coresync_clk) + dp_SPR_spr1_spr0_0 <= \dp_SPR_spr1_spr0_0$next ; + always @(posedge coresync_clk) + dp_FAST_fast1_trap0_4 <= \dp_FAST_fast1_trap0_4$next ; + always @(posedge coresync_clk) + dp_FAST_fast1_branch0_3 <= \dp_FAST_fast1_branch0_3$next ; + always @(posedge coresync_clk) + dp_FAST_fast1_spr0_2 <= \dp_FAST_fast1_spr0_2$next ; + always @(posedge coresync_clk) + dp_FAST_fast1_trap0_1 <= \dp_FAST_fast1_trap0_1$next ; + always @(posedge coresync_clk) + dp_FAST_fast1_branch0_0 <= \dp_FAST_fast1_branch0_0$next ; + always @(posedge coresync_clk) + dp_CR_cr_c_cr0_0 <= \dp_CR_cr_c_cr0_0$next ; + always @(posedge coresync_clk) + dp_CR_cr_b_cr0_0 <= \dp_CR_cr_b_cr0_0$next ; + always @(posedge coresync_clk) + dp_CR_cr_a_branch0_1 <= \dp_CR_cr_a_branch0_1$next ; + always @(posedge coresync_clk) + dp_CR_cr_a_cr0_0 <= \dp_CR_cr_a_cr0_0$next ; + always @(posedge coresync_clk) + dp_CR_full_cr_cr0_0 <= \dp_CR_full_cr_cr0_0$next ; + always @(posedge coresync_clk) + dp_XER_xer_ov_spr0_0 <= \dp_XER_xer_ov_spr0_0$next ; + always @(posedge coresync_clk) + dp_XER_xer_ca_shiftrot0_2 <= \dp_XER_xer_ca_shiftrot0_2$next ; + always @(posedge coresync_clk) + dp_XER_xer_ca_spr0_1 <= \dp_XER_xer_ca_spr0_1$next ; + always @(posedge coresync_clk) + dp_XER_xer_ca_alu0_0 <= \dp_XER_xer_ca_alu0_0$next ; + always @(posedge coresync_clk) + dp_XER_xer_so_shiftrot0_5 <= \dp_XER_xer_so_shiftrot0_5$next ; + always @(posedge coresync_clk) + dp_XER_xer_so_mul0_4 <= \dp_XER_xer_so_mul0_4$next ; + always @(posedge coresync_clk) + dp_XER_xer_so_div0_3 <= \dp_XER_xer_so_div0_3$next ; + always @(posedge coresync_clk) + dp_XER_xer_so_spr0_2 <= \dp_XER_xer_so_spr0_2$next ; + always @(posedge coresync_clk) + dp_XER_xer_so_logical0_1 <= \dp_XER_xer_so_logical0_1$next ; + always @(posedge coresync_clk) + dp_XER_xer_so_alu0_0 <= \dp_XER_xer_so_alu0_0$next ; + always @(posedge coresync_clk) + dp_INT_rabc_ldst0_18 <= \dp_INT_rabc_ldst0_18$next ; + always @(posedge coresync_clk) + dp_INT_rabc_shiftrot0_17 <= \dp_INT_rabc_shiftrot0_17$next ; + always @(posedge coresync_clk) + dp_INT_rabc_mul0_16 <= \dp_INT_rabc_mul0_16$next ; + always @(posedge coresync_clk) + dp_INT_rabc_div0_15 <= \dp_INT_rabc_div0_15$next ; + always @(posedge coresync_clk) + dp_INT_rabc_spr0_14 <= \dp_INT_rabc_spr0_14$next ; + always @(posedge coresync_clk) + dp_INT_rabc_logical0_13 <= \dp_INT_rabc_logical0_13$next ; + always @(posedge coresync_clk) + dp_INT_rabc_trap0_12 <= \dp_INT_rabc_trap0_12$next ; + always @(posedge coresync_clk) + dp_INT_rabc_cr0_11 <= \dp_INT_rabc_cr0_11$next ; + always @(posedge coresync_clk) + dp_INT_rabc_alu0_10 <= \dp_INT_rabc_alu0_10$next ; + always @(posedge coresync_clk) + dp_INT_rabc_ldst0_9 <= \dp_INT_rabc_ldst0_9$next ; + always @(posedge coresync_clk) + dp_INT_rabc_shiftrot0_8 <= \dp_INT_rabc_shiftrot0_8$next ; + always @(posedge coresync_clk) + dp_INT_rabc_ldst0_7 <= \dp_INT_rabc_ldst0_7$next ; + always @(posedge coresync_clk) + dp_INT_rabc_shiftrot0_6 <= \dp_INT_rabc_shiftrot0_6$next ; + always @(posedge coresync_clk) + dp_INT_rabc_mul0_5 <= \dp_INT_rabc_mul0_5$next ; + always @(posedge coresync_clk) + dp_INT_rabc_div0_4 <= \dp_INT_rabc_div0_4$next ; + always @(posedge coresync_clk) + dp_INT_rabc_logical0_3 <= \dp_INT_rabc_logical0_3$next ; + always @(posedge coresync_clk) + dp_INT_rabc_trap0_2 <= \dp_INT_rabc_trap0_2$next ; + always @(posedge coresync_clk) + dp_INT_rabc_cr0_1 <= \dp_INT_rabc_cr0_1$next ; + always @(posedge coresync_clk) + dp_INT_rabc_alu0_0 <= \dp_INT_rabc_alu0_0$next ; + always @(posedge coresync_clk) + core_terminate_o <= \core_terminate_o$next ; + always @(posedge coresync_clk) + counter <= \counter$next ; + cr cr ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .data_i(cr_data_i), + .full_rd2__data_o(full_rd2__data_o), + .full_rd2__ren(full_rd2__ren), + .full_rd__data_o(cr_full_rd__data_o), + .full_rd__ren(cr_full_rd__ren), + .full_wr__data_i(cr_full_wr__data_i), + .full_wr__wen(cr_full_wr__wen), + .src1__data_o(cr_src1__data_o), + .src1__ren(cr_src1__ren), + .src2__data_o(cr_src2__data_o), + .src2__ren(cr_src2__ren), + .src3__data_o(cr_src3__data_o), + .src3__ren(cr_src3__ren), + .wen(cr_wen) + ); + dec_ALU dec_ALU ( + .ALU__data_len(dec_ALU_ALU__data_len), + .ALU__fn_unit(dec_ALU_ALU__fn_unit), + .ALU__imm_data__data(dec_ALU_ALU__imm_data__data), + .ALU__imm_data__ok(dec_ALU_ALU__imm_data__ok), + .ALU__input_carry(dec_ALU_ALU__input_carry), + .ALU__insn(dec_ALU_ALU__insn), + .ALU__insn_type(dec_ALU_ALU__insn_type), + .ALU__invert_in(dec_ALU_ALU__invert_in), + .ALU__invert_out(dec_ALU_ALU__invert_out), + .ALU__is_32bit(dec_ALU_ALU__is_32bit), + .ALU__is_signed(dec_ALU_ALU__is_signed), + .ALU__oe__oe(dec_ALU_ALU__oe__oe), + .ALU__oe__ok(dec_ALU_ALU__oe__ok), + .ALU__output_carry(dec_ALU_ALU__output_carry), + .ALU__rc__ok(dec_ALU_ALU__rc__ok), + .ALU__rc__rc(dec_ALU_ALU__rc__rc), + .ALU__write_cr0(dec_ALU_ALU__write_cr0), + .ALU__zero_a(dec_ALU_ALU__zero_a), + .bigendian(dec_ALU_bigendian), + .raw_opcode_in(dec_ALU_raw_opcode_in), + .sv_a_nz(dec_ALU_sv_a_nz) + ); + dec_BRANCH dec_BRANCH ( + .BRANCH__cia(dec_BRANCH_BRANCH__cia), + .BRANCH__fn_unit(dec_BRANCH_BRANCH__fn_unit), + .BRANCH__imm_data__data(dec_BRANCH_BRANCH__imm_data__data), + .BRANCH__imm_data__ok(dec_BRANCH_BRANCH__imm_data__ok), + .BRANCH__insn(dec_BRANCH_BRANCH__insn), + .BRANCH__insn_type(dec_BRANCH_BRANCH__insn_type), + .BRANCH__is_32bit(dec_BRANCH_BRANCH__is_32bit), + .BRANCH__lk(dec_BRANCH_BRANCH__lk), + .bigendian(dec_BRANCH_bigendian), + .core_pc(core_pc), + .raw_opcode_in(dec_BRANCH_raw_opcode_in) + ); + dec_CR dec_CR ( + .CR__fn_unit(dec_CR_CR__fn_unit), + .CR__insn(dec_CR_CR__insn), + .CR__insn_type(dec_CR_CR__insn_type), + .bigendian(dec_CR_bigendian), + .raw_opcode_in(dec_CR_raw_opcode_in) + ); + dec_DIV dec_DIV ( + .DIV__data_len(dec_DIV_DIV__data_len), + .DIV__fn_unit(dec_DIV_DIV__fn_unit), + .DIV__imm_data__data(dec_DIV_DIV__imm_data__data), + .DIV__imm_data__ok(dec_DIV_DIV__imm_data__ok), + .DIV__input_carry(dec_DIV_DIV__input_carry), + .DIV__insn(dec_DIV_DIV__insn), + .DIV__insn_type(dec_DIV_DIV__insn_type), + .DIV__invert_in(dec_DIV_DIV__invert_in), + .DIV__invert_out(dec_DIV_DIV__invert_out), + .DIV__is_32bit(dec_DIV_DIV__is_32bit), + .DIV__is_signed(dec_DIV_DIV__is_signed), + .DIV__oe__oe(dec_DIV_DIV__oe__oe), + .DIV__oe__ok(dec_DIV_DIV__oe__ok), + .DIV__output_carry(dec_DIV_DIV__output_carry), + .DIV__rc__ok(dec_DIV_DIV__rc__ok), + .DIV__rc__rc(dec_DIV_DIV__rc__rc), + .DIV__write_cr0(dec_DIV_DIV__write_cr0), + .DIV__zero_a(dec_DIV_DIV__zero_a), + .bigendian(dec_DIV_bigendian), + .raw_opcode_in(dec_DIV_raw_opcode_in), + .sv_a_nz(dec_DIV_sv_a_nz) + ); + dec_LDST dec_LDST ( + .LDST__byte_reverse(dec_LDST_LDST__byte_reverse), + .LDST__data_len(dec_LDST_LDST__data_len), + .LDST__fn_unit(dec_LDST_LDST__fn_unit), + .LDST__imm_data__data(dec_LDST_LDST__imm_data__data), + .LDST__imm_data__ok(dec_LDST_LDST__imm_data__ok), + .LDST__insn(dec_LDST_LDST__insn), + .LDST__insn_type(dec_LDST_LDST__insn_type), + .LDST__is_32bit(dec_LDST_LDST__is_32bit), + .LDST__is_signed(dec_LDST_LDST__is_signed), + .LDST__ldst_mode(dec_LDST_LDST__ldst_mode), + .LDST__oe__oe(dec_LDST_LDST__oe__oe), + .LDST__oe__ok(dec_LDST_LDST__oe__ok), + .LDST__rc__ok(dec_LDST_LDST__rc__ok), + .LDST__rc__rc(dec_LDST_LDST__rc__rc), + .LDST__sign_extend(dec_LDST_LDST__sign_extend), + .LDST__zero_a(dec_LDST_LDST__zero_a), + .bigendian(dec_LDST_bigendian), + .raw_opcode_in(dec_LDST_raw_opcode_in), + .sv_a_nz(dec_LDST_sv_a_nz) + ); + dec_LOGICAL dec_LOGICAL ( + .LOGICAL__data_len(dec_LOGICAL_LOGICAL__data_len), + .LOGICAL__fn_unit(dec_LOGICAL_LOGICAL__fn_unit), + .LOGICAL__imm_data__data(dec_LOGICAL_LOGICAL__imm_data__data), + .LOGICAL__imm_data__ok(dec_LOGICAL_LOGICAL__imm_data__ok), + .LOGICAL__input_carry(dec_LOGICAL_LOGICAL__input_carry), + .LOGICAL__insn(dec_LOGICAL_LOGICAL__insn), + .LOGICAL__insn_type(dec_LOGICAL_LOGICAL__insn_type), + .LOGICAL__invert_in(dec_LOGICAL_LOGICAL__invert_in), + .LOGICAL__invert_out(dec_LOGICAL_LOGICAL__invert_out), + .LOGICAL__is_32bit(dec_LOGICAL_LOGICAL__is_32bit), + .LOGICAL__is_signed(dec_LOGICAL_LOGICAL__is_signed), + .LOGICAL__oe__oe(dec_LOGICAL_LOGICAL__oe__oe), + .LOGICAL__oe__ok(dec_LOGICAL_LOGICAL__oe__ok), + .LOGICAL__output_carry(dec_LOGICAL_LOGICAL__output_carry), + .LOGICAL__rc__ok(dec_LOGICAL_LOGICAL__rc__ok), + .LOGICAL__rc__rc(dec_LOGICAL_LOGICAL__rc__rc), + .LOGICAL__write_cr0(dec_LOGICAL_LOGICAL__write_cr0), + .LOGICAL__zero_a(dec_LOGICAL_LOGICAL__zero_a), + .bigendian(dec_LOGICAL_bigendian), + .raw_opcode_in(dec_LOGICAL_raw_opcode_in), + .sv_a_nz(dec_LOGICAL_sv_a_nz) + ); + dec_MUL dec_MUL ( + .MUL__fn_unit(dec_MUL_MUL__fn_unit), + .MUL__imm_data__data(dec_MUL_MUL__imm_data__data), + .MUL__imm_data__ok(dec_MUL_MUL__imm_data__ok), + .MUL__insn(dec_MUL_MUL__insn), + .MUL__insn_type(dec_MUL_MUL__insn_type), + .MUL__is_32bit(dec_MUL_MUL__is_32bit), + .MUL__is_signed(dec_MUL_MUL__is_signed), + .MUL__oe__oe(dec_MUL_MUL__oe__oe), + .MUL__oe__ok(dec_MUL_MUL__oe__ok), + .MUL__rc__ok(dec_MUL_MUL__rc__ok), + .MUL__rc__rc(dec_MUL_MUL__rc__rc), + .MUL__write_cr0(dec_MUL_MUL__write_cr0), + .bigendian(dec_MUL_bigendian), + .raw_opcode_in(dec_MUL_raw_opcode_in) + ); + dec_SHIFT_ROT dec_SHIFT_ROT ( + .SHIFT_ROT__fn_unit(dec_SHIFT_ROT_SHIFT_ROT__fn_unit), + .SHIFT_ROT__imm_data__data(dec_SHIFT_ROT_SHIFT_ROT__imm_data__data), + .SHIFT_ROT__imm_data__ok(dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok), + .SHIFT_ROT__input_carry(dec_SHIFT_ROT_SHIFT_ROT__input_carry), + .SHIFT_ROT__input_cr(dec_SHIFT_ROT_SHIFT_ROT__input_cr), + .SHIFT_ROT__insn(dec_SHIFT_ROT_SHIFT_ROT__insn), + .SHIFT_ROT__insn_type(dec_SHIFT_ROT_SHIFT_ROT__insn_type), + .SHIFT_ROT__invert_in(dec_SHIFT_ROT_SHIFT_ROT__invert_in), + .SHIFT_ROT__is_32bit(dec_SHIFT_ROT_SHIFT_ROT__is_32bit), + .SHIFT_ROT__is_signed(dec_SHIFT_ROT_SHIFT_ROT__is_signed), + .SHIFT_ROT__oe__oe(dec_SHIFT_ROT_SHIFT_ROT__oe__oe), + .SHIFT_ROT__oe__ok(dec_SHIFT_ROT_SHIFT_ROT__oe__ok), + .SHIFT_ROT__output_carry(dec_SHIFT_ROT_SHIFT_ROT__output_carry), + .SHIFT_ROT__output_cr(dec_SHIFT_ROT_SHIFT_ROT__output_cr), + .SHIFT_ROT__rc__ok(dec_SHIFT_ROT_SHIFT_ROT__rc__ok), + .SHIFT_ROT__rc__rc(dec_SHIFT_ROT_SHIFT_ROT__rc__rc), + .SHIFT_ROT__write_cr0(dec_SHIFT_ROT_SHIFT_ROT__write_cr0), + .bigendian(dec_SHIFT_ROT_bigendian), + .raw_opcode_in(dec_SHIFT_ROT_raw_opcode_in) + ); + dec_SPR dec_SPR ( + .SPR__fn_unit(dec_SPR_SPR__fn_unit), + .SPR__insn(dec_SPR_SPR__insn), + .SPR__insn_type(dec_SPR_SPR__insn_type), + .SPR__is_32bit(dec_SPR_SPR__is_32bit), + .bigendian(dec_SPR_bigendian), + .raw_opcode_in(dec_SPR_raw_opcode_in) + ); + fast fast ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest1__addr(fast_dest1__addr), + .dest1__data_i(fast_dest1__data_i), + .dest1__wen(fast_dest1__wen), + .issue__addr(issue__addr), + .\issue__addr$1 (\issue__addr$12 ), + .issue__data_i(issue__data_i), + .issue__data_o(issue__data_o), + .issue__ren(issue__ren), + .issue__wen(issue__wen), + .src1__addr(fast_src1__addr), + .src1__data_o(fast_src1__data_o), + .src1__ren(fast_src1__ren) + ); + fus fus ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a_ok(fus_cr_a_ok), + .\cr_a_ok$110 (\fus_cr_a_ok$122 ), + .\cr_a_ok$111 (\fus_cr_a_ok$123 ), + .\cr_a_ok$112 (\fus_cr_a_ok$124 ), + .\cr_a_ok$113 (\fus_cr_a_ok$125 ), + .\cr_a_ok$114 (\fus_cr_a_ok$126 ), + .cu_ad__go_i(cu_ad__go_i), + .cu_ad__rel_o(cu_ad__rel_o), + .cu_busy_o(fus_cu_busy_o), + .\cu_busy_o$11 (\fus_cu_busy_o$23 ), + .\cu_busy_o$14 (\fus_cu_busy_o$26 ), + .\cu_busy_o$17 (\fus_cu_busy_o$29 ), + .\cu_busy_o$2 (\fus_cu_busy_o$14 ), + .\cu_busy_o$20 (\fus_cu_busy_o$32 ), + .\cu_busy_o$23 (\fus_cu_busy_o$35 ), + .\cu_busy_o$26 (\fus_cu_busy_o$38 ), + .\cu_busy_o$5 (\fus_cu_busy_o$17 ), + .\cu_busy_o$8 (\fus_cu_busy_o$20 ), + .cu_issue_i(fus_cu_issue_i), + .\cu_issue_i$1 (\fus_cu_issue_i$13 ), + .\cu_issue_i$10 (\fus_cu_issue_i$22 ), + .\cu_issue_i$13 (\fus_cu_issue_i$25 ), + .\cu_issue_i$16 (\fus_cu_issue_i$28 ), + .\cu_issue_i$19 (\fus_cu_issue_i$31 ), + .\cu_issue_i$22 (\fus_cu_issue_i$34 ), + .\cu_issue_i$25 (\fus_cu_issue_i$37 ), + .\cu_issue_i$4 (\fus_cu_issue_i$16 ), + .\cu_issue_i$7 (\fus_cu_issue_i$19 ), + .cu_rd__go_i(fus_cu_rd__go_i), + .\cu_rd__go_i$29 (\fus_cu_rd__go_i$41 ), + .\cu_rd__go_i$32 (\fus_cu_rd__go_i$44 ), + .\cu_rd__go_i$35 (\fus_cu_rd__go_i$47 ), + .\cu_rd__go_i$38 (\fus_cu_rd__go_i$50 ), + .\cu_rd__go_i$41 (\fus_cu_rd__go_i$53 ), + .\cu_rd__go_i$44 (\fus_cu_rd__go_i$56 ), + .\cu_rd__go_i$47 (\fus_cu_rd__go_i$59 ), + .\cu_rd__go_i$54 (\fus_cu_rd__go_i$66 ), + .\cu_rd__go_i$70 (\fus_cu_rd__go_i$82 ), + .cu_rd__rel_o(fus_cu_rd__rel_o), + .\cu_rd__rel_o$28 (\fus_cu_rd__rel_o$40 ), + .\cu_rd__rel_o$31 (\fus_cu_rd__rel_o$43 ), + .\cu_rd__rel_o$34 (\fus_cu_rd__rel_o$46 ), + .\cu_rd__rel_o$37 (\fus_cu_rd__rel_o$49 ), + .\cu_rd__rel_o$40 (\fus_cu_rd__rel_o$52 ), + .\cu_rd__rel_o$43 (\fus_cu_rd__rel_o$55 ), + .\cu_rd__rel_o$46 (\fus_cu_rd__rel_o$58 ), + .\cu_rd__rel_o$53 (\fus_cu_rd__rel_o$65 ), + .\cu_rd__rel_o$69 (\fus_cu_rd__rel_o$81 ), + .cu_rdmaskn_i(fus_cu_rdmaskn_i), + .\cu_rdmaskn_i$12 (\fus_cu_rdmaskn_i$24 ), + .\cu_rdmaskn_i$15 (\fus_cu_rdmaskn_i$27 ), + .\cu_rdmaskn_i$18 (\fus_cu_rdmaskn_i$30 ), + .\cu_rdmaskn_i$21 (\fus_cu_rdmaskn_i$33 ), + .\cu_rdmaskn_i$24 (\fus_cu_rdmaskn_i$36 ), + .\cu_rdmaskn_i$27 (\fus_cu_rdmaskn_i$39 ), + .\cu_rdmaskn_i$3 (\fus_cu_rdmaskn_i$15 ), + .\cu_rdmaskn_i$6 (\fus_cu_rdmaskn_i$18 ), + .\cu_rdmaskn_i$9 (\fus_cu_rdmaskn_i$21 ), + .cu_st__go_i(cu_st__go_i), + .cu_st__rel_o(cu_st__rel_o), + .cu_wr__go_i(fus_cu_wr__go_i), + .\cu_wr__go_i$100 (\fus_cu_wr__go_i$112 ), + .\cu_wr__go_i$102 (\fus_cu_wr__go_i$114 ), + .\cu_wr__go_i$137 (\fus_cu_wr__go_i$149 ), + .\cu_wr__go_i$82 (\fus_cu_wr__go_i$94 ), + .\cu_wr__go_i$85 (\fus_cu_wr__go_i$97 ), + .\cu_wr__go_i$88 (\fus_cu_wr__go_i$100 ), + .\cu_wr__go_i$91 (\fus_cu_wr__go_i$103 ), + .\cu_wr__go_i$94 (\fus_cu_wr__go_i$106 ), + .\cu_wr__go_i$97 (\fus_cu_wr__go_i$109 ), + .cu_wr__rel_o(fus_cu_wr__rel_o), + .\cu_wr__rel_o$101 (\fus_cu_wr__rel_o$113 ), + .\cu_wr__rel_o$136 (\fus_cu_wr__rel_o$148 ), + .\cu_wr__rel_o$81 (\fus_cu_wr__rel_o$93 ), + .\cu_wr__rel_o$84 (\fus_cu_wr__rel_o$96 ), + .\cu_wr__rel_o$87 (\fus_cu_wr__rel_o$99 ), + .\cu_wr__rel_o$90 (\fus_cu_wr__rel_o$102 ), + .\cu_wr__rel_o$93 (\fus_cu_wr__rel_o$105 ), + .\cu_wr__rel_o$96 (\fus_cu_wr__rel_o$108 ), + .\cu_wr__rel_o$99 (\fus_cu_wr__rel_o$111 ), + .dest1_o(fus_dest1_o), + .\dest1_o$103 (\fus_dest1_o$115 ), + .\dest1_o$104 (\fus_dest1_o$116 ), + .\dest1_o$105 (\fus_dest1_o$117 ), + .\dest1_o$106 (\fus_dest1_o$118 ), + .\dest1_o$107 (\fus_dest1_o$119 ), + .\dest1_o$108 (\fus_dest1_o$120 ), + .\dest1_o$109 (\fus_dest1_o$121 ), + .\dest1_o$141 (\fus_dest1_o$153 ), + .dest2_o(fus_dest2_o), + .\dest2_o$115 (\fus_dest2_o$127 ), + .\dest2_o$116 (\fus_dest2_o$128 ), + .\dest2_o$117 (\fus_dest2_o$129 ), + .\dest2_o$118 (\fus_dest2_o$130 ), + .\dest2_o$119 (\fus_dest2_o$131 ), + .\dest2_o$142 (\fus_dest2_o$154 ), + .\dest2_o$144 (\fus_dest2_o$156 ), + .\dest2_o$150 (\fus_dest2_o$162 ), + .dest3_o(fus_dest3_o), + .\dest3_o$122 (\fus_dest3_o$134 ), + .\dest3_o$123 (\fus_dest3_o$135 ), + .\dest3_o$127 (\fus_dest3_o$139 ), + .\dest3_o$128 (\fus_dest3_o$140 ), + .\dest3_o$143 (\fus_dest3_o$155 ), + .\dest3_o$145 (\fus_dest3_o$157 ), + .\dest3_o$147 (\fus_dest3_o$159 ), + .dest4_o(fus_dest4_o), + .\dest4_o$133 (\fus_dest4_o$145 ), + .\dest4_o$134 (\fus_dest4_o$146 ), + .\dest4_o$135 (\fus_dest4_o$147 ), + .\dest4_o$148 (\fus_dest4_o$160 ), + .dest5_o(fus_dest5_o), + .\dest5_o$132 (\fus_dest5_o$144 ), + .\dest5_o$149 (\fus_dest5_o$161 ), + .dest6_o(fus_dest6_o), + .ea(fus_ea), + .fast1_ok(fus_fast1_ok), + .\fast1_ok$138 (\fus_fast1_ok$150 ), + .\fast1_ok$139 (\fus_fast1_ok$151 ), + .fast2_ok(fus_fast2_ok), + .\fast2_ok$140 (\fus_fast2_ok$152 ), + .full_cr_ok(fus_full_cr_ok), + .ldst_port0_addr_i(fus_ldst_port0_addr_i), + .ldst_port0_addr_i_ok(fus_ldst_port0_addr_i_ok), + .ldst_port0_addr_ok_o(fus_ldst_port0_addr_ok_o), + .ldst_port0_busy_o(fus_ldst_port0_busy_o), + .ldst_port0_data_len(fus_ldst_port0_data_len), + .\ldst_port0_exc_$signal (\fus_ldst_port0_exc_$signal ), + .\ldst_port0_exc_$signal$151 (\fus_ldst_port0_exc_$signal$163 ), + .\ldst_port0_exc_$signal$152 (\fus_ldst_port0_exc_$signal$164 ), + .\ldst_port0_exc_$signal$153 (\fus_ldst_port0_exc_$signal$165 ), + .\ldst_port0_exc_$signal$154 (\fus_ldst_port0_exc_$signal$166 ), + .\ldst_port0_exc_$signal$155 (\fus_ldst_port0_exc_$signal$167 ), + .\ldst_port0_exc_$signal$156 (\fus_ldst_port0_exc_$signal$168 ), + .\ldst_port0_exc_$signal$157 (\fus_ldst_port0_exc_$signal$169 ), + .ldst_port0_is_ld_i(fus_ldst_port0_is_ld_i), + .ldst_port0_is_st_i(fus_ldst_port0_is_st_i), + .ldst_port0_ld_data_o(fus_ldst_port0_ld_data_o), + .ldst_port0_ld_data_o_ok(fus_ldst_port0_ld_data_o_ok), + .ldst_port0_st_data_i(fus_ldst_port0_st_data_i), + .ldst_port0_st_data_i_ok(fus_ldst_port0_st_data_i_ok), + .msr_ok(fus_msr_ok), + .nia_ok(fus_nia_ok), + .\nia_ok$146 (\fus_nia_ok$158 ), + .o(fus_o), + .o_ok(fus_o_ok), + .\o_ok$80 (\fus_o_ok$92 ), + .\o_ok$83 (\fus_o_ok$95 ), + .\o_ok$86 (\fus_o_ok$98 ), + .\o_ok$89 (\fus_o_ok$101 ), + .\o_ok$92 (\fus_o_ok$104 ), + .\o_ok$95 (\fus_o_ok$107 ), + .\o_ok$98 (\fus_o_ok$110 ), + .oper_i_alu_alu0__data_len(fus_oper_i_alu_alu0__data_len), + .oper_i_alu_alu0__fn_unit(fus_oper_i_alu_alu0__fn_unit), + .oper_i_alu_alu0__imm_data__data(fus_oper_i_alu_alu0__imm_data__data), + .oper_i_alu_alu0__imm_data__ok(fus_oper_i_alu_alu0__imm_data__ok), + .oper_i_alu_alu0__input_carry(fus_oper_i_alu_alu0__input_carry), + .oper_i_alu_alu0__insn(fus_oper_i_alu_alu0__insn), + .oper_i_alu_alu0__insn_type(fus_oper_i_alu_alu0__insn_type), + .oper_i_alu_alu0__invert_in(fus_oper_i_alu_alu0__invert_in), + .oper_i_alu_alu0__invert_out(fus_oper_i_alu_alu0__invert_out), + .oper_i_alu_alu0__is_32bit(fus_oper_i_alu_alu0__is_32bit), + .oper_i_alu_alu0__is_signed(fus_oper_i_alu_alu0__is_signed), + .oper_i_alu_alu0__oe__oe(fus_oper_i_alu_alu0__oe__oe), + .oper_i_alu_alu0__oe__ok(fus_oper_i_alu_alu0__oe__ok), + .oper_i_alu_alu0__output_carry(fus_oper_i_alu_alu0__output_carry), + .oper_i_alu_alu0__rc__ok(fus_oper_i_alu_alu0__rc__ok), + .oper_i_alu_alu0__rc__rc(fus_oper_i_alu_alu0__rc__rc), + .oper_i_alu_alu0__write_cr0(fus_oper_i_alu_alu0__write_cr0), + .oper_i_alu_alu0__zero_a(fus_oper_i_alu_alu0__zero_a), + .oper_i_alu_branch0__cia(fus_oper_i_alu_branch0__cia), + .oper_i_alu_branch0__fn_unit(fus_oper_i_alu_branch0__fn_unit), + .oper_i_alu_branch0__imm_data__data(fus_oper_i_alu_branch0__imm_data__data), + .oper_i_alu_branch0__imm_data__ok(fus_oper_i_alu_branch0__imm_data__ok), + .oper_i_alu_branch0__insn(fus_oper_i_alu_branch0__insn), + .oper_i_alu_branch0__insn_type(fus_oper_i_alu_branch0__insn_type), + .oper_i_alu_branch0__is_32bit(fus_oper_i_alu_branch0__is_32bit), + .oper_i_alu_branch0__lk(fus_oper_i_alu_branch0__lk), + .oper_i_alu_cr0__fn_unit(fus_oper_i_alu_cr0__fn_unit), + .oper_i_alu_cr0__insn(fus_oper_i_alu_cr0__insn), + .oper_i_alu_cr0__insn_type(fus_oper_i_alu_cr0__insn_type), + .oper_i_alu_div0__data_len(fus_oper_i_alu_div0__data_len), + .oper_i_alu_div0__fn_unit(fus_oper_i_alu_div0__fn_unit), + .oper_i_alu_div0__imm_data__data(fus_oper_i_alu_div0__imm_data__data), + .oper_i_alu_div0__imm_data__ok(fus_oper_i_alu_div0__imm_data__ok), + .oper_i_alu_div0__input_carry(fus_oper_i_alu_div0__input_carry), + .oper_i_alu_div0__insn(fus_oper_i_alu_div0__insn), + .oper_i_alu_div0__insn_type(fus_oper_i_alu_div0__insn_type), + .oper_i_alu_div0__invert_in(fus_oper_i_alu_div0__invert_in), + .oper_i_alu_div0__invert_out(fus_oper_i_alu_div0__invert_out), + .oper_i_alu_div0__is_32bit(fus_oper_i_alu_div0__is_32bit), + .oper_i_alu_div0__is_signed(fus_oper_i_alu_div0__is_signed), + .oper_i_alu_div0__oe__oe(fus_oper_i_alu_div0__oe__oe), + .oper_i_alu_div0__oe__ok(fus_oper_i_alu_div0__oe__ok), + .oper_i_alu_div0__output_carry(fus_oper_i_alu_div0__output_carry), + .oper_i_alu_div0__rc__ok(fus_oper_i_alu_div0__rc__ok), + .oper_i_alu_div0__rc__rc(fus_oper_i_alu_div0__rc__rc), + .oper_i_alu_div0__write_cr0(fus_oper_i_alu_div0__write_cr0), + .oper_i_alu_div0__zero_a(fus_oper_i_alu_div0__zero_a), + .oper_i_alu_logical0__data_len(fus_oper_i_alu_logical0__data_len), + .oper_i_alu_logical0__fn_unit(fus_oper_i_alu_logical0__fn_unit), + .oper_i_alu_logical0__imm_data__data(fus_oper_i_alu_logical0__imm_data__data), + .oper_i_alu_logical0__imm_data__ok(fus_oper_i_alu_logical0__imm_data__ok), + .oper_i_alu_logical0__input_carry(fus_oper_i_alu_logical0__input_carry), + .oper_i_alu_logical0__insn(fus_oper_i_alu_logical0__insn), + .oper_i_alu_logical0__insn_type(fus_oper_i_alu_logical0__insn_type), + .oper_i_alu_logical0__invert_in(fus_oper_i_alu_logical0__invert_in), + .oper_i_alu_logical0__invert_out(fus_oper_i_alu_logical0__invert_out), + .oper_i_alu_logical0__is_32bit(fus_oper_i_alu_logical0__is_32bit), + .oper_i_alu_logical0__is_signed(fus_oper_i_alu_logical0__is_signed), + .oper_i_alu_logical0__oe__oe(fus_oper_i_alu_logical0__oe__oe), + .oper_i_alu_logical0__oe__ok(fus_oper_i_alu_logical0__oe__ok), + .oper_i_alu_logical0__output_carry(fus_oper_i_alu_logical0__output_carry), + .oper_i_alu_logical0__rc__ok(fus_oper_i_alu_logical0__rc__ok), + .oper_i_alu_logical0__rc__rc(fus_oper_i_alu_logical0__rc__rc), + .oper_i_alu_logical0__write_cr0(fus_oper_i_alu_logical0__write_cr0), + .oper_i_alu_logical0__zero_a(fus_oper_i_alu_logical0__zero_a), + .oper_i_alu_mul0__fn_unit(fus_oper_i_alu_mul0__fn_unit), + .oper_i_alu_mul0__imm_data__data(fus_oper_i_alu_mul0__imm_data__data), + .oper_i_alu_mul0__imm_data__ok(fus_oper_i_alu_mul0__imm_data__ok), + .oper_i_alu_mul0__insn(fus_oper_i_alu_mul0__insn), + .oper_i_alu_mul0__insn_type(fus_oper_i_alu_mul0__insn_type), + .oper_i_alu_mul0__is_32bit(fus_oper_i_alu_mul0__is_32bit), + .oper_i_alu_mul0__is_signed(fus_oper_i_alu_mul0__is_signed), + .oper_i_alu_mul0__oe__oe(fus_oper_i_alu_mul0__oe__oe), + .oper_i_alu_mul0__oe__ok(fus_oper_i_alu_mul0__oe__ok), + .oper_i_alu_mul0__rc__ok(fus_oper_i_alu_mul0__rc__ok), + .oper_i_alu_mul0__rc__rc(fus_oper_i_alu_mul0__rc__rc), + .oper_i_alu_mul0__write_cr0(fus_oper_i_alu_mul0__write_cr0), + .oper_i_alu_shift_rot0__fn_unit(fus_oper_i_alu_shift_rot0__fn_unit), + .oper_i_alu_shift_rot0__imm_data__data(fus_oper_i_alu_shift_rot0__imm_data__data), + .oper_i_alu_shift_rot0__imm_data__ok(fus_oper_i_alu_shift_rot0__imm_data__ok), + .oper_i_alu_shift_rot0__input_carry(fus_oper_i_alu_shift_rot0__input_carry), + .oper_i_alu_shift_rot0__input_cr(fus_oper_i_alu_shift_rot0__input_cr), + .oper_i_alu_shift_rot0__insn(fus_oper_i_alu_shift_rot0__insn), + .oper_i_alu_shift_rot0__insn_type(fus_oper_i_alu_shift_rot0__insn_type), + .oper_i_alu_shift_rot0__invert_in(fus_oper_i_alu_shift_rot0__invert_in), + .oper_i_alu_shift_rot0__is_32bit(fus_oper_i_alu_shift_rot0__is_32bit), + .oper_i_alu_shift_rot0__is_signed(fus_oper_i_alu_shift_rot0__is_signed), + .oper_i_alu_shift_rot0__oe__oe(fus_oper_i_alu_shift_rot0__oe__oe), + .oper_i_alu_shift_rot0__oe__ok(fus_oper_i_alu_shift_rot0__oe__ok), + .oper_i_alu_shift_rot0__output_carry(fus_oper_i_alu_shift_rot0__output_carry), + .oper_i_alu_shift_rot0__output_cr(fus_oper_i_alu_shift_rot0__output_cr), + .oper_i_alu_shift_rot0__rc__ok(fus_oper_i_alu_shift_rot0__rc__ok), + .oper_i_alu_shift_rot0__rc__rc(fus_oper_i_alu_shift_rot0__rc__rc), + .oper_i_alu_shift_rot0__write_cr0(fus_oper_i_alu_shift_rot0__write_cr0), + .oper_i_alu_spr0__fn_unit(fus_oper_i_alu_spr0__fn_unit), + .oper_i_alu_spr0__insn(fus_oper_i_alu_spr0__insn), + .oper_i_alu_spr0__insn_type(fus_oper_i_alu_spr0__insn_type), + .oper_i_alu_spr0__is_32bit(fus_oper_i_alu_spr0__is_32bit), + .oper_i_alu_trap0__cia(fus_oper_i_alu_trap0__cia), + .oper_i_alu_trap0__fn_unit(fus_oper_i_alu_trap0__fn_unit), + .oper_i_alu_trap0__insn(fus_oper_i_alu_trap0__insn), + .oper_i_alu_trap0__insn_type(fus_oper_i_alu_trap0__insn_type), + .oper_i_alu_trap0__is_32bit(fus_oper_i_alu_trap0__is_32bit), + .oper_i_alu_trap0__ldst_exc(fus_oper_i_alu_trap0__ldst_exc), + .oper_i_alu_trap0__msr(fus_oper_i_alu_trap0__msr), + .oper_i_alu_trap0__trapaddr(fus_oper_i_alu_trap0__trapaddr), + .oper_i_alu_trap0__traptype(fus_oper_i_alu_trap0__traptype), + .oper_i_ldst_ldst0__byte_reverse(fus_oper_i_ldst_ldst0__byte_reverse), + .oper_i_ldst_ldst0__data_len(fus_oper_i_ldst_ldst0__data_len), + .oper_i_ldst_ldst0__fn_unit(fus_oper_i_ldst_ldst0__fn_unit), + .oper_i_ldst_ldst0__imm_data__data(fus_oper_i_ldst_ldst0__imm_data__data), + .oper_i_ldst_ldst0__imm_data__ok(fus_oper_i_ldst_ldst0__imm_data__ok), + .oper_i_ldst_ldst0__insn(fus_oper_i_ldst_ldst0__insn), + .oper_i_ldst_ldst0__insn_type(fus_oper_i_ldst_ldst0__insn_type), + .oper_i_ldst_ldst0__is_32bit(fus_oper_i_ldst_ldst0__is_32bit), + .oper_i_ldst_ldst0__is_signed(fus_oper_i_ldst_ldst0__is_signed), + .oper_i_ldst_ldst0__ldst_mode(fus_oper_i_ldst_ldst0__ldst_mode), + .oper_i_ldst_ldst0__oe__oe(fus_oper_i_ldst_ldst0__oe__oe), + .oper_i_ldst_ldst0__oe__ok(fus_oper_i_ldst_ldst0__oe__ok), + .oper_i_ldst_ldst0__rc__ok(fus_oper_i_ldst_ldst0__rc__ok), + .oper_i_ldst_ldst0__rc__rc(fus_oper_i_ldst_ldst0__rc__rc), + .oper_i_ldst_ldst0__sign_extend(fus_oper_i_ldst_ldst0__sign_extend), + .oper_i_ldst_ldst0__zero_a(fus_oper_i_ldst_ldst0__zero_a), + .spr1_ok(fus_spr1_ok), + .src1_i(fus_src1_i), + .\src1_i$50 (\fus_src1_i$62 ), + .\src1_i$51 (\fus_src1_i$63 ), + .\src1_i$52 (\fus_src1_i$64 ), + .\src1_i$55 (\fus_src1_i$67 ), + .\src1_i$56 (\fus_src1_i$68 ), + .\src1_i$57 (\fus_src1_i$69 ), + .\src1_i$58 (\fus_src1_i$70 ), + .\src1_i$59 (\fus_src1_i$71 ), + .\src1_i$74 (\fus_src1_i$86 ), + .src2_i(fus_src2_i), + .\src2_i$30 (\fus_src2_i$42 ), + .\src2_i$33 (\fus_src2_i$45 ), + .\src2_i$36 (\fus_src2_i$48 ), + .\src2_i$39 (\fus_src2_i$51 ), + .\src2_i$42 (\fus_src2_i$54 ), + .\src2_i$45 (\fus_src2_i$57 ), + .\src2_i$48 (\fus_src2_i$60 ), + .\src2_i$77 (\fus_src2_i$89 ), + .\src2_i$79 (\fus_src2_i$91 ), + .src3_i(fus_src3_i), + .\src3_i$49 (\fus_src3_i$61 ), + .\src3_i$60 (\fus_src3_i$72 ), + .\src3_i$61 (\fus_src3_i$73 ), + .\src3_i$62 (\fus_src3_i$74 ), + .\src3_i$63 (\fus_src3_i$75 ), + .\src3_i$67 (\fus_src3_i$79 ), + .\src3_i$71 (\fus_src3_i$83 ), + .\src3_i$75 (\fus_src3_i$87 ), + .\src3_i$76 (\fus_src3_i$88 ), + .src4_i(fus_src4_i), + .\src4_i$64 (\fus_src4_i$76 ), + .\src4_i$65 (\fus_src4_i$77 ), + .\src4_i$68 (\fus_src4_i$80 ), + .\src4_i$78 (\fus_src4_i$90 ), + .src5_i(fus_src5_i), + .\src5_i$66 (\fus_src5_i$78 ), + .\src5_i$72 (\fus_src5_i$84 ), + .src6_i(fus_src6_i), + .\src6_i$73 (\fus_src6_i$85 ), + .xer_ca_ok(fus_xer_ca_ok), + .\xer_ca_ok$120 (\fus_xer_ca_ok$132 ), + .\xer_ca_ok$121 (\fus_xer_ca_ok$133 ), + .xer_ov_ok(fus_xer_ov_ok), + .\xer_ov_ok$124 (\fus_xer_ov_ok$136 ), + .\xer_ov_ok$125 (\fus_xer_ov_ok$137 ), + .\xer_ov_ok$126 (\fus_xer_ov_ok$138 ), + .xer_so_ok(fus_xer_so_ok), + .\xer_so_ok$129 (\fus_xer_so_ok$141 ), + .\xer_so_ok$130 (\fus_xer_so_ok$142 ), + .\xer_so_ok$131 (\fus_xer_so_ok$143 ) + ); + \int \int ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest1__addr(int_dest1__addr), + .dest1__data_i(int_dest1__data_i), + .dest1__wen(int_dest1__wen), + .dmi__addr(dmi__addr), + .dmi__data_o(dmi__data_o), + .dmi__ren(dmi__ren), + .src1__addr(int_src1__addr), + .src1__data_o(int_src1__data_o), + .src1__ren(int_src1__ren) + ); + l0 l0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dbus__ack(dbus__ack), + .dbus__adr(dbus__adr), + .dbus__cyc(dbus__cyc), + .dbus__dat_r(dbus__dat_r), + .dbus__dat_w(dbus__dat_w), + .dbus__err(dbus__err), + .dbus__sel(dbus__sel), + .dbus__stb(dbus__stb), + .dbus__we(dbus__we), + .ldst_port0_addr_i(fus_ldst_port0_addr_i), + .ldst_port0_addr_i_ok(fus_ldst_port0_addr_i_ok), + .ldst_port0_addr_ok_o(fus_ldst_port0_addr_ok_o), + .ldst_port0_busy_o(fus_ldst_port0_busy_o), + .ldst_port0_data_len(fus_ldst_port0_data_len), + .\ldst_port0_exc_$signal (\fus_ldst_port0_exc_$signal ), + .\ldst_port0_exc_$signal$1 (\fus_ldst_port0_exc_$signal$163 ), + .\ldst_port0_exc_$signal$2 (\fus_ldst_port0_exc_$signal$164 ), + .\ldst_port0_exc_$signal$3 (\fus_ldst_port0_exc_$signal$165 ), + .\ldst_port0_exc_$signal$4 (\fus_ldst_port0_exc_$signal$166 ), + .\ldst_port0_exc_$signal$5 (\fus_ldst_port0_exc_$signal$167 ), + .\ldst_port0_exc_$signal$6 (\fus_ldst_port0_exc_$signal$168 ), + .\ldst_port0_exc_$signal$7 (\fus_ldst_port0_exc_$signal$169 ), + .ldst_port0_is_ld_i(fus_ldst_port0_is_ld_i), + .ldst_port0_is_st_i(fus_ldst_port0_is_st_i), + .ldst_port0_ld_data_o(fus_ldst_port0_ld_data_o), + .ldst_port0_ld_data_o_ok(fus_ldst_port0_ld_data_o_ok), + .ldst_port0_st_data_i(fus_ldst_port0_st_data_i), + .ldst_port0_st_data_i_ok(fus_ldst_port0_st_data_i_ok), + .wb_dcache_en(wb_dcache_en) + ); + rdpick_CR_cr_a rdpick_CR_cr_a ( + .en_o(rdpick_CR_cr_a_en_o), + .i(rdpick_CR_cr_a_i), + .o(rdpick_CR_cr_a_o) + ); + rdpick_CR_cr_b rdpick_CR_cr_b ( + .en_o(rdpick_CR_cr_b_en_o), + .i(rdpick_CR_cr_b_i), + .o(rdpick_CR_cr_b_o) + ); + rdpick_CR_cr_c rdpick_CR_cr_c ( + .en_o(rdpick_CR_cr_c_en_o), + .i(rdpick_CR_cr_c_i), + .o(rdpick_CR_cr_c_o) + ); + rdpick_CR_full_cr rdpick_CR_full_cr ( + .en_o(rdpick_CR_full_cr_en_o), + .i(rdpick_CR_full_cr_i), + .o(rdpick_CR_full_cr_o) + ); + rdpick_FAST_fast1 rdpick_FAST_fast1 ( + .en_o(rdpick_FAST_fast1_en_o), + .i(rdpick_FAST_fast1_i), + .o(rdpick_FAST_fast1_o) + ); + rdpick_INT_rabc rdpick_INT_rabc ( + .en_o(rdpick_INT_rabc_en_o), + .i(rdpick_INT_rabc_i), + .o(rdpick_INT_rabc_o) + ); + rdpick_SPR_spr1 rdpick_SPR_spr1 ( + .en_o(rdpick_SPR_spr1_en_o), + .i(rdpick_SPR_spr1_i), + .o(rdpick_SPR_spr1_o) + ); + rdpick_XER_xer_ca rdpick_XER_xer_ca ( + .en_o(rdpick_XER_xer_ca_en_o), + .i(rdpick_XER_xer_ca_i), + .o(rdpick_XER_xer_ca_o) + ); + rdpick_XER_xer_ov rdpick_XER_xer_ov ( + .en_o(rdpick_XER_xer_ov_en_o), + .i(rdpick_XER_xer_ov_i), + .o(rdpick_XER_xer_ov_o) + ); + rdpick_XER_xer_so rdpick_XER_xer_so ( + .en_o(rdpick_XER_xer_so_en_o), + .i(rdpick_XER_xer_so_i), + .o(rdpick_XER_xer_so_o) + ); + spr spr ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .spr1__addr(spr_spr1__addr), + .\spr1__addr$1 (\spr_spr1__addr$175 ), + .spr1__data_i(spr_spr1__data_i), + .spr1__data_o(spr_spr1__data_o), + .spr1__ren(spr_spr1__ren), + .spr1__wen(spr_spr1__wen) + ); + state state ( + .cia__data_o(cia__data_o), + .cia__ren(cia__ren), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .data_i(data_i), + .\data_i$2 (\data_i$11 ), + .\data_i$3 (state_data_i), + .\data_i$4 (\state_data_i$174 ), + .msr__data_o(msr__data_o), + .msr__ren(msr__ren), + .state_nia_wen(state_nia_wen), + .sv__data_o(sv__data_o), + .sv__ren(sv__ren), + .wen(wen), + .\wen$1 (\wen$10 ), + .\wen$5 (state_wen) + ); + wrpick_CR_cr_a wrpick_CR_cr_a ( + .en_o(wrpick_CR_cr_a_en_o), + .i(wrpick_CR_cr_a_i), + .o(wrpick_CR_cr_a_o) + ); + wrpick_CR_full_cr wrpick_CR_full_cr ( + .en_o(wrpick_CR_full_cr_en_o), + .i(wrpick_CR_full_cr_i), + .o(wrpick_CR_full_cr_o) + ); + wrpick_FAST_fast1 wrpick_FAST_fast1 ( + .en_o(wrpick_FAST_fast1_en_o), + .i(wrpick_FAST_fast1_i), + .o(wrpick_FAST_fast1_o) + ); + wrpick_INT_o wrpick_INT_o ( + .en_o(wrpick_INT_o_en_o), + .i(wrpick_INT_o_i), + .o(wrpick_INT_o_o) + ); + wrpick_SPR_spr1 wrpick_SPR_spr1 ( + .en_o(wrpick_SPR_spr1_en_o), + .i(wrpick_SPR_spr1_i), + .o(wrpick_SPR_spr1_o) + ); + wrpick_STATE_msr wrpick_STATE_msr ( + .en_o(wrpick_STATE_msr_en_o), + .i(wrpick_STATE_msr_i), + .o(wrpick_STATE_msr_o) + ); + wrpick_STATE_nia wrpick_STATE_nia ( + .en_o(wrpick_STATE_nia_en_o), + .i(wrpick_STATE_nia_i), + .o(wrpick_STATE_nia_o) + ); + wrpick_XER_xer_ca wrpick_XER_xer_ca ( + .en_o(wrpick_XER_xer_ca_en_o), + .i(wrpick_XER_xer_ca_i), + .o(wrpick_XER_xer_ca_o) + ); + wrpick_XER_xer_ov wrpick_XER_xer_ov ( + .en_o(wrpick_XER_xer_ov_en_o), + .i(wrpick_XER_xer_ov_i), + .o(wrpick_XER_xer_ov_o) + ); + wrpick_XER_xer_so wrpick_XER_xer_so ( + .en_o(wrpick_XER_xer_so_en_o), + .i(wrpick_XER_xer_so_i), + .o(wrpick_XER_xer_so_o) + ); + xer xer ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .data_i(xer_data_i), + .\data_i$1 (\xer_data_i$170 ), + .\data_i$3 (\xer_data_i$172 ), + .full_rd__data_o(full_rd__data_o), + .full_rd__ren(full_rd__ren), + .src1__data_o(xer_src1__data_o), + .src1__ren(xer_src1__ren), + .src2__data_o(xer_src2__data_o), + .src2__ren(xer_src2__ren), + .src3__data_o(xer_src3__data_o), + .src3__ren(xer_src3__ren), + .wen(xer_wen), + .\wen$2 (\xer_wen$171 ), + .\wen$4 (\xer_wen$173 ) + ); + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__output_carry = dec_LOGICAL_LOGICAL__output_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__is_32bit = dec_LOGICAL_LOGICAL__is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__is_signed = dec_LOGICAL_LOGICAL__is_signed; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__data_len = dec_LOGICAL_LOGICAL__data_len; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__insn = dec_LOGICAL_LOGICAL__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$22 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$22 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$24 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$24 = \$256 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_spr0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_spr0__insn_type = dec_SPR_SPR__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_spr0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_spr0__fn_unit = dec_SPR_SPR__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_spr0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_spr0__insn = dec_SPR_SPR__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_spr0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_spr0__is_32bit = dec_SPR_SPR__is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$25 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$25 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$27 = 6'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$27 = \$270 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__insn_type = dec_DIV_DIV__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__fn_unit = dec_DIV_DIV__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_div0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_div0__imm_data__ok, fus_oper_i_alu_div0__imm_data__data } = { dec_DIV_DIV__imm_data__ok, dec_DIV_DIV__imm_data__data }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__rc__rc = 1'h0; + fus_oper_i_alu_div0__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_div0__rc__ok, fus_oper_i_alu_div0__rc__rc } = { dec_DIV_DIV__rc__ok, dec_DIV_DIV__rc__rc }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__oe__oe = 1'h0; + fus_oper_i_alu_div0__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_div0__oe__ok, fus_oper_i_alu_div0__oe__oe } = { dec_DIV_DIV__oe__ok, dec_DIV_DIV__oe__oe }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__invert_in = dec_DIV_DIV__invert_in; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__zero_a = dec_DIV_DIV__zero_a; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__input_carry = dec_DIV_DIV__input_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__invert_out = dec_DIV_DIV__invert_out; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__write_cr0 = dec_DIV_DIV__write_cr0; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__output_carry = dec_DIV_DIV__output_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__is_32bit = dec_DIV_DIV__is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__is_signed = dec_DIV_DIV__is_signed; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__data_len = dec_DIV_DIV__data_len; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_div0__insn = dec_DIV_DIV__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$28 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$28 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$30 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$30 = \$300 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_mul0__insn_type = dec_MUL_MUL__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_mul0__fn_unit = dec_MUL_MUL__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_mul0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_mul0__imm_data__ok, fus_oper_i_alu_mul0__imm_data__data } = { dec_MUL_MUL__imm_data__ok, dec_MUL_MUL__imm_data__data }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__rc__rc = 1'h0; + fus_oper_i_alu_mul0__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_mul0__rc__ok, fus_oper_i_alu_mul0__rc__rc } = { dec_MUL_MUL__rc__ok, dec_MUL_MUL__rc__rc }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__oe__oe = 1'h0; + fus_oper_i_alu_mul0__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_mul0__oe__ok, fus_oper_i_alu_mul0__oe__oe } = { dec_MUL_MUL__oe__ok, dec_MUL_MUL__oe__oe }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_mul0__write_cr0 = dec_MUL_MUL__write_cr0; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_mul0__is_32bit = dec_MUL_MUL__is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_mul0__is_signed = dec_MUL_MUL__is_signed; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_mul0__insn = dec_MUL_MUL__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$31 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$31 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$33 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$33 = \$314 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__insn_type = dec_SHIFT_ROT_SHIFT_ROT__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__fn_unit = dec_SHIFT_ROT_SHIFT_ROT__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_shift_rot0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_shift_rot0__imm_data__ok, fus_oper_i_alu_shift_rot0__imm_data__data } = { dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok, dec_SHIFT_ROT_SHIFT_ROT__imm_data__data }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__rc__rc = 1'h0; + fus_oper_i_alu_shift_rot0__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_shift_rot0__rc__ok, fus_oper_i_alu_shift_rot0__rc__rc } = { dec_SHIFT_ROT_SHIFT_ROT__rc__ok, dec_SHIFT_ROT_SHIFT_ROT__rc__rc }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__oe__oe = 1'h0; + fus_oper_i_alu_shift_rot0__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_shift_rot0__oe__ok, fus_oper_i_alu_shift_rot0__oe__oe } = { dec_SHIFT_ROT_SHIFT_ROT__oe__ok, dec_SHIFT_ROT_SHIFT_ROT__oe__oe }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__write_cr0 = dec_SHIFT_ROT_SHIFT_ROT__write_cr0; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__invert_in = dec_SHIFT_ROT_SHIFT_ROT__invert_in; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__input_carry = dec_SHIFT_ROT_SHIFT_ROT__input_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__output_carry = dec_SHIFT_ROT_SHIFT_ROT__output_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__input_cr = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__input_cr = dec_SHIFT_ROT_SHIFT_ROT__input_cr; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__output_cr = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__output_cr = dec_SHIFT_ROT_SHIFT_ROT__output_cr; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__is_32bit = dec_SHIFT_ROT_SHIFT_ROT__is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__is_signed = dec_SHIFT_ROT_SHIFT_ROT__is_signed; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_shift_rot0__insn = dec_SHIFT_ROT_SHIFT_ROT__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$34 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$34 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$36 = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$36 = \$328 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__insn_type = dec_LDST_LDST__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__fn_unit = dec_LDST_LDST__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__imm_data__data = 64'h0000000000000000; + fus_oper_i_ldst_ldst0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_ldst_ldst0__imm_data__ok, fus_oper_i_ldst_ldst0__imm_data__data } = { dec_LDST_LDST__imm_data__ok, dec_LDST_LDST__imm_data__data }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__zero_a = dec_LDST_LDST__zero_a; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__rc__rc = 1'h0; + fus_oper_i_ldst_ldst0__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_ldst_ldst0__rc__ok, fus_oper_i_ldst_ldst0__rc__rc } = { dec_LDST_LDST__rc__ok, dec_LDST_LDST__rc__rc }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__oe__oe = 1'h0; + fus_oper_i_ldst_ldst0__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_ldst_ldst0__oe__ok, fus_oper_i_ldst_ldst0__oe__oe } = { dec_LDST_LDST__oe__ok, dec_LDST_LDST__oe__oe }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__is_32bit = dec_LDST_LDST__is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__is_signed = dec_LDST_LDST__is_signed; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__data_len = dec_LDST_LDST__data_len; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__byte_reverse = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__byte_reverse = dec_LDST_LDST__byte_reverse; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__sign_extend = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__sign_extend = dec_LDST_LDST__sign_extend; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__ldst_mode = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__ldst_mode = dec_LDST_LDST__ldst_mode; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_ldst_ldst0__insn = dec_LDST_LDST__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$37 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$37 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$39 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$39 = \$350 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_alu0_0$next = rp_INT_rabc_alu0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_alu0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_src2_i = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_alu0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + fus_src2_i = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_cr0_1$next = rp_INT_rabc_cr0_1; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_cr0_1$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$42 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_cr0_1) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$42 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_trap0_2$next = rp_INT_rabc_trap0_2; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_trap0_2$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$45 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_trap0_2) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$45 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_logical0_3$next = rp_INT_rabc_logical0_3; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_logical0_3$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$48 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_logical0_3) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$48 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_div0_4$next = rp_INT_rabc_div0_4; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_div0_4$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$51 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_div0_4) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$51 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_mul0_5$next = rp_INT_rabc_mul0_5; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_mul0_5$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$54 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_mul0_5) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$54 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_shiftrot0_6$next = rp_INT_rabc_shiftrot0_6; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_shiftrot0_6$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$57 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_shiftrot0_6) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$57 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_ldst0_7$next = rp_INT_rabc_ldst0_7; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_ldst0_7$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$60 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_ldst0_7) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$60 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_shiftrot0_8$next = rp_INT_rabc_shiftrot0_8; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_shiftrot0_8$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_src3_i = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_shiftrot0_8) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + fus_src3_i = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_ldst0_9$next = rp_INT_rabc_ldst0_9; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_ldst0_9$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$61 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_ldst0_9) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$61 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_alu0_10$next = rp_INT_rabc_alu0_10; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_alu0_10$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_src1_i = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_alu0_10) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + fus_src1_i = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_cr0_11$next = rp_INT_rabc_cr0_11; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_cr0_11$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$62 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_cr0_11) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$62 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_trap0_12$next = rp_INT_rabc_trap0_12; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_trap0_12$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$63 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_trap0_12) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$63 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_logical0_13$next = rp_INT_rabc_logical0_13; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_logical0_13$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$64 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_logical0_13) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$64 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_spr0_14$next = rp_INT_rabc_spr0_14; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_spr0_14$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$67 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_spr0_14) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$67 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_div0_15$next = rp_INT_rabc_div0_15; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_div0_15$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$68 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_div0_15) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$68 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_mul0_16$next = rp_INT_rabc_mul0_16; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_mul0_16$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$69 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_mul0_16) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$69 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_shiftrot0_17$next = rp_INT_rabc_shiftrot0_17; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_shiftrot0_17$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$70 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_shiftrot0_17) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$70 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_INT_rabc_ldst0_18$next = rp_INT_rabc_ldst0_18; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_INT_rabc_ldst0_18$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$71 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_INT_rabc_ldst0_18) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$71 = int_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_so_alu0_0$next = rp_XER_xer_so_alu0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_so_alu0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$72 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_so_alu0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$72 = xer_src1__data_o[0]; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_so_logical0_1$next = rp_XER_xer_so_logical0_1; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_so_logical0_1$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$73 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_so_logical0_1) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$73 = xer_src1__data_o[0]; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_so_spr0_2$next = rp_XER_xer_so_spr0_2; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_so_spr0_2$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_src4_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_so_spr0_2) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + fus_src4_i = xer_src1__data_o[0]; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_so_div0_3$next = rp_XER_xer_so_div0_3; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_so_div0_3$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$74 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_so_div0_3) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$74 = xer_src1__data_o[0]; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_so_mul0_4$next = rp_XER_xer_so_mul0_4; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_so_mul0_4$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$75 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_so_mul0_4) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$75 = xer_src1__data_o[0]; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_so_shiftrot0_5$next = rp_XER_xer_so_shiftrot0_5; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_so_shiftrot0_5$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src4_i$76 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_so_shiftrot0_5) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src4_i$76 = xer_src1__data_o[0]; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_ca_alu0_0$next = rp_XER_xer_ca_alu0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_ca_alu0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src4_i$77 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_ca_alu0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src4_i$77 = xer_src2__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_ca_spr0_1$next = rp_XER_xer_ca_spr0_1; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_ca_spr0_1$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_src6_i = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_ca_spr0_1) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + fus_src6_i = xer_src2__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_ca_shiftrot0_2$next = rp_XER_xer_ca_shiftrot0_2; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_ca_shiftrot0_2$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_src5_i = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_ca_shiftrot0_2) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + fus_src5_i = xer_src2__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_XER_xer_ov_spr0_0$next = rp_XER_xer_ov_spr0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_XER_xer_ov_spr0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src5_i$78 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_XER_xer_ov_spr0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src5_i$78 = xer_src3__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_CR_full_cr_cr0_0$next = rp_CR_full_cr_cr0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_CR_full_cr_cr0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$79 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_CR_full_cr_cr0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$79 = cr_full_rd__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_CR_cr_a_cr0_0$next = rp_CR_cr_a_cr0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_CR_cr_a_cr0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src4_i$80 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_CR_cr_a_cr0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src4_i$80 = cr_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_CR_cr_a_branch0_1$next = rp_CR_cr_a_branch0_1; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_CR_cr_a_branch0_1$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$83 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_CR_cr_a_branch0_1) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$83 = cr_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_CR_cr_b_cr0_0$next = rp_CR_cr_b_cr0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_CR_cr_b_cr0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \counter$next = counter; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) + casez (\$221 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" */ + 1'h1: + \counter$next = \$223 [1:0]; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + \counter$next = 2'h2; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \counter$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src5_i$84 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_CR_cr_b_cr0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src5_i$84 = cr_src2__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_CR_cr_c_cr0_0$next = rp_CR_cr_c_cr0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_CR_cr_c_cr0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src6_i$85 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_CR_cr_c_cr0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src6_i$85 = cr_src3__data_o; + endcase + end + always @* begin + if (\initial ) begin end + corebusy_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) + casez (\$226 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" */ + 1'h1: + corebusy_o = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + corebusy_o = 1'h1; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = fus_cu_busy_o; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$14 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$17 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$20 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$23 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$26 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$29 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$32 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$35 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$38 ; + endcase + end + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dp_FAST_fast1_branch0_0$next = rp_FAST_fast1_branch0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_FAST_fast1_branch0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src1_i$86 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_FAST_fast1_branch0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src1_i$86 = fast_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \core_terminate_o$next = core_terminate_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + \core_terminate_o$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \core_terminate_o$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dp_FAST_fast1_trap0_1$next = rp_FAST_fast1_trap0_1; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_FAST_fast1_trap0_1$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$87 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_FAST_fast1_trap0_1) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$87 = fast_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_FAST_fast1_spr0_2$next = rp_FAST_fast1_spr0_2; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_FAST_fast1_spr0_2$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src3_i$88 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_FAST_fast1_spr0_2) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src3_i$88 = fast_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__insn_type = dec_ALU_ALU__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dp_FAST_fast1_branch0_3$next = rp_FAST_fast1_branch0_3; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_FAST_fast1_branch0_3$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$89 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_FAST_fast1_branch0_3) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$89 = fast_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + \dp_FAST_fast1_trap0_4$next = rp_FAST_fast1_trap0_4; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_FAST_fast1_trap0_4$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src4_i$90 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_FAST_fast1_trap0_4) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src4_i$90 = fast_src1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__fn_unit = dec_ALU_ALU__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dp_SPR_spr1_spr0_0$next = rp_SPR_spr1_spr0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dp_SPR_spr1_spr0_0$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_src2_i$91 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *) + casez (dp_SPR_spr1_spr0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */ + 1'h1: + \fus_src2_i$91 = spr_spr1__data_o; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_alu0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_alu0__imm_data__ok, fus_oper_i_alu_alu0__imm_data__data } = { dec_ALU_ALU__imm_data__ok, dec_ALU_ALU__imm_data__data }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$next = wr_pick; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$989$next = \wr_pick$986 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$989$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1008$next = \wr_pick$1005 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1008$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__rc__rc = 1'h0; + fus_oper_i_alu_alu0__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_alu0__rc__ok, fus_oper_i_alu_alu0__rc__rc } = { dec_ALU_ALU__rc__ok, dec_ALU_ALU__rc__rc }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1029$next = \wr_pick$1026 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1029$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1047$next = \wr_pick$1044 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1047$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1069$next = \wr_pick$1066 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1069$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__oe__oe = 1'h0; + fus_oper_i_alu_alu0__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_alu0__oe__ok, fus_oper_i_alu_alu0__oe__oe } = { dec_ALU_ALU__oe__ok, dec_ALU_ALU__oe__oe }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1089$next = \wr_pick$1086 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1089$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1109$next = \wr_pick$1106 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1109$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1128$next = \wr_pick$1125 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1128$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__invert_in = dec_ALU_ALU__invert_in; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1146$next = \wr_pick$1143 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1146$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__zero_a = dec_ALU_ALU__zero_a; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1220$next = \wr_pick$1217 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1220$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__invert_out = dec_ALU_ALU__invert_out; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1248$next = \wr_pick$1245 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1248$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__write_cr0 = dec_ALU_ALU__write_cr0; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1268$next = \wr_pick$1265 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1268$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1288$next = \wr_pick$1285 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1288$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__input_carry = dec_ALU_ALU__input_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1308$next = \wr_pick$1305 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1308$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1328$next = \wr_pick$1325 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1328$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__output_carry = dec_ALU_ALU__output_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1348$next = \wr_pick$1345 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1348$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__is_32bit = dec_ALU_ALU__is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1395$next = \wr_pick$1392 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1395$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__is_signed = dec_ALU_ALU__is_signed; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1411$next = \wr_pick$1408 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1411$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1427$next = \wr_pick$1424 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1427$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__data_len = dec_ALU_ALU__data_len; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1461$next = \wr_pick$1458 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1461$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_alu0__insn = dec_ALU_ALU__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1477$next = \wr_pick$1474 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1477$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1493$next = \wr_pick$1490 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1493$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_cu_issue_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_cu_issue_i = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1509$next = \wr_pick$1506 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1509$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_cu_rdmaskn_i = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_cu_rdmaskn_i = \$228 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1545$next = \wr_pick$1542 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1545$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1561$next = \wr_pick$1558 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1561$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_cr0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_cr0__insn_type = dec_CR_CR__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1577$next = \wr_pick$1574 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1577$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_cr0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_cr0__fn_unit = dec_CR_CR__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1593$next = \wr_pick$1590 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1593$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1635$next = \wr_pick$1632 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1635$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_cr0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_cr0__insn = dec_CR_CR__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1654$next = \wr_pick$1651 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1654$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$13 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1670$next = \wr_pick$1667 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1670$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1686$next = \wr_pick$1683 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1686$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$15 = 6'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$15 = \$250 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1702$next = \wr_pick$1699 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1702$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__cia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_branch0__cia = dec_BRANCH_BRANCH__cia; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1746$next = \wr_pick$1743 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1746$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_branch0__insn_type = dec_BRANCH_BRANCH__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1762$next = \wr_pick$1759 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1762$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1786$next = \wr_pick$1783 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1786$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_branch0__fn_unit = dec_BRANCH_BRANCH__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1806$next = \wr_pick$1803 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1806$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_branch0__insn = dec_BRANCH_BRANCH__insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_branch0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_branch0__imm_data__ok, fus_oper_i_alu_branch0__imm_data__data } = { dec_BRANCH_BRANCH__imm_data__ok, dec_BRANCH_BRANCH__imm_data__data }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_branch0__lk = dec_BRANCH_BRANCH__lk; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_branch0__is_32bit = dec_BRANCH_BRANCH__is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$16 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$16 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$18 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$18 = \$252 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__insn_type = core_core_insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__fn_unit = core_core_fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__insn = core_core_insn; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__msr = core_core_msr; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__cia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__cia = core_core_cia; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__is_32bit = core_core_is_32bit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__traptype = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__traptype = core_core_traptype; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__trapaddr = 13'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__trapaddr = core_core_trapaddr; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__ldst_exc = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_trap0__ldst_exc = { \core_core_exc_$signal$9 , \core_core_exc_$signal$8 , \core_core_exc_$signal$7 , \core_core_exc_$signal$6 , \core_core_exc_$signal$5 , \core_core_exc_$signal$4 , \core_core_exc_$signal$3 , \core_core_exc_$signal }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$19 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_issue_i$19 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$21 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + \fus_cu_rdmaskn_i$21 = \$254 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__insn_type = dec_LOGICAL_LOGICAL__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__fn_unit = dec_LOGICAL_LOGICAL__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_logical0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_logical0__imm_data__ok, fus_oper_i_alu_logical0__imm_data__data } = { dec_LOGICAL_LOGICAL__imm_data__ok, dec_LOGICAL_LOGICAL__imm_data__data }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__rc__rc = 1'h0; + fus_oper_i_alu_logical0__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_logical0__rc__ok, fus_oper_i_alu_logical0__rc__rc } = { dec_LOGICAL_LOGICAL__rc__ok, dec_LOGICAL_LOGICAL__rc__rc }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__oe__oe = 1'h0; + fus_oper_i_alu_logical0__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + { fus_oper_i_alu_logical0__oe__ok, fus_oper_i_alu_logical0__oe__oe } = { dec_LOGICAL_LOGICAL__oe__ok, dec_LOGICAL_LOGICAL__oe__oe }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__invert_in = dec_LOGICAL_LOGICAL__invert_in; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__zero_a = dec_LOGICAL_LOGICAL__zero_a; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__input_carry = dec_LOGICAL_LOGICAL__input_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__invert_out = dec_LOGICAL_LOGICAL__invert_out; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */ + 1'h1: + fus_oper_i_alu_logical0__write_cr0 = dec_LOGICAL_LOGICAL__write_cr0; + endcase + endcase + endcase + end + assign \$223 = \$224 ; + assign \$580 = \$615 ; + assign \$829 = \$830 ; + assign \$1157 = \$1174 ; + assign \$1176 = \$1193 ; + assign \$1373 = \$1382 ; + assign o_ok = 1'h0; + assign ea_ok = 1'h0; + assign spr_spr1__wen = \wp$1811 ; + assign \spr_spr1__addr$175 = \addr_en$1814 [3:0]; + assign spr_spr1__data_i = \fus_dest2_o$162 ; + assign \addr_en$1814 = \$1815 ; + assign \wp$1811 = \$1812 ; + assign \wr_pick_rise$1057 = \$1809 ; + assign \wr_pick$1803 = \$1804 ; + assign wrpick_SPR_spr1_i = \$1801 ; + assign wrflag_spr0_spr1_1 = \$1799 ; + assign state_wen = \$1797 ; + assign \state_data_i$174 = \fus_dest5_o$161 ; + assign \addr_en$1794 = \$1795 ; + assign \wp$1791 = \$1792 ; + assign \wr_pick_rise$1017 = \$1789 ; + assign \wr_pick$1783 = \$1784 ; + assign wrpick_STATE_msr_i = \$1781 ; + assign wrflag_trap0_msr_4 = \$1779 ; + assign state_nia_wen = \$1775 ; + assign state_data_i = \$1773 ; + assign \addr_en$1770 = \$1771 ; + assign \wp$1767 = \$1768 ; + assign \wr_pick_rise$1016 = \$1765 ; + assign \wr_pick$1759 = \$1760 ; + assign wrflag_trap0_nia_3 = \$1757 ; + assign \addr_en$1754 = \$1755 ; + assign \wp$1751 = \$1752 ; + assign \wr_pick_rise$1642 = \$1749 ; + assign \wr_pick$1743 = \$1744 ; + assign wrpick_STATE_nia_i[1] = \$1741 ; + assign wrpick_STATE_nia_i[0] = \$1739 ; + assign wrflag_branch0_nia_2 = \$1737 ; + assign fast_dest1__wen = \$1735 ; + assign fast_dest1__addr = \$1727 ; + assign fast_dest1__data_i = \$1719 ; + assign \addr_en$1710 = \$1711 ; + assign \wp$1707 = \$1708 ; + assign \wr_pick_rise$1015 = \$1705 ; + assign \wr_pick$1699 = \$1700 ; + assign wrflag_trap0_fast1_2 = \$1697 ; + assign \addr_en$1694 = \$1695 ; + assign \wp$1691 = \$1692 ; + assign \wr_pick_rise$1641 = \$1689 ; + assign \wr_pick$1683 = \$1684 ; + assign wrflag_branch0_fast1_1 = \$1681 ; + assign \addr_en$1678 = \$1679 ; + assign \wp$1675 = \$1676 ; + assign \wr_pick_rise$1056 = \$1673 ; + assign \wr_pick$1667 = \$1668 ; + assign wrflag_spr0_fast1_2 = \$1665 ; + assign \addr_en$1662 = \$1663 ; + assign \wp$1659 = \$1660 ; + assign \wr_pick_rise$1014 = \$1657 ; + assign \wr_pick$1651 = \$1652 ; + assign wrflag_trap0_fast1_1 = \$1649 ; + assign \addr_en$1646 = \$1647 ; + assign \wp$1643 = \$1644 ; + assign \fus_cu_wr__go_i$149 [2] = \wr_pick_rise$1642 ; + assign \fus_cu_wr__go_i$149 [1] = \wr_pick_rise$1641 ; + assign \fus_cu_wr__go_i$149 [0] = \wr_pick_rise$1636 ; + assign \wr_pick_rise$1636 = \$1639 ; + assign \wr_pick$1632 = \$1633 ; + assign wrpick_FAST_fast1_i[4] = \$1630 ; + assign wrpick_FAST_fast1_i[3] = \$1628 ; + assign wrpick_FAST_fast1_i[2] = \$1626 ; + assign wrpick_FAST_fast1_i[1] = \$1624 ; + assign wrpick_FAST_fast1_i[0] = \$1622 ; + assign wrflag_branch0_fast1_0 = \$1620 ; + assign \xer_wen$173 = \$1612 ; + assign \xer_data_i$172 = \$1604 ; + assign \addr_en$1601 = \$1602 ; + assign \wp$1598 = \$1599 ; + assign \wr_pick_rise$1097 = \$1596 ; + assign \wr_pick$1590 = \$1591 ; + assign wrflag_mul0_xer_so_3 = \$1588 ; + assign \addr_en$1585 = \$1586 ; + assign \wp$1582 = \$1583 ; + assign \wr_pick_rise$1077 = \$1580 ; + assign \wr_pick$1574 = \$1575 ; + assign wrflag_div0_xer_so_3 = \$1572 ; + assign \addr_en$1569 = \$1570 ; + assign \wp$1566 = \$1567 ; + assign \wr_pick_rise$1055 = \$1564 ; + assign \wr_pick$1558 = \$1559 ; + assign wrflag_spr0_xer_so_3 = \$1556 ; + assign \addr_en$1553 = \$1554 ; + assign \wp$1550 = \$1551 ; + assign \wr_pick_rise$979 = \$1548 ; + assign \wr_pick$1542 = \$1543 ; + assign wrpick_XER_xer_so_i[3] = \$1540 ; + assign wrpick_XER_xer_so_i[2] = \$1538 ; + assign wrpick_XER_xer_so_i[1] = \$1536 ; + assign wrpick_XER_xer_so_i[0] = \$1534 ; + assign wrflag_alu0_xer_so_4 = \$1532 ; + assign \xer_wen$171 = \$1530 ; + assign \xer_data_i$170 = \$1524 ; + assign \addr_en$1517 = \$1518 ; + assign \wp$1514 = \$1515 ; + assign \wr_pick_rise$1096 = \$1512 ; + assign \wr_pick$1506 = \$1507 ; + assign wrflag_mul0_xer_ov_2 = \$1504 ; + assign \addr_en$1501 = \$1502 ; + assign \wp$1498 = \$1499 ; + assign \wr_pick_rise$1076 = \$1496 ; + assign \wr_pick$1490 = \$1491 ; + assign wrflag_div0_xer_ov_2 = \$1488 ; + assign \addr_en$1485 = \$1486 ; + assign \wp$1482 = \$1483 ; + assign \wr_pick_rise$1054 = \$1480 ; + assign \wr_pick$1474 = \$1475 ; + assign wrflag_spr0_xer_ov_4 = \$1472 ; + assign \addr_en$1469 = \$1470 ; + assign \wp$1466 = \$1467 ; + assign \wr_pick_rise$978 = \$1464 ; + assign \wr_pick$1458 = \$1459 ; + assign wrpick_XER_xer_ov_i[3] = \$1456 ; + assign wrpick_XER_xer_ov_i[2] = \$1454 ; + assign wrpick_XER_xer_ov_i[1] = \$1452 ; + assign wrpick_XER_xer_ov_i[0] = \$1450 ; + assign wrflag_alu0_xer_ov_3 = \$1448 ; + assign xer_wen = \$1442 ; + assign xer_data_i = \$1440 ; + assign \addr_en$1435 = \$1436 ; + assign \wp$1432 = \$1433 ; + assign \wr_pick_rise$1116 = \$1430 ; + assign \wr_pick$1424 = \$1425 ; + assign wrflag_shiftrot0_xer_ca_2 = \$1422 ; + assign \addr_en$1419 = \$1420 ; + assign \wp$1416 = \$1417 ; + assign \wr_pick_rise$1053 = \$1414 ; + assign \wr_pick$1408 = \$1409 ; + assign wrflag_spr0_xer_ca_5 = \$1406 ; + assign \addr_en$1403 = \$1404 ; + assign \wp$1400 = \$1401 ; + assign \wr_pick_rise$977 = \$1398 ; + assign \wr_pick$1392 = \$1393 ; + assign wrpick_XER_xer_ca_i[2] = \$1390 ; + assign wrpick_XER_xer_ca_i[1] = \$1388 ; + assign wrpick_XER_xer_ca_i[0] = \$1386 ; + assign wrflag_alu0_xer_ca_2 = \$1384 ; + assign cr_wen = \$1382 [7:0]; + assign cr_data_i = \$1371 ; + assign \addr_en$1356 = \$1361 ; + assign \wp$1353 = \$1354 ; + assign \wr_pick_rise$1115 = \$1351 ; + assign \wr_pick$1345 = \$1346 ; + assign wrflag_shiftrot0_cr_a_1 = \$1343 ; + assign \addr_en$1336 = \$1341 ; + assign \wp$1333 = \$1334 ; + assign \wr_pick_rise$1095 = \$1331 ; + assign \wr_pick$1325 = \$1326 ; + assign wrflag_mul0_cr_a_1 = \$1323 ; + assign \addr_en$1316 = \$1321 ; + assign \wp$1313 = \$1314 ; + assign \wr_pick_rise$1075 = \$1311 ; + assign \wr_pick$1305 = \$1306 ; + assign wrflag_div0_cr_a_1 = \$1303 ; + assign \addr_en$1296 = \$1301 ; + assign \wp$1293 = \$1294 ; + assign \wr_pick_rise$1035 = \$1291 ; + assign \wr_pick$1285 = \$1286 ; + assign wrflag_logical0_cr_a_1 = \$1283 ; + assign \addr_en$1276 = \$1281 ; + assign \wp$1273 = \$1274 ; + assign \wr_pick_rise$996 = \$1271 ; + assign \wr_pick$1265 = \$1266 ; + assign wrflag_cr0_cr_a_2 = \$1263 ; + assign \addr_en$1256 = \$1261 ; + assign \wp$1253 = \$1254 ; + assign \wr_pick_rise$976 = \$1251 ; + assign \wr_pick$1245 = \$1246 ; + assign wrpick_CR_cr_a_i[5] = \$1243 ; + assign wrpick_CR_cr_a_i[4] = \$1241 ; + assign wrpick_CR_cr_a_i[3] = \$1239 ; + assign wrpick_CR_cr_a_i[2] = \$1237 ; + assign wrpick_CR_cr_a_i[1] = \$1235 ; + assign wrpick_CR_cr_a_i[0] = \$1233 ; + assign wrflag_alu0_cr_a_1 = \$1231 ; + assign cr_full_wr__wen = \addr_en$1228 ; + assign cr_full_wr__data_i = fus_dest2_o; + assign \addr_en$1228 = \$1229 ; + assign \wp$1225 = \$1226 ; + assign \wr_pick_rise$995 = \$1223 ; + assign \wr_pick$1217 = \$1218 ; + assign wrpick_CR_full_cr_i = \$1215 ; + assign wrflag_cr0_full_cr_1 = \$1213 ; + assign int_dest1__wen = \$1211 ; + assign int_dest1__addr = \$1193 [4:0]; + assign int_dest1__data_i = \$1174 [63:0]; + assign \addr_en$1154 = \$1155 ; + assign \wp$1151 = \$1152 ; + assign \wr_pick_rise$1134 = \$1149 ; + assign \wr_pick$1143 = \$1144 ; + assign wrflag_ldst0_o_1 = \$1141 ; + assign \addr_en$1138 = \$1139 ; + assign \wp$1135 = \$1136 ; + assign \fus_cu_wr__go_i$114 [1] = \wr_pick_rise$1134 ; + assign \fus_cu_wr__go_i$114 [0] = \wr_pick_rise$1129 ; + assign \wr_pick_rise$1129 = \$1132 ; + assign \wr_pick$1125 = \$1126 ; + assign wrflag_ldst0_o_0 = \$1123 ; + assign \addr_en$1120 = \$1121 ; + assign \wp$1117 = \$1118 ; + assign \fus_cu_wr__go_i$112 [2] = \wr_pick_rise$1116 ; + assign \fus_cu_wr__go_i$112 [1] = \wr_pick_rise$1115 ; + assign \fus_cu_wr__go_i$112 [0] = \wr_pick_rise$1110 ; + assign \wr_pick_rise$1110 = \$1113 ; + assign \wr_pick$1106 = \$1107 ; + assign wrflag_shiftrot0_o_0 = \$1104 ; + assign \addr_en$1101 = \$1102 ; + assign \wp$1098 = \$1099 ; + assign \fus_cu_wr__go_i$109 [3] = \wr_pick_rise$1097 ; + assign \fus_cu_wr__go_i$109 [2] = \wr_pick_rise$1096 ; + assign \fus_cu_wr__go_i$109 [1] = \wr_pick_rise$1095 ; + assign \fus_cu_wr__go_i$109 [0] = \wr_pick_rise$1090 ; + assign \wr_pick_rise$1090 = \$1093 ; + assign \wr_pick$1086 = \$1087 ; + assign wrflag_mul0_o_0 = \$1084 ; + assign \addr_en$1081 = \$1082 ; + assign \wp$1078 = \$1079 ; + assign \fus_cu_wr__go_i$106 [3] = \wr_pick_rise$1077 ; + assign \fus_cu_wr__go_i$106 [2] = \wr_pick_rise$1076 ; + assign \fus_cu_wr__go_i$106 [1] = \wr_pick_rise$1075 ; + assign \fus_cu_wr__go_i$106 [0] = \wr_pick_rise$1070 ; + assign \wr_pick_rise$1070 = \$1073 ; + assign \wr_pick$1066 = \$1067 ; + assign wrflag_div0_o_0 = \$1064 ; + assign \addr_en$1061 = \$1062 ; + assign \wp$1058 = \$1059 ; + assign \fus_cu_wr__go_i$103 [1] = \wr_pick_rise$1057 ; + assign \fus_cu_wr__go_i$103 [2] = \wr_pick_rise$1056 ; + assign \fus_cu_wr__go_i$103 [3] = \wr_pick_rise$1055 ; + assign \fus_cu_wr__go_i$103 [4] = \wr_pick_rise$1054 ; + assign \fus_cu_wr__go_i$103 [5] = \wr_pick_rise$1053 ; + assign \fus_cu_wr__go_i$103 [0] = \wr_pick_rise$1048 ; + assign \wr_pick_rise$1048 = \$1051 ; + assign \wr_pick$1044 = \$1045 ; + assign wrflag_spr0_o_0 = \$1042 ; + assign \addr_en$1039 = \$1040 ; + assign \wp$1036 = \$1037 ; + assign \fus_cu_wr__go_i$100 [1] = \wr_pick_rise$1035 ; + assign \fus_cu_wr__go_i$100 [0] = \wr_pick_rise$1030 ; + assign \wr_pick_rise$1030 = \$1033 ; + assign \wr_pick$1026 = \$1027 ; + assign wrflag_logical0_o_0 = \$1024 ; + assign \addr_en$1021 = \$1022 ; + assign \wp$1018 = \$1019 ; + assign \fus_cu_wr__go_i$97 [4] = \wr_pick_rise$1017 ; + assign \fus_cu_wr__go_i$97 [3] = \wr_pick_rise$1016 ; + assign \fus_cu_wr__go_i$97 [2] = \wr_pick_rise$1015 ; + assign \fus_cu_wr__go_i$97 [1] = \wr_pick_rise$1014 ; + assign \fus_cu_wr__go_i$97 [0] = \wr_pick_rise$1009 ; + assign \wr_pick_rise$1009 = \$1012 ; + assign \wr_pick$1005 = \$1006 ; + assign wrflag_trap0_o_0 = \$1003 ; + assign \addr_en$1000 = \$1001 ; + assign \wp$997 = \$998 ; + assign \fus_cu_wr__go_i$94 [2] = \wr_pick_rise$996 ; + assign \fus_cu_wr__go_i$94 [1] = \wr_pick_rise$995 ; + assign \fus_cu_wr__go_i$94 [0] = \wr_pick_rise$990 ; + assign \wr_pick_rise$990 = \$993 ; + assign \wr_pick$986 = \$987 ; + assign wrflag_cr0_o_0 = \$984 ; + assign addr_en = \$982 ; + assign wp = \$980 ; + assign fus_cu_wr__go_i[4] = \wr_pick_rise$979 ; + assign fus_cu_wr__go_i[3] = \wr_pick_rise$978 ; + assign fus_cu_wr__go_i[2] = \wr_pick_rise$977 ; + assign fus_cu_wr__go_i[1] = \wr_pick_rise$976 ; + assign fus_cu_wr__go_i[0] = wr_pick_rise; + assign wr_pick_rise = \$974 ; + assign wr_pick = \$970 ; + assign wrpick_INT_o_i[9] = \$968 ; + assign wrpick_INT_o_i[8] = \$966 ; + assign wrpick_INT_o_i[7] = \$964 ; + assign wrpick_INT_o_i[6] = \$962 ; + assign wrpick_INT_o_i[5] = \$960 ; + assign wrpick_INT_o_i[4] = \$958 ; + assign wrpick_INT_o_i[3] = \$956 ; + assign wrpick_INT_o_i[2] = \$954 ; + assign wrpick_INT_o_i[1] = \$952 ; + assign wrpick_INT_o_i[0] = \$950 ; + assign wrflag_alu0_o_0 = \$948 ; + assign spr_spr1__ren = \$946 ; + assign spr_spr1__addr = addr_en_SPR_spr1_spr0_0[3:0]; + assign addr_en_SPR_spr1_spr0_0 = \$944 ; + assign rp_SPR_spr1_spr0_0 = \$942 ; + assign rdpick_SPR_spr1_i = pick_SPR_spr1_spr0_0; + assign pick_SPR_spr1_spr0_0 = \$940 ; + assign rdflag_SPR_spr1_0 = core_spr1_ok; + assign fast_src1__ren = \$932 ; + assign fast_src1__addr = \$930 ; + assign addr_en_FAST_fast1_trap0_4 = \$922 ; + assign rp_FAST_fast1_trap0_4 = \$920 ; + assign pick_FAST_fast1_trap0_4 = \$918 ; + assign addr_en_FAST_fast1_branch0_3 = \$910 ; + assign rp_FAST_fast1_branch0_3 = \$908 ; + assign pick_FAST_fast1_branch0_3 = \$906 ; + assign addr_en_FAST_fast1_spr0_2 = \$898 ; + assign rp_FAST_fast1_spr0_2 = \$896 ; + assign pick_FAST_fast1_spr0_2 = \$894 ; + assign addr_en_FAST_fast1_trap0_1 = \$886 ; + assign rp_FAST_fast1_trap0_1 = \$884 ; + assign pick_FAST_fast1_trap0_1 = \$882 ; + assign addr_en_FAST_fast1_branch0_0 = \$874 ; + assign rp_FAST_fast1_branch0_0 = \$872 ; + assign rdpick_FAST_fast1_i[4] = pick_FAST_fast1_trap0_4; + assign rdpick_FAST_fast1_i[3] = pick_FAST_fast1_branch0_3; + assign rdpick_FAST_fast1_i[2] = pick_FAST_fast1_spr0_2; + assign rdpick_FAST_fast1_i[1] = pick_FAST_fast1_trap0_1; + assign rdpick_FAST_fast1_i[0] = pick_FAST_fast1_branch0_0; + assign pick_FAST_fast1_branch0_0 = \$870 ; + assign rdflag_FAST_fast1_1 = core_fast2_ok; + assign rdflag_FAST_fast1_0 = core_fast1_ok; + assign cr_src3__ren = addr_en_CR_cr_c_cr0_0[7:0]; + assign addr_en_CR_cr_c_cr0_0 = \$862 ; + assign rp_CR_cr_c_cr0_0 = \$856 ; + assign rdpick_CR_cr_c_i = pick_CR_cr_c_cr0_0; + assign pick_CR_cr_c_cr0_0 = \$854 ; + assign rdflag_CR_cr_c_0 = \core_cr_in2_ok$2 ; + assign cr_src2__ren = addr_en_CR_cr_b_cr0_0[7:0]; + assign addr_en_CR_cr_b_cr0_0 = \$846 ; + assign rp_CR_cr_b_cr0_0 = \$840 ; + assign rdpick_CR_cr_b_i = pick_CR_cr_b_cr0_0; + assign pick_CR_cr_b_cr0_0 = \$838 ; + assign rdflag_CR_cr_b_0 = core_cr_in2_ok; + assign cr_src1__ren = \$830 [7:0]; + assign addr_en_CR_cr_a_branch0_1 = \$827 ; + assign rp_CR_cr_a_branch0_1 = \$821 ; + assign \fus_cu_rd__go_i$82 [1] = dp_FAST_fast1_branch0_3; + assign \fus_cu_rd__go_i$82 [0] = dp_FAST_fast1_branch0_0; + assign \fus_cu_rd__go_i$82 [2] = dp_CR_cr_a_branch0_1; + assign pick_CR_cr_a_branch0_1 = \$819 ; + assign addr_en_CR_cr_a_cr0_0 = \$811 ; + assign rp_CR_cr_a_cr0_0 = \$805 ; + assign rdpick_CR_cr_a_i[1] = pick_CR_cr_a_branch0_1; + assign rdpick_CR_cr_a_i[0] = pick_CR_cr_a_cr0_0; + assign pick_CR_cr_a_cr0_0 = \$803 ; + assign rdflag_CR_cr_a_0 = core_cr_in1_ok; + assign cr_full_rd__ren = addr_en_CR_full_cr_cr0_0; + assign addr_en_CR_full_cr_cr0_0 = \$795 ; + assign rp_CR_full_cr_cr0_0 = \$793 ; + assign rdpick_CR_full_cr_i = pick_CR_full_cr_cr0_0; + assign pick_CR_full_cr_cr0_0 = \$791 ; + assign rdflag_CR_full_cr_0 = core_core_cr_rd_ok; + assign xer_src3__ren = addr_en_XER_xer_ov_spr0_0; + assign addr_en_XER_xer_ov_spr0_0 = \$783 ; + assign rp_XER_xer_ov_spr0_0 = \$781 ; + assign rdpick_XER_xer_ov_i = pick_XER_xer_ov_spr0_0; + assign pick_XER_xer_ov_spr0_0 = \$779 ; + assign rdflag_XER_xer_ov_0 = \$771 ; + assign xer_src2__ren = \$759 ; + assign addr_en_XER_xer_ca_shiftrot0_2 = \$757 ; + assign rp_XER_xer_ca_shiftrot0_2 = \$755 ; + assign pick_XER_xer_ca_shiftrot0_2 = \$753 ; + assign addr_en_XER_xer_ca_spr0_1 = \$745 ; + assign rp_XER_xer_ca_spr0_1 = \$743 ; + assign pick_XER_xer_ca_spr0_1 = \$741 ; + assign addr_en_XER_xer_ca_alu0_0 = \$733 ; + assign rp_XER_xer_ca_alu0_0 = \$731 ; + assign rdpick_XER_xer_ca_i[2] = pick_XER_xer_ca_shiftrot0_2; + assign rdpick_XER_xer_ca_i[1] = pick_XER_xer_ca_spr0_1; + assign rdpick_XER_xer_ca_i[0] = pick_XER_xer_ca_alu0_0; + assign pick_XER_xer_ca_alu0_0 = \$729 ; + assign rdflag_XER_xer_ca_0 = \$721 ; + assign xer_src1__ren = \$703 ; + assign addr_en_XER_xer_so_shiftrot0_5 = \$701 ; + assign rp_XER_xer_so_shiftrot0_5 = \$699 ; + assign pick_XER_xer_so_shiftrot0_5 = \$697 ; + assign addr_en_XER_xer_so_mul0_4 = \$689 ; + assign rp_XER_xer_so_mul0_4 = \$687 ; + assign pick_XER_xer_so_mul0_4 = \$685 ; + assign addr_en_XER_xer_so_div0_3 = \$677 ; + assign rp_XER_xer_so_div0_3 = \$675 ; + assign pick_XER_xer_so_div0_3 = \$673 ; + assign addr_en_XER_xer_so_spr0_2 = \$665 ; + assign rp_XER_xer_so_spr0_2 = \$663 ; + assign pick_XER_xer_so_spr0_2 = \$661 ; + assign addr_en_XER_xer_so_logical0_1 = \$653 ; + assign rp_XER_xer_so_logical0_1 = \$651 ; + assign pick_XER_xer_so_logical0_1 = \$649 ; + assign addr_en_XER_xer_so_alu0_0 = \$641 ; + assign rp_XER_xer_so_alu0_0 = \$639 ; + assign rdpick_XER_xer_so_i[5] = pick_XER_xer_so_shiftrot0_5; + assign rdpick_XER_xer_so_i[4] = pick_XER_xer_so_mul0_4; + assign rdpick_XER_xer_so_i[3] = pick_XER_xer_so_div0_3; + assign rdpick_XER_xer_so_i[2] = pick_XER_xer_so_spr0_2; + assign rdpick_XER_xer_so_i[1] = pick_XER_xer_so_logical0_1; + assign rdpick_XER_xer_so_i[0] = pick_XER_xer_so_alu0_0; + assign pick_XER_xer_so_alu0_0 = \$637 ; + assign rdflag_XER_xer_so_0 = \$629 ; + assign int_src1__ren = \$617 ; + assign int_src1__addr = \$615 [4:0]; + assign addr_en_INT_rabc_ldst0_18 = \$578 ; + assign rp_INT_rabc_ldst0_18 = \$576 ; + assign pick_INT_rabc_ldst0_18 = \$574 ; + assign addr_en_INT_rabc_shiftrot0_17 = \$566 ; + assign rp_INT_rabc_shiftrot0_17 = \$564 ; + assign pick_INT_rabc_shiftrot0_17 = \$562 ; + assign addr_en_INT_rabc_mul0_16 = \$554 ; + assign rp_INT_rabc_mul0_16 = \$552 ; + assign pick_INT_rabc_mul0_16 = \$550 ; + assign addr_en_INT_rabc_div0_15 = \$542 ; + assign rp_INT_rabc_div0_15 = \$540 ; + assign pick_INT_rabc_div0_15 = \$538 ; + assign addr_en_INT_rabc_spr0_14 = \$530 ; + assign rp_INT_rabc_spr0_14 = \$528 ; + assign \fus_cu_rd__go_i$66 [1] = dp_SPR_spr1_spr0_0; + assign \fus_cu_rd__go_i$66 [2] = dp_FAST_fast1_spr0_2; + assign \fus_cu_rd__go_i$66 [4] = dp_XER_xer_ov_spr0_0; + assign \fus_cu_rd__go_i$66 [5] = dp_XER_xer_ca_spr0_1; + assign \fus_cu_rd__go_i$66 [3] = dp_XER_xer_so_spr0_2; + assign \fus_cu_rd__go_i$66 [0] = dp_INT_rabc_spr0_14; + assign pick_INT_rabc_spr0_14 = \$526 ; + assign addr_en_INT_rabc_logical0_13 = \$518 ; + assign rp_INT_rabc_logical0_13 = \$516 ; + assign pick_INT_rabc_logical0_13 = \$514 ; + assign addr_en_INT_rabc_trap0_12 = \$506 ; + assign rp_INT_rabc_trap0_12 = \$504 ; + assign pick_INT_rabc_trap0_12 = \$502 ; + assign addr_en_INT_rabc_cr0_11 = \$494 ; + assign rp_INT_rabc_cr0_11 = \$492 ; + assign pick_INT_rabc_cr0_11 = \$490 ; + assign addr_en_INT_rabc_alu0_10 = \$482 ; + assign rp_INT_rabc_alu0_10 = \$480 ; + assign pick_INT_rabc_alu0_10 = \$478 ; + assign addr_en_INT_rabc_ldst0_9 = \$470 ; + assign rp_INT_rabc_ldst0_9 = \$468 ; + assign pick_INT_rabc_ldst0_9 = \$466 ; + assign addr_en_INT_rabc_shiftrot0_8 = \$458 ; + assign rp_INT_rabc_shiftrot0_8 = \$456 ; + assign pick_INT_rabc_shiftrot0_8 = \$454 ; + assign addr_en_INT_rabc_ldst0_7 = \$446 ; + assign rp_INT_rabc_ldst0_7 = \$444 ; + assign \fus_cu_rd__go_i$59 [0] = dp_INT_rabc_ldst0_18; + assign \fus_cu_rd__go_i$59 [2] = dp_INT_rabc_ldst0_9; + assign \fus_cu_rd__go_i$59 [1] = dp_INT_rabc_ldst0_7; + assign pick_INT_rabc_ldst0_7 = \$442 ; + assign addr_en_INT_rabc_shiftrot0_6 = \$434 ; + assign rp_INT_rabc_shiftrot0_6 = \$432 ; + assign \fus_cu_rd__go_i$56 [4] = dp_XER_xer_ca_shiftrot0_2; + assign \fus_cu_rd__go_i$56 [3] = dp_XER_xer_so_shiftrot0_5; + assign \fus_cu_rd__go_i$56 [0] = dp_INT_rabc_shiftrot0_17; + assign \fus_cu_rd__go_i$56 [2] = dp_INT_rabc_shiftrot0_8; + assign \fus_cu_rd__go_i$56 [1] = dp_INT_rabc_shiftrot0_6; + assign pick_INT_rabc_shiftrot0_6 = \$430 ; + assign addr_en_INT_rabc_mul0_5 = \$422 ; + assign rp_INT_rabc_mul0_5 = \$420 ; + assign \fus_cu_rd__go_i$53 [2] = dp_XER_xer_so_mul0_4; + assign \fus_cu_rd__go_i$53 [0] = dp_INT_rabc_mul0_16; + assign \fus_cu_rd__go_i$53 [1] = dp_INT_rabc_mul0_5; + assign pick_INT_rabc_mul0_5 = \$418 ; + assign addr_en_INT_rabc_div0_4 = \$410 ; + assign rp_INT_rabc_div0_4 = \$408 ; + assign \fus_cu_rd__go_i$50 [2] = dp_XER_xer_so_div0_3; + assign \fus_cu_rd__go_i$50 [0] = dp_INT_rabc_div0_15; + assign \fus_cu_rd__go_i$50 [1] = dp_INT_rabc_div0_4; + assign pick_INT_rabc_div0_4 = \$406 ; + assign addr_en_INT_rabc_logical0_3 = \$398 ; + assign rp_INT_rabc_logical0_3 = \$396 ; + assign \fus_cu_rd__go_i$47 [2] = dp_XER_xer_so_logical0_1; + assign \fus_cu_rd__go_i$47 [0] = dp_INT_rabc_logical0_13; + assign \fus_cu_rd__go_i$47 [1] = dp_INT_rabc_logical0_3; + assign pick_INT_rabc_logical0_3 = \$394 ; + assign addr_en_INT_rabc_trap0_2 = \$386 ; + assign rp_INT_rabc_trap0_2 = \$384 ; + assign \fus_cu_rd__go_i$44 [3] = dp_FAST_fast1_trap0_4; + assign \fus_cu_rd__go_i$44 [2] = dp_FAST_fast1_trap0_1; + assign \fus_cu_rd__go_i$44 [0] = dp_INT_rabc_trap0_12; + assign \fus_cu_rd__go_i$44 [1] = dp_INT_rabc_trap0_2; + assign pick_INT_rabc_trap0_2 = \$382 ; + assign addr_en_INT_rabc_cr0_1 = \$374 ; + assign rp_INT_rabc_cr0_1 = \$372 ; + assign \fus_cu_rd__go_i$41 [5] = dp_CR_cr_c_cr0_0; + assign \fus_cu_rd__go_i$41 [4] = dp_CR_cr_b_cr0_0; + assign \fus_cu_rd__go_i$41 [3] = dp_CR_cr_a_cr0_0; + assign \fus_cu_rd__go_i$41 [2] = dp_CR_full_cr_cr0_0; + assign \fus_cu_rd__go_i$41 [0] = dp_INT_rabc_cr0_11; + assign \fus_cu_rd__go_i$41 [1] = dp_INT_rabc_cr0_1; + assign pick_INT_rabc_cr0_1 = \$370 ; + assign addr_en_INT_rabc_alu0_0 = \$362 ; + assign rp_INT_rabc_alu0_0 = \$360 ; + assign fus_cu_rd__go_i[3] = dp_XER_xer_ca_alu0_0; + assign fus_cu_rd__go_i[2] = dp_XER_xer_so_alu0_0; + assign fus_cu_rd__go_i[0] = dp_INT_rabc_alu0_10; + assign fus_cu_rd__go_i[1] = dp_INT_rabc_alu0_0; + assign rdpick_INT_rabc_i[18] = pick_INT_rabc_ldst0_18; + assign rdpick_INT_rabc_i[17] = pick_INT_rabc_shiftrot0_17; + assign rdpick_INT_rabc_i[16] = pick_INT_rabc_mul0_16; + assign rdpick_INT_rabc_i[15] = pick_INT_rabc_div0_15; + assign rdpick_INT_rabc_i[14] = pick_INT_rabc_spr0_14; + assign rdpick_INT_rabc_i[13] = pick_INT_rabc_logical0_13; + assign rdpick_INT_rabc_i[12] = pick_INT_rabc_trap0_12; + assign rdpick_INT_rabc_i[11] = pick_INT_rabc_cr0_11; + assign rdpick_INT_rabc_i[10] = pick_INT_rabc_alu0_10; + assign rdpick_INT_rabc_i[9] = pick_INT_rabc_ldst0_9; + assign rdpick_INT_rabc_i[8] = pick_INT_rabc_shiftrot0_8; + assign rdpick_INT_rabc_i[7] = pick_INT_rabc_ldst0_7; + assign rdpick_INT_rabc_i[6] = pick_INT_rabc_shiftrot0_6; + assign rdpick_INT_rabc_i[5] = pick_INT_rabc_mul0_5; + assign rdpick_INT_rabc_i[4] = pick_INT_rabc_div0_4; + assign rdpick_INT_rabc_i[3] = pick_INT_rabc_logical0_3; + assign rdpick_INT_rabc_i[2] = pick_INT_rabc_trap0_2; + assign rdpick_INT_rabc_i[1] = pick_INT_rabc_cr0_1; + assign rdpick_INT_rabc_i[0] = pick_INT_rabc_alu0_0; + assign pick_INT_rabc_alu0_0 = \$358 ; + assign rdflag_INT_rabc_2 = core_reg1_ok; + assign rdflag_INT_rabc_1 = core_reg3_ok; + assign rdflag_INT_rabc_0 = core_reg2_ok; + assign en_ldst0 = \$217 ; + assign en_shiftrot0 = \$213 ; + assign en_mul0 = \$209 ; + assign en_div0 = \$205 ; + assign en_spr0 = \$201 ; + assign en_logical0 = \$197 ; + assign en_trap0 = \$193 ; + assign en_branch0 = \$189 ; + assign en_cr0 = \$185 ; + assign fu_enable[9] = en_ldst0; + assign fu_enable[8] = en_shiftrot0; + assign fu_enable[7] = en_mul0; + assign fu_enable[6] = en_div0; + assign fu_enable[5] = en_spr0; + assign fu_enable[4] = en_logical0; + assign fu_enable[3] = en_trap0; + assign fu_enable[2] = en_branch0; + assign fu_enable[1] = en_cr0; + assign fu_enable[0] = en_alu0; + assign en_alu0 = \$181 ; + assign dec_LDST_sv_a_nz = sv_a_nz; + assign dec_LDST_bigendian = bigendian_i; + assign dec_LDST_raw_opcode_in = raw_insn_i; + assign \sv_a_nz$180 = sv_a_nz; + assign dec_SHIFT_ROT_bigendian = bigendian_i; + assign dec_SHIFT_ROT_raw_opcode_in = raw_insn_i; + assign \sv_a_nz$179 = sv_a_nz; + assign dec_MUL_bigendian = bigendian_i; + assign dec_MUL_raw_opcode_in = raw_insn_i; + assign dec_DIV_sv_a_nz = sv_a_nz; + assign dec_DIV_bigendian = bigendian_i; + assign dec_DIV_raw_opcode_in = raw_insn_i; + assign \sv_a_nz$178 = sv_a_nz; + assign dec_SPR_bigendian = bigendian_i; + assign dec_SPR_raw_opcode_in = raw_insn_i; + assign dec_LOGICAL_sv_a_nz = sv_a_nz; + assign dec_LOGICAL_bigendian = bigendian_i; + assign dec_LOGICAL_raw_opcode_in = raw_insn_i; + assign \sv_a_nz$177 = sv_a_nz; + assign dec_BRANCH_bigendian = bigendian_i; + assign dec_BRANCH_raw_opcode_in = raw_insn_i; + assign \sv_a_nz$176 = sv_a_nz; + assign dec_CR_bigendian = bigendian_i; + assign dec_CR_raw_opcode_in = raw_insn_i; + assign dec_ALU_sv_a_nz = sv_a_nz; + assign dec_ALU_bigendian = bigendian_i; + assign dec_ALU_raw_opcode_in = raw_insn_i; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr" *) +(* generator = "nMigen" *) +module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_rd__ren, src1__data_o, src1__ren, src2__data_o, src2__ren, src3__data_o, src3__ren, full_wr__data_i, full_wr__wen, data_i, wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$26 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$30 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$32 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$37 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$39 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$45 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$47 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$49 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [3:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] \data_i$52 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [31:0] full_rd2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [7:0] full_rd2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [31:0] full_rd__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [7:0] full_rd__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [31:0] full_wr__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [7:0] full_wr__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_0_dest10__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_dest10__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_0_dest20__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_dest20__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_0_r0__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_r0__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_0_r20__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_r20__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_0_src10__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_src10__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_0_src20__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_src20__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_0_src30__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_src30__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_0_w0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_w0__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_1_dest11__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_dest11__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_1_dest21__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_dest21__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_1_r1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_r1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_1_r21__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_r21__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_1_src11__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_src11__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_1_src21__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_src21__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_1_src31__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_src31__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_1_w1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_w1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_2_dest12__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_dest12__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_2_dest22__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_dest22__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_2_r22__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_r22__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_2_r2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_r2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_2_src12__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_src12__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_2_src22__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_src22__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_2_src32__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_src32__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_2_w2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_w2__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_3_dest13__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_3_dest13__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_3_dest23__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_3_dest23__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_3_r23__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_3_r23__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_3_r3__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_3_r3__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_3_src13__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_3_src13__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_3_src23__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_3_src23__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_3_src33__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_3_src33__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_3_w3__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_3_w3__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_4_dest14__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_4_dest14__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_4_dest24__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_4_dest24__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_4_r24__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_4_r24__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_4_r4__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_4_r4__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_4_src14__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_4_src14__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_4_src24__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_4_src24__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_4_src34__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_4_src34__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_4_w4__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_4_w4__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_5_dest15__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_5_dest15__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_5_dest25__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_5_dest25__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_5_r25__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_5_r25__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_5_r5__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_5_r5__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_5_src15__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_5_src15__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_5_src25__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_5_src25__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_5_src35__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_5_src35__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_5_w5__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_5_w5__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_6_dest16__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_6_dest16__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_6_dest26__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_6_dest26__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_6_r26__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_6_r26__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_6_r6__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_6_r6__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_6_src16__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_6_src16__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_6_src26__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_6_src26__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_6_src36__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_6_src36__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_6_w6__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_6_w6__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_7_dest17__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_7_dest17__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_7_dest27__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_7_dest27__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_7_r27__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_7_r27__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_7_r7__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_7_r7__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_7_src17__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_7_src17__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_7_src27__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_7_src27__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_7_src37__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_7_src37__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [3:0] reg_7_w7__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_7_w7__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [7:0] ren_delay = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [7:0] \ren_delay$17 = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [7:0] \ren_delay$17$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [7:0] \ren_delay$34 = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [7:0] \ren_delay$34$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [7:0] \ren_delay$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src1__data_o; + reg [3:0] src1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [7:0] src1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src2__data_o; + reg [3:0] src2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [7:0] src2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src3__data_o; + reg [3:0] src3__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [7:0] src3__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [7:0] wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [7:0] \wen$51 ; + assign \$9 = reg_4_src14__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_5_src15__data_o; + assign \$11 = reg_6_src16__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_7_src17__data_o; + assign \$13 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$11 ; + assign \$15 = \$7 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$13 ; + assign \$18 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$17 ; + assign \$1 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) ren_delay; + assign \$20 = reg_0_src20__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_1_src21__data_o; + assign \$22 = reg_2_src22__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_3_src23__data_o; + assign \$24 = \$20 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$22 ; + assign \$26 = reg_4_src24__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_5_src25__data_o; + assign \$28 = reg_6_src26__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_7_src27__data_o; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$28 ; + assign \$32 = \$24 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$30 ; + assign \$35 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$34 ; + assign \$37 = reg_0_src30__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_1_src31__data_o; + assign \$3 = reg_0_src10__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_1_src11__data_o; + assign \$39 = reg_2_src32__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_3_src33__data_o; + assign \$41 = \$37 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$39 ; + assign \$43 = reg_4_src34__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_5_src35__data_o; + assign \$45 = reg_6_src36__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_7_src37__data_o; + assign \$47 = \$43 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$45 ; + assign \$49 = \$41 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$47 ; + assign \$5 = reg_2_src12__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_3_src13__data_o; + assign \$7 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$5 ; + always @(posedge coresync_clk) + \ren_delay$34 <= \ren_delay$34$next ; + always @(posedge coresync_clk) + \ren_delay$17 <= \ren_delay$17$next ; + always @(posedge coresync_clk) + ren_delay <= \ren_delay$next ; + reg_0 reg_0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest10__data_i(reg_0_dest10__data_i), + .dest10__wen(reg_0_dest10__wen), + .dest20__data_i(reg_0_dest20__data_i), + .dest20__wen(reg_0_dest20__wen), + .r0__data_o(reg_0_r0__data_o), + .r0__ren(reg_0_r0__ren), + .r20__data_o(reg_0_r20__data_o), + .r20__ren(reg_0_r20__ren), + .src10__data_o(reg_0_src10__data_o), + .src10__ren(reg_0_src10__ren), + .src20__data_o(reg_0_src20__data_o), + .src20__ren(reg_0_src20__ren), + .src30__data_o(reg_0_src30__data_o), + .src30__ren(reg_0_src30__ren), + .w0__data_i(reg_0_w0__data_i), + .w0__wen(reg_0_w0__wen) + ); + reg_1 reg_1 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest11__data_i(reg_1_dest11__data_i), + .dest11__wen(reg_1_dest11__wen), + .dest21__data_i(reg_1_dest21__data_i), + .dest21__wen(reg_1_dest21__wen), + .r1__data_o(reg_1_r1__data_o), + .r1__ren(reg_1_r1__ren), + .r21__data_o(reg_1_r21__data_o), + .r21__ren(reg_1_r21__ren), + .src11__data_o(reg_1_src11__data_o), + .src11__ren(reg_1_src11__ren), + .src21__data_o(reg_1_src21__data_o), + .src21__ren(reg_1_src21__ren), + .src31__data_o(reg_1_src31__data_o), + .src31__ren(reg_1_src31__ren), + .w1__data_i(reg_1_w1__data_i), + .w1__wen(reg_1_w1__wen) + ); + reg_2 reg_2 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest12__data_i(reg_2_dest12__data_i), + .dest12__wen(reg_2_dest12__wen), + .dest22__data_i(reg_2_dest22__data_i), + .dest22__wen(reg_2_dest22__wen), + .r22__data_o(reg_2_r22__data_o), + .r22__ren(reg_2_r22__ren), + .r2__data_o(reg_2_r2__data_o), + .r2__ren(reg_2_r2__ren), + .src12__data_o(reg_2_src12__data_o), + .src12__ren(reg_2_src12__ren), + .src22__data_o(reg_2_src22__data_o), + .src22__ren(reg_2_src22__ren), + .src32__data_o(reg_2_src32__data_o), + .src32__ren(reg_2_src32__ren), + .w2__data_i(reg_2_w2__data_i), + .w2__wen(reg_2_w2__wen) + ); + reg_3 reg_3 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest13__data_i(reg_3_dest13__data_i), + .dest13__wen(reg_3_dest13__wen), + .dest23__data_i(reg_3_dest23__data_i), + .dest23__wen(reg_3_dest23__wen), + .r23__data_o(reg_3_r23__data_o), + .r23__ren(reg_3_r23__ren), + .r3__data_o(reg_3_r3__data_o), + .r3__ren(reg_3_r3__ren), + .src13__data_o(reg_3_src13__data_o), + .src13__ren(reg_3_src13__ren), + .src23__data_o(reg_3_src23__data_o), + .src23__ren(reg_3_src23__ren), + .src33__data_o(reg_3_src33__data_o), + .src33__ren(reg_3_src33__ren), + .w3__data_i(reg_3_w3__data_i), + .w3__wen(reg_3_w3__wen) + ); + reg_4 reg_4 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest14__data_i(reg_4_dest14__data_i), + .dest14__wen(reg_4_dest14__wen), + .dest24__data_i(reg_4_dest24__data_i), + .dest24__wen(reg_4_dest24__wen), + .r24__data_o(reg_4_r24__data_o), + .r24__ren(reg_4_r24__ren), + .r4__data_o(reg_4_r4__data_o), + .r4__ren(reg_4_r4__ren), + .src14__data_o(reg_4_src14__data_o), + .src14__ren(reg_4_src14__ren), + .src24__data_o(reg_4_src24__data_o), + .src24__ren(reg_4_src24__ren), + .src34__data_o(reg_4_src34__data_o), + .src34__ren(reg_4_src34__ren), + .w4__data_i(reg_4_w4__data_i), + .w4__wen(reg_4_w4__wen) + ); + reg_5 reg_5 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest15__data_i(reg_5_dest15__data_i), + .dest15__wen(reg_5_dest15__wen), + .dest25__data_i(reg_5_dest25__data_i), + .dest25__wen(reg_5_dest25__wen), + .r25__data_o(reg_5_r25__data_o), + .r25__ren(reg_5_r25__ren), + .r5__data_o(reg_5_r5__data_o), + .r5__ren(reg_5_r5__ren), + .src15__data_o(reg_5_src15__data_o), + .src15__ren(reg_5_src15__ren), + .src25__data_o(reg_5_src25__data_o), + .src25__ren(reg_5_src25__ren), + .src35__data_o(reg_5_src35__data_o), + .src35__ren(reg_5_src35__ren), + .w5__data_i(reg_5_w5__data_i), + .w5__wen(reg_5_w5__wen) + ); + reg_6 reg_6 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest16__data_i(reg_6_dest16__data_i), + .dest16__wen(reg_6_dest16__wen), + .dest26__data_i(reg_6_dest26__data_i), + .dest26__wen(reg_6_dest26__wen), + .r26__data_o(reg_6_r26__data_o), + .r26__ren(reg_6_r26__ren), + .r6__data_o(reg_6_r6__data_o), + .r6__ren(reg_6_r6__ren), + .src16__data_o(reg_6_src16__data_o), + .src16__ren(reg_6_src16__ren), + .src26__data_o(reg_6_src26__data_o), + .src26__ren(reg_6_src26__ren), + .src36__data_o(reg_6_src36__data_o), + .src36__ren(reg_6_src36__ren), + .w6__data_i(reg_6_w6__data_i), + .w6__wen(reg_6_w6__wen) + ); + reg_7 reg_7 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest17__data_i(reg_7_dest17__data_i), + .dest17__wen(reg_7_dest17__wen), + .dest27__data_i(reg_7_dest27__data_i), + .dest27__wen(reg_7_dest27__wen), + .r27__data_o(reg_7_r27__data_o), + .r27__ren(reg_7_r27__ren), + .r7__data_o(reg_7_r7__data_o), + .r7__ren(reg_7_r7__ren), + .src17__data_o(reg_7_src17__data_o), + .src17__ren(reg_7_src17__ren), + .src27__data_o(reg_7_src27__data_o), + .src27__ren(reg_7_src27__ren), + .src37__data_o(reg_7_src37__data_o), + .src37__ren(reg_7_src37__ren), + .w7__data_i(reg_7_w7__data_i), + .w7__wen(reg_7_w7__wen) + ); + always @* begin + if (\initial ) begin end + \ren_delay$17$next = src2__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$17$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + src2__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$18 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + src2__data_o = \$32 ; + endcase + end + always @* begin + if (\initial ) begin end + \ren_delay$34$next = src3__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$34$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + src3__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$35 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + src3__data_o = \$49 ; + endcase + end + always @* begin + if (\initial ) begin end + \ren_delay$next = src1__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + src1__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + src1__data_o = \$15 ; + endcase + end + assign \wen$51 = 8'h00; + assign \data_i$52 = 4'h0; + assign { reg_7_w7__wen, reg_6_w6__wen, reg_5_w5__wen, reg_4_w4__wen, reg_3_w3__wen, reg_2_w2__wen, reg_1_w1__wen, reg_0_w0__wen } = full_wr__wen; + assign { reg_7_w7__data_i, reg_6_w6__data_i, reg_5_w5__data_i, reg_4_w4__data_i, reg_3_w3__data_i, reg_2_w2__data_i, reg_1_w1__data_i, reg_0_w0__data_i } = full_wr__data_i; + assign { reg_7_r27__ren, reg_6_r26__ren, reg_5_r25__ren, reg_4_r24__ren, reg_3_r23__ren, reg_2_r22__ren, reg_1_r21__ren, reg_0_r20__ren } = full_rd2__ren; + assign full_rd2__data_o = { reg_7_r27__data_o, reg_6_r26__data_o, reg_5_r25__data_o, reg_4_r24__data_o, reg_3_r23__data_o, reg_2_r22__data_o, reg_1_r21__data_o, reg_0_r20__data_o }; + assign { reg_7_r7__ren, reg_6_r6__ren, reg_5_r5__ren, reg_4_r4__ren, reg_3_r3__ren, reg_2_r2__ren, reg_1_r1__ren, reg_0_r0__ren } = full_rd__ren; + assign full_rd__data_o = { reg_7_r7__data_o, reg_6_r6__data_o, reg_5_r5__data_o, reg_4_r4__data_o, reg_3_r3__data_o, reg_2_r2__data_o, reg_1_r1__data_o, reg_0_r0__data_o }; + assign reg_7_dest27__data_i = 4'h0; + assign reg_6_dest26__data_i = 4'h0; + assign reg_5_dest25__data_i = 4'h0; + assign reg_4_dest24__data_i = 4'h0; + assign reg_3_dest23__data_i = 4'h0; + assign reg_2_dest22__data_i = 4'h0; + assign reg_1_dest21__data_i = 4'h0; + assign reg_0_dest20__data_i = 4'h0; + assign { reg_7_dest27__wen, reg_6_dest26__wen, reg_5_dest25__wen, reg_4_dest24__wen, reg_3_dest23__wen, reg_2_dest22__wen, reg_1_dest21__wen, reg_0_dest20__wen } = 8'h00; + assign reg_7_dest17__data_i = data_i; + assign reg_6_dest16__data_i = data_i; + assign reg_5_dest15__data_i = data_i; + assign reg_4_dest14__data_i = data_i; + assign reg_3_dest13__data_i = data_i; + assign reg_2_dest12__data_i = data_i; + assign reg_1_dest11__data_i = data_i; + assign reg_0_dest10__data_i = data_i; + assign { reg_7_dest17__wen, reg_6_dest16__wen, reg_5_dest15__wen, reg_4_dest14__wen, reg_3_dest13__wen, reg_2_dest12__wen, reg_1_dest11__wen, reg_0_dest10__wen } = wen; + assign { reg_7_src37__ren, reg_6_src36__ren, reg_5_src35__ren, reg_4_src34__ren, reg_3_src33__ren, reg_2_src32__ren, reg_1_src31__ren, reg_0_src30__ren } = src3__ren; + assign { reg_7_src27__ren, reg_6_src26__ren, reg_5_src25__ren, reg_4_src24__ren, reg_3_src23__ren, reg_2_src22__ren, reg_1_src21__ren, reg_0_src20__ren } = src2__ren; + assign { reg_7_src17__ren, reg_6_src16__ren, reg_5_src15__ren, reg_4_src14__ren, reg_3_src13__ren, reg_2_src12__ren, reg_1_src11__ren, reg_0_src10__ren } = src1__ren; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0" *) +(* generator = "nMigen" *) +module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, src6_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, full_cr_ok, dest2_o, cr_a_ok, dest3_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [2:0] \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [2:0] \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [2:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [2:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [2:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [2:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [5:0] \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [2:0] \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [5:0] \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [2:0] \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [2:0] \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$77 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [5:0] \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [31:0] \$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [3:0] \$83 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [3:0] \$85 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [3:0] \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [5:0] \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [5:0] \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [5:0] \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [5:0] \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] alu_cr0_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] \alu_cr0_cr_a$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] alu_cr0_cr_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] alu_cr0_cr_c; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_cr0_cr_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_cr0_cr_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_cr0_cr_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_cr0_cr_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_cr0_cr_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_cr0_cr_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [31:0] alu_cr0_full_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [31:0] \alu_cr0_full_cr$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_cr0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_cr0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_cr0_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_cr0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_cr0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_cr0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_cr0_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [2:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [5:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [5:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [5:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [2:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [31:0] data_r1__full_cr = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [31:0] \data_r1__full_cr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__full_cr_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__full_cr_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] data_r2__cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] \data_r2__cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r2__cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r2__cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [31:0] dest2_o; + reg [31:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] dest3_o; + reg [3:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output full_cr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_cr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_cr0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_cr0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [2:0] prev_wr_go = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [2:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [2:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] req_l_r_req = 3'h7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] req_l_s_req = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [5:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [2:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [31:0] src3_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [3:0] src4_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [3:0] src5_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [3:0] src6_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [5:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [5:0] src_l_r_src = 6'h3f; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [5:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [5:0] src_l_s_src = 6'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [5:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [31:0] src_r2 = 32'd0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [31:0] \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [3:0] src_r3 = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [3:0] \src_r3$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [3:0] src_r4 = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [3:0] \src_r4$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [3:0] src_r5 = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [3:0] \src_r5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + assign \$5 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ; + assign \$99 = \$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$97 ; + assign \$101 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$103 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$105 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$107 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$101 , \$103 , \$105 }; + assign \$109 = \$107 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$111 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$113 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$115 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$15 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ; + assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$19 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ; + assign \$21 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$27 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ; + assign \$24 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; + assign \$31 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; + assign \$33 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$35 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ; + assign \$3 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_cr0_n_ready_i; + assign \$41 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ; + assign \$43 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$45 = \$43 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$47 = \$41 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ; + assign \$49 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$51 = \$49 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_cr0_n_ready_i; + assign \$53 = \$51 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_cr0_n_valid_o; + assign \$55 = \$53 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$57 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$59 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$61 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$63 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$65 = alu_cr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$67 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$69 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$71 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$73 = full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$75 = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$77 = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0; + assign \$79 = src_l_q_src[1] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src2_i : src_r1; + assign \$81 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$83 = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3; + assign \$85 = src_l_q_src[4] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src5_i : src_r4; + assign \$87 = src_l_q_src[5] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src6_i : src_r5; + assign \$8 = \$6 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$89 = alu_cr0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$91 = alu_cr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$93 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$95 = \$93 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) 6'h3f; + assign \$97 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r5 <= \src_r5$next ; + always @(posedge coresync_clk) + src_r4 <= \src_r4$next ; + always @(posedge coresync_clk) + src_r3 <= \src_r3$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r2__cr_a <= \data_r2__cr_a$next ; + always @(posedge coresync_clk) + data_r2__cr_a_ok <= \data_r2__cr_a_ok$next ; + always @(posedge coresync_clk) + data_r1__full_cr <= \data_r1__full_cr$next ; + always @(posedge coresync_clk) + data_r1__full_cr_ok <= \data_r1__full_cr_ok$next ; + always @(posedge coresync_clk) + data_r0__o <= \data_r0__o$next ; + always @(posedge coresync_clk) + data_r0__o_ok <= \data_r0__o_ok$next ; + always @(posedge coresync_clk) + alu_cr0_cr_op__insn_type <= \alu_cr0_cr_op__insn_type$next ; + always @(posedge coresync_clk) + alu_cr0_cr_op__fn_unit <= \alu_cr0_cr_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_cr0_cr_op__insn <= \alu_cr0_cr_op__insn$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_cr0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$11 ; + alu_cr0 alu_cr0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(alu_cr0_cr_a), + .\cr_a$2 (\alu_cr0_cr_a$2 ), + .cr_a_ok(cr_a_ok), + .cr_b(alu_cr0_cr_b), + .cr_c(alu_cr0_cr_c), + .cr_op__fn_unit(alu_cr0_cr_op__fn_unit), + .cr_op__insn(alu_cr0_cr_op__insn), + .cr_op__insn_type(alu_cr0_cr_op__insn_type), + .full_cr(alu_cr0_full_cr), + .\full_cr$1 (\alu_cr0_full_cr$1 ), + .full_cr_ok(full_cr_ok), + .n_ready_i(alu_cr0_n_ready_i), + .n_valid_o(alu_cr0_n_valid_o), + .o(alu_cr0_o), + .o_ok(o_ok), + .p_ready_o(alu_cr0_p_ready_o), + .p_valid_i(alu_cr0_p_valid_i), + .ra(alu_cr0_ra), + .rb(alu_cr0_rb) + ); + \alu_l$16 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + \alui_l$15 alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + \opc_l$11 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \req_l$12 req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + \rok_l$14 rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + \rst_l$13 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$10 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$55 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$65 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 6'h00; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 6'h3f; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$67 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$69 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \alu_cr0_cr_op__insn_type$next = alu_cr0_cr_op__insn_type; + \alu_cr0_cr_op__fn_unit$next = alu_cr0_cr_op__fn_unit; + \alu_cr0_cr_op__insn$next = alu_cr0_cr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_cr0_cr_op__insn$next , \alu_cr0_cr_op__fn_unit$next , \alu_cr0_cr_op__insn_type$next } = { oper_i_alu_cr0__insn, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn_type }; + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__o$next = data_r0__o; + \data_r0__o_ok$next = data_r0__o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = { o_ok, alu_cr0_o }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__full_cr$next = data_r1__full_cr; + \data_r1__full_cr_ok$next = data_r1__full_cr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__full_cr_ok$next , \data_r1__full_cr$next } = { full_cr_ok, alu_cr0_full_cr }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__full_cr_ok$next , \data_r1__full_cr$next } = 33'h000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__full_cr_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r2__cr_a$next = data_r2__cr_a; + \data_r2__cr_a_ok$next = data_r2__cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r2__cr_a_ok$next , \data_r2__cr_a$next } = { cr_a_ok, alu_cr0_cr_a }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r2__cr_a_ok$next , \data_r2__cr_a$next } = 5'h00; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r2__cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[0]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src1_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[1]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = src2_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r3$next = src_r3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[3]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r3$next = src4_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r4$next = src_r4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[4]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r4$next = src5_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r5$next = src_r5; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[5]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r5$next = src6_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$89 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$91 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$111 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__o; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$113 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__full_cr; + endcase + end + always @* begin + if (\initial ) begin end + dest3_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$115 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest3_o = data_r2__cr_a; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$21 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 3'h0; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$109 ; + assign cu_rd__rel_o = \$99 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_cr0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_cr0_p_valid_i = alui_l_q_alui; + assign alu_cr0_cr_c = \$87 ; + assign alu_cr0_cr_b = \$85 ; + assign \alu_cr0_cr_a$2 = \$83 ; + assign \alu_cr0_full_cr$1 = \$81 ; + assign alu_cr0_rb = \$79 ; + assign alu_cr0_ra = \$77 ; + assign cu_wrmask_o = { \$75 , \$73 , \$71 }; + assign reset_r = \$63 ; + assign reset_w = \$61 ; + assign rst_r = \$59 ; + assign reset = \$57 ; + assign wr_any = \$37 ; + assign cu_done_o = \$31 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$19 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_cr0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$15 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.cyc_l" *) +(* generator = "nMigen" *) +module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_cyc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_cyc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_cyc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_cyc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_cyc; + assign \$9 = q_cyc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_cyc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_cyc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_cyc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_cyc = \$9 ; + assign qn_cyc = \$7 ; + assign q_cyc = q_int; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dbg" *) +(* generator = "nMigen" *) +module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_rst_o, terminate_i, core_dbg_pc, core_dbg_core_dbg_svstep, core_dbg_core_dbg_subvl, core_dbg_core_dbg_dststep, core_dbg_core_dbg_srcstep, core_dbg_core_dbg_vl, core_dbg_core_dbg_maxvl, core_dbg_msr, core_stop_o, core_stopped_i, d_gpr_req, d_gpr_addr, d_gpr_data, d_gpr_ack, d_cr_req, d_cr_data, d_cr_ack, d_xer_req, d_xer_data, d_xer_ack, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" *) + wire [2:0] \$117 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" *) + wire [2:0] \$118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" *) + wire \$120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" *) + wire \$122 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" *) + wire \$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" *) + wire \$126 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) + wire [63:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + input [6:0] core_dbg_core_dbg_dststep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + input [6:0] core_dbg_core_dbg_maxvl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + input [6:0] core_dbg_core_dbg_srcstep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + input [1:0] core_dbg_core_dbg_subvl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + input [1:0] core_dbg_core_dbg_svstep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + input [6:0] core_dbg_core_dbg_vl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + input [63:0] core_dbg_msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + input [63:0] core_dbg_pc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" *) + output core_rst_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" *) + output core_stop_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" *) + input core_stopped_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *) + input d_cr_ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *) + input [63:0] d_cr_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *) + output d_cr_req; + reg d_cr_req; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *) + input d_gpr_ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" *) + output [6:0] d_gpr_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *) + input [63:0] d_gpr_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *) + output d_gpr_req; + reg d_gpr_req; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *) + input d_xer_ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *) + input [63:0] d_xer_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *) + output d_xer_req; + reg d_xer_req; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" *) + output dmi_ack_o; + reg dmi_ack_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" *) + input [3:0] dmi_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" *) + input [63:0] dmi_din; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" *) + output [63:0] dmi_dout; + reg [63:0] dmi_dout; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" *) + reg dmi_read_log_data = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" *) + reg \dmi_read_log_data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" *) + reg dmi_read_log_data_1 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" *) + reg \dmi_read_log_data_1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" *) + input dmi_req_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" *) + reg dmi_req_i_1 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" *) + reg \dmi_req_i_1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" *) + input dmi_we_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" *) + reg do_dmi_log_rd = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" *) + reg \do_dmi_log_rd$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" *) + reg do_icreset = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" *) + reg \do_icreset$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" *) + reg do_reset = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" *) + reg \do_reset$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" *) + reg do_step = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" *) + reg \do_step$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144" *) + reg [6:0] gspr_index = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144" *) + reg [6:0] \gspr_index$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" *) + wire icache_rst_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" *) + reg [31:0] log_dmi_addr = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" *) + reg [31:0] \log_dmi_addr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" *) + wire [63:0] log_dmi_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *) + wire [31:0] log_write_addr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *) + wire [63:0] stat_reg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" *) + reg stopping = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" *) + reg \stopping$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" *) + input terminate_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" *) + reg terminated = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" *) + reg \terminated$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" *) + wire terminated_o; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; + assign \$99 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; + assign \$101 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6; + assign \$103 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; + assign \$105 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$103 ; + assign \$107 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; + assign \$109 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$107 ; + assign \$111 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; + assign \$113 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; + assign \$115 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6; + assign \$118 = log_dmi_addr[1:0] + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" *) 1'h1; + assign \$11 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$9 ; + assign \$120 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" *) 3'h7; + assign \$122 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" *) \$120 ; + assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" *) do_step; + assign \$126 = stopping & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" *) \$124 ; + assign \$13 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; + assign \$15 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; + assign \$17 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" *) { terminated, core_stopped_i, stopping }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; + assign \$21 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$19 ; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; + assign \$25 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$23 ; + assign \$27 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; + assign \$29 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; + assign \$31 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6; + assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; + assign \$35 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$33 ; + assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { core_dbg_core_dbg_maxvl, core_dbg_core_dbg_vl, core_dbg_core_dbg_srcstep, core_dbg_core_dbg_dststep, core_dbg_core_dbg_subvl, core_dbg_core_dbg_svstep }; + assign \$39 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$37 ; + assign \$41 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; + assign \$43 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; + assign \$45 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; + assign \$49 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$47 ; + assign \$51 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; + assign \$53 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$51 ; + assign \$55 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; + assign \$57 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; + assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; + assign \$59 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6; + assign \$61 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; + assign \$63 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$61 ; + assign \$65 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; + assign \$67 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$65 ; + assign \$69 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; + assign \$71 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; + assign \$73 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6; + assign \$75 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; + assign \$77 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$75 ; + assign \$7 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$5 ; + assign \$79 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; + assign \$81 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$79 ; + assign \$83 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; + assign \$85 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; + assign \$87 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6; + assign \$89 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; + assign \$91 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$89 ; + assign \$93 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; + assign \$95 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$93 ; + assign \$97 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; + always @(posedge clk) + dmi_read_log_data <= \dmi_read_log_data$next ; + always @(posedge clk) + dmi_read_log_data_1 <= \dmi_read_log_data_1$next ; + always @(posedge clk) + log_dmi_addr <= \log_dmi_addr$next ; + always @(posedge clk) + gspr_index <= \gspr_index$next ; + always @(posedge clk) + stopping <= \stopping$next ; + always @(posedge clk) + terminated <= \terminated$next ; + always @(posedge clk) + dmi_req_i_1 <= \dmi_req_i_1$next ; + always @(posedge clk) + do_dmi_log_rd <= \do_dmi_log_rd$next ; + always @(posedge clk) + do_icreset <= \do_icreset$next ; + always @(posedge clk) + do_reset <= \do_reset$next ; + always @(posedge clk) + do_step <= \do_step$next ; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *) + casez (dmi_addr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" */ + 4'h5: + dmi_ack_o = d_gpr_ack; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:159" */ + 4'h8: + dmi_ack_o = d_cr_ack; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:162" */ + 4'h9: + dmi_ack_o = d_xer_ack; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" */ + default: + dmi_ack_o = dmi_req_i; + endcase + end + always @* begin + if (\initial ) begin end + d_gpr_req = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *) + casez (dmi_addr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" */ + 4'h5: + d_gpr_req = dmi_req_i; + endcase + end + always @* begin + if (\initial ) begin end + \dmi_req_i_1$next = dmi_req_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi_req_i_1$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \terminated$next = terminated; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + casez ({ \$67 , \$63 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *) + casez (dmi_we_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + casez ({ \$73 , \$71 , \$69 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" */ + 3'b??1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" *) + casez (dmi_din[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" */ + 1'h1: + \terminated$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" *) + casez (dmi_din[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" */ + 1'h1: + \terminated$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" *) + casez (dmi_din[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" */ + 1'h1: + \terminated$next = 1'h0; + endcase + end + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" *) + casez (terminate_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" */ + 1'h1: + \terminated$next = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \terminated$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \stopping$next = stopping; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + casez ({ \$81 , \$77 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *) + casez (dmi_we_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + casez ({ \$87 , \$85 , \$83 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" */ + 3'b??1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" *) + casez (dmi_din[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" */ + 1'h1: + \stopping$next = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" *) + casez (dmi_din[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" */ + 1'h1: + \stopping$next = 1'h0; + endcase + end + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" *) + casez (terminate_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" */ + 1'h1: + \stopping$next = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \stopping$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \gspr_index$next = gspr_index; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + casez ({ \$95 , \$91 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *) + casez (dmi_we_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + casez ({ \$101 , \$99 , \$97 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" */ + 3'b??1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" */ + 3'b?1?: + \gspr_index$next = dmi_din[6:0]; + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \gspr_index$next = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + \log_dmi_addr$next = log_dmi_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + casez ({ \$109 , \$105 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *) + casez (dmi_we_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + casez ({ \$115 , \$113 , \$111 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" */ + 3'b??1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" */ + 3'b?1?: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" */ + 3'b1??: + \log_dmi_addr$next = dmi_din[31:0]; + endcase + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" */ + 2'b1?: + \log_dmi_addr$next [1:0] = \$117 [1:0]; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \log_dmi_addr$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi_read_log_data_1$next = dmi_read_log_data; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi_read_log_data_1$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi_read_log_data$next = \$122 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi_read_log_data$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + d_cr_req = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *) + casez (dmi_addr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" */ + 4'h5: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:159" */ + 4'h8: + d_cr_req = dmi_req_i; + endcase + end + always @* begin + if (\initial ) begin end + d_xer_req = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *) + casez (dmi_addr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" */ + 4'h5: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:159" */ + 4'h8: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:162" */ + 4'h9: + d_xer_req = dmi_req_i; + endcase + end + always @* begin + if (\initial ) begin end + dmi_dout = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:174" *) + casez (dmi_addr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175" */ + 4'h1: + dmi_dout = stat_reg; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" */ + 4'h2: + dmi_dout = core_dbg_pc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:179" */ + 4'h3: + dmi_dout = core_dbg_msr; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:181" */ + 4'ha: + dmi_dout = \$3 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:183" */ + 4'h5: + dmi_dout = d_gpr_data; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:185" */ + 4'h6: + dmi_dout = { log_write_addr_o, log_dmi_addr }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" */ + 4'h7: + dmi_dout = log_dmi_data; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:189" */ + 4'h8: + dmi_dout = d_cr_data; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" */ + 4'h9: + dmi_dout = d_xer_data; + endcase + end + always @* begin + if (\initial ) begin end + \do_step$next = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + casez ({ \$11 , \$7 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *) + casez (dmi_we_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + casez ({ \$17 , \$15 , \$13 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" */ + 3'b??1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" *) + casez (dmi_din[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" */ + 1'h1: + \do_step$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \do_step$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \do_reset$next = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + casez ({ \$25 , \$21 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *) + casez (dmi_we_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + casez ({ \$31 , \$29 , \$27 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" */ + 3'b??1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" *) + casez (dmi_din[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" */ + 1'h1: + \do_reset$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \do_reset$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \do_icreset$next = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + casez ({ \$39 , \$35 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *) + casez (dmi_we_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + casez ({ \$45 , \$43 , \$41 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" */ + 3'b??1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" *) + casez (dmi_din[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" */ + 1'h1: + \do_icreset$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \do_icreset$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \do_dmi_log_rd$next = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) + casez ({ \$53 , \$49 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *) + casez (dmi_we_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) + casez ({ \$59 , \$57 , \$55 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" */ + 3'b??1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" */ + 3'b?1?: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" */ + 3'b1??: + \do_dmi_log_rd$next = 1'h1; + endcase + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" */ + 2'b1?: + \do_dmi_log_rd$next = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \do_dmi_log_rd$next = 1'h0; + endcase + end + assign \$117 = \$118 ; + assign log_write_addr_o = 32'd0; + assign log_dmi_data = 64'h0000000000000000; + assign terminated_o = terminated; + assign icache_rst_o = do_icreset; + assign core_rst_o = do_reset; + assign core_stop_o = \$126 ; + assign d_gpr_addr = gspr_index; + assign stat_reg = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec" *) +(* generator = "nMigen" *) +module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_function_unit, ALU_in1_sel, ALU_in2_sel, ALU_cr_out, ALU_ldst_len, ALU_inv_a, ALU_inv_out, ALU_cry_in, ALU_cry_out, ALU_is_32b, ALU_sgn, ALU_RA, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_Rc, ALU_OE, ALU_BD, ALU_DS, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire ALU_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] ALU_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] ALU_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] ALU_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] ALU_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] ALU_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] ALU_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] ALU_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire ALU_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [23:0] ALU_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire ALU_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output ALU_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] ALU_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] ALU_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output ALU_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] ALU_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] ALU_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] ALU_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ALU_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] ALU_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] ALU_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_cr_out; + reg [2:0] ALU_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_cry_in; + reg [1:0] ALU_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_cry_out; + reg ALU_cry_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec19_ALU_dec19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec19_ALU_dec19_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec19_ALU_dec19_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec19_ALU_dec19_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] ALU_dec19_ALU_dec19_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec19_ALU_dec19_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec19_ALU_dec19_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] ALU_dec19_ALU_dec19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec19_ALU_dec19_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec19_ALU_dec19_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec19_ALU_dec19_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec19_ALU_dec19_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec19_ALU_dec19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec19_ALU_dec19_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] ALU_dec19_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_ALU_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_ALU_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_ALU_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_ALU_dec31_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] ALU_dec31_ALU_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] ALU_dec31_ALU_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_ALU_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] ALU_dec31_ALU_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_ALU_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_ALU_dec31_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_ALU_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] ALU_dec31_ALU_dec31_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_ALU_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire ALU_dec31_ALU_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] ALU_dec31_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] ALU_function_unit; + reg [13:0] ALU_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] ALU_in1_sel; + reg [2:0] ALU_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_in2_sel; + reg [3:0] ALU_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] ALU_internal_op; + reg [6:0] ALU_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_inv_a; + reg ALU_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_inv_out; + reg ALU_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_is_32b; + reg ALU_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] ALU_ldst_len; + reg [3:0] ALU_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] ALU_rc_sel; + reg [1:0] ALU_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output ALU_sgn; + reg ALU_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [5:0] ALU_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + ALU_dec19 ALU_dec19 ( + .ALU_dec19_cr_in(ALU_dec19_ALU_dec19_cr_in), + .ALU_dec19_cr_out(ALU_dec19_ALU_dec19_cr_out), + .ALU_dec19_cry_in(ALU_dec19_ALU_dec19_cry_in), + .ALU_dec19_cry_out(ALU_dec19_ALU_dec19_cry_out), + .ALU_dec19_function_unit(ALU_dec19_ALU_dec19_function_unit), + .ALU_dec19_in1_sel(ALU_dec19_ALU_dec19_in1_sel), + .ALU_dec19_in2_sel(ALU_dec19_ALU_dec19_in2_sel), + .ALU_dec19_internal_op(ALU_dec19_ALU_dec19_internal_op), + .ALU_dec19_inv_a(ALU_dec19_ALU_dec19_inv_a), + .ALU_dec19_inv_out(ALU_dec19_ALU_dec19_inv_out), + .ALU_dec19_is_32b(ALU_dec19_ALU_dec19_is_32b), + .ALU_dec19_ldst_len(ALU_dec19_ALU_dec19_ldst_len), + .ALU_dec19_rc_sel(ALU_dec19_ALU_dec19_rc_sel), + .ALU_dec19_sgn(ALU_dec19_ALU_dec19_sgn), + .opcode_in(ALU_dec19_opcode_in) + ); + ALU_dec31 ALU_dec31 ( + .ALU_dec31_cr_in(ALU_dec31_ALU_dec31_cr_in), + .ALU_dec31_cr_out(ALU_dec31_ALU_dec31_cr_out), + .ALU_dec31_cry_in(ALU_dec31_ALU_dec31_cry_in), + .ALU_dec31_cry_out(ALU_dec31_ALU_dec31_cry_out), + .ALU_dec31_function_unit(ALU_dec31_ALU_dec31_function_unit), + .ALU_dec31_in1_sel(ALU_dec31_ALU_dec31_in1_sel), + .ALU_dec31_in2_sel(ALU_dec31_ALU_dec31_in2_sel), + .ALU_dec31_internal_op(ALU_dec31_ALU_dec31_internal_op), + .ALU_dec31_inv_a(ALU_dec31_ALU_dec31_inv_a), + .ALU_dec31_inv_out(ALU_dec31_ALU_dec31_inv_out), + .ALU_dec31_is_32b(ALU_dec31_ALU_dec31_is_32b), + .ALU_dec31_ldst_len(ALU_dec31_ALU_dec31_ldst_len), + .ALU_dec31_rc_sel(ALU_dec31_ALU_dec31_rc_sel), + .ALU_dec31_sgn(ALU_dec31_ALU_dec31_sgn), + .opcode_in(ALU_dec31_opcode_in) + ); + always @* begin + if (\initial ) begin end + ALU_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_rc_sel = ALU_dec19_ALU_dec19_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_rc_sel = ALU_dec31_ALU_dec31_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_cry_in = ALU_dec19_ALU_dec19_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_cry_in = ALU_dec31_ALU_dec31_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_cry_in = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_inv_a = ALU_dec19_ALU_dec19_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_inv_a = ALU_dec31_ALU_dec31_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_inv_a = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_inv_out = ALU_dec19_ALU_dec19_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_inv_out = ALU_dec31_ALU_dec31_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_cry_out = ALU_dec19_ALU_dec19_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_cry_out = ALU_dec31_ALU_dec31_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_cry_out = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_is_32b = ALU_dec19_ALU_dec19_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_is_32b = ALU_dec31_ALU_dec31_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_sgn = ALU_dec19_ALU_dec19_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_sgn = ALU_dec31_ALU_dec31_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_function_unit = ALU_dec19_ALU_dec19_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_function_unit = ALU_dec31_ALU_dec31_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_internal_op = ALU_dec19_ALU_dec19_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_internal_op = ALU_dec31_ALU_dec31_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_internal_op = 7'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_internal_op = 7'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_internal_op = 7'h02; + endcase + end + always @* begin + if (\initial ) begin end + ALU_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_in1_sel = ALU_dec19_ALU_dec19_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_in1_sel = ALU_dec31_ALU_dec31_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_in2_sel = ALU_dec19_ALU_dec19_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_in2_sel = ALU_dec31_ALU_dec31_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_in2_sel = 4'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_in2_sel = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_in2_sel = 4'h3; + endcase + end + always @* begin + if (\initial ) begin end + ALU_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_cr_in = ALU_dec19_ALU_dec19_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_cr_in = ALU_dec31_ALU_dec31_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_cr_out = ALU_dec19_ALU_dec19_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_cr_out = ALU_dec31_ALU_dec31_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ALU_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ALU_ldst_len = ALU_dec19_ALU_dec19_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ALU_ldst_len = ALU_dec31_ALU_dec31_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ALU_ldst_len = 4'h0; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign ALU_SPR = opcode_in[20:11]; + assign ALU_MB = opcode_in[10:6]; + assign ALU_ME = opcode_in[5:1]; + assign ALU_SH = opcode_in[15:11]; + assign ALU_BC = opcode_in[10:6]; + assign ALU_TO = opcode_in[25:21]; + assign ALU_DS = opcode_in[15:2]; + assign ALU_D = opcode_in[15:0]; + assign ALU_BH = opcode_in[12:11]; + assign ALU_BI = opcode_in[20:16]; + assign ALU_BO = opcode_in[25:21]; + assign ALU_FXM = opcode_in[19:12]; + assign ALU_BT = opcode_in[25:21]; + assign ALU_BA = opcode_in[20:16]; + assign ALU_BB = opcode_in[15:11]; + assign ALU_CR = opcode_in[10:1]; + assign ALU_BF = opcode_in[25:23]; + assign ALU_BD = opcode_in[15:2]; + assign ALU_OE = opcode_in[10]; + assign ALU_Rc = opcode_in[0]; + assign ALU_AA = opcode_in[1]; + assign ALU_LK = opcode_in[0]; + assign ALU_LI = opcode_in[25:2]; + assign ALU_ME32 = opcode_in[5:1]; + assign ALU_MB32 = opcode_in[10:6]; + assign ALU_sh = { opcode_in[1], opcode_in[15:11] }; + assign ALU_SH32 = opcode_in[15:11]; + assign ALU_L = opcode_in[21]; + assign ALU_UI = opcode_in[15:0]; + assign ALU_SI = opcode_in[15:0]; + assign ALU_RB = opcode_in[15:11]; + assign ALU_RA = opcode_in[20:16]; + assign ALU_RT = opcode_in[25:21]; + assign ALU_RS = opcode_in[25:21]; + assign ALU_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign ALU_dec31_opcode_in = opcode_in; + assign ALU_dec19_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec" *) +(* generator = "nMigen" *) +module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_function_unit, CR_cr_out, CR_Rc, CR_OE, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire CR_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] CR_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] CR_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] CR_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] CR_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] CR_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] CR_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] CR_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire CR_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] CR_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire CR_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output CR_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] CR_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output CR_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] CR_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] CR_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] CR_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] CR_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] CR_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] CR_cr_out; + reg [2:0] CR_cr_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec19_CR_dec19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec19_CR_dec19_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] CR_dec19_CR_dec19_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] CR_dec19_CR_dec19_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec19_CR_dec19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] CR_dec19_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_CR_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] CR_dec31_CR_dec31_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] CR_dec31_CR_dec31_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] CR_dec31_CR_dec31_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_CR_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] CR_dec31_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] CR_function_unit; + reg [13:0] CR_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] CR_internal_op; + reg [6:0] CR_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] CR_rc_sel; + reg [1:0] CR_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] CR_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + CR_dec19 CR_dec19 ( + .CR_dec19_cr_in(CR_dec19_CR_dec19_cr_in), + .CR_dec19_cr_out(CR_dec19_CR_dec19_cr_out), + .CR_dec19_function_unit(CR_dec19_CR_dec19_function_unit), + .CR_dec19_internal_op(CR_dec19_CR_dec19_internal_op), + .CR_dec19_rc_sel(CR_dec19_CR_dec19_rc_sel), + .opcode_in(CR_dec19_opcode_in) + ); + CR_dec31 CR_dec31 ( + .CR_dec31_cr_in(CR_dec31_CR_dec31_cr_in), + .CR_dec31_cr_out(CR_dec31_CR_dec31_cr_out), + .CR_dec31_function_unit(CR_dec31_CR_dec31_function_unit), + .CR_dec31_internal_op(CR_dec31_CR_dec31_internal_op), + .CR_dec31_rc_sel(CR_dec31_CR_dec31_rc_sel), + .opcode_in(CR_dec31_opcode_in) + ); + always @* begin + if (\initial ) begin end + CR_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + CR_function_unit = CR_dec19_CR_dec19_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + CR_function_unit = CR_dec31_CR_dec31_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + CR_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + CR_internal_op = CR_dec19_CR_dec19_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + CR_internal_op = CR_dec31_CR_dec31_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + CR_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + CR_cr_in = CR_dec19_CR_dec19_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + CR_cr_in = CR_dec31_CR_dec31_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + CR_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + CR_cr_out = CR_dec19_CR_dec19_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + CR_cr_out = CR_dec31_CR_dec31_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + CR_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + CR_rc_sel = CR_dec19_CR_dec19_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + CR_rc_sel = CR_dec31_CR_dec31_rc_sel; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign CR_SPR = opcode_in[20:11]; + assign CR_MB = opcode_in[10:6]; + assign CR_ME = opcode_in[5:1]; + assign CR_SH = opcode_in[15:11]; + assign CR_BC = opcode_in[10:6]; + assign CR_TO = opcode_in[25:21]; + assign CR_DS = opcode_in[15:2]; + assign CR_D = opcode_in[15:0]; + assign CR_BH = opcode_in[12:11]; + assign CR_BI = opcode_in[20:16]; + assign CR_BO = opcode_in[25:21]; + assign CR_FXM = opcode_in[19:12]; + assign CR_BT = opcode_in[25:21]; + assign CR_BA = opcode_in[20:16]; + assign CR_BB = opcode_in[15:11]; + assign CR_CR = opcode_in[10:1]; + assign CR_BF = opcode_in[25:23]; + assign CR_BD = opcode_in[15:2]; + assign CR_OE = opcode_in[10]; + assign CR_Rc = opcode_in[0]; + assign CR_AA = opcode_in[1]; + assign CR_LK = opcode_in[0]; + assign CR_LI = opcode_in[25:2]; + assign CR_ME32 = opcode_in[5:1]; + assign CR_MB32 = opcode_in[10:6]; + assign CR_sh = { opcode_in[1], opcode_in[15:11] }; + assign CR_SH32 = opcode_in[15:11]; + assign CR_L = opcode_in[21]; + assign CR_UI = opcode_in[15:0]; + assign CR_SI = opcode_in[15:0]; + assign CR_RB = opcode_in[15:11]; + assign CR_RA = opcode_in[20:16]; + assign CR_RT = opcode_in[25:21]; + assign CR_RS = opcode_in[25:21]; + assign CR_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign CR_dec31_opcode_in = opcode_in; + assign CR_dec19_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_BRANCH.dec" *) +(* generator = "nMigen" *) +module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH_SPR, BRANCH_function_unit, BRANCH_in2_sel, BRANCH_cr_out, BRANCH_is_32b, BRANCH_lk, BRANCH_LK, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_sh, BRANCH_LI, BRANCH_Rc, BRANCH_OE, BRANCH_BD, BRANCH_DS, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire BRANCH_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] BRANCH_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] BRANCH_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] BRANCH_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] BRANCH_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] BRANCH_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] BRANCH_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] BRANCH_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire BRANCH_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [23:0] BRANCH_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output BRANCH_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output BRANCH_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] BRANCH_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output BRANCH_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] BRANCH_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] BRANCH_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] BRANCH_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] BRANCH_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] BRANCH_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] BRANCH_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] BRANCH_cr_out; + reg [2:0] BRANCH_cr_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] BRANCH_dec19_BRANCH_dec19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] BRANCH_dec19_BRANCH_dec19_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] BRANCH_dec19_BRANCH_dec19_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] BRANCH_dec19_BRANCH_dec19_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] BRANCH_dec19_BRANCH_dec19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire BRANCH_dec19_BRANCH_dec19_is_32b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire BRANCH_dec19_BRANCH_dec19_lk; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] BRANCH_dec19_BRANCH_dec19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] BRANCH_dec19_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] BRANCH_function_unit; + reg [13:0] BRANCH_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] BRANCH_in2_sel; + reg [3:0] BRANCH_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] BRANCH_internal_op; + reg [6:0] BRANCH_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output BRANCH_is_32b; + reg BRANCH_is_32b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output BRANCH_lk; + reg BRANCH_lk; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] BRANCH_rc_sel; + reg [1:0] BRANCH_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [5:0] BRANCH_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + BRANCH_dec19 BRANCH_dec19 ( + .BRANCH_dec19_cr_in(BRANCH_dec19_BRANCH_dec19_cr_in), + .BRANCH_dec19_cr_out(BRANCH_dec19_BRANCH_dec19_cr_out), + .BRANCH_dec19_function_unit(BRANCH_dec19_BRANCH_dec19_function_unit), + .BRANCH_dec19_in2_sel(BRANCH_dec19_BRANCH_dec19_in2_sel), + .BRANCH_dec19_internal_op(BRANCH_dec19_BRANCH_dec19_internal_op), + .BRANCH_dec19_is_32b(BRANCH_dec19_BRANCH_dec19_is_32b), + .BRANCH_dec19_lk(BRANCH_dec19_BRANCH_dec19_lk), + .BRANCH_dec19_rc_sel(BRANCH_dec19_BRANCH_dec19_rc_sel), + .opcode_in(BRANCH_dec19_opcode_in) + ); + always @* begin + if (\initial ) begin end + BRANCH_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + BRANCH_function_unit = BRANCH_dec19_BRANCH_dec19_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + BRANCH_function_unit = 14'h0020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + BRANCH_function_unit = 14'h0020; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + BRANCH_internal_op = BRANCH_dec19_BRANCH_dec19_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + BRANCH_internal_op = 7'h06; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + BRANCH_internal_op = 7'h07; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + BRANCH_in2_sel = BRANCH_dec19_BRANCH_dec19_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + BRANCH_in2_sel = 4'h6; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + BRANCH_in2_sel = 4'h7; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + BRANCH_cr_in = BRANCH_dec19_BRANCH_dec19_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + BRANCH_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + BRANCH_cr_in = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + BRANCH_cr_out = BRANCH_dec19_BRANCH_dec19_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + BRANCH_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + BRANCH_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + BRANCH_rc_sel = BRANCH_dec19_BRANCH_dec19_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + BRANCH_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + BRANCH_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + BRANCH_is_32b = BRANCH_dec19_BRANCH_dec19_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + BRANCH_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + BRANCH_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + BRANCH_lk = BRANCH_dec19_BRANCH_dec19_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + BRANCH_lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + BRANCH_lk = 1'h1; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign BRANCH_SPR = opcode_in[20:11]; + assign BRANCH_MB = opcode_in[10:6]; + assign BRANCH_ME = opcode_in[5:1]; + assign BRANCH_SH = opcode_in[15:11]; + assign BRANCH_BC = opcode_in[10:6]; + assign BRANCH_TO = opcode_in[25:21]; + assign BRANCH_DS = opcode_in[15:2]; + assign BRANCH_D = opcode_in[15:0]; + assign BRANCH_BH = opcode_in[12:11]; + assign BRANCH_BI = opcode_in[20:16]; + assign BRANCH_BO = opcode_in[25:21]; + assign BRANCH_FXM = opcode_in[19:12]; + assign BRANCH_BT = opcode_in[25:21]; + assign BRANCH_BA = opcode_in[20:16]; + assign BRANCH_BB = opcode_in[15:11]; + assign BRANCH_CR = opcode_in[10:1]; + assign BRANCH_BF = opcode_in[25:23]; + assign BRANCH_BD = opcode_in[15:2]; + assign BRANCH_OE = opcode_in[10]; + assign BRANCH_Rc = opcode_in[0]; + assign BRANCH_AA = opcode_in[1]; + assign BRANCH_LK = opcode_in[0]; + assign BRANCH_LI = opcode_in[25:2]; + assign BRANCH_ME32 = opcode_in[5:1]; + assign BRANCH_MB32 = opcode_in[10:6]; + assign BRANCH_sh = { opcode_in[1], opcode_in[15:11] }; + assign BRANCH_SH32 = opcode_in[15:11]; + assign BRANCH_L = opcode_in[21]; + assign BRANCH_UI = opcode_in[15:0]; + assign BRANCH_SI = opcode_in[15:0]; + assign BRANCH_RB = opcode_in[15:11]; + assign BRANCH_RA = opcode_in[20:16]; + assign BRANCH_RT = opcode_in[25:21]; + assign BRANCH_RS = opcode_in[25:21]; + assign BRANCH_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign BRANCH_dec19_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec" *) +(* generator = "nMigen" *) +module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGICAL_SPR, LOGICAL_function_unit, LOGICAL_in1_sel, LOGICAL_in2_sel, LOGICAL_cr_out, LOGICAL_ldst_len, LOGICAL_inv_a, LOGICAL_inv_out, LOGICAL_cry_in, LOGICAL_cry_out, LOGICAL_is_32b, LOGICAL_sgn, LOGICAL_RA, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGICAL_sh, LOGICAL_LI, LOGICAL_Rc, LOGICAL_OE, LOGICAL_BD, LOGICAL_DS, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire LOGICAL_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] LOGICAL_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] LOGICAL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] LOGICAL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] LOGICAL_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] LOGICAL_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] LOGICAL_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] LOGICAL_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire LOGICAL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [23:0] LOGICAL_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire LOGICAL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output LOGICAL_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] LOGICAL_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] LOGICAL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output LOGICAL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] LOGICAL_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] LOGICAL_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] LOGICAL_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LOGICAL_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] LOGICAL_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] LOGICAL_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_cr_out; + reg [2:0] LOGICAL_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_cry_in; + reg [1:0] LOGICAL_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_cry_out; + reg LOGICAL_cry_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_LOGICAL_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_LOGICAL_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_LOGICAL_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_LOGICAL_dec31_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LOGICAL_dec31_LOGICAL_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LOGICAL_dec31_LOGICAL_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LOGICAL_dec31_LOGICAL_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LOGICAL_dec31_LOGICAL_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_LOGICAL_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_LOGICAL_dec31_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_LOGICAL_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LOGICAL_dec31_LOGICAL_dec31_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_LOGICAL_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LOGICAL_dec31_LOGICAL_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LOGICAL_dec31_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LOGICAL_function_unit; + reg [13:0] LOGICAL_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LOGICAL_in1_sel; + reg [2:0] LOGICAL_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LOGICAL_in2_sel; + reg [3:0] LOGICAL_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LOGICAL_internal_op; + reg [6:0] LOGICAL_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_inv_a; + reg LOGICAL_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_inv_out; + reg LOGICAL_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_is_32b; + reg LOGICAL_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LOGICAL_ldst_len; + reg [3:0] LOGICAL_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_rc_sel; + reg [1:0] LOGICAL_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LOGICAL_sgn; + reg LOGICAL_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [5:0] LOGICAL_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + LOGICAL_dec31 LOGICAL_dec31 ( + .LOGICAL_dec31_cr_in(LOGICAL_dec31_LOGICAL_dec31_cr_in), + .LOGICAL_dec31_cr_out(LOGICAL_dec31_LOGICAL_dec31_cr_out), + .LOGICAL_dec31_cry_in(LOGICAL_dec31_LOGICAL_dec31_cry_in), + .LOGICAL_dec31_cry_out(LOGICAL_dec31_LOGICAL_dec31_cry_out), + .LOGICAL_dec31_function_unit(LOGICAL_dec31_LOGICAL_dec31_function_unit), + .LOGICAL_dec31_in1_sel(LOGICAL_dec31_LOGICAL_dec31_in1_sel), + .LOGICAL_dec31_in2_sel(LOGICAL_dec31_LOGICAL_dec31_in2_sel), + .LOGICAL_dec31_internal_op(LOGICAL_dec31_LOGICAL_dec31_internal_op), + .LOGICAL_dec31_inv_a(LOGICAL_dec31_LOGICAL_dec31_inv_a), + .LOGICAL_dec31_inv_out(LOGICAL_dec31_LOGICAL_dec31_inv_out), + .LOGICAL_dec31_is_32b(LOGICAL_dec31_LOGICAL_dec31_is_32b), + .LOGICAL_dec31_ldst_len(LOGICAL_dec31_LOGICAL_dec31_ldst_len), + .LOGICAL_dec31_rc_sel(LOGICAL_dec31_LOGICAL_dec31_rc_sel), + .LOGICAL_dec31_sgn(LOGICAL_dec31_LOGICAL_dec31_sgn), + .opcode_in(LOGICAL_dec31_opcode_in) + ); + always @* begin + if (\initial ) begin end + LOGICAL_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_cry_in = LOGICAL_dec31_LOGICAL_dec31_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_inv_a = LOGICAL_dec31_LOGICAL_dec31_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_inv_out = LOGICAL_dec31_LOGICAL_dec31_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_cry_out = LOGICAL_dec31_LOGICAL_dec31_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_is_32b = LOGICAL_dec31_LOGICAL_dec31_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_sgn = LOGICAL_dec31_LOGICAL_dec31_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_function_unit = LOGICAL_dec31_LOGICAL_dec31_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_function_unit = 14'h0010; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_internal_op = LOGICAL_dec31_LOGICAL_dec31_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_internal_op = 7'h43; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_internal_op = 7'h43; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_in1_sel = LOGICAL_dec31_LOGICAL_dec31_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_in1_sel = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_in2_sel = LOGICAL_dec31_LOGICAL_dec31_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_in2_sel = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_in2_sel = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_in2_sel = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_in2_sel = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_in2_sel = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_in2_sel = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_cr_in = LOGICAL_dec31_LOGICAL_dec31_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_cr_out = LOGICAL_dec31_LOGICAL_dec31_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_ldst_len = LOGICAL_dec31_LOGICAL_dec31_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LOGICAL_rc_sel = LOGICAL_dec31_LOGICAL_dec31_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + LOGICAL_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + LOGICAL_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + LOGICAL_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + LOGICAL_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + LOGICAL_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + LOGICAL_rc_sel = 2'h0; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign LOGICAL_SPR = opcode_in[20:11]; + assign LOGICAL_MB = opcode_in[10:6]; + assign LOGICAL_ME = opcode_in[5:1]; + assign LOGICAL_SH = opcode_in[15:11]; + assign LOGICAL_BC = opcode_in[10:6]; + assign LOGICAL_TO = opcode_in[25:21]; + assign LOGICAL_DS = opcode_in[15:2]; + assign LOGICAL_D = opcode_in[15:0]; + assign LOGICAL_BH = opcode_in[12:11]; + assign LOGICAL_BI = opcode_in[20:16]; + assign LOGICAL_BO = opcode_in[25:21]; + assign LOGICAL_FXM = opcode_in[19:12]; + assign LOGICAL_BT = opcode_in[25:21]; + assign LOGICAL_BA = opcode_in[20:16]; + assign LOGICAL_BB = opcode_in[15:11]; + assign LOGICAL_CR = opcode_in[10:1]; + assign LOGICAL_BF = opcode_in[25:23]; + assign LOGICAL_BD = opcode_in[15:2]; + assign LOGICAL_OE = opcode_in[10]; + assign LOGICAL_Rc = opcode_in[0]; + assign LOGICAL_AA = opcode_in[1]; + assign LOGICAL_LK = opcode_in[0]; + assign LOGICAL_LI = opcode_in[25:2]; + assign LOGICAL_ME32 = opcode_in[5:1]; + assign LOGICAL_MB32 = opcode_in[10:6]; + assign LOGICAL_sh = { opcode_in[1], opcode_in[15:11] }; + assign LOGICAL_SH32 = opcode_in[15:11]; + assign LOGICAL_L = opcode_in[21]; + assign LOGICAL_UI = opcode_in[15:0]; + assign LOGICAL_SI = opcode_in[15:0]; + assign LOGICAL_RB = opcode_in[15:11]; + assign LOGICAL_RA = opcode_in[20:16]; + assign LOGICAL_RT = opcode_in[25:21]; + assign LOGICAL_RS = opcode_in[25:21]; + assign LOGICAL_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign LOGICAL_dec31_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SPR.dec" *) +(* generator = "nMigen" *) +module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR_function_unit, SPR_cr_out, SPR_is_32b, SPR_Rc, SPR_OE, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire SPR_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] SPR_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] SPR_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] SPR_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] SPR_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] SPR_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] SPR_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] SPR_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire SPR_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] SPR_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire SPR_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output SPR_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] SPR_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output SPR_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] SPR_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] SPR_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SPR_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] SPR_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] SPR_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SPR_cr_out; + reg [2:0] SPR_cr_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SPR_dec31_SPR_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SPR_dec31_SPR_dec31_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] SPR_dec31_SPR_dec31_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] SPR_dec31_SPR_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SPR_dec31_SPR_dec31_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SPR_dec31_SPR_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] SPR_dec31_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SPR_function_unit; + reg [13:0] SPR_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SPR_internal_op; + reg [6:0] SPR_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SPR_is_32b; + reg SPR_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SPR_rc_sel; + reg [1:0] SPR_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] SPR_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + SPR_dec31 SPR_dec31 ( + .SPR_dec31_cr_in(SPR_dec31_SPR_dec31_cr_in), + .SPR_dec31_cr_out(SPR_dec31_SPR_dec31_cr_out), + .SPR_dec31_function_unit(SPR_dec31_SPR_dec31_function_unit), + .SPR_dec31_internal_op(SPR_dec31_SPR_dec31_internal_op), + .SPR_dec31_is_32b(SPR_dec31_SPR_dec31_is_32b), + .SPR_dec31_rc_sel(SPR_dec31_SPR_dec31_rc_sel), + .opcode_in(SPR_dec31_opcode_in) + ); + always @* begin + if (\initial ) begin end + SPR_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SPR_function_unit = SPR_dec31_SPR_dec31_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + SPR_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SPR_internal_op = SPR_dec31_SPR_dec31_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + SPR_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SPR_cr_in = SPR_dec31_SPR_dec31_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + SPR_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SPR_cr_out = SPR_dec31_SPR_dec31_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + SPR_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SPR_rc_sel = SPR_dec31_SPR_dec31_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + SPR_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SPR_is_32b = SPR_dec31_SPR_dec31_is_32b; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign SPR_SPR = opcode_in[20:11]; + assign SPR_MB = opcode_in[10:6]; + assign SPR_ME = opcode_in[5:1]; + assign SPR_SH = opcode_in[15:11]; + assign SPR_BC = opcode_in[10:6]; + assign SPR_TO = opcode_in[25:21]; + assign SPR_DS = opcode_in[15:2]; + assign SPR_D = opcode_in[15:0]; + assign SPR_BH = opcode_in[12:11]; + assign SPR_BI = opcode_in[20:16]; + assign SPR_BO = opcode_in[25:21]; + assign SPR_FXM = opcode_in[19:12]; + assign SPR_BT = opcode_in[25:21]; + assign SPR_BA = opcode_in[20:16]; + assign SPR_BB = opcode_in[15:11]; + assign SPR_CR = opcode_in[10:1]; + assign SPR_BF = opcode_in[25:23]; + assign SPR_BD = opcode_in[15:2]; + assign SPR_OE = opcode_in[10]; + assign SPR_Rc = opcode_in[0]; + assign SPR_AA = opcode_in[1]; + assign SPR_LK = opcode_in[0]; + assign SPR_LI = opcode_in[25:2]; + assign SPR_ME32 = opcode_in[5:1]; + assign SPR_MB32 = opcode_in[10:6]; + assign SPR_sh = { opcode_in[1], opcode_in[15:11] }; + assign SPR_SH32 = opcode_in[15:11]; + assign SPR_L = opcode_in[21]; + assign SPR_UI = opcode_in[15:0]; + assign SPR_SI = opcode_in[15:0]; + assign SPR_RB = opcode_in[15:11]; + assign SPR_RA = opcode_in[20:16]; + assign SPR_RT = opcode_in[25:21]; + assign SPR_RS = opcode_in[25:21]; + assign SPR_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign SPR_dec31_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec" *) +(* generator = "nMigen" *) +module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV_function_unit, DIV_in1_sel, DIV_in2_sel, DIV_cr_out, DIV_ldst_len, DIV_inv_a, DIV_inv_out, DIV_cry_in, DIV_cry_out, DIV_is_32b, DIV_sgn, DIV_RA, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, DIV_Rc, DIV_OE, DIV_BD, DIV_DS, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire DIV_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] DIV_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] DIV_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] DIV_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] DIV_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] DIV_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] DIV_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] DIV_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire DIV_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [23:0] DIV_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire DIV_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output DIV_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] DIV_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] DIV_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output DIV_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] DIV_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] DIV_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] DIV_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] DIV_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] DIV_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] DIV_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_cr_out; + reg [2:0] DIV_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] DIV_cry_in; + reg [1:0] DIV_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_cry_out; + reg DIV_cry_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_DIV_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_DIV_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_DIV_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_DIV_dec31_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] DIV_dec31_DIV_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] DIV_dec31_DIV_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] DIV_dec31_DIV_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] DIV_dec31_DIV_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_DIV_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_DIV_dec31_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_DIV_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] DIV_dec31_DIV_dec31_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_DIV_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire DIV_dec31_DIV_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] DIV_dec31_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] DIV_function_unit; + reg [13:0] DIV_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] DIV_in1_sel; + reg [2:0] DIV_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] DIV_in2_sel; + reg [3:0] DIV_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] DIV_internal_op; + reg [6:0] DIV_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_inv_a; + reg DIV_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_inv_out; + reg DIV_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_is_32b; + reg DIV_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] DIV_ldst_len; + reg [3:0] DIV_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] DIV_rc_sel; + reg [1:0] DIV_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output DIV_sgn; + reg DIV_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [5:0] DIV_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + DIV_dec31 DIV_dec31 ( + .DIV_dec31_cr_in(DIV_dec31_DIV_dec31_cr_in), + .DIV_dec31_cr_out(DIV_dec31_DIV_dec31_cr_out), + .DIV_dec31_cry_in(DIV_dec31_DIV_dec31_cry_in), + .DIV_dec31_cry_out(DIV_dec31_DIV_dec31_cry_out), + .DIV_dec31_function_unit(DIV_dec31_DIV_dec31_function_unit), + .DIV_dec31_in1_sel(DIV_dec31_DIV_dec31_in1_sel), + .DIV_dec31_in2_sel(DIV_dec31_DIV_dec31_in2_sel), + .DIV_dec31_internal_op(DIV_dec31_DIV_dec31_internal_op), + .DIV_dec31_inv_a(DIV_dec31_DIV_dec31_inv_a), + .DIV_dec31_inv_out(DIV_dec31_DIV_dec31_inv_out), + .DIV_dec31_is_32b(DIV_dec31_DIV_dec31_is_32b), + .DIV_dec31_ldst_len(DIV_dec31_DIV_dec31_ldst_len), + .DIV_dec31_rc_sel(DIV_dec31_DIV_dec31_rc_sel), + .DIV_dec31_sgn(DIV_dec31_DIV_dec31_sgn), + .opcode_in(DIV_dec31_opcode_in) + ); + always @* begin + if (\initial ) begin end + DIV_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_cry_in = DIV_dec31_DIV_dec31_cry_in; + endcase + end + always @* begin + if (\initial ) begin end + DIV_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_inv_a = DIV_dec31_DIV_dec31_inv_a; + endcase + end + always @* begin + if (\initial ) begin end + DIV_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_inv_out = DIV_dec31_DIV_dec31_inv_out; + endcase + end + always @* begin + if (\initial ) begin end + DIV_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_cry_out = DIV_dec31_DIV_dec31_cry_out; + endcase + end + always @* begin + if (\initial ) begin end + DIV_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_is_32b = DIV_dec31_DIV_dec31_is_32b; + endcase + end + always @* begin + if (\initial ) begin end + DIV_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_sgn = DIV_dec31_DIV_dec31_sgn; + endcase + end + always @* begin + if (\initial ) begin end + DIV_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_function_unit = DIV_dec31_DIV_dec31_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + DIV_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_internal_op = DIV_dec31_DIV_dec31_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + DIV_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_in1_sel = DIV_dec31_DIV_dec31_in1_sel; + endcase + end + always @* begin + if (\initial ) begin end + DIV_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_in2_sel = DIV_dec31_DIV_dec31_in2_sel; + endcase + end + always @* begin + if (\initial ) begin end + DIV_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_cr_in = DIV_dec31_DIV_dec31_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + DIV_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_cr_out = DIV_dec31_DIV_dec31_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + DIV_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_ldst_len = DIV_dec31_DIV_dec31_ldst_len; + endcase + end + always @* begin + if (\initial ) begin end + DIV_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + DIV_rc_sel = DIV_dec31_DIV_dec31_rc_sel; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign DIV_SPR = opcode_in[20:11]; + assign DIV_MB = opcode_in[10:6]; + assign DIV_ME = opcode_in[5:1]; + assign DIV_SH = opcode_in[15:11]; + assign DIV_BC = opcode_in[10:6]; + assign DIV_TO = opcode_in[25:21]; + assign DIV_DS = opcode_in[15:2]; + assign DIV_D = opcode_in[15:0]; + assign DIV_BH = opcode_in[12:11]; + assign DIV_BI = opcode_in[20:16]; + assign DIV_BO = opcode_in[25:21]; + assign DIV_FXM = opcode_in[19:12]; + assign DIV_BT = opcode_in[25:21]; + assign DIV_BA = opcode_in[20:16]; + assign DIV_BB = opcode_in[15:11]; + assign DIV_CR = opcode_in[10:1]; + assign DIV_BF = opcode_in[25:23]; + assign DIV_BD = opcode_in[15:2]; + assign DIV_OE = opcode_in[10]; + assign DIV_Rc = opcode_in[0]; + assign DIV_AA = opcode_in[1]; + assign DIV_LK = opcode_in[0]; + assign DIV_LI = opcode_in[25:2]; + assign DIV_ME32 = opcode_in[5:1]; + assign DIV_MB32 = opcode_in[10:6]; + assign DIV_sh = { opcode_in[1], opcode_in[15:11] }; + assign DIV_SH32 = opcode_in[15:11]; + assign DIV_L = opcode_in[21]; + assign DIV_UI = opcode_in[15:0]; + assign DIV_SI = opcode_in[15:0]; + assign DIV_RB = opcode_in[15:11]; + assign DIV_RA = opcode_in[20:16]; + assign DIV_RT = opcode_in[25:21]; + assign DIV_RS = opcode_in[25:21]; + assign DIV_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign DIV_dec31_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec" *) +(* generator = "nMigen" *) +module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL_function_unit, MUL_in2_sel, MUL_cr_out, MUL_is_32b, MUL_sgn, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, MUL_Rc, MUL_OE, MUL_BD, MUL_DS, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire MUL_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] MUL_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] MUL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] MUL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] MUL_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] MUL_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] MUL_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] MUL_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire MUL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [23:0] MUL_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire MUL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output MUL_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] MUL_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output MUL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] MUL_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] MUL_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] MUL_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MUL_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] MUL_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] MUL_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] MUL_cr_out; + reg [2:0] MUL_cr_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] MUL_dec31_MUL_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] MUL_dec31_MUL_dec31_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] MUL_dec31_MUL_dec31_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] MUL_dec31_MUL_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] MUL_dec31_MUL_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire MUL_dec31_MUL_dec31_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] MUL_dec31_MUL_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire MUL_dec31_MUL_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] MUL_dec31_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] MUL_function_unit; + reg [13:0] MUL_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] MUL_in2_sel; + reg [3:0] MUL_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] MUL_internal_op; + reg [6:0] MUL_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output MUL_is_32b; + reg MUL_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] MUL_rc_sel; + reg [1:0] MUL_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output MUL_sgn; + reg MUL_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [5:0] MUL_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + MUL_dec31 MUL_dec31 ( + .MUL_dec31_cr_in(MUL_dec31_MUL_dec31_cr_in), + .MUL_dec31_cr_out(MUL_dec31_MUL_dec31_cr_out), + .MUL_dec31_function_unit(MUL_dec31_MUL_dec31_function_unit), + .MUL_dec31_in2_sel(MUL_dec31_MUL_dec31_in2_sel), + .MUL_dec31_internal_op(MUL_dec31_MUL_dec31_internal_op), + .MUL_dec31_is_32b(MUL_dec31_MUL_dec31_is_32b), + .MUL_dec31_rc_sel(MUL_dec31_MUL_dec31_rc_sel), + .MUL_dec31_sgn(MUL_dec31_MUL_dec31_sgn), + .opcode_in(MUL_dec31_opcode_in) + ); + always @* begin + if (\initial ) begin end + MUL_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + MUL_function_unit = MUL_dec31_MUL_dec31_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + MUL_function_unit = 14'h0100; + endcase + end + always @* begin + if (\initial ) begin end + MUL_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + MUL_internal_op = MUL_dec31_MUL_dec31_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + MUL_internal_op = 7'h32; + endcase + end + always @* begin + if (\initial ) begin end + MUL_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + MUL_in2_sel = MUL_dec31_MUL_dec31_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + MUL_in2_sel = 4'h3; + endcase + end + always @* begin + if (\initial ) begin end + MUL_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + MUL_cr_in = MUL_dec31_MUL_dec31_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + MUL_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + MUL_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + MUL_cr_out = MUL_dec31_MUL_dec31_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + MUL_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + MUL_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + MUL_rc_sel = MUL_dec31_MUL_dec31_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + MUL_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + MUL_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + MUL_is_32b = MUL_dec31_MUL_dec31_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + MUL_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + MUL_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + MUL_sgn = MUL_dec31_MUL_dec31_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + MUL_sgn = 1'h1; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign MUL_SPR = opcode_in[20:11]; + assign MUL_MB = opcode_in[10:6]; + assign MUL_ME = opcode_in[5:1]; + assign MUL_SH = opcode_in[15:11]; + assign MUL_BC = opcode_in[10:6]; + assign MUL_TO = opcode_in[25:21]; + assign MUL_DS = opcode_in[15:2]; + assign MUL_D = opcode_in[15:0]; + assign MUL_BH = opcode_in[12:11]; + assign MUL_BI = opcode_in[20:16]; + assign MUL_BO = opcode_in[25:21]; + assign MUL_FXM = opcode_in[19:12]; + assign MUL_BT = opcode_in[25:21]; + assign MUL_BA = opcode_in[20:16]; + assign MUL_BB = opcode_in[15:11]; + assign MUL_CR = opcode_in[10:1]; + assign MUL_BF = opcode_in[25:23]; + assign MUL_BD = opcode_in[15:2]; + assign MUL_OE = opcode_in[10]; + assign MUL_Rc = opcode_in[0]; + assign MUL_AA = opcode_in[1]; + assign MUL_LK = opcode_in[0]; + assign MUL_LI = opcode_in[25:2]; + assign MUL_ME32 = opcode_in[5:1]; + assign MUL_MB32 = opcode_in[10:6]; + assign MUL_sh = { opcode_in[1], opcode_in[15:11] }; + assign MUL_SH32 = opcode_in[15:11]; + assign MUL_L = opcode_in[21]; + assign MUL_UI = opcode_in[15:0]; + assign MUL_SI = opcode_in[15:0]; + assign MUL_RB = opcode_in[15:11]; + assign MUL_RA = opcode_in[20:16]; + assign MUL_RT = opcode_in[25:21]; + assign MUL_RS = opcode_in[25:21]; + assign MUL_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign MUL_dec31_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec" *) +(* generator = "nMigen" *) +module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, SHIFT_ROT_SPR, SHIFT_ROT_function_unit, SHIFT_ROT_in2_sel, SHIFT_ROT_cr_out, SHIFT_ROT_cr_in, SHIFT_ROT_inv_a, SHIFT_ROT_cry_in, SHIFT_ROT_cry_out, SHIFT_ROT_is_32b, SHIFT_ROT_sgn, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, SHIFT_ROT_sh, SHIFT_ROT_LI, SHIFT_ROT_Rc, SHIFT_ROT_OE, SHIFT_ROT_BD, SHIFT_ROT_DS, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire SHIFT_ROT_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] SHIFT_ROT_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] SHIFT_ROT_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] SHIFT_ROT_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] SHIFT_ROT_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] SHIFT_ROT_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] SHIFT_ROT_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] SHIFT_ROT_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire SHIFT_ROT_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [23:0] SHIFT_ROT_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire SHIFT_ROT_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output SHIFT_ROT_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] SHIFT_ROT_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output SHIFT_ROT_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] SHIFT_ROT_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] SHIFT_ROT_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] SHIFT_ROT_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SHIFT_ROT_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] SHIFT_ROT_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_cr_in; + reg [2:0] SHIFT_ROT_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] SHIFT_ROT_cr_out; + reg [2:0] SHIFT_ROT_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_cry_in; + reg [1:0] SHIFT_ROT_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_cry_out; + reg SHIFT_ROT_cry_out; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] SHIFT_ROT_dec30_opcode_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] SHIFT_ROT_dec31_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] SHIFT_ROT_function_unit; + reg [13:0] SHIFT_ROT_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] SHIFT_ROT_in2_sel; + reg [3:0] SHIFT_ROT_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] SHIFT_ROT_internal_op; + reg [6:0] SHIFT_ROT_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_inv_a; + reg SHIFT_ROT_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_is_32b; + reg SHIFT_ROT_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_rc_sel; + reg [1:0] SHIFT_ROT_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output SHIFT_ROT_sgn; + reg SHIFT_ROT_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [5:0] SHIFT_ROT_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + SHIFT_ROT_dec30 SHIFT_ROT_dec30 ( + .SHIFT_ROT_dec30_cr_in(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in), + .SHIFT_ROT_dec30_cr_out(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out), + .SHIFT_ROT_dec30_cry_in(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in), + .SHIFT_ROT_dec30_cry_out(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out), + .SHIFT_ROT_dec30_function_unit(SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit), + .SHIFT_ROT_dec30_in2_sel(SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel), + .SHIFT_ROT_dec30_internal_op(SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op), + .SHIFT_ROT_dec30_inv_a(SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a), + .SHIFT_ROT_dec30_is_32b(SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b), + .SHIFT_ROT_dec30_rc_sel(SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel), + .SHIFT_ROT_dec30_sgn(SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn), + .opcode_in(SHIFT_ROT_dec30_opcode_in) + ); + SHIFT_ROT_dec31 SHIFT_ROT_dec31 ( + .SHIFT_ROT_dec31_cr_in(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in), + .SHIFT_ROT_dec31_cr_out(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out), + .SHIFT_ROT_dec31_cry_in(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in), + .SHIFT_ROT_dec31_cry_out(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out), + .SHIFT_ROT_dec31_function_unit(SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit), + .SHIFT_ROT_dec31_in2_sel(SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel), + .SHIFT_ROT_dec31_internal_op(SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op), + .SHIFT_ROT_dec31_inv_a(SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a), + .SHIFT_ROT_dec31_is_32b(SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b), + .SHIFT_ROT_dec31_rc_sel(SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel), + .SHIFT_ROT_dec31_sgn(SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn), + .opcode_in(SHIFT_ROT_dec31_opcode_in) + ); + always @* begin + if (\initial ) begin end + SHIFT_ROT_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_inv_a = SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_inv_a = SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_cry_out = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_cry_out = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_is_32b = SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_is_32b = SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_is_32b = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_sgn = SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_sgn = SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_function_unit = SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_function_unit = SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_internal_op = SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_internal_op = SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_internal_op = 7'h38; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_in2_sel = SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_in2_sel = SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_in2_sel = 4'hb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_in2_sel = 4'hb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_cr_in = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_cr_in = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_cr_out = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_cr_out = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_rc_sel = SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_rc_sel = SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SHIFT_ROT_cry_in = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SHIFT_ROT_cry_in = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SHIFT_ROT_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SHIFT_ROT_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SHIFT_ROT_cry_in = 2'h0; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign SHIFT_ROT_SPR = opcode_in[20:11]; + assign SHIFT_ROT_MB = opcode_in[10:6]; + assign SHIFT_ROT_ME = opcode_in[5:1]; + assign SHIFT_ROT_SH = opcode_in[15:11]; + assign SHIFT_ROT_BC = opcode_in[10:6]; + assign SHIFT_ROT_TO = opcode_in[25:21]; + assign SHIFT_ROT_DS = opcode_in[15:2]; + assign SHIFT_ROT_D = opcode_in[15:0]; + assign SHIFT_ROT_BH = opcode_in[12:11]; + assign SHIFT_ROT_BI = opcode_in[20:16]; + assign SHIFT_ROT_BO = opcode_in[25:21]; + assign SHIFT_ROT_FXM = opcode_in[19:12]; + assign SHIFT_ROT_BT = opcode_in[25:21]; + assign SHIFT_ROT_BA = opcode_in[20:16]; + assign SHIFT_ROT_BB = opcode_in[15:11]; + assign SHIFT_ROT_CR = opcode_in[10:1]; + assign SHIFT_ROT_BF = opcode_in[25:23]; + assign SHIFT_ROT_BD = opcode_in[15:2]; + assign SHIFT_ROT_OE = opcode_in[10]; + assign SHIFT_ROT_Rc = opcode_in[0]; + assign SHIFT_ROT_AA = opcode_in[1]; + assign SHIFT_ROT_LK = opcode_in[0]; + assign SHIFT_ROT_LI = opcode_in[25:2]; + assign SHIFT_ROT_ME32 = opcode_in[5:1]; + assign SHIFT_ROT_MB32 = opcode_in[10:6]; + assign SHIFT_ROT_sh = { opcode_in[1], opcode_in[15:11] }; + assign SHIFT_ROT_SH32 = opcode_in[15:11]; + assign SHIFT_ROT_L = opcode_in[21]; + assign SHIFT_ROT_UI = opcode_in[15:0]; + assign SHIFT_ROT_SI = opcode_in[15:0]; + assign SHIFT_ROT_RB = opcode_in[15:11]; + assign SHIFT_ROT_RA = opcode_in[20:16]; + assign SHIFT_ROT_RT = opcode_in[25:21]; + assign SHIFT_ROT_RS = opcode_in[25:21]; + assign SHIFT_ROT_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign SHIFT_ROT_dec31_opcode_in = opcode_in; + assign SHIFT_ROT_dec30_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec" *) +(* generator = "nMigen" *) +module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, LDST_function_unit, LDST_in1_sel, LDST_in2_sel, LDST_cr_out, LDST_ldst_len, LDST_is_32b, LDST_sgn, LDST_br, LDST_sgn_ext, LDST_upd, LDST_RA, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_LI, LDST_Rc, LDST_OE, LDST_BD, LDST_DS, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire LDST_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] LDST_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] LDST_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] LDST_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] LDST_CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] LDST_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [13:0] LDST_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] LDST_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire LDST_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [23:0] LDST_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire LDST_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output LDST_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] LDST_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] LDST_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output LDST_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] LDST_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] LDST_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] LDST_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] LDST_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [15:0] LDST_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_br; + reg LDST_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] LDST_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_cr_out; + reg [2:0] LDST_cr_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_LDST_dec31_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_LDST_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_LDST_dec31_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LDST_dec31_LDST_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec31_LDST_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_LDST_dec31_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LDST_dec31_LDST_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_LDST_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec31_LDST_dec31_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_LDST_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_LDST_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec31_LDST_dec31_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_LDST_dec31_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LDST_dec31_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec58_LDST_dec58_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec58_LDST_dec58_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec58_LDST_dec58_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LDST_dec58_LDST_dec58_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec58_LDST_dec58_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec58_LDST_dec58_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LDST_dec58_LDST_dec58_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec58_LDST_dec58_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec58_LDST_dec58_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec58_LDST_dec58_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec58_LDST_dec58_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec58_LDST_dec58_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec58_LDST_dec58_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LDST_dec58_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec62_LDST_dec62_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec62_LDST_dec62_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec62_LDST_dec62_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] LDST_dec62_LDST_dec62_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] LDST_dec62_LDST_dec62_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec62_LDST_dec62_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] LDST_dec62_LDST_dec62_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec62_LDST_dec62_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] LDST_dec62_LDST_dec62_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec62_LDST_dec62_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec62_LDST_dec62_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire LDST_dec62_LDST_dec62_sgn_ext; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec62_LDST_dec62_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] LDST_dec62_opcode_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] LDST_function_unit; + reg [13:0] LDST_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] LDST_in1_sel; + reg [2:0] LDST_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_in2_sel; + reg [3:0] LDST_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] LDST_internal_op; + reg [6:0] LDST_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_is_32b; + reg LDST_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] LDST_ldst_len; + reg [3:0] LDST_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_rc_sel; + reg [1:0] LDST_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_sgn; + reg LDST_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output LDST_sgn_ext; + reg LDST_sgn_ext; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [5:0] LDST_sh; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] LDST_upd; + reg [1:0] LDST_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + LDST_dec31 LDST_dec31 ( + .LDST_dec31_br(LDST_dec31_LDST_dec31_br), + .LDST_dec31_cr_in(LDST_dec31_LDST_dec31_cr_in), + .LDST_dec31_cr_out(LDST_dec31_LDST_dec31_cr_out), + .LDST_dec31_function_unit(LDST_dec31_LDST_dec31_function_unit), + .LDST_dec31_in1_sel(LDST_dec31_LDST_dec31_in1_sel), + .LDST_dec31_in2_sel(LDST_dec31_LDST_dec31_in2_sel), + .LDST_dec31_internal_op(LDST_dec31_LDST_dec31_internal_op), + .LDST_dec31_is_32b(LDST_dec31_LDST_dec31_is_32b), + .LDST_dec31_ldst_len(LDST_dec31_LDST_dec31_ldst_len), + .LDST_dec31_rc_sel(LDST_dec31_LDST_dec31_rc_sel), + .LDST_dec31_sgn(LDST_dec31_LDST_dec31_sgn), + .LDST_dec31_sgn_ext(LDST_dec31_LDST_dec31_sgn_ext), + .LDST_dec31_upd(LDST_dec31_LDST_dec31_upd), + .opcode_in(LDST_dec31_opcode_in) + ); + LDST_dec58 LDST_dec58 ( + .LDST_dec58_br(LDST_dec58_LDST_dec58_br), + .LDST_dec58_cr_in(LDST_dec58_LDST_dec58_cr_in), + .LDST_dec58_cr_out(LDST_dec58_LDST_dec58_cr_out), + .LDST_dec58_function_unit(LDST_dec58_LDST_dec58_function_unit), + .LDST_dec58_in1_sel(LDST_dec58_LDST_dec58_in1_sel), + .LDST_dec58_in2_sel(LDST_dec58_LDST_dec58_in2_sel), + .LDST_dec58_internal_op(LDST_dec58_LDST_dec58_internal_op), + .LDST_dec58_is_32b(LDST_dec58_LDST_dec58_is_32b), + .LDST_dec58_ldst_len(LDST_dec58_LDST_dec58_ldst_len), + .LDST_dec58_rc_sel(LDST_dec58_LDST_dec58_rc_sel), + .LDST_dec58_sgn(LDST_dec58_LDST_dec58_sgn), + .LDST_dec58_sgn_ext(LDST_dec58_LDST_dec58_sgn_ext), + .LDST_dec58_upd(LDST_dec58_LDST_dec58_upd), + .opcode_in(LDST_dec58_opcode_in) + ); + LDST_dec62 LDST_dec62 ( + .LDST_dec62_br(LDST_dec62_LDST_dec62_br), + .LDST_dec62_cr_in(LDST_dec62_LDST_dec62_cr_in), + .LDST_dec62_cr_out(LDST_dec62_LDST_dec62_cr_out), + .LDST_dec62_function_unit(LDST_dec62_LDST_dec62_function_unit), + .LDST_dec62_in1_sel(LDST_dec62_LDST_dec62_in1_sel), + .LDST_dec62_in2_sel(LDST_dec62_LDST_dec62_in2_sel), + .LDST_dec62_internal_op(LDST_dec62_LDST_dec62_internal_op), + .LDST_dec62_is_32b(LDST_dec62_LDST_dec62_is_32b), + .LDST_dec62_ldst_len(LDST_dec62_LDST_dec62_ldst_len), + .LDST_dec62_rc_sel(LDST_dec62_LDST_dec62_rc_sel), + .LDST_dec62_sgn(LDST_dec62_LDST_dec62_sgn), + .LDST_dec62_sgn_ext(LDST_dec62_LDST_dec62_sgn_ext), + .LDST_dec62_upd(LDST_dec62_LDST_dec62_upd), + .opcode_in(LDST_dec62_opcode_in) + ); + always @* begin + if (\initial ) begin end + LDST_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_ldst_len = LDST_dec31_LDST_dec31_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_ldst_len = LDST_dec58_LDST_dec58_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_ldst_len = LDST_dec62_LDST_dec62_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + LDST_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_upd = LDST_dec31_LDST_dec31_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_upd = LDST_dec58_LDST_dec58_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_upd = LDST_dec62_LDST_dec62_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_upd = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + LDST_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_rc_sel = LDST_dec31_LDST_dec31_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_rc_sel = LDST_dec58_LDST_dec58_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_rc_sel = LDST_dec62_LDST_dec62_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_br = LDST_dec31_LDST_dec31_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_br = LDST_dec58_LDST_dec58_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_br = LDST_dec62_LDST_dec62_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_sgn_ext = LDST_dec31_LDST_dec31_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_sgn_ext = LDST_dec58_LDST_dec58_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_sgn_ext = LDST_dec62_LDST_dec62_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_is_32b = LDST_dec31_LDST_dec31_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_is_32b = LDST_dec58_LDST_dec58_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_is_32b = LDST_dec62_LDST_dec62_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_sgn = LDST_dec31_LDST_dec31_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_sgn = LDST_dec58_LDST_dec58_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_sgn = LDST_dec62_LDST_dec62_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_function_unit = LDST_dec31_LDST_dec31_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_function_unit = LDST_dec58_LDST_dec58_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_function_unit = LDST_dec62_LDST_dec62_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_internal_op = LDST_dec31_LDST_dec31_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_internal_op = LDST_dec58_LDST_dec58_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_internal_op = LDST_dec62_LDST_dec62_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + LDST_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_in1_sel = LDST_dec31_LDST_dec31_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_in1_sel = LDST_dec58_LDST_dec58_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_in1_sel = LDST_dec62_LDST_dec62_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + LDST_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_in2_sel = LDST_dec31_LDST_dec31_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_in2_sel = LDST_dec58_LDST_dec58_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_in2_sel = LDST_dec62_LDST_dec62_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_in2_sel = 4'h3; + endcase + end + always @* begin + if (\initial ) begin end + LDST_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_cr_in = LDST_dec31_LDST_dec31_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_cr_in = LDST_dec58_LDST_dec58_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_cr_in = LDST_dec62_LDST_dec62_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + LDST_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + LDST_cr_out = LDST_dec31_LDST_dec31_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + LDST_cr_out = LDST_dec58_LDST_dec58_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + LDST_cr_out = LDST_dec62_LDST_dec62_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + LDST_cr_out = 3'h0; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign LDST_SPR = opcode_in[20:11]; + assign LDST_MB = opcode_in[10:6]; + assign LDST_ME = opcode_in[5:1]; + assign LDST_SH = opcode_in[15:11]; + assign LDST_BC = opcode_in[10:6]; + assign LDST_TO = opcode_in[25:21]; + assign LDST_DS = opcode_in[15:2]; + assign LDST_D = opcode_in[15:0]; + assign LDST_BH = opcode_in[12:11]; + assign LDST_BI = opcode_in[20:16]; + assign LDST_BO = opcode_in[25:21]; + assign LDST_FXM = opcode_in[19:12]; + assign LDST_BT = opcode_in[25:21]; + assign LDST_BA = opcode_in[20:16]; + assign LDST_BB = opcode_in[15:11]; + assign LDST_CR = opcode_in[10:1]; + assign LDST_BF = opcode_in[25:23]; + assign LDST_BD = opcode_in[15:2]; + assign LDST_OE = opcode_in[10]; + assign LDST_Rc = opcode_in[0]; + assign LDST_AA = opcode_in[1]; + assign LDST_LK = opcode_in[0]; + assign LDST_LI = opcode_in[25:2]; + assign LDST_ME32 = opcode_in[5:1]; + assign LDST_MB32 = opcode_in[10:6]; + assign LDST_sh = { opcode_in[1], opcode_in[15:11] }; + assign LDST_SH32 = opcode_in[15:11]; + assign LDST_L = opcode_in[21]; + assign LDST_UI = opcode_in[15:0]; + assign LDST_SI = opcode_in[15:0]; + assign LDST_RB = opcode_in[15:11]; + assign LDST_RA = opcode_in[20:16]; + assign LDST_RT = opcode_in[25:21]; + assign LDST_RS = opcode_in[25:21]; + assign LDST_PO = opcode_in[31:26]; + assign opcode_in = \$1 ; + assign LDST_dec62_opcode_in = opcode_in; + assign LDST_dec58_opcode_in = opcode_in; + assign LDST_dec31_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec" *) +(* generator = "nMigen" *) +module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_unit, cr_out, cry_in, is_32b, lk, LK, cr_in, in1_sel, in2_sel, in3_sel, out_sel, asmcode, upd, RS, RT, RA, RB, Rc, OE, BB, BA, BT, FXM, BO, BI, BC, X_BF, X_BFA, XL_BT, XL_XO, bigendian); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + wire [31:0] \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire A_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] A_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [2:0] BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [1:0] BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] B_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] B_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire B_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] CR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQE_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DQE_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [11:0] DQ_DQ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] DQ_PT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DQ_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DQ_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] DQ_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] DQ_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [13:0] DS_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DS_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] DS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] DX_d0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] DX_d0_d1_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] DX_d1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire DX_d2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] D_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_D; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire D_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] D_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [15:0] D_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] EVS_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [7:0] FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_AA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [23:0] I_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire I_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] MB32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_IS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MDS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MDS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XBI_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] MDS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MDS_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] MD_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire MD_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] MD_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] MD_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] ME32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_MB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_ME; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire M_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] M_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [4:0] RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] SC_LEV; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] SC_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + output [9:0] SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] SVL_SVi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] SVL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_ms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire SVL_vs; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [1:0] SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [1:0] SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] TX_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] TX_XBI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] TX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VA_SHB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VA_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] VA_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VC_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VC_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VC_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire VX_PS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_SIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] VX_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] VX_UIM_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] VX_UIM_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] VX_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] VX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [10:0] VX_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFL_FLM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFL_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XFL_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_BHRBE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_DUI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_DUIS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XFX_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XFX_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] XFX_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XL_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XL_BH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XL_BO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + output [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [14:0] XL_OC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XL_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + output [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XO_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XO_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XO_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XS_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XS_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XS_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XS_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX2_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX2_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX2_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX2_UIM_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX2_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] XX2_dc_dm_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX2_dm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX2_dx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] XX3_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_DM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX3_SHW; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX3_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX3_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX3_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] XX3_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] XX3_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] XX3_XO_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_AX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_AX_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_BX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_BX_B; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_CX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_CX_C; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] XX4_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire XX4_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] XX4_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] XX4_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_A; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + output [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + output [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_CT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [6:0] X_DCMX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_DRM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_E; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_EO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_EO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_EX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_E_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] X_IH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_IMM8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_L1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_L3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_MO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_NB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_PRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RIC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_RM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_RO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RSp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_RTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_R_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_SP; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_SR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_SX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_SX_S; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_TBR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_TO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_TX; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] X_TX_T; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [3:0] X_U; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_UIM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] X_VRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire X_W; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] X_WC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] X_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] X_XO_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] Z22_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DCM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_DGM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z22_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z22_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] Z22_SH; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [8:0] Z22_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRAp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRBp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_FRTp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_R; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [1:0] Z23_RMC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire Z23_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] Z23_TE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [7:0] Z23_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [5:0] all_PO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] asmcode; + reg [7:0] asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + reg br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] cr_in; + reg [2:0] cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] cr_out; + reg [2:0] cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] cry_in; + reg [1:0] cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + reg cry_out; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec19_dec19_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec19_dec19_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec19_dec19_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec19_dec19_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec19_dec19_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec19_dec19_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec19_dec19_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec19_dec19_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec19_dec19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec19_dec19_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec19_dec19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec19_dec19_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec19_dec19_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec19_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec22_dec22_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec22_dec22_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec22_dec22_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec22_dec22_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec22_dec22_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec22_dec22_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec22_dec22_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec22_dec22_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec22_dec22_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec22_dec22_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec22_dec22_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec22_dec22_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec22_dec22_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec22_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec30_dec30_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec30_dec30_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec30_dec30_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec30_dec30_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec30_dec30_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec30_dec30_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec30_dec30_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec30_dec30_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec30_dec30_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec30_dec30_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec30_dec30_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec30_dec30_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec30_dec30_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec30_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec31_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec31_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec31_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec31_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec31_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec31_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec31_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec31_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec31_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec58_dec58_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec58_dec58_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec58_dec58_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec58_dec58_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec58_dec58_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec58_dec58_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec58_dec58_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec58_dec58_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec58_dec58_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec58_dec58_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec58_dec58_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec58_dec58_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec58_dec58_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec58_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec62_dec62_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec62_dec62_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec62_dec62_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec62_dec62_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec62_dec62_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec62_dec62_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec62_dec62_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec62_dec62_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec62_dec62_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec62_dec62_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec62_dec62_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec62_dec62_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec62_dec62_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec62_opcode_in; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [4:0] form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] function_unit; + reg [13:0] function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] in1_sel; + reg [2:0] in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] in2_sel; + reg [3:0] in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] in3_sel; + reg [1:0] in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] internal_op; + reg [6:0] internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + reg inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + reg inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output is_32b; + reg is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [3:0] ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output lk; + reg lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + output [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [5:0] opcode_switch; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [31:0] \opcode_switch$1 ; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] out_sel; + reg [2:0] out_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] rc_sel; + reg [1:0] rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + reg rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + reg sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + reg sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + reg sgn_ext; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] sh; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + reg [2:0] sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] upd; + reg [1:0] upd; + assign \$2 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + dec19 dec19 ( + .dec19_SV_Etype(dec19_dec19_SV_Etype), + .dec19_SV_Ptype(dec19_dec19_SV_Ptype), + .dec19_asmcode(dec19_dec19_asmcode), + .dec19_br(dec19_dec19_br), + .dec19_cr_in(dec19_dec19_cr_in), + .dec19_cr_out(dec19_dec19_cr_out), + .dec19_cry_in(dec19_dec19_cry_in), + .dec19_cry_out(dec19_dec19_cry_out), + .dec19_form(dec19_dec19_form), + .dec19_function_unit(dec19_dec19_function_unit), + .dec19_in1_sel(dec19_dec19_in1_sel), + .dec19_in2_sel(dec19_dec19_in2_sel), + .dec19_in3_sel(dec19_dec19_in3_sel), + .dec19_internal_op(dec19_dec19_internal_op), + .dec19_inv_a(dec19_dec19_inv_a), + .dec19_inv_out(dec19_dec19_inv_out), + .dec19_is_32b(dec19_dec19_is_32b), + .dec19_ldst_len(dec19_dec19_ldst_len), + .dec19_lk(dec19_dec19_lk), + .dec19_out_sel(dec19_dec19_out_sel), + .dec19_rc_sel(dec19_dec19_rc_sel), + .dec19_rsrv(dec19_dec19_rsrv), + .dec19_sgl_pipe(dec19_dec19_sgl_pipe), + .dec19_sgn(dec19_dec19_sgn), + .dec19_sgn_ext(dec19_dec19_sgn_ext), + .dec19_sv_cr_in(dec19_dec19_sv_cr_in), + .dec19_sv_cr_out(dec19_dec19_sv_cr_out), + .dec19_sv_in1(dec19_dec19_sv_in1), + .dec19_sv_in2(dec19_dec19_sv_in2), + .dec19_sv_in3(dec19_dec19_sv_in3), + .dec19_sv_out(dec19_dec19_sv_out), + .dec19_sv_out2(dec19_dec19_sv_out2), + .dec19_upd(dec19_dec19_upd), + .opcode_in(dec19_opcode_in) + ); + dec22 dec22 ( + .dec22_SV_Etype(dec22_dec22_SV_Etype), + .dec22_SV_Ptype(dec22_dec22_SV_Ptype), + .dec22_asmcode(dec22_dec22_asmcode), + .dec22_br(dec22_dec22_br), + .dec22_cr_in(dec22_dec22_cr_in), + .dec22_cr_out(dec22_dec22_cr_out), + .dec22_cry_in(dec22_dec22_cry_in), + .dec22_cry_out(dec22_dec22_cry_out), + .dec22_form(dec22_dec22_form), + .dec22_function_unit(dec22_dec22_function_unit), + .dec22_in1_sel(dec22_dec22_in1_sel), + .dec22_in2_sel(dec22_dec22_in2_sel), + .dec22_in3_sel(dec22_dec22_in3_sel), + .dec22_internal_op(dec22_dec22_internal_op), + .dec22_inv_a(dec22_dec22_inv_a), + .dec22_inv_out(dec22_dec22_inv_out), + .dec22_is_32b(dec22_dec22_is_32b), + .dec22_ldst_len(dec22_dec22_ldst_len), + .dec22_lk(dec22_dec22_lk), + .dec22_out_sel(dec22_dec22_out_sel), + .dec22_rc_sel(dec22_dec22_rc_sel), + .dec22_rsrv(dec22_dec22_rsrv), + .dec22_sgl_pipe(dec22_dec22_sgl_pipe), + .dec22_sgn(dec22_dec22_sgn), + .dec22_sgn_ext(dec22_dec22_sgn_ext), + .dec22_sv_cr_in(dec22_dec22_sv_cr_in), + .dec22_sv_cr_out(dec22_dec22_sv_cr_out), + .dec22_sv_in1(dec22_dec22_sv_in1), + .dec22_sv_in2(dec22_dec22_sv_in2), + .dec22_sv_in3(dec22_dec22_sv_in3), + .dec22_sv_out(dec22_dec22_sv_out), + .dec22_sv_out2(dec22_dec22_sv_out2), + .dec22_upd(dec22_dec22_upd), + .opcode_in(dec22_opcode_in) + ); + dec30 dec30 ( + .dec30_SV_Etype(dec30_dec30_SV_Etype), + .dec30_SV_Ptype(dec30_dec30_SV_Ptype), + .dec30_asmcode(dec30_dec30_asmcode), + .dec30_br(dec30_dec30_br), + .dec30_cr_in(dec30_dec30_cr_in), + .dec30_cr_out(dec30_dec30_cr_out), + .dec30_cry_in(dec30_dec30_cry_in), + .dec30_cry_out(dec30_dec30_cry_out), + .dec30_form(dec30_dec30_form), + .dec30_function_unit(dec30_dec30_function_unit), + .dec30_in1_sel(dec30_dec30_in1_sel), + .dec30_in2_sel(dec30_dec30_in2_sel), + .dec30_in3_sel(dec30_dec30_in3_sel), + .dec30_internal_op(dec30_dec30_internal_op), + .dec30_inv_a(dec30_dec30_inv_a), + .dec30_inv_out(dec30_dec30_inv_out), + .dec30_is_32b(dec30_dec30_is_32b), + .dec30_ldst_len(dec30_dec30_ldst_len), + .dec30_lk(dec30_dec30_lk), + .dec30_out_sel(dec30_dec30_out_sel), + .dec30_rc_sel(dec30_dec30_rc_sel), + .dec30_rsrv(dec30_dec30_rsrv), + .dec30_sgl_pipe(dec30_dec30_sgl_pipe), + .dec30_sgn(dec30_dec30_sgn), + .dec30_sgn_ext(dec30_dec30_sgn_ext), + .dec30_sv_cr_in(dec30_dec30_sv_cr_in), + .dec30_sv_cr_out(dec30_dec30_sv_cr_out), + .dec30_sv_in1(dec30_dec30_sv_in1), + .dec30_sv_in2(dec30_dec30_sv_in2), + .dec30_sv_in3(dec30_dec30_sv_in3), + .dec30_sv_out(dec30_dec30_sv_out), + .dec30_sv_out2(dec30_dec30_sv_out2), + .dec30_upd(dec30_dec30_upd), + .opcode_in(dec30_opcode_in) + ); + dec31 dec31 ( + .dec31_SV_Etype(dec31_dec31_SV_Etype), + .dec31_SV_Ptype(dec31_dec31_SV_Ptype), + .dec31_asmcode(dec31_dec31_asmcode), + .dec31_br(dec31_dec31_br), + .dec31_cr_in(dec31_dec31_cr_in), + .dec31_cr_out(dec31_dec31_cr_out), + .dec31_cry_in(dec31_dec31_cry_in), + .dec31_cry_out(dec31_dec31_cry_out), + .dec31_form(dec31_dec31_form), + .dec31_function_unit(dec31_dec31_function_unit), + .dec31_in1_sel(dec31_dec31_in1_sel), + .dec31_in2_sel(dec31_dec31_in2_sel), + .dec31_in3_sel(dec31_dec31_in3_sel), + .dec31_internal_op(dec31_dec31_internal_op), + .dec31_inv_a(dec31_dec31_inv_a), + .dec31_inv_out(dec31_dec31_inv_out), + .dec31_is_32b(dec31_dec31_is_32b), + .dec31_ldst_len(dec31_dec31_ldst_len), + .dec31_lk(dec31_dec31_lk), + .dec31_out_sel(dec31_dec31_out_sel), + .dec31_rc_sel(dec31_dec31_rc_sel), + .dec31_rsrv(dec31_dec31_rsrv), + .dec31_sgl_pipe(dec31_dec31_sgl_pipe), + .dec31_sgn(dec31_dec31_sgn), + .dec31_sgn_ext(dec31_dec31_sgn_ext), + .dec31_sv_cr_in(dec31_dec31_sv_cr_in), + .dec31_sv_cr_out(dec31_dec31_sv_cr_out), + .dec31_sv_in1(dec31_dec31_sv_in1), + .dec31_sv_in2(dec31_dec31_sv_in2), + .dec31_sv_in3(dec31_dec31_sv_in3), + .dec31_sv_out(dec31_dec31_sv_out), + .dec31_sv_out2(dec31_dec31_sv_out2), + .dec31_upd(dec31_dec31_upd), + .opcode_in(dec31_opcode_in) + ); + dec58 dec58 ( + .dec58_SV_Etype(dec58_dec58_SV_Etype), + .dec58_SV_Ptype(dec58_dec58_SV_Ptype), + .dec58_asmcode(dec58_dec58_asmcode), + .dec58_br(dec58_dec58_br), + .dec58_cr_in(dec58_dec58_cr_in), + .dec58_cr_out(dec58_dec58_cr_out), + .dec58_cry_in(dec58_dec58_cry_in), + .dec58_cry_out(dec58_dec58_cry_out), + .dec58_form(dec58_dec58_form), + .dec58_function_unit(dec58_dec58_function_unit), + .dec58_in1_sel(dec58_dec58_in1_sel), + .dec58_in2_sel(dec58_dec58_in2_sel), + .dec58_in3_sel(dec58_dec58_in3_sel), + .dec58_internal_op(dec58_dec58_internal_op), + .dec58_inv_a(dec58_dec58_inv_a), + .dec58_inv_out(dec58_dec58_inv_out), + .dec58_is_32b(dec58_dec58_is_32b), + .dec58_ldst_len(dec58_dec58_ldst_len), + .dec58_lk(dec58_dec58_lk), + .dec58_out_sel(dec58_dec58_out_sel), + .dec58_rc_sel(dec58_dec58_rc_sel), + .dec58_rsrv(dec58_dec58_rsrv), + .dec58_sgl_pipe(dec58_dec58_sgl_pipe), + .dec58_sgn(dec58_dec58_sgn), + .dec58_sgn_ext(dec58_dec58_sgn_ext), + .dec58_sv_cr_in(dec58_dec58_sv_cr_in), + .dec58_sv_cr_out(dec58_dec58_sv_cr_out), + .dec58_sv_in1(dec58_dec58_sv_in1), + .dec58_sv_in2(dec58_dec58_sv_in2), + .dec58_sv_in3(dec58_dec58_sv_in3), + .dec58_sv_out(dec58_dec58_sv_out), + .dec58_sv_out2(dec58_dec58_sv_out2), + .dec58_upd(dec58_dec58_upd), + .opcode_in(dec58_opcode_in) + ); + dec62 dec62 ( + .dec62_SV_Etype(dec62_dec62_SV_Etype), + .dec62_SV_Ptype(dec62_dec62_SV_Ptype), + .dec62_asmcode(dec62_dec62_asmcode), + .dec62_br(dec62_dec62_br), + .dec62_cr_in(dec62_dec62_cr_in), + .dec62_cr_out(dec62_dec62_cr_out), + .dec62_cry_in(dec62_dec62_cry_in), + .dec62_cry_out(dec62_dec62_cry_out), + .dec62_form(dec62_dec62_form), + .dec62_function_unit(dec62_dec62_function_unit), + .dec62_in1_sel(dec62_dec62_in1_sel), + .dec62_in2_sel(dec62_dec62_in2_sel), + .dec62_in3_sel(dec62_dec62_in3_sel), + .dec62_internal_op(dec62_dec62_internal_op), + .dec62_inv_a(dec62_dec62_inv_a), + .dec62_inv_out(dec62_dec62_inv_out), + .dec62_is_32b(dec62_dec62_is_32b), + .dec62_ldst_len(dec62_dec62_ldst_len), + .dec62_lk(dec62_dec62_lk), + .dec62_out_sel(dec62_dec62_out_sel), + .dec62_rc_sel(dec62_dec62_rc_sel), + .dec62_rsrv(dec62_dec62_rsrv), + .dec62_sgl_pipe(dec62_dec62_sgl_pipe), + .dec62_sgn(dec62_dec62_sgn), + .dec62_sgn_ext(dec62_dec62_sgn_ext), + .dec62_sv_cr_in(dec62_dec62_sv_cr_in), + .dec62_sv_cr_out(dec62_dec62_sv_cr_out), + .dec62_sv_in1(dec62_dec62_sv_in1), + .dec62_sv_in2(dec62_dec62_sv_in2), + .dec62_sv_in3(dec62_dec62_sv_in3), + .dec62_sv_out(dec62_dec62_sv_out), + .dec62_sv_out2(dec62_dec62_sv_out2), + .dec62_upd(dec62_dec62_upd), + .opcode_in(dec62_opcode_in) + ); + always @* begin + if (\initial ) begin end + form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + form = dec19_dec19_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + form = dec30_dec30_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + form = dec31_dec31_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + form = dec58_dec58_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + form = dec62_dec62_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + form = dec22_dec22_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + form = 5'h03; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + form = 5'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + form = 5'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + form = 5'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + form = 5'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + form = 5'h13; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + form = 5'h13; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + form = 5'h13; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + form = 5'h04; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + form = 5'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + form = 5'h00; + endcase + end + always @* begin + if (\initial ) begin end + asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + asmcode = dec19_dec19_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + asmcode = dec30_dec30_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + asmcode = dec31_dec31_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + asmcode = dec58_dec58_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + asmcode = dec62_dec62_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + asmcode = dec22_dec22_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + asmcode = 8'h07; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + asmcode = 8'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + asmcode = 8'h06; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + asmcode = 8'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + asmcode = 8'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + asmcode = 8'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + asmcode = 8'h14; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + asmcode = 8'h15; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + asmcode = 8'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + asmcode = 8'h1f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + asmcode = 8'h4e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + asmcode = 8'h4f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + asmcode = 8'h58; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + asmcode = 8'h5a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + asmcode = 8'h5e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + asmcode = 8'h5f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + asmcode = 8'h67; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + asmcode = 8'h69; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + asmcode = 8'h80; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + asmcode = 8'h8a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + asmcode = 8'h8b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + asmcode = 8'h98; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + asmcode = 8'h99; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + asmcode = 8'h9a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + asmcode = 8'ha7; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + asmcode = 8'haa; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + asmcode = 8'hb3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + asmcode = 8'hb6; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + asmcode = 8'hb9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + asmcode = 8'hbc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + asmcode = 8'hc4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + asmcode = 8'hcc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + asmcode = 8'hd0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + asmcode = 8'hd2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + asmcode = 8'hd3; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + asmcode = 8'h13; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + asmcode = 8'h86; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + asmcode = 8'h9d; + endcase + end + always @* begin + if (\initial ) begin end + SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + SV_Etype = dec19_dec19_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SV_Etype = dec30_dec30_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SV_Etype = dec31_dec31_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + SV_Etype = dec58_dec58_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + SV_Etype = dec62_dec62_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + SV_Etype = dec22_dec22_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + SV_Etype = 2'h2; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + SV_Etype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + SV_Ptype = dec19_dec19_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + SV_Ptype = dec30_dec30_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + SV_Ptype = dec31_dec31_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + SV_Ptype = dec58_dec58_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + SV_Ptype = dec62_dec62_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + SV_Ptype = dec22_dec22_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + SV_Ptype = 2'h2; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + SV_Ptype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + in1_sel = dec19_dec19_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + in1_sel = dec30_dec30_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + in1_sel = dec31_dec31_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + in1_sel = dec58_dec58_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + in1_sel = dec62_dec62_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + in1_sel = dec22_dec22_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + in1_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + in1_sel = 3'h4; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + in2_sel = dec19_dec19_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + in2_sel = dec30_dec30_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + in2_sel = dec31_dec31_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + in2_sel = dec58_dec58_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + in2_sel = dec62_dec62_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + in2_sel = dec22_dec22_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + in2_sel = 4'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + in2_sel = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + in2_sel = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + in2_sel = 4'h6; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + in2_sel = 4'h7; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + in2_sel = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + in2_sel = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + in2_sel = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + in2_sel = 4'hb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + in2_sel = 4'hb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + in2_sel = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + in2_sel = 4'h4; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + in3_sel = dec19_dec19_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + in3_sel = dec30_dec30_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + in3_sel = dec31_dec31_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + in3_sel = dec58_dec58_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + in3_sel = dec62_dec62_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + in3_sel = dec22_dec22_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + in3_sel = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + out_sel = dec19_dec19_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + out_sel = dec30_dec30_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + out_sel = dec31_dec31_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + out_sel = dec58_dec58_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + out_sel = dec62_dec62_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + out_sel = dec22_dec22_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + out_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + out_sel = 3'h2; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + out_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + cr_in = dec19_dec19_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + cr_in = dec30_dec30_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + cr_in = dec31_dec31_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + cr_in = dec58_dec58_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + cr_in = dec62_dec62_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + cr_in = dec22_dec22_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + cr_in = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + cr_in = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + cr_out = dec19_dec19_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + cr_out = dec30_dec30_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + cr_out = dec31_dec31_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + cr_out = dec58_dec58_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + cr_out = dec62_dec62_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + cr_out = dec22_dec22_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + cr_out = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sv_in1 = dec19_dec19_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sv_in1 = dec30_dec30_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sv_in1 = dec31_dec31_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sv_in1 = dec58_dec58_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sv_in1 = dec62_dec62_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sv_in1 = dec22_dec22_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sv_in1 = 3'h2; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sv_in2 = dec19_dec19_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sv_in2 = dec30_dec30_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sv_in2 = dec31_dec31_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sv_in2 = dec58_dec58_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sv_in2 = dec62_dec62_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sv_in2 = dec22_dec22_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sv_in2 = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sv_in3 = dec19_dec19_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sv_in3 = dec30_dec30_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sv_in3 = dec31_dec31_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sv_in3 = dec58_dec58_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sv_in3 = dec62_dec62_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sv_in3 = dec22_dec22_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sv_in3 = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sv_out = dec19_dec19_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sv_out = dec30_dec30_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sv_out = dec31_dec31_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sv_out = dec58_dec58_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sv_out = dec62_dec62_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sv_out = dec22_dec22_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sv_out = 3'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sv_out2 = dec19_dec19_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sv_out2 = dec30_dec30_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sv_out2 = dec31_dec31_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sv_out2 = dec58_dec58_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sv_out2 = dec62_dec62_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sv_out2 = dec22_dec22_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sv_out2 = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sv_cr_in = dec19_dec19_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sv_cr_in = dec30_dec30_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sv_cr_in = dec31_dec31_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sv_cr_in = dec58_dec58_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sv_cr_in = dec62_dec62_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sv_cr_in = dec22_dec22_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sv_cr_in = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sv_cr_out = dec19_dec19_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sv_cr_out = dec30_dec30_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sv_cr_out = dec31_dec31_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sv_cr_out = dec58_dec58_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sv_cr_out = dec62_dec62_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sv_cr_out = dec22_dec22_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sv_cr_out = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + ldst_len = dec19_dec19_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + ldst_len = dec30_dec30_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + ldst_len = dec31_dec31_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + ldst_len = dec58_dec58_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + ldst_len = dec62_dec62_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + ldst_len = dec22_dec22_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + ldst_len = 4'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + upd = dec19_dec19_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + upd = dec30_dec30_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + upd = dec31_dec31_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + upd = dec58_dec58_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + upd = dec62_dec62_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + upd = dec22_dec22_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + upd = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + rc_sel = dec19_dec19_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + rc_sel = dec30_dec30_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + rc_sel = dec31_dec31_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + rc_sel = dec58_dec58_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + rc_sel = dec62_dec62_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + rc_sel = dec22_dec22_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + rc_sel = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + cry_in = dec19_dec19_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + cry_in = dec30_dec30_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + cry_in = dec31_dec31_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + cry_in = dec58_dec58_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + cry_in = dec62_dec62_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + cry_in = dec22_dec22_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + cry_in = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + inv_a = dec19_dec19_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + inv_a = dec30_dec30_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + inv_a = dec31_dec31_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + inv_a = dec58_dec58_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + inv_a = dec62_dec62_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + inv_a = dec22_dec22_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + inv_a = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + inv_out = dec19_dec19_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + inv_out = dec30_dec30_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + inv_out = dec31_dec31_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + inv_out = dec58_dec58_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + inv_out = dec62_dec62_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + inv_out = dec22_dec22_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + inv_out = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + cry_out = dec19_dec19_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + cry_out = dec30_dec30_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + cry_out = dec31_dec31_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + cry_out = dec58_dec58_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + cry_out = dec62_dec62_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + cry_out = dec22_dec22_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + cry_out = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + br = dec19_dec19_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + br = dec30_dec30_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + br = dec31_dec31_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + br = dec58_dec58_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + br = dec62_dec62_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + br = dec22_dec22_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + br = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sgn_ext = dec19_dec19_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sgn_ext = dec30_dec30_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sgn_ext = dec31_dec31_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sgn_ext = dec58_dec58_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sgn_ext = dec62_dec62_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sgn_ext = dec22_dec22_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sgn_ext = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + rsrv = dec19_dec19_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + rsrv = dec30_dec30_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + rsrv = dec31_dec31_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + rsrv = dec58_dec58_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + rsrv = dec62_dec62_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + rsrv = dec22_dec22_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + rsrv = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + is_32b = dec19_dec19_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + is_32b = dec30_dec30_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + is_32b = dec31_dec31_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + is_32b = dec58_dec58_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + is_32b = dec62_dec62_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + is_32b = dec22_dec22_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + is_32b = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sgn = dec19_dec19_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sgn = dec30_dec30_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sgn = dec31_dec31_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sgn = dec58_dec58_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sgn = dec62_dec62_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sgn = dec22_dec22_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sgn = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + lk = dec19_dec19_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + lk = dec30_dec30_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + lk = dec31_dec31_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + lk = dec58_dec58_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + lk = dec62_dec62_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + lk = dec22_dec22_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + lk = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + sgl_pipe = dec19_dec19_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + sgl_pipe = dec30_dec30_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + sgl_pipe = dec31_dec31_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + sgl_pipe = dec58_dec58_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + sgl_pipe = dec62_dec62_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + sgl_pipe = dec22_dec22_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + sgl_pipe = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + function_unit = dec19_dec19_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + function_unit = dec30_dec30_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + function_unit = dec31_dec31_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + function_unit = dec58_dec58_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + function_unit = dec62_dec62_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + function_unit = dec22_dec22_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + function_unit = 14'h0080; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + function_unit = 14'h0020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + function_unit = 14'h0020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + function_unit = 14'h0080; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + function_unit = 14'h0080; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + function_unit = 14'h0010; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + function_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + function_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + function_unit = 14'h0000; + endcase + end + always @* begin + if (\initial ) begin end + internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h13: + internal_op = dec19_dec19_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1e: + internal_op = dec30_dec30_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1f: + internal_op = dec31_dec31_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3a: + internal_op = dec58_dec58_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h3e: + internal_op = dec62_dec62_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h16: + internal_op = dec22_dec22_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0c: + internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0d: + internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0e: + internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0f: + internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h11: + internal_op = 7'h49; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1c: + internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1d: + internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h12: + internal_op = 7'h06; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h10: + internal_op = 7'h07; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0b: + internal_op = 7'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h0a: + internal_op = 7'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h22: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h23: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2a: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2b: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h28: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h29: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h20: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h21: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h07: + internal_op = 7'h32; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h18: + internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h19: + internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h14: + internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h15: + internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h17: + internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h26: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h27: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2c: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h2d: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h24: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h25: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h08: + internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h02: + internal_op = 7'h3f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h03: + internal_op = 7'h3f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1a: + internal_op = 7'h43; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 6'h1b: + internal_op = 7'h43; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (\opcode_switch$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000000???????????????0100000000?: + internal_op = 7'h05; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'd1610612736: + internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 32'b000001???????????????0000000011?: + internal_op = 7'h44; + endcase + end + assign VC_XO = opcode_in[9:0]; + assign VC_VRT = opcode_in[25:21]; + assign VC_VRB = opcode_in[15:11]; + assign VC_VRA = opcode_in[20:16]; + assign VC_Rc = opcode_in[10]; + assign XS_XO = opcode_in[10:2]; + assign XS_sh = { opcode_in[1], opcode_in[15:11] }; + assign XS_RS = opcode_in[25:21]; + assign XS_Rc = opcode_in[0]; + assign XS_RA = opcode_in[20:16]; + assign VA_XO = opcode_in[5:0]; + assign VA_VRT = opcode_in[25:21]; + assign VA_VRC = opcode_in[10:6]; + assign VA_VRB = opcode_in[15:11]; + assign VA_VRA = opcode_in[20:16]; + assign VA_SHB = opcode_in[9:6]; + assign VA_RT = opcode_in[25:21]; + assign VA_RC = opcode_in[10:6]; + assign VA_RB = opcode_in[15:11]; + assign VA_RA = opcode_in[20:16]; + assign TX_XO = opcode_in[6:1]; + assign TX_XBI = opcode_in[10:7]; + assign TX_UI = opcode_in[15:11]; + assign TX_RA = opcode_in[20:16]; + assign DQE_XO = opcode_in[1:0]; + assign DQE_RT = opcode_in[25:21]; + assign DQE_RA = opcode_in[20:16]; + assign all_PO = opcode_in[31:26]; + assign XO_XO = opcode_in[9:1]; + assign XO_RT = opcode_in[25:21]; + assign XO_Rc = opcode_in[0]; + assign XO_RB = opcode_in[15:11]; + assign XO_RA = opcode_in[20:16]; + assign XO_OE = opcode_in[10]; + assign SVL_XO = opcode_in[5:1]; + assign SVL_vs = opcode_in[7]; + assign SVL_SVi = opcode_in[15:8]; + assign SVL_RT = opcode_in[25:21]; + assign SVL_Rc = opcode_in[0]; + assign SVL_RA = opcode_in[20:16]; + assign SVL_ms = opcode_in[6]; + assign MD_XO = opcode_in[4:2]; + assign MD_sh = { opcode_in[1], opcode_in[15:11] }; + assign MD_RS = opcode_in[25:21]; + assign MD_Rc = opcode_in[0]; + assign MD_RA = opcode_in[20:16]; + assign MD_me = opcode_in[10:5]; + assign MD_mb = opcode_in[10:5]; + assign M_SH = opcode_in[15:11]; + assign M_RS = opcode_in[25:21]; + assign M_Rc = opcode_in[0]; + assign M_RB = opcode_in[15:11]; + assign M_RA = opcode_in[20:16]; + assign M_ME = opcode_in[5:1]; + assign M_MB = opcode_in[10:6]; + assign SC_XO_1 = opcode_in[1:0]; + assign SC_XO = opcode_in[1]; + assign SC_LEV = opcode_in[11:5]; + assign MDS_XO = opcode_in[4:1]; + assign MDS_XBI_1 = opcode_in[10:7]; + assign MDS_XBI = opcode_in[10:7]; + assign MDS_RS = opcode_in[25:21]; + assign MDS_Rc = opcode_in[0]; + assign MDS_RB = opcode_in[15:11]; + assign MDS_RA = opcode_in[20:16]; + assign MDS_me = opcode_in[10:5]; + assign MDS_mb = opcode_in[10:5]; + assign MDS_IS = opcode_in[25:21]; + assign MDS_IB = opcode_in[15:11]; + assign Z23_XO = opcode_in[8:1]; + assign Z23_TE = opcode_in[20:16]; + assign Z23_RMC = opcode_in[10:9]; + assign Z23_Rc = opcode_in[0]; + assign Z23_R = opcode_in[16]; + assign Z23_FRTp = opcode_in[25:21]; + assign Z23_FRT = opcode_in[25:21]; + assign Z23_FRBp = opcode_in[15:11]; + assign Z23_FRB = opcode_in[15:11]; + assign Z23_FRAp = opcode_in[20:16]; + assign Z23_FRA = opcode_in[20:16]; + assign XFL_XO = opcode_in[10:1]; + assign XFL_W = opcode_in[16]; + assign XFL_Rc = opcode_in[0]; + assign XFL_L = opcode_in[25]; + assign XFL_FRB = opcode_in[15:11]; + assign XFL_FLM = opcode_in[24:17]; + assign VX_XO_1 = opcode_in[10:0]; + assign VX_XO = { opcode_in[10], opcode_in[8:0] }; + assign VX_VRT = opcode_in[25:21]; + assign VX_VRB = opcode_in[15:11]; + assign VX_VRA = opcode_in[20:16]; + assign VX_UIM_3 = opcode_in[17:16]; + assign VX_UIM_2 = opcode_in[18:16]; + assign VX_UIM_1 = opcode_in[19:16]; + assign VX_UIM = opcode_in[20:16]; + assign VX_SIM = opcode_in[20:16]; + assign VX_RT = opcode_in[25:21]; + assign VX_RA = opcode_in[20:16]; + assign VX_PS = opcode_in[9]; + assign VX_EO = opcode_in[20:16]; + assign DS_XO = opcode_in[1:0]; + assign DS_VRT = opcode_in[25:21]; + assign DS_VRS = opcode_in[25:21]; + assign DS_RT = opcode_in[25:21]; + assign DS_RSp = opcode_in[25:21]; + assign DS_RS = opcode_in[25:21]; + assign DS_RA = opcode_in[20:16]; + assign DS_FRTp = opcode_in[25:21]; + assign DS_FRSp = opcode_in[25:21]; + assign DS_DS = opcode_in[15:2]; + assign DQ_XO = opcode_in[2:0]; + assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] }; + assign DQ_T = opcode_in[25:21]; + assign DQ_TX = opcode_in[3]; + assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] }; + assign DQ_S = opcode_in[25:21]; + assign DQ_SX = opcode_in[3]; + assign DQ_RTp = opcode_in[25:21]; + assign DQ_RA = opcode_in[20:16]; + assign DQ_PT = opcode_in[3:0]; + assign DQ_DQ = opcode_in[15:4]; + assign DX_XO = opcode_in[5:1]; + assign DX_RT = opcode_in[25:21]; + assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] }; + assign DX_d2 = opcode_in[0]; + assign DX_d1 = opcode_in[20:16]; + assign DX_d0 = opcode_in[15:6]; + assign XFX_XO = opcode_in[10:1]; + assign XFX_SPR = opcode_in[20:11]; + assign XFX_RT = opcode_in[25:21]; + assign XFX_RS = opcode_in[25:21]; + assign XFX_FXM = opcode_in[19:12]; + assign XFX_DUIS = opcode_in[20:11]; + assign XFX_DUI = opcode_in[25:21]; + assign XFX_BHRBE = opcode_in[20:11]; + assign EVS_BFA = opcode_in[2:0]; + assign Z22_XO = opcode_in[9:1]; + assign Z22_SH = opcode_in[15:10]; + assign Z22_Rc = opcode_in[0]; + assign Z22_FRTp = opcode_in[25:21]; + assign Z22_FRT = opcode_in[25:21]; + assign Z22_FRAp = opcode_in[20:16]; + assign Z22_FRA = opcode_in[20:16]; + assign Z22_DGM = opcode_in[15:10]; + assign Z22_DCM = opcode_in[15:10]; + assign Z22_BF = opcode_in[25:23]; + assign XX2_XO_1 = opcode_in[10:2]; + assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] }; + assign XX2_UIM_1 = opcode_in[17:16]; + assign XX2_UIM = opcode_in[19:16]; + assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX2_T = opcode_in[25:21]; + assign XX2_TX = opcode_in[0]; + assign XX2_RT = opcode_in[25:21]; + assign XX2_EO = opcode_in[20:16]; + assign XX2_DCMX = opcode_in[22:16]; + assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] }; + assign XX2_dx = opcode_in[20:16]; + assign XX2_dm = opcode_in[2]; + assign XX2_dc = opcode_in[6]; + assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX2_B = opcode_in[15:11]; + assign XX2_BX = opcode_in[1]; + assign XX2_BF = opcode_in[25:23]; + assign D_UI = opcode_in[15:0]; + assign D_TO = opcode_in[25:21]; + assign D_SI = opcode_in[15:0]; + assign D_RT = opcode_in[25:21]; + assign D_RS = opcode_in[25:21]; + assign D_RA = opcode_in[20:16]; + assign D_L = opcode_in[21]; + assign D_FRT = opcode_in[25:21]; + assign D_FRS = opcode_in[25:21]; + assign D_D = opcode_in[15:0]; + assign D_BF = opcode_in[25:23]; + assign A_XO = opcode_in[5:1]; + assign A_RT = opcode_in[25:21]; + assign A_Rc = opcode_in[0]; + assign A_RB = opcode_in[15:11]; + assign A_RA = opcode_in[20:16]; + assign A_FRT = opcode_in[25:21]; + assign A_FRC = opcode_in[10:6]; + assign A_FRB = opcode_in[15:11]; + assign A_FRA = opcode_in[20:16]; + assign A_BC = opcode_in[10:6]; + assign XL_XO = opcode_in[10:1]; + assign XL_S = opcode_in[11]; + assign XL_OC = opcode_in[25:11]; + assign XL_LK = opcode_in[0]; + assign XL_BT = opcode_in[25:21]; + assign XL_BO_1 = opcode_in[25:21]; + assign XL_BO = opcode_in[25:21]; + assign XL_BI = opcode_in[20:16]; + assign XL_BH = opcode_in[12:11]; + assign XL_BFA = opcode_in[20:18]; + assign XL_BF = opcode_in[25:23]; + assign XL_BB = opcode_in[15:11]; + assign XL_BA = opcode_in[20:16]; + assign XX4_XO = opcode_in[5:4]; + assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX4_T = opcode_in[25:21]; + assign XX4_TX = opcode_in[0]; + assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] }; + assign XX4_C = opcode_in[10:6]; + assign XX4_CX = opcode_in[3]; + assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX4_B = opcode_in[15:11]; + assign XX4_BX = opcode_in[1]; + assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX4_A = opcode_in[20:16]; + assign XX4_AX = opcode_in[2]; + assign XX3_XO_2 = opcode_in[9:1]; + assign XX3_XO_1 = opcode_in[10:3]; + assign XX3_XO = opcode_in[10:7]; + assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign XX3_T = opcode_in[25:21]; + assign XX3_TX = opcode_in[0]; + assign XX3_SHW = opcode_in[9:8]; + assign XX3_Rc = opcode_in[10]; + assign XX3_DM = opcode_in[9:8]; + assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] }; + assign XX3_B = opcode_in[15:11]; + assign XX3_BX = opcode_in[1]; + assign XX3_BF = opcode_in[25:23]; + assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] }; + assign XX3_A = opcode_in[20:16]; + assign XX3_AX = opcode_in[2]; + assign I_LK = opcode_in[0]; + assign I_LI = opcode_in[25:2]; + assign I_AA = opcode_in[1]; + assign B_LK = opcode_in[0]; + assign B_BO = opcode_in[25:21]; + assign B_BI = opcode_in[20:16]; + assign B_BD = opcode_in[15:2]; + assign B_AA = opcode_in[1]; + assign X_XO_1 = opcode_in[8:1]; + assign X_XO = opcode_in[10:1]; + assign X_WC = opcode_in[22:21]; + assign X_W = opcode_in[16]; + assign X_VRT = opcode_in[25:21]; + assign X_VRS = opcode_in[25:21]; + assign X_UIM = opcode_in[20:16]; + assign X_U = opcode_in[15:12]; + assign X_TX_T = { opcode_in[0], opcode_in[25:21] }; + assign X_TX = opcode_in[0]; + assign X_TO = opcode_in[25:21]; + assign X_TH = opcode_in[25:21]; + assign X_TBR = opcode_in[20:11]; + assign X_T = opcode_in[25:21]; + assign X_SX_S = { opcode_in[0], opcode_in[25:21] }; + assign X_SX = opcode_in[0]; + assign X_SR = opcode_in[19:16]; + assign X_SP = opcode_in[20:19]; + assign X_SI = opcode_in[15:11]; + assign X_SH = opcode_in[15:11]; + assign X_S = opcode_in[25:21]; + assign X_RTp = opcode_in[25:21]; + assign X_RT = opcode_in[25:21]; + assign X_RSp = opcode_in[25:21]; + assign X_RS = opcode_in[25:21]; + assign X_RO = opcode_in[0]; + assign X_RM = opcode_in[12:11]; + assign X_RIC = opcode_in[19:18]; + assign X_Rc = opcode_in[0]; + assign X_RB = opcode_in[15:11]; + assign X_RA = opcode_in[20:16]; + assign X_R_1 = opcode_in[16]; + assign X_R = opcode_in[21]; + assign X_PRS = opcode_in[17]; + assign X_NB = opcode_in[15:11]; + assign X_MO = opcode_in[25:21]; + assign X_L3 = opcode_in[17:16]; + assign X_L1 = opcode_in[16]; + assign X_L = opcode_in[21]; + assign X_L2 = opcode_in[22:21]; + assign X_IMM8 = opcode_in[18:11]; + assign X_IH = opcode_in[23:21]; + assign X_FRTp = opcode_in[25:21]; + assign X_FRT = opcode_in[25:21]; + assign X_FRSp = opcode_in[25:21]; + assign X_FRS = opcode_in[25:21]; + assign X_FRBp = opcode_in[15:11]; + assign X_FRB = opcode_in[15:11]; + assign X_FRAp = opcode_in[20:16]; + assign X_FRA = opcode_in[20:16]; + assign X_FC = opcode_in[15:11]; + assign X_EX = opcode_in[0]; + assign X_EO_1 = opcode_in[20:16]; + assign X_EO = opcode_in[20:19]; + assign X_E_1 = opcode_in[19:16]; + assign X_E = opcode_in[15]; + assign X_DRM = opcode_in[13:11]; + assign X_DCMX = opcode_in[22:16]; + assign X_CT = opcode_in[24:21]; + assign X_BO = opcode_in[25:21]; + assign X_BFA = opcode_in[20:18]; + assign X_BF = opcode_in[25:23]; + assign X_A = opcode_in[25]; + assign SPR = opcode_in[20:11]; + assign MB = opcode_in[10:6]; + assign ME = opcode_in[5:1]; + assign SH = opcode_in[15:11]; + assign BC = opcode_in[10:6]; + assign TO = opcode_in[25:21]; + assign DS = opcode_in[15:2]; + assign D = opcode_in[15:0]; + assign BH = opcode_in[12:11]; + assign BI = opcode_in[20:16]; + assign BO = opcode_in[25:21]; + assign FXM = opcode_in[19:12]; + assign BT = opcode_in[25:21]; + assign BA = opcode_in[20:16]; + assign BB = opcode_in[15:11]; + assign CR = opcode_in[10:1]; + assign BF = opcode_in[25:23]; + assign BD = opcode_in[15:2]; + assign OE = opcode_in[10]; + assign Rc = opcode_in[0]; + assign AA = opcode_in[1]; + assign LK = opcode_in[0]; + assign LI = opcode_in[25:2]; + assign ME32 = opcode_in[5:1]; + assign MB32 = opcode_in[10:6]; + assign sh = { opcode_in[1], opcode_in[15:11] }; + assign SH32 = opcode_in[15:11]; + assign L = opcode_in[21]; + assign UI = opcode_in[15:0]; + assign SI = opcode_in[15:0]; + assign RB = opcode_in[15:11]; + assign RA = opcode_in[20:16]; + assign RT = opcode_in[25:21]; + assign RS = opcode_in[25:21]; + assign PO = opcode_in[31:26]; + assign opcode_in = \$2 ; + assign \opcode_switch$1 = opcode_in; + assign dec22_opcode_in = opcode_in; + assign dec62_opcode_in = opcode_in; + assign dec58_opcode_in = opcode_in; + assign dec31_opcode_in = opcode_in; + assign dec30_opcode_in = opcode_in; + assign dec19_opcode_in = opcode_in; + assign opcode_switch = opcode_in[31:26]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec19" *) +(* generator = "nMigen" *) +module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, dec19_SV_Etype, dec19_SV_Ptype, dec19_in1_sel, dec19_in2_sel, dec19_in3_sel, dec19_out_sel, dec19_cr_in, dec19_cr_out, dec19_sv_in1, dec19_sv_in2, dec19_sv_in3, dec19_sv_out, dec19_sv_out2, dec19_sv_cr_in, dec19_sv_cr_out, dec19_ldst_len, dec19_upd, dec19_rc_sel, dec19_cry_in, dec19_inv_a, dec19_inv_out, dec19_cry_out, dec19_br, dec19_sgn_ext, dec19_rsrv, dec19_is_32b, dec19_sgn, dec19_lk, dec19_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec19_SV_Etype; + reg [1:0] dec19_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec19_SV_Ptype; + reg [1:0] dec19_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec19_asmcode; + reg [7:0] dec19_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_br; + reg dec19_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_cr_in; + reg [2:0] dec19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_cr_out; + reg [2:0] dec19_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec19_cry_in; + reg [1:0] dec19_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_cry_out; + reg dec19_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec19_form; + reg [4:0] dec19_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec19_function_unit; + reg [13:0] dec19_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_in1_sel; + reg [2:0] dec19_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec19_in2_sel; + reg [3:0] dec19_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec19_in3_sel; + reg [1:0] dec19_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec19_internal_op; + reg [6:0] dec19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_inv_a; + reg dec19_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_inv_out; + reg dec19_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_is_32b; + reg dec19_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec19_ldst_len; + reg [3:0] dec19_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_lk; + reg dec19_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_out_sel; + reg [2:0] dec19_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec19_rc_sel; + reg [1:0] dec19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_rsrv; + reg dec19_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_sgl_pipe; + reg dec19_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_sgn; + reg dec19_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec19_sgn_ext; + reg dec19_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_sv_cr_in; + reg [2:0] dec19_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_sv_cr_out; + reg [2:0] dec19_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_sv_in1; + reg [2:0] dec19_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_sv_in2; + reg [2:0] dec19_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_sv_in3; + reg [2:0] dec19_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_sv_out; + reg [2:0] dec19_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec19_sv_out2; + reg [2:0] dec19_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec19_upd; + reg [1:0] dec19_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec19_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_function_unit = 14'h0020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_function_unit = 14'h0020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_function_unit = 14'h0020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_function_unit = 14'h0080; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_function_unit = 14'h0080; + endcase + end + always @* begin + if (\initial ) begin end + dec19_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_cr_in = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_cr_in = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_cr_in = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_cr_in = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_cr_out = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sv_cr_in = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sv_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sv_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sv_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sv_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sv_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sv_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sv_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sv_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_internal_op = 7'h2a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_internal_op = 7'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_internal_op = 7'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_internal_op = 7'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_internal_op = 7'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_internal_op = 7'h24; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_internal_op = 7'h46; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_internal_op = 7'h46; + endcase + end + always @* begin + if (\initial ) begin end + dec19_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_asmcode = 8'h6c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_asmcode = 8'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_asmcode = 8'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_asmcode = 8'h27; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_asmcode = 8'h28; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_asmcode = 8'h29; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_asmcode = 8'h2a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_asmcode = 8'h2b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_asmcode = 8'h2c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_asmcode = 8'h16; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_asmcode = 8'h17; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_asmcode = 8'h18; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_asmcode = 8'h4c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_asmcode = 8'h91; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_asmcode = 8'h48; + endcase + end + always @* begin + if (\initial ) begin end + dec19_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_form = 5'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_form = 5'h09; + endcase + end + always @* begin + if (\initial ) begin end + dec19_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_SV_Etype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_SV_Ptype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_in1_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_in1_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_in1_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_in1_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_in1_sel = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec19_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_in2_sel = 4'hc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_in2_sel = 4'hc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_in2_sel = 4'hc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_in2_sel = 4'hc; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_in2_sel = 4'hc; + endcase + end + always @* begin + if (\initial ) begin end + dec19_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec19_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h000: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h101: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h081: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h121: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0e1: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h021: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1c1: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h1a1: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h0c1: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h210: + dec19_out_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h010: + dec19_out_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h230: + dec19_out_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h096: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h012: + dec19_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 10'h112: + dec19_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2" *) +(* generator = "nMigen" *) +module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, msr, cia, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, \exc_$signal , \exc_$signal$3 , \exc_$signal$4 , \exc_$signal$5 , \exc_$signal$6 , \exc_$signal$7 , \exc_$signal$8 , \exc_$signal$9 , trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, sv_a_nz, cur_eint); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) + wire \$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) + wire \$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) + wire \$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) + wire \$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" *) + wire \$114 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" *) + wire \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" *) + wire \$118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" *) + wire \$120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + output [7:0] asmcode; + reg [7:0] asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + output [63:0] cia; + reg [63:0] cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] cr_in1; + reg [6:0] cr_in1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_in1_ok; + reg cr_in1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] cr_in2; + reg [6:0] cr_in2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] \cr_in2$1 ; + reg [6:0] \cr_in2$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_in2_ok; + reg cr_in2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_in2_ok$2 ; + reg \cr_in2_ok$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] cr_out; + reg [6:0] cr_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_out_ok; + reg cr_out_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [7:0] cr_rd; + reg [7:0] cr_rd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_rd_ok; + reg cr_rd_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [7:0] cr_wr; + reg [7:0] cr_wr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_wr_ok; + reg cr_wr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + input [63:0] cur_dec; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + input cur_eint; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + input [63:0] cur_msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + input [63:0] cur_pc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [7:0] dec_FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [4:0] dec_XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [9:0] dec_XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] dec_X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + wire [2:0] dec_X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec_a_fast_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_a_fast_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [4:0] dec_a_reg_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_a_reg_a_ok; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" *) + wire [2:0] dec_a_sel_in; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [9:0] dec_a_spr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_a_spr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" *) + wire dec_a_sv_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec_b_fast_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_b_fast_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec_b_reg_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_b_reg_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" *) + wire [3:0] dec_b_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [4:0] dec_c_reg_c; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_c_reg_c_ok; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" *) + wire [1:0] dec_c_sel_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_cr_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec_cr_in_cr_bitfield; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec_cr_in_cr_bitfield_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_cr_in_cr_bitfield_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec_cr_in_cr_bitfield_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_cr_in_cr_bitfield_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_cr_in_cr_bitfield_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [7:0] dec_cr_in_cr_fxm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_cr_in_cr_fxm_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" *) + wire [31:0] dec_cr_in_insn_in; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" *) + wire [2:0] dec_cr_in_sel_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_cr_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec_cr_out_cr_bitfield; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_cr_out_cr_bitfield_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [7:0] dec_cr_out_cr_fxm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_cr_out_cr_fxm_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" *) + wire [31:0] dec_cr_out_insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" *) + wire dec_cr_out_rc_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" *) + wire [2:0] dec_cr_out_sel_in; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_cry_in; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1244" *) + wire dec_irq_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_is_32b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec_o2_fast_o2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_o2_fast_o2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" *) + wire dec_o2_lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [4:0] dec_o2_reg_o2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_o2_reg_o2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec_o_fast_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_o_fast_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [4:0] dec_o_reg_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_o_reg_o_ok; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" *) + wire [2:0] dec_o_sel_in; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [9:0] dec_o_spr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_o_spr_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_out_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_rc_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] ea; + reg [6:0] ea; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output ea_ok; + reg ea_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \exc_$signal ; + reg \exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \exc_$signal$3 ; + reg \exc_$signal$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \exc_$signal$4 ; + reg \exc_$signal$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \exc_$signal$5 ; + reg \exc_$signal$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \exc_$signal$6 ; + reg \exc_$signal$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \exc_$signal$7 ; + reg \exc_$signal$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \exc_$signal$8 ; + reg \exc_$signal$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \exc_$signal$9 ; + reg \exc_$signal$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1243" *) + wire ext_irq_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fast1; + reg [2:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + reg fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fast2; + reg [2:0] fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + reg fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fasto1; + reg [2:0] fasto1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fasto1_ok; + reg fasto1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fasto2; + reg [2:0] fasto2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fasto2_ok; + reg fasto2_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + output [13:0] fn_unit; + reg [13:0] fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1246" *) + wire illeg_ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + output [1:0] input_carry; + reg [1:0] input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + output [31:0] insn; + reg [31:0] insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" *) + wire [31:0] \insn_in$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" *) + wire [31:0] \insn_in$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" *) + wire [31:0] \insn_in$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" *) + wire [31:0] \insn_in$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" *) + wire [31:0] \insn_in$89 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + output [6:0] insn_type; + reg [6:0] insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + output is_32bit; + reg is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" *) + reg is_priv_insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + output lk; + reg lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + output [63:0] msr; + reg [63:0] msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe; + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe_ok; + reg oe_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1245" *) + wire priv_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc; + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc_ok; + reg rc_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] reg1; + reg [6:0] reg1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output reg1_ok; + reg reg1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] reg2; + reg [6:0] reg2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output reg2_ok; + reg reg2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] reg3; + reg [6:0] reg3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output reg3_ok; + reg reg3_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] rego; + reg [6:0] rego; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rego_ok; + reg rego_ok; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:415" *) + wire [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [9:0] spr1; + reg [9:0] spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr1_ok; + reg spr1_ok; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [9:0] spro; + reg [9:0] spro; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spro_ok; + reg spro_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + input sv_a_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + wire [7:0] tmp_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] tmp_cr_in1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_cr_in1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] tmp_cr_in2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \tmp_cr_in2$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_cr_in2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \tmp_cr_in2_ok$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] tmp_cr_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_cr_out_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] tmp_ea; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_ea_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] tmp_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] tmp_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] tmp_fasto1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_fasto1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] tmp_fasto2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_fasto2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] tmp_reg1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_reg1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] tmp_reg2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_reg2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] tmp_reg3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_reg3_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] tmp_rego; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_rego_ok; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [9:0] tmp_spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_spr1_ok; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [9:0] tmp_spro; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_spro_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + wire [63:0] tmp_tmp_cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [7:0] tmp_tmp_cr_rd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_tmp_cr_rd_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [7:0] tmp_tmp_cr_wr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_tmp_cr_wr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \tmp_tmp_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \tmp_tmp_exc_$signal$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \tmp_tmp_exc_$signal$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \tmp_tmp_exc_$signal$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \tmp_tmp_exc_$signal$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \tmp_tmp_exc_$signal$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \tmp_tmp_exc_$signal$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \tmp_tmp_exc_$signal$27 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + reg [13:0] tmp_tmp_fn_unit; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + wire [1:0] tmp_tmp_input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + wire [31:0] tmp_tmp_insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + reg [6:0] tmp_tmp_insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + wire tmp_tmp_is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + reg tmp_tmp_lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + wire [63:0] tmp_tmp_msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_tmp_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_tmp_oe_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_tmp_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire tmp_tmp_rc_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + reg [12:0] tmp_tmp_trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + wire [7:0] tmp_tmp_traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + reg [2:0] tmp_xer_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + reg tmp_xer_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + output [12:0] trapaddr; + reg [12:0] trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + output [7:0] traptype; + reg [7:0] traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + output [2:0] xer_in; + reg [2:0] xer_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + output xer_out; + reg xer_out; + assign \$100 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_b; + assign \$102 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_o; + assign \$104 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_out_cr_bitfield; + assign \$106 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) 7'h2e; + assign \$108 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) 7'h0a; + assign \$110 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) 7'h31; + assign \$112 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) 7'h3f; + assign \$114 = cur_eint & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" *) cur_msr[15]; + assign \$116 = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" *) cur_msr[15]; + assign \$118 = is_priv_insn & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" *) cur_msr[14]; + assign \$120 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" *) 7'h00; + assign \$28 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" *) 7'h3f; + assign \$30 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) 7'h49; + assign \$32 = \$28 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) \$30 ; + assign \$34 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) 7'h46; + assign \$37 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$39 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$37 ; + assign \$41 = \$39 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$43 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$45 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$43 ; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$49 = \$45 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$47 ; + assign \$51 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$53 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$55 = \$51 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$53 ; + assign \$57 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$59 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$61 = \$57 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$59 ; + assign \$63 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$65 = \$61 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$63 ; + assign \$67 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$69 = \$65 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$67 ; + assign \$71 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$73 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$71 ; + assign \$75 = \$73 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$77 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$79 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$77 ; + assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$83 = \$79 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$81 ; + assign \$90 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_a_reg_a; + assign \$92 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_c_reg_c; + assign \$94 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_o_reg_o; + assign \$96 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_o2_reg_o2; + assign \$98 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield; + \dec$171 dec ( + .BA(dec_BA), + .BB(dec_BB), + .BC(dec_BC), + .BI(dec_BI), + .BO(dec_BO), + .BT(dec_BT), + .FXM(dec_FXM), + .LK(dec_LK), + .OE(dec_OE), + .RA(dec_RA), + .RB(dec_RB), + .RS(dec_RS), + .RT(dec_RT), + .Rc(dec_Rc), + .SPR(dec_SPR), + .XL_BT(dec_XL_BT), + .XL_XO(dec_XL_XO), + .X_BF(dec_X_BF), + .X_BFA(dec_X_BFA), + .asmcode(dec_asmcode), + .bigendian(bigendian), + .cr_in(dec_cr_in), + .cr_out(dec_cr_out), + .cry_in(dec_cry_in), + .function_unit(dec_function_unit), + .in1_sel(dec_in1_sel), + .in2_sel(dec_in2_sel), + .in3_sel(dec_in3_sel), + .internal_op(dec_internal_op), + .is_32b(dec_is_32b), + .lk(dec_lk), + .opcode_in(dec_opcode_in), + .out_sel(dec_out_sel), + .raw_opcode_in(raw_opcode_in), + .rc_sel(dec_rc_sel), + .upd(dec_upd) + ); + dec_a dec_a ( + .BO(dec_BO), + .RA(dec_RA), + .RS(dec_RS), + .SPR(dec_SPR), + .XL_XO(dec_XL_XO), + .fast_a(dec_a_fast_a), + .fast_a_ok(dec_a_fast_a_ok), + .internal_op(dec_internal_op), + .reg_a(dec_a_reg_a), + .reg_a_ok(dec_a_reg_a_ok), + .sel_in(dec_a_sel_in), + .spr_a(dec_a_spr_a), + .spr_a_ok(dec_a_spr_a_ok), + .sv_nz(dec_a_sv_nz) + ); + dec_b dec_b ( + .RB(dec_RB), + .RS(dec_RS), + .XL_XO(dec_XL_XO), + .fast_b(dec_b_fast_b), + .fast_b_ok(dec_b_fast_b_ok), + .internal_op(dec_internal_op), + .reg_b(dec_b_reg_b), + .reg_b_ok(dec_b_reg_b_ok), + .sel_in(dec_b_sel_in) + ); + dec_c dec_c ( + .RB(dec_RB), + .RS(dec_RS), + .reg_c(dec_c_reg_c), + .reg_c_ok(dec_c_reg_c_ok), + .sel_in(dec_c_sel_in) + ); + dec_cr_in \dec_cr_in$10 ( + .BA(dec_BA), + .BB(dec_BB), + .BC(dec_BC), + .BI(dec_BI), + .BT(dec_BT), + .FXM(dec_FXM), + .X_BFA(dec_X_BFA), + .cr_bitfield(dec_cr_in_cr_bitfield), + .cr_bitfield_b(dec_cr_in_cr_bitfield_b), + .cr_bitfield_b_ok(dec_cr_in_cr_bitfield_b_ok), + .cr_bitfield_o(dec_cr_in_cr_bitfield_o), + .cr_bitfield_o_ok(dec_cr_in_cr_bitfield_o_ok), + .cr_bitfield_ok(dec_cr_in_cr_bitfield_ok), + .cr_fxm(dec_cr_in_cr_fxm), + .cr_fxm_ok(dec_cr_in_cr_fxm_ok), + .insn_in(dec_cr_in_insn_in), + .internal_op(dec_internal_op), + .sel_in(dec_cr_in_sel_in) + ); + dec_cr_out \dec_cr_out$11 ( + .FXM(dec_FXM), + .XL_BT(dec_XL_BT), + .X_BF(dec_X_BF), + .cr_bitfield(dec_cr_out_cr_bitfield), + .cr_bitfield_ok(dec_cr_out_cr_bitfield_ok), + .cr_fxm(dec_cr_out_cr_fxm), + .cr_fxm_ok(dec_cr_out_cr_fxm_ok), + .insn_in(dec_cr_out_insn_in), + .internal_op(dec_internal_op), + .rc_in(dec_cr_out_rc_in), + .sel_in(dec_cr_out_sel_in) + ); + dec_o dec_o ( + .BO(dec_BO), + .RA(dec_RA), + .RT(dec_RT), + .SPR(dec_SPR), + .fast_o(dec_o_fast_o), + .fast_o_ok(dec_o_fast_o_ok), + .internal_op(dec_internal_op), + .reg_o(dec_o_reg_o), + .reg_o_ok(dec_o_reg_o_ok), + .sel_in(dec_o_sel_in), + .spr_o(dec_o_spr_o), + .spr_o_ok(dec_o_spr_o_ok) + ); + dec_o2 dec_o2 ( + .RA(dec_RA), + .fast_o2(dec_o2_fast_o2), + .fast_o2_ok(dec_o2_fast_o2_ok), + .internal_op(dec_internal_op), + .lk(dec_o2_lk), + .reg_o2(dec_o2_reg_o2), + .reg_o2_ok(dec_o2_reg_o2_ok), + .upd(dec_upd) + ); + \dec_oe$173 dec_oe ( + .OE(dec_OE), + .internal_op(dec_internal_op), + .oe(dec_oe_oe), + .oe_ok(dec_oe_oe_ok), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$172 dec_rc ( + .Rc(dec_Rc), + .rc(dec_rc_rc), + .rc_ok(dec_rc_rc_ok), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$83 , \$75 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + tmp_tmp_fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + tmp_tmp_fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + tmp_tmp_fn_unit = dec_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + tmp_tmp_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" *) + casez (dec_lk) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" */ + 1'h1: + tmp_tmp_lk = dec_LK; + endcase + end + always @* begin + if (\initial ) begin end + tmp_tmp_insn_type = dec_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$49 , \$41 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + tmp_tmp_insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + tmp_tmp_insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + tmp_xer_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) + casez (\$106 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" */ + 1'h1: + tmp_xer_in = 3'h7; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) + casez (\$108 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" */ + 1'h1: + tmp_xer_in = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + tmp_xer_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) + casez (\$110 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" */ + 1'h1: + tmp_xer_out = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + tmp_tmp_trapaddr = 13'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) + casez (\$112 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" */ + 1'h1: + tmp_tmp_trapaddr = 13'h0070; + endcase + end + always @* begin + if (\initial ) begin end + is_priv_insn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54" *) + casez (dec_internal_op) + /* \nmigen.decoding = "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" */ + 7'h05, 7'h47, 7'h48, 7'h4a, 7'h46: + is_priv_insn = 1'h1; + /* \nmigen.decoding = "OP_TLBIE/75" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58" */ + 7'h4b: + is_priv_insn = 1'h1; + /* \nmigen.decoding = "OP_MFSPR/46|OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" */ + 7'h2e, 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" *) + casez (tmp_tmp_insn[20]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" */ + 1'h1: + is_priv_insn = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" *) + casez ({ illeg_ok, priv_ok, ext_irq_ok, dec_irq_ok, \dec2_exc_$signal }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" */ + 5'b????1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" *) + casez ({ \dec2_exc_$signal$13 , \dec2_exc_$signal$12 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" */ + 2'b?1: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0060; + traptype = 8'h02; + msr = cur_msr; + cia = cur_pc; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1259" */ + 2'b1?: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" *) + casez (\dec2_exc_$signal$14 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" */ + 1'h1: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0048; + traptype = 8'h02; + msr = cur_msr; + cia = cur_pc; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1262" */ + default: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0040; + traptype = 8'h40; + { \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal } = { \dec2_exc_$signal$14 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal$15 , \dec2_exc_$signal$13 , \dec2_exc_$signal$12 , \dec2_exc_$signal }; + msr = cur_msr; + cia = cur_pc; + end + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1265" */ + default: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" *) + casez (\dec2_exc_$signal$14 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" */ + 1'h1: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0038; + traptype = 8'h02; + msr = cur_msr; + cia = cur_pc; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1268" */ + default: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0030; + traptype = 8'h02; + msr = cur_msr; + cia = cur_pc; + end + endcase + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" */ + 5'b???1?: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0090; + traptype = 8'h20; + msr = cur_msr; + cia = cur_pc; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1276" */ + 5'b??1??: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0050; + traptype = 8'h10; + msr = cur_msr; + cia = cur_pc; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1280" */ + 5'b?1???: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0070; + traptype = 8'h02; + msr = cur_msr; + cia = cur_pc; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1287" */ + 5'h1?: + begin + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + insn = dec_opcode_in; + insn_type = 7'h3f; + fn_unit = 14'h0080; + trapaddr = 13'h0070; + traptype = 8'h80; + msr = cur_msr; + cia = cur_pc; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1292" */ + default: + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, \tmp_tmp_exc_$signal$27 , \tmp_tmp_exc_$signal$26 , \tmp_tmp_exc_$signal$25 , \tmp_tmp_exc_$signal$24 , \tmp_tmp_exc_$signal$23 , \tmp_tmp_exc_$signal$22 , \tmp_tmp_exc_$signal$21 , \tmp_tmp_exc_$signal , tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_cia, tmp_tmp_msr, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$20 , \tmp_cr_in2$19 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + casez (\$32 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" */ + 1'h1: + begin + fasto1 = 3'h3; + fasto1_ok = 1'h1; + fasto2 = 3'h4; + fasto2_ok = 1'h1; + end + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) + casez (\$34 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" */ + 1'h1: + begin + fast1 = 3'h3; + fast1_ok = 1'h1; + fast2 = 3'h4; + fast2_ok = 1'h1; + end + endcase + begin + asmcode = dec_asmcode; + end + end + assign \dec2_exc_$signal = 1'h0; + assign \dec2_exc_$signal$12 = 1'h0; + assign \dec2_exc_$signal$13 = 1'h0; + assign \dec2_exc_$signal$14 = 1'h0; + assign \dec2_exc_$signal$15 = 1'h0; + assign \dec2_exc_$signal$16 = 1'h0; + assign \dec2_exc_$signal$17 = 1'h0; + assign \dec2_exc_$signal$18 = 1'h0; + assign tmp_asmcode = 8'h00; + assign tmp_tmp_traptype = 8'h00; + assign \tmp_tmp_exc_$signal = 1'h0; + assign \tmp_tmp_exc_$signal$21 = 1'h0; + assign \tmp_tmp_exc_$signal$22 = 1'h0; + assign \tmp_tmp_exc_$signal$23 = 1'h0; + assign \tmp_tmp_exc_$signal$24 = 1'h0; + assign \tmp_tmp_exc_$signal$25 = 1'h0; + assign \tmp_tmp_exc_$signal$26 = 1'h0; + assign \tmp_tmp_exc_$signal$27 = 1'h0; + assign illeg_ok = \$120 ; + assign priv_ok = \$118 ; + assign dec_irq_ok = \$116 ; + assign ext_irq_ok = \$114 ; + assign { tmp_fasto2_ok, tmp_fasto2 } = { dec_o2_fast_o2_ok, dec_o2_fast_o2 }; + assign { tmp_fasto1_ok, tmp_fasto1 } = { dec_o_fast_o_ok, dec_o_fast_o }; + assign { tmp_fast2_ok, tmp_fast2 } = { dec_b_fast_b_ok, dec_b_fast_b }; + assign { tmp_fast1_ok, tmp_fast1 } = { dec_a_fast_a_ok, dec_a_fast_a }; + assign { tmp_spro_ok, tmp_spro } = { dec_o_spr_o_ok, dec_o_spr_o }; + assign { tmp_spr1_ok, tmp_spr1 } = { dec_a_spr_a_ok, dec_a_spr_a }; + assign tmp_cr_out_ok = dec_cr_out_cr_bitfield_ok; + assign tmp_cr_out = \$104 ; + assign \tmp_cr_in2_ok$20 = dec_cr_in_cr_bitfield_o_ok; + assign \tmp_cr_in2$19 = \$102 ; + assign tmp_cr_in2_ok = dec_cr_in_cr_bitfield_b_ok; + assign tmp_cr_in2 = \$100 ; + assign tmp_cr_in1_ok = dec_cr_in_cr_bitfield_ok; + assign tmp_cr_in1 = \$98 ; + assign tmp_ea_ok = dec_o2_reg_o2_ok; + assign tmp_ea = \$96 ; + assign tmp_rego_ok = dec_o_reg_o_ok; + assign tmp_rego = \$94 ; + assign tmp_reg3_ok = dec_c_reg_c_ok; + assign tmp_reg3 = \$92 ; + assign tmp_reg2_ok = dec_b_reg_b_ok; + assign tmp_reg2 = dec_b_reg_b; + assign tmp_reg1_ok = dec_a_reg_a_ok; + assign tmp_reg1 = \$90 ; + assign dec_o2_lk = tmp_tmp_lk; + assign sel_in = dec_out_sel; + assign dec_o_sel_in = dec_out_sel; + assign dec_c_sel_in = dec_in3_sel; + assign dec_b_sel_in = dec_in2_sel; + assign dec_a_sel_in = dec_in1_sel; + assign { tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr } = { dec_cr_out_cr_fxm_ok, dec_cr_out_cr_fxm }; + assign { tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd } = { dec_cr_in_cr_fxm_ok, dec_cr_in_cr_fxm }; + assign dec_cr_out_rc_in = dec_rc_rc; + assign dec_cr_out_sel_in = dec_cr_out; + assign dec_cr_in_sel_in = dec_cr_in; + assign \insn_in$89 = dec_opcode_in; + assign \insn_in$88 = dec_opcode_in; + assign \insn_in$87 = dec_opcode_in; + assign dec_cr_out_insn_in = dec_opcode_in; + assign dec_cr_in_insn_in = dec_opcode_in; + assign \insn_in$86 = dec_opcode_in; + assign \insn_in$85 = dec_opcode_in; + assign tmp_tmp_insn = dec_opcode_in; + assign dec_a_sv_nz = sv_a_nz; + assign tmp_tmp_is_32bit = dec_is_32b; + assign tmp_tmp_input_carry = dec_cry_in; + assign { tmp_tmp_oe_ok, tmp_tmp_oe } = { dec_oe_oe_ok, dec_oe_oe }; + assign { tmp_tmp_rc_ok, tmp_tmp_rc } = { dec_rc_rc_ok, dec_rc_rc }; + assign is_mmu_spr = \$69 ; + assign is_spr_mv = \$55 ; + assign spr = { dec_SPR[4:0], dec_SPR[9:5] }; + assign tmp_tmp_cia = cur_pc; + assign tmp_tmp_msr = cur_msr; + assign dec_oe_sel_in = dec_rc_sel; + assign dec_rc_sel_in = dec_rc_sel; + assign \insn_in$36 = dec_opcode_in; + assign insn_in = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec22" *) +(* generator = "nMigen" *) +module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, dec22_SV_Etype, dec22_SV_Ptype, dec22_in1_sel, dec22_in2_sel, dec22_in3_sel, dec22_out_sel, dec22_cr_in, dec22_cr_out, dec22_sv_in1, dec22_sv_in2, dec22_sv_in3, dec22_sv_out, dec22_sv_out2, dec22_sv_cr_in, dec22_sv_cr_out, dec22_ldst_len, dec22_upd, dec22_rc_sel, dec22_cry_in, dec22_inv_a, dec22_inv_out, dec22_cry_out, dec22_br, dec22_sgn_ext, dec22_rsrv, dec22_is_32b, dec22_sgn, dec22_lk, dec22_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec22_SV_Etype; + reg [1:0] dec22_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec22_SV_Ptype; + reg [1:0] dec22_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec22_asmcode; + reg [7:0] dec22_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_br; + reg dec22_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_cr_in; + reg [2:0] dec22_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_cr_out; + reg [2:0] dec22_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec22_cry_in; + reg [1:0] dec22_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_cry_out; + reg dec22_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec22_form; + reg [4:0] dec22_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec22_function_unit; + reg [13:0] dec22_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_in1_sel; + reg [2:0] dec22_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec22_in2_sel; + reg [3:0] dec22_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec22_in3_sel; + reg [1:0] dec22_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec22_internal_op; + reg [6:0] dec22_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_inv_a; + reg dec22_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_inv_out; + reg dec22_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_is_32b; + reg dec22_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec22_ldst_len; + reg [3:0] dec22_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_lk; + reg dec22_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_out_sel; + reg [2:0] dec22_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec22_rc_sel; + reg [1:0] dec22_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_rsrv; + reg dec22_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_sgl_pipe; + reg dec22_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_sgn; + reg dec22_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec22_sgn_ext; + reg dec22_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_sv_cr_in; + reg [2:0] dec22_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_sv_cr_out; + reg [2:0] dec22_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_sv_in1; + reg [2:0] dec22_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_sv_in2; + reg [2:0] dec22_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_sv_in3; + reg [2:0] dec22_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_sv_out; + reg [2:0] dec22_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec22_sv_out2; + reg [2:0] dec22_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec22_upd; + reg [1:0] dec22_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [3:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec22_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_function_unit = 14'h2000; + endcase + end + always @* begin + if (\initial ) begin end + dec22_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_internal_op = 7'h4c; + endcase + end + always @* begin + if (\initial ) begin end + dec22_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec22_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_asmcode = 8'h9c; + endcase + end + always @* begin + if (\initial ) begin end + dec22_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_form = 5'h1d; + endcase + end + always @* begin + if (\initial ) begin end + dec22_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_SV_Etype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_SV_Ptype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec22_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec22_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec22_out_sel = 3'h4; + endcase + end + assign opcode_switch = opcode_in[4:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec30" *) +(* generator = "nMigen" *) +module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, dec30_SV_Etype, dec30_SV_Ptype, dec30_in1_sel, dec30_in2_sel, dec30_in3_sel, dec30_out_sel, dec30_cr_in, dec30_cr_out, dec30_sv_in1, dec30_sv_in2, dec30_sv_in3, dec30_sv_out, dec30_sv_out2, dec30_sv_cr_in, dec30_sv_cr_out, dec30_ldst_len, dec30_upd, dec30_rc_sel, dec30_cry_in, dec30_inv_a, dec30_inv_out, dec30_cry_out, dec30_br, dec30_sgn_ext, dec30_rsrv, dec30_is_32b, dec30_sgn, dec30_lk, dec30_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec30_SV_Etype; + reg [1:0] dec30_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec30_SV_Ptype; + reg [1:0] dec30_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec30_asmcode; + reg [7:0] dec30_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_br; + reg dec30_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_cr_in; + reg [2:0] dec30_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_cr_out; + reg [2:0] dec30_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec30_cry_in; + reg [1:0] dec30_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_cry_out; + reg dec30_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec30_form; + reg [4:0] dec30_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec30_function_unit; + reg [13:0] dec30_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_in1_sel; + reg [2:0] dec30_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec30_in2_sel; + reg [3:0] dec30_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec30_in3_sel; + reg [1:0] dec30_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec30_internal_op; + reg [6:0] dec30_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_inv_a; + reg dec30_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_inv_out; + reg dec30_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_is_32b; + reg dec30_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec30_ldst_len; + reg [3:0] dec30_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_lk; + reg dec30_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_out_sel; + reg [2:0] dec30_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec30_rc_sel; + reg [1:0] dec30_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_rsrv; + reg dec30_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_sgl_pipe; + reg dec30_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_sgn; + reg dec30_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec30_sgn_ext; + reg dec30_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_sv_cr_in; + reg [2:0] dec30_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_sv_cr_out; + reg [2:0] dec30_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_sv_in1; + reg [2:0] dec30_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_sv_in2; + reg [2:0] dec30_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_sv_in3; + reg [2:0] dec30_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_sv_out; + reg [2:0] dec30_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec30_sv_out2; + reg [2:0] dec30_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec30_upd; + reg [1:0] dec30_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [3:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec30_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + dec30_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sv_in2 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sv_in3 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec30_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_internal_op = 7'h39; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_internal_op = 7'h39; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_internal_op = 7'h3a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_internal_op = 7'h3a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_internal_op = 7'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_internal_op = 7'h39; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_internal_op = 7'h3a; + endcase + end + always @* begin + if (\initial ) begin end + dec30_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec30_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_asmcode = 8'h94; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_asmcode = 8'h94; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_asmcode = 8'h95; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_asmcode = 8'h95; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_asmcode = 8'h96; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_asmcode = 8'h96; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_asmcode = 8'h97; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_asmcode = 8'h97; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_asmcode = 8'h92; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_asmcode = 8'h93; + endcase + end + always @* begin + if (\initial ) begin end + dec30_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_form = 5'h14; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_form = 5'h14; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_form = 5'h15; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_form = 5'h15; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_form = 5'h14; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_form = 5'h14; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_form = 5'h14; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_form = 5'h14; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_form = 5'h14; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_form = 5'h14; + endcase + end + always @* begin + if (\initial ) begin end + dec30_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec30_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_SV_Ptype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec30_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec30_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec30_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_in3_sel = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec30_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h4: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h5: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h0: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h1: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h2: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h3: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h6: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h7: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h8: + dec30_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 4'h9: + dec30_out_sel = 3'h2; + endcase + end + assign opcode_switch = opcode_in[4:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31" *) +(* generator = "nMigen" *) +module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, dec31_SV_Etype, dec31_SV_Ptype, dec31_in1_sel, dec31_in2_sel, dec31_in3_sel, dec31_out_sel, dec31_cr_in, dec31_cr_out, dec31_sv_in1, dec31_sv_in2, dec31_sv_in3, dec31_sv_out, dec31_sv_out2, dec31_sv_cr_in, dec31_sv_cr_out, dec31_ldst_len, dec31_upd, dec31_rc_sel, dec31_cry_in, dec31_inv_a, dec31_inv_out, dec31_cry_out, dec31_br, dec31_sgn_ext, dec31_rsrv, dec31_is_32b, dec31_sgn, dec31_lk, dec31_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_SV_Etype; + reg [1:0] dec31_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_SV_Ptype; + reg [1:0] dec31_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_asmcode; + reg [7:0] dec31_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_br; + reg dec31_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_cr_in; + reg [2:0] dec31_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_cr_out; + reg [2:0] dec31_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_cry_in; + reg [1:0] dec31_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_cry_out; + reg dec31_cry_out; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub0_dec31_dec_sub0_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub0_dec31_dec_sub0_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub0_dec31_dec_sub0_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub0_dec31_dec_sub0_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub0_dec31_dec_sub0_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub0_dec31_dec_sub0_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub0_dec31_dec_sub0_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub0_dec31_dec_sub0_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub0_dec31_dec_sub0_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub0_dec31_dec_sub0_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub0_dec31_dec_sub0_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub0_dec31_dec_sub0_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub0_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub10_dec31_dec_sub10_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub10_dec31_dec_sub10_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub10_dec31_dec_sub10_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub10_dec31_dec_sub10_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub10_dec31_dec_sub10_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub10_dec31_dec_sub10_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub10_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub11_dec31_dec_sub11_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub11_dec31_dec_sub11_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub11_dec31_dec_sub11_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub11_dec31_dec_sub11_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub11_dec31_dec_sub11_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub11_dec31_dec_sub11_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub11_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub15_dec31_dec_sub15_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub15_dec31_dec_sub15_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub15_dec31_dec_sub15_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub15_dec31_dec_sub15_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub15_dec31_dec_sub15_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub15_dec31_dec_sub15_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub15_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub16_dec31_dec_sub16_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub16_dec31_dec_sub16_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub16_dec31_dec_sub16_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub16_dec31_dec_sub16_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub16_dec31_dec_sub16_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub16_dec31_dec_sub16_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub16_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub18_dec31_dec_sub18_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub18_dec31_dec_sub18_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub18_dec31_dec_sub18_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub18_dec31_dec_sub18_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub18_dec31_dec_sub18_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub18_dec31_dec_sub18_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub18_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub19_dec31_dec_sub19_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub19_dec31_dec_sub19_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub19_dec31_dec_sub19_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub19_dec31_dec_sub19_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub19_dec31_dec_sub19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub19_dec31_dec_sub19_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub19_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub20_dec31_dec_sub20_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub20_dec31_dec_sub20_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub20_dec31_dec_sub20_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub20_dec31_dec_sub20_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub20_dec31_dec_sub20_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub20_dec31_dec_sub20_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub20_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub21_dec31_dec_sub21_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub21_dec31_dec_sub21_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub21_dec31_dec_sub21_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub21_dec31_dec_sub21_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub21_dec31_dec_sub21_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub21_dec31_dec_sub21_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub21_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub22_dec31_dec_sub22_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub22_dec31_dec_sub22_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub22_dec31_dec_sub22_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub22_dec31_dec_sub22_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub22_dec31_dec_sub22_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub22_dec31_dec_sub22_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub22_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub23_dec31_dec_sub23_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub23_dec31_dec_sub23_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub23_dec31_dec_sub23_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub23_dec31_dec_sub23_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub23_dec31_dec_sub23_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub23_dec31_dec_sub23_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub23_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub24_dec31_dec_sub24_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub24_dec31_dec_sub24_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub24_dec31_dec_sub24_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub24_dec31_dec_sub24_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub24_dec31_dec_sub24_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub24_dec31_dec_sub24_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub24_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub26_dec31_dec_sub26_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub26_dec31_dec_sub26_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub26_dec31_dec_sub26_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub26_dec31_dec_sub26_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub26_dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub26_dec31_dec_sub26_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub26_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub27_dec31_dec_sub27_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub27_dec31_dec_sub27_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub27_dec31_dec_sub27_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub27_dec31_dec_sub27_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub27_dec31_dec_sub27_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub27_dec31_dec_sub27_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub27_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub28_dec31_dec_sub28_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub28_dec31_dec_sub28_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub28_dec31_dec_sub28_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub28_dec31_dec_sub28_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub28_dec31_dec_sub28_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub28_dec31_dec_sub28_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub28_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub4_dec31_dec_sub4_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub4_dec31_dec_sub4_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub4_dec31_dec_sub4_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub4_dec31_dec_sub4_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub4_dec31_dec_sub4_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub4_dec31_dec_sub4_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub4_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub8_dec31_dec_sub8_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub8_dec31_dec_sub8_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub8_dec31_dec_sub8_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub8_dec31_dec_sub8_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub8_dec31_dec_sub8_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub8_dec31_dec_sub8_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub8_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub9_dec31_dec_sub9_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub9_dec31_dec_sub9_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec31_dec_sub9_dec31_dec_sub9_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub9_dec31_dec_sub9_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub9_dec31_dec_sub9_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub9_dec31_dec_sub9_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec31_dec_sub9_opcode_in; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_form; + reg [4:0] dec31_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_function_unit; + reg [13:0] dec31_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_in1_sel; + reg [2:0] dec31_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_in2_sel; + reg [3:0] dec31_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_in3_sel; + reg [1:0] dec31_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_internal_op; + reg [6:0] dec31_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_inv_a; + reg dec31_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_inv_out; + reg dec31_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_is_32b; + reg dec31_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_ldst_len; + reg [3:0] dec31_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_lk; + reg dec31_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_out_sel; + reg [2:0] dec31_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_rc_sel; + reg [1:0] dec31_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_rsrv; + reg dec31_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_sgl_pipe; + reg dec31_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_sgn; + reg dec31_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_sgn_ext; + reg dec31_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_sv_cr_in; + reg [2:0] dec31_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_sv_cr_out; + reg [2:0] dec31_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_sv_in1; + reg [2:0] dec31_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_sv_in2; + reg [2:0] dec31_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_sv_in3; + reg [2:0] dec31_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_sv_out; + reg [2:0] dec31_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_sv_out2; + reg [2:0] dec31_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_upd; + reg [1:0] dec31_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + wire [4:0] opc_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [9:0] opcode_switch; + dec31_dec_sub0 dec31_dec_sub0 ( + .dec31_dec_sub0_SV_Etype(dec31_dec_sub0_dec31_dec_sub0_SV_Etype), + .dec31_dec_sub0_SV_Ptype(dec31_dec_sub0_dec31_dec_sub0_SV_Ptype), + .dec31_dec_sub0_asmcode(dec31_dec_sub0_dec31_dec_sub0_asmcode), + .dec31_dec_sub0_br(dec31_dec_sub0_dec31_dec_sub0_br), + .dec31_dec_sub0_cr_in(dec31_dec_sub0_dec31_dec_sub0_cr_in), + .dec31_dec_sub0_cr_out(dec31_dec_sub0_dec31_dec_sub0_cr_out), + .dec31_dec_sub0_cry_in(dec31_dec_sub0_dec31_dec_sub0_cry_in), + .dec31_dec_sub0_cry_out(dec31_dec_sub0_dec31_dec_sub0_cry_out), + .dec31_dec_sub0_form(dec31_dec_sub0_dec31_dec_sub0_form), + .dec31_dec_sub0_function_unit(dec31_dec_sub0_dec31_dec_sub0_function_unit), + .dec31_dec_sub0_in1_sel(dec31_dec_sub0_dec31_dec_sub0_in1_sel), + .dec31_dec_sub0_in2_sel(dec31_dec_sub0_dec31_dec_sub0_in2_sel), + .dec31_dec_sub0_in3_sel(dec31_dec_sub0_dec31_dec_sub0_in3_sel), + .dec31_dec_sub0_internal_op(dec31_dec_sub0_dec31_dec_sub0_internal_op), + .dec31_dec_sub0_inv_a(dec31_dec_sub0_dec31_dec_sub0_inv_a), + .dec31_dec_sub0_inv_out(dec31_dec_sub0_dec31_dec_sub0_inv_out), + .dec31_dec_sub0_is_32b(dec31_dec_sub0_dec31_dec_sub0_is_32b), + .dec31_dec_sub0_ldst_len(dec31_dec_sub0_dec31_dec_sub0_ldst_len), + .dec31_dec_sub0_lk(dec31_dec_sub0_dec31_dec_sub0_lk), + .dec31_dec_sub0_out_sel(dec31_dec_sub0_dec31_dec_sub0_out_sel), + .dec31_dec_sub0_rc_sel(dec31_dec_sub0_dec31_dec_sub0_rc_sel), + .dec31_dec_sub0_rsrv(dec31_dec_sub0_dec31_dec_sub0_rsrv), + .dec31_dec_sub0_sgl_pipe(dec31_dec_sub0_dec31_dec_sub0_sgl_pipe), + .dec31_dec_sub0_sgn(dec31_dec_sub0_dec31_dec_sub0_sgn), + .dec31_dec_sub0_sgn_ext(dec31_dec_sub0_dec31_dec_sub0_sgn_ext), + .dec31_dec_sub0_sv_cr_in(dec31_dec_sub0_dec31_dec_sub0_sv_cr_in), + .dec31_dec_sub0_sv_cr_out(dec31_dec_sub0_dec31_dec_sub0_sv_cr_out), + .dec31_dec_sub0_sv_in1(dec31_dec_sub0_dec31_dec_sub0_sv_in1), + .dec31_dec_sub0_sv_in2(dec31_dec_sub0_dec31_dec_sub0_sv_in2), + .dec31_dec_sub0_sv_in3(dec31_dec_sub0_dec31_dec_sub0_sv_in3), + .dec31_dec_sub0_sv_out(dec31_dec_sub0_dec31_dec_sub0_sv_out), + .dec31_dec_sub0_sv_out2(dec31_dec_sub0_dec31_dec_sub0_sv_out2), + .dec31_dec_sub0_upd(dec31_dec_sub0_dec31_dec_sub0_upd), + .opcode_in(dec31_dec_sub0_opcode_in) + ); + dec31_dec_sub10 dec31_dec_sub10 ( + .dec31_dec_sub10_SV_Etype(dec31_dec_sub10_dec31_dec_sub10_SV_Etype), + .dec31_dec_sub10_SV_Ptype(dec31_dec_sub10_dec31_dec_sub10_SV_Ptype), + .dec31_dec_sub10_asmcode(dec31_dec_sub10_dec31_dec_sub10_asmcode), + .dec31_dec_sub10_br(dec31_dec_sub10_dec31_dec_sub10_br), + .dec31_dec_sub10_cr_in(dec31_dec_sub10_dec31_dec_sub10_cr_in), + .dec31_dec_sub10_cr_out(dec31_dec_sub10_dec31_dec_sub10_cr_out), + .dec31_dec_sub10_cry_in(dec31_dec_sub10_dec31_dec_sub10_cry_in), + .dec31_dec_sub10_cry_out(dec31_dec_sub10_dec31_dec_sub10_cry_out), + .dec31_dec_sub10_form(dec31_dec_sub10_dec31_dec_sub10_form), + .dec31_dec_sub10_function_unit(dec31_dec_sub10_dec31_dec_sub10_function_unit), + .dec31_dec_sub10_in1_sel(dec31_dec_sub10_dec31_dec_sub10_in1_sel), + .dec31_dec_sub10_in2_sel(dec31_dec_sub10_dec31_dec_sub10_in2_sel), + .dec31_dec_sub10_in3_sel(dec31_dec_sub10_dec31_dec_sub10_in3_sel), + .dec31_dec_sub10_internal_op(dec31_dec_sub10_dec31_dec_sub10_internal_op), + .dec31_dec_sub10_inv_a(dec31_dec_sub10_dec31_dec_sub10_inv_a), + .dec31_dec_sub10_inv_out(dec31_dec_sub10_dec31_dec_sub10_inv_out), + .dec31_dec_sub10_is_32b(dec31_dec_sub10_dec31_dec_sub10_is_32b), + .dec31_dec_sub10_ldst_len(dec31_dec_sub10_dec31_dec_sub10_ldst_len), + .dec31_dec_sub10_lk(dec31_dec_sub10_dec31_dec_sub10_lk), + .dec31_dec_sub10_out_sel(dec31_dec_sub10_dec31_dec_sub10_out_sel), + .dec31_dec_sub10_rc_sel(dec31_dec_sub10_dec31_dec_sub10_rc_sel), + .dec31_dec_sub10_rsrv(dec31_dec_sub10_dec31_dec_sub10_rsrv), + .dec31_dec_sub10_sgl_pipe(dec31_dec_sub10_dec31_dec_sub10_sgl_pipe), + .dec31_dec_sub10_sgn(dec31_dec_sub10_dec31_dec_sub10_sgn), + .dec31_dec_sub10_sgn_ext(dec31_dec_sub10_dec31_dec_sub10_sgn_ext), + .dec31_dec_sub10_sv_cr_in(dec31_dec_sub10_dec31_dec_sub10_sv_cr_in), + .dec31_dec_sub10_sv_cr_out(dec31_dec_sub10_dec31_dec_sub10_sv_cr_out), + .dec31_dec_sub10_sv_in1(dec31_dec_sub10_dec31_dec_sub10_sv_in1), + .dec31_dec_sub10_sv_in2(dec31_dec_sub10_dec31_dec_sub10_sv_in2), + .dec31_dec_sub10_sv_in3(dec31_dec_sub10_dec31_dec_sub10_sv_in3), + .dec31_dec_sub10_sv_out(dec31_dec_sub10_dec31_dec_sub10_sv_out), + .dec31_dec_sub10_sv_out2(dec31_dec_sub10_dec31_dec_sub10_sv_out2), + .dec31_dec_sub10_upd(dec31_dec_sub10_dec31_dec_sub10_upd), + .opcode_in(dec31_dec_sub10_opcode_in) + ); + dec31_dec_sub11 dec31_dec_sub11 ( + .dec31_dec_sub11_SV_Etype(dec31_dec_sub11_dec31_dec_sub11_SV_Etype), + .dec31_dec_sub11_SV_Ptype(dec31_dec_sub11_dec31_dec_sub11_SV_Ptype), + .dec31_dec_sub11_asmcode(dec31_dec_sub11_dec31_dec_sub11_asmcode), + .dec31_dec_sub11_br(dec31_dec_sub11_dec31_dec_sub11_br), + .dec31_dec_sub11_cr_in(dec31_dec_sub11_dec31_dec_sub11_cr_in), + .dec31_dec_sub11_cr_out(dec31_dec_sub11_dec31_dec_sub11_cr_out), + .dec31_dec_sub11_cry_in(dec31_dec_sub11_dec31_dec_sub11_cry_in), + .dec31_dec_sub11_cry_out(dec31_dec_sub11_dec31_dec_sub11_cry_out), + .dec31_dec_sub11_form(dec31_dec_sub11_dec31_dec_sub11_form), + .dec31_dec_sub11_function_unit(dec31_dec_sub11_dec31_dec_sub11_function_unit), + .dec31_dec_sub11_in1_sel(dec31_dec_sub11_dec31_dec_sub11_in1_sel), + .dec31_dec_sub11_in2_sel(dec31_dec_sub11_dec31_dec_sub11_in2_sel), + .dec31_dec_sub11_in3_sel(dec31_dec_sub11_dec31_dec_sub11_in3_sel), + .dec31_dec_sub11_internal_op(dec31_dec_sub11_dec31_dec_sub11_internal_op), + .dec31_dec_sub11_inv_a(dec31_dec_sub11_dec31_dec_sub11_inv_a), + .dec31_dec_sub11_inv_out(dec31_dec_sub11_dec31_dec_sub11_inv_out), + .dec31_dec_sub11_is_32b(dec31_dec_sub11_dec31_dec_sub11_is_32b), + .dec31_dec_sub11_ldst_len(dec31_dec_sub11_dec31_dec_sub11_ldst_len), + .dec31_dec_sub11_lk(dec31_dec_sub11_dec31_dec_sub11_lk), + .dec31_dec_sub11_out_sel(dec31_dec_sub11_dec31_dec_sub11_out_sel), + .dec31_dec_sub11_rc_sel(dec31_dec_sub11_dec31_dec_sub11_rc_sel), + .dec31_dec_sub11_rsrv(dec31_dec_sub11_dec31_dec_sub11_rsrv), + .dec31_dec_sub11_sgl_pipe(dec31_dec_sub11_dec31_dec_sub11_sgl_pipe), + .dec31_dec_sub11_sgn(dec31_dec_sub11_dec31_dec_sub11_sgn), + .dec31_dec_sub11_sgn_ext(dec31_dec_sub11_dec31_dec_sub11_sgn_ext), + .dec31_dec_sub11_sv_cr_in(dec31_dec_sub11_dec31_dec_sub11_sv_cr_in), + .dec31_dec_sub11_sv_cr_out(dec31_dec_sub11_dec31_dec_sub11_sv_cr_out), + .dec31_dec_sub11_sv_in1(dec31_dec_sub11_dec31_dec_sub11_sv_in1), + .dec31_dec_sub11_sv_in2(dec31_dec_sub11_dec31_dec_sub11_sv_in2), + .dec31_dec_sub11_sv_in3(dec31_dec_sub11_dec31_dec_sub11_sv_in3), + .dec31_dec_sub11_sv_out(dec31_dec_sub11_dec31_dec_sub11_sv_out), + .dec31_dec_sub11_sv_out2(dec31_dec_sub11_dec31_dec_sub11_sv_out2), + .dec31_dec_sub11_upd(dec31_dec_sub11_dec31_dec_sub11_upd), + .opcode_in(dec31_dec_sub11_opcode_in) + ); + dec31_dec_sub15 dec31_dec_sub15 ( + .dec31_dec_sub15_SV_Etype(dec31_dec_sub15_dec31_dec_sub15_SV_Etype), + .dec31_dec_sub15_SV_Ptype(dec31_dec_sub15_dec31_dec_sub15_SV_Ptype), + .dec31_dec_sub15_asmcode(dec31_dec_sub15_dec31_dec_sub15_asmcode), + .dec31_dec_sub15_br(dec31_dec_sub15_dec31_dec_sub15_br), + .dec31_dec_sub15_cr_in(dec31_dec_sub15_dec31_dec_sub15_cr_in), + .dec31_dec_sub15_cr_out(dec31_dec_sub15_dec31_dec_sub15_cr_out), + .dec31_dec_sub15_cry_in(dec31_dec_sub15_dec31_dec_sub15_cry_in), + .dec31_dec_sub15_cry_out(dec31_dec_sub15_dec31_dec_sub15_cry_out), + .dec31_dec_sub15_form(dec31_dec_sub15_dec31_dec_sub15_form), + .dec31_dec_sub15_function_unit(dec31_dec_sub15_dec31_dec_sub15_function_unit), + .dec31_dec_sub15_in1_sel(dec31_dec_sub15_dec31_dec_sub15_in1_sel), + .dec31_dec_sub15_in2_sel(dec31_dec_sub15_dec31_dec_sub15_in2_sel), + .dec31_dec_sub15_in3_sel(dec31_dec_sub15_dec31_dec_sub15_in3_sel), + .dec31_dec_sub15_internal_op(dec31_dec_sub15_dec31_dec_sub15_internal_op), + .dec31_dec_sub15_inv_a(dec31_dec_sub15_dec31_dec_sub15_inv_a), + .dec31_dec_sub15_inv_out(dec31_dec_sub15_dec31_dec_sub15_inv_out), + .dec31_dec_sub15_is_32b(dec31_dec_sub15_dec31_dec_sub15_is_32b), + .dec31_dec_sub15_ldst_len(dec31_dec_sub15_dec31_dec_sub15_ldst_len), + .dec31_dec_sub15_lk(dec31_dec_sub15_dec31_dec_sub15_lk), + .dec31_dec_sub15_out_sel(dec31_dec_sub15_dec31_dec_sub15_out_sel), + .dec31_dec_sub15_rc_sel(dec31_dec_sub15_dec31_dec_sub15_rc_sel), + .dec31_dec_sub15_rsrv(dec31_dec_sub15_dec31_dec_sub15_rsrv), + .dec31_dec_sub15_sgl_pipe(dec31_dec_sub15_dec31_dec_sub15_sgl_pipe), + .dec31_dec_sub15_sgn(dec31_dec_sub15_dec31_dec_sub15_sgn), + .dec31_dec_sub15_sgn_ext(dec31_dec_sub15_dec31_dec_sub15_sgn_ext), + .dec31_dec_sub15_sv_cr_in(dec31_dec_sub15_dec31_dec_sub15_sv_cr_in), + .dec31_dec_sub15_sv_cr_out(dec31_dec_sub15_dec31_dec_sub15_sv_cr_out), + .dec31_dec_sub15_sv_in1(dec31_dec_sub15_dec31_dec_sub15_sv_in1), + .dec31_dec_sub15_sv_in2(dec31_dec_sub15_dec31_dec_sub15_sv_in2), + .dec31_dec_sub15_sv_in3(dec31_dec_sub15_dec31_dec_sub15_sv_in3), + .dec31_dec_sub15_sv_out(dec31_dec_sub15_dec31_dec_sub15_sv_out), + .dec31_dec_sub15_sv_out2(dec31_dec_sub15_dec31_dec_sub15_sv_out2), + .dec31_dec_sub15_upd(dec31_dec_sub15_dec31_dec_sub15_upd), + .opcode_in(dec31_dec_sub15_opcode_in) + ); + dec31_dec_sub16 dec31_dec_sub16 ( + .dec31_dec_sub16_SV_Etype(dec31_dec_sub16_dec31_dec_sub16_SV_Etype), + .dec31_dec_sub16_SV_Ptype(dec31_dec_sub16_dec31_dec_sub16_SV_Ptype), + .dec31_dec_sub16_asmcode(dec31_dec_sub16_dec31_dec_sub16_asmcode), + .dec31_dec_sub16_br(dec31_dec_sub16_dec31_dec_sub16_br), + .dec31_dec_sub16_cr_in(dec31_dec_sub16_dec31_dec_sub16_cr_in), + .dec31_dec_sub16_cr_out(dec31_dec_sub16_dec31_dec_sub16_cr_out), + .dec31_dec_sub16_cry_in(dec31_dec_sub16_dec31_dec_sub16_cry_in), + .dec31_dec_sub16_cry_out(dec31_dec_sub16_dec31_dec_sub16_cry_out), + .dec31_dec_sub16_form(dec31_dec_sub16_dec31_dec_sub16_form), + .dec31_dec_sub16_function_unit(dec31_dec_sub16_dec31_dec_sub16_function_unit), + .dec31_dec_sub16_in1_sel(dec31_dec_sub16_dec31_dec_sub16_in1_sel), + .dec31_dec_sub16_in2_sel(dec31_dec_sub16_dec31_dec_sub16_in2_sel), + .dec31_dec_sub16_in3_sel(dec31_dec_sub16_dec31_dec_sub16_in3_sel), + .dec31_dec_sub16_internal_op(dec31_dec_sub16_dec31_dec_sub16_internal_op), + .dec31_dec_sub16_inv_a(dec31_dec_sub16_dec31_dec_sub16_inv_a), + .dec31_dec_sub16_inv_out(dec31_dec_sub16_dec31_dec_sub16_inv_out), + .dec31_dec_sub16_is_32b(dec31_dec_sub16_dec31_dec_sub16_is_32b), + .dec31_dec_sub16_ldst_len(dec31_dec_sub16_dec31_dec_sub16_ldst_len), + .dec31_dec_sub16_lk(dec31_dec_sub16_dec31_dec_sub16_lk), + .dec31_dec_sub16_out_sel(dec31_dec_sub16_dec31_dec_sub16_out_sel), + .dec31_dec_sub16_rc_sel(dec31_dec_sub16_dec31_dec_sub16_rc_sel), + .dec31_dec_sub16_rsrv(dec31_dec_sub16_dec31_dec_sub16_rsrv), + .dec31_dec_sub16_sgl_pipe(dec31_dec_sub16_dec31_dec_sub16_sgl_pipe), + .dec31_dec_sub16_sgn(dec31_dec_sub16_dec31_dec_sub16_sgn), + .dec31_dec_sub16_sgn_ext(dec31_dec_sub16_dec31_dec_sub16_sgn_ext), + .dec31_dec_sub16_sv_cr_in(dec31_dec_sub16_dec31_dec_sub16_sv_cr_in), + .dec31_dec_sub16_sv_cr_out(dec31_dec_sub16_dec31_dec_sub16_sv_cr_out), + .dec31_dec_sub16_sv_in1(dec31_dec_sub16_dec31_dec_sub16_sv_in1), + .dec31_dec_sub16_sv_in2(dec31_dec_sub16_dec31_dec_sub16_sv_in2), + .dec31_dec_sub16_sv_in3(dec31_dec_sub16_dec31_dec_sub16_sv_in3), + .dec31_dec_sub16_sv_out(dec31_dec_sub16_dec31_dec_sub16_sv_out), + .dec31_dec_sub16_sv_out2(dec31_dec_sub16_dec31_dec_sub16_sv_out2), + .dec31_dec_sub16_upd(dec31_dec_sub16_dec31_dec_sub16_upd), + .opcode_in(dec31_dec_sub16_opcode_in) + ); + dec31_dec_sub18 dec31_dec_sub18 ( + .dec31_dec_sub18_SV_Etype(dec31_dec_sub18_dec31_dec_sub18_SV_Etype), + .dec31_dec_sub18_SV_Ptype(dec31_dec_sub18_dec31_dec_sub18_SV_Ptype), + .dec31_dec_sub18_asmcode(dec31_dec_sub18_dec31_dec_sub18_asmcode), + .dec31_dec_sub18_br(dec31_dec_sub18_dec31_dec_sub18_br), + .dec31_dec_sub18_cr_in(dec31_dec_sub18_dec31_dec_sub18_cr_in), + .dec31_dec_sub18_cr_out(dec31_dec_sub18_dec31_dec_sub18_cr_out), + .dec31_dec_sub18_cry_in(dec31_dec_sub18_dec31_dec_sub18_cry_in), + .dec31_dec_sub18_cry_out(dec31_dec_sub18_dec31_dec_sub18_cry_out), + .dec31_dec_sub18_form(dec31_dec_sub18_dec31_dec_sub18_form), + .dec31_dec_sub18_function_unit(dec31_dec_sub18_dec31_dec_sub18_function_unit), + .dec31_dec_sub18_in1_sel(dec31_dec_sub18_dec31_dec_sub18_in1_sel), + .dec31_dec_sub18_in2_sel(dec31_dec_sub18_dec31_dec_sub18_in2_sel), + .dec31_dec_sub18_in3_sel(dec31_dec_sub18_dec31_dec_sub18_in3_sel), + .dec31_dec_sub18_internal_op(dec31_dec_sub18_dec31_dec_sub18_internal_op), + .dec31_dec_sub18_inv_a(dec31_dec_sub18_dec31_dec_sub18_inv_a), + .dec31_dec_sub18_inv_out(dec31_dec_sub18_dec31_dec_sub18_inv_out), + .dec31_dec_sub18_is_32b(dec31_dec_sub18_dec31_dec_sub18_is_32b), + .dec31_dec_sub18_ldst_len(dec31_dec_sub18_dec31_dec_sub18_ldst_len), + .dec31_dec_sub18_lk(dec31_dec_sub18_dec31_dec_sub18_lk), + .dec31_dec_sub18_out_sel(dec31_dec_sub18_dec31_dec_sub18_out_sel), + .dec31_dec_sub18_rc_sel(dec31_dec_sub18_dec31_dec_sub18_rc_sel), + .dec31_dec_sub18_rsrv(dec31_dec_sub18_dec31_dec_sub18_rsrv), + .dec31_dec_sub18_sgl_pipe(dec31_dec_sub18_dec31_dec_sub18_sgl_pipe), + .dec31_dec_sub18_sgn(dec31_dec_sub18_dec31_dec_sub18_sgn), + .dec31_dec_sub18_sgn_ext(dec31_dec_sub18_dec31_dec_sub18_sgn_ext), + .dec31_dec_sub18_sv_cr_in(dec31_dec_sub18_dec31_dec_sub18_sv_cr_in), + .dec31_dec_sub18_sv_cr_out(dec31_dec_sub18_dec31_dec_sub18_sv_cr_out), + .dec31_dec_sub18_sv_in1(dec31_dec_sub18_dec31_dec_sub18_sv_in1), + .dec31_dec_sub18_sv_in2(dec31_dec_sub18_dec31_dec_sub18_sv_in2), + .dec31_dec_sub18_sv_in3(dec31_dec_sub18_dec31_dec_sub18_sv_in3), + .dec31_dec_sub18_sv_out(dec31_dec_sub18_dec31_dec_sub18_sv_out), + .dec31_dec_sub18_sv_out2(dec31_dec_sub18_dec31_dec_sub18_sv_out2), + .dec31_dec_sub18_upd(dec31_dec_sub18_dec31_dec_sub18_upd), + .opcode_in(dec31_dec_sub18_opcode_in) + ); + dec31_dec_sub19 dec31_dec_sub19 ( + .dec31_dec_sub19_SV_Etype(dec31_dec_sub19_dec31_dec_sub19_SV_Etype), + .dec31_dec_sub19_SV_Ptype(dec31_dec_sub19_dec31_dec_sub19_SV_Ptype), + .dec31_dec_sub19_asmcode(dec31_dec_sub19_dec31_dec_sub19_asmcode), + .dec31_dec_sub19_br(dec31_dec_sub19_dec31_dec_sub19_br), + .dec31_dec_sub19_cr_in(dec31_dec_sub19_dec31_dec_sub19_cr_in), + .dec31_dec_sub19_cr_out(dec31_dec_sub19_dec31_dec_sub19_cr_out), + .dec31_dec_sub19_cry_in(dec31_dec_sub19_dec31_dec_sub19_cry_in), + .dec31_dec_sub19_cry_out(dec31_dec_sub19_dec31_dec_sub19_cry_out), + .dec31_dec_sub19_form(dec31_dec_sub19_dec31_dec_sub19_form), + .dec31_dec_sub19_function_unit(dec31_dec_sub19_dec31_dec_sub19_function_unit), + .dec31_dec_sub19_in1_sel(dec31_dec_sub19_dec31_dec_sub19_in1_sel), + .dec31_dec_sub19_in2_sel(dec31_dec_sub19_dec31_dec_sub19_in2_sel), + .dec31_dec_sub19_in3_sel(dec31_dec_sub19_dec31_dec_sub19_in3_sel), + .dec31_dec_sub19_internal_op(dec31_dec_sub19_dec31_dec_sub19_internal_op), + .dec31_dec_sub19_inv_a(dec31_dec_sub19_dec31_dec_sub19_inv_a), + .dec31_dec_sub19_inv_out(dec31_dec_sub19_dec31_dec_sub19_inv_out), + .dec31_dec_sub19_is_32b(dec31_dec_sub19_dec31_dec_sub19_is_32b), + .dec31_dec_sub19_ldst_len(dec31_dec_sub19_dec31_dec_sub19_ldst_len), + .dec31_dec_sub19_lk(dec31_dec_sub19_dec31_dec_sub19_lk), + .dec31_dec_sub19_out_sel(dec31_dec_sub19_dec31_dec_sub19_out_sel), + .dec31_dec_sub19_rc_sel(dec31_dec_sub19_dec31_dec_sub19_rc_sel), + .dec31_dec_sub19_rsrv(dec31_dec_sub19_dec31_dec_sub19_rsrv), + .dec31_dec_sub19_sgl_pipe(dec31_dec_sub19_dec31_dec_sub19_sgl_pipe), + .dec31_dec_sub19_sgn(dec31_dec_sub19_dec31_dec_sub19_sgn), + .dec31_dec_sub19_sgn_ext(dec31_dec_sub19_dec31_dec_sub19_sgn_ext), + .dec31_dec_sub19_sv_cr_in(dec31_dec_sub19_dec31_dec_sub19_sv_cr_in), + .dec31_dec_sub19_sv_cr_out(dec31_dec_sub19_dec31_dec_sub19_sv_cr_out), + .dec31_dec_sub19_sv_in1(dec31_dec_sub19_dec31_dec_sub19_sv_in1), + .dec31_dec_sub19_sv_in2(dec31_dec_sub19_dec31_dec_sub19_sv_in2), + .dec31_dec_sub19_sv_in3(dec31_dec_sub19_dec31_dec_sub19_sv_in3), + .dec31_dec_sub19_sv_out(dec31_dec_sub19_dec31_dec_sub19_sv_out), + .dec31_dec_sub19_sv_out2(dec31_dec_sub19_dec31_dec_sub19_sv_out2), + .dec31_dec_sub19_upd(dec31_dec_sub19_dec31_dec_sub19_upd), + .opcode_in(dec31_dec_sub19_opcode_in) + ); + dec31_dec_sub20 dec31_dec_sub20 ( + .dec31_dec_sub20_SV_Etype(dec31_dec_sub20_dec31_dec_sub20_SV_Etype), + .dec31_dec_sub20_SV_Ptype(dec31_dec_sub20_dec31_dec_sub20_SV_Ptype), + .dec31_dec_sub20_asmcode(dec31_dec_sub20_dec31_dec_sub20_asmcode), + .dec31_dec_sub20_br(dec31_dec_sub20_dec31_dec_sub20_br), + .dec31_dec_sub20_cr_in(dec31_dec_sub20_dec31_dec_sub20_cr_in), + .dec31_dec_sub20_cr_out(dec31_dec_sub20_dec31_dec_sub20_cr_out), + .dec31_dec_sub20_cry_in(dec31_dec_sub20_dec31_dec_sub20_cry_in), + .dec31_dec_sub20_cry_out(dec31_dec_sub20_dec31_dec_sub20_cry_out), + .dec31_dec_sub20_form(dec31_dec_sub20_dec31_dec_sub20_form), + .dec31_dec_sub20_function_unit(dec31_dec_sub20_dec31_dec_sub20_function_unit), + .dec31_dec_sub20_in1_sel(dec31_dec_sub20_dec31_dec_sub20_in1_sel), + .dec31_dec_sub20_in2_sel(dec31_dec_sub20_dec31_dec_sub20_in2_sel), + .dec31_dec_sub20_in3_sel(dec31_dec_sub20_dec31_dec_sub20_in3_sel), + .dec31_dec_sub20_internal_op(dec31_dec_sub20_dec31_dec_sub20_internal_op), + .dec31_dec_sub20_inv_a(dec31_dec_sub20_dec31_dec_sub20_inv_a), + .dec31_dec_sub20_inv_out(dec31_dec_sub20_dec31_dec_sub20_inv_out), + .dec31_dec_sub20_is_32b(dec31_dec_sub20_dec31_dec_sub20_is_32b), + .dec31_dec_sub20_ldst_len(dec31_dec_sub20_dec31_dec_sub20_ldst_len), + .dec31_dec_sub20_lk(dec31_dec_sub20_dec31_dec_sub20_lk), + .dec31_dec_sub20_out_sel(dec31_dec_sub20_dec31_dec_sub20_out_sel), + .dec31_dec_sub20_rc_sel(dec31_dec_sub20_dec31_dec_sub20_rc_sel), + .dec31_dec_sub20_rsrv(dec31_dec_sub20_dec31_dec_sub20_rsrv), + .dec31_dec_sub20_sgl_pipe(dec31_dec_sub20_dec31_dec_sub20_sgl_pipe), + .dec31_dec_sub20_sgn(dec31_dec_sub20_dec31_dec_sub20_sgn), + .dec31_dec_sub20_sgn_ext(dec31_dec_sub20_dec31_dec_sub20_sgn_ext), + .dec31_dec_sub20_sv_cr_in(dec31_dec_sub20_dec31_dec_sub20_sv_cr_in), + .dec31_dec_sub20_sv_cr_out(dec31_dec_sub20_dec31_dec_sub20_sv_cr_out), + .dec31_dec_sub20_sv_in1(dec31_dec_sub20_dec31_dec_sub20_sv_in1), + .dec31_dec_sub20_sv_in2(dec31_dec_sub20_dec31_dec_sub20_sv_in2), + .dec31_dec_sub20_sv_in3(dec31_dec_sub20_dec31_dec_sub20_sv_in3), + .dec31_dec_sub20_sv_out(dec31_dec_sub20_dec31_dec_sub20_sv_out), + .dec31_dec_sub20_sv_out2(dec31_dec_sub20_dec31_dec_sub20_sv_out2), + .dec31_dec_sub20_upd(dec31_dec_sub20_dec31_dec_sub20_upd), + .opcode_in(dec31_dec_sub20_opcode_in) + ); + dec31_dec_sub21 dec31_dec_sub21 ( + .dec31_dec_sub21_SV_Etype(dec31_dec_sub21_dec31_dec_sub21_SV_Etype), + .dec31_dec_sub21_SV_Ptype(dec31_dec_sub21_dec31_dec_sub21_SV_Ptype), + .dec31_dec_sub21_asmcode(dec31_dec_sub21_dec31_dec_sub21_asmcode), + .dec31_dec_sub21_br(dec31_dec_sub21_dec31_dec_sub21_br), + .dec31_dec_sub21_cr_in(dec31_dec_sub21_dec31_dec_sub21_cr_in), + .dec31_dec_sub21_cr_out(dec31_dec_sub21_dec31_dec_sub21_cr_out), + .dec31_dec_sub21_cry_in(dec31_dec_sub21_dec31_dec_sub21_cry_in), + .dec31_dec_sub21_cry_out(dec31_dec_sub21_dec31_dec_sub21_cry_out), + .dec31_dec_sub21_form(dec31_dec_sub21_dec31_dec_sub21_form), + .dec31_dec_sub21_function_unit(dec31_dec_sub21_dec31_dec_sub21_function_unit), + .dec31_dec_sub21_in1_sel(dec31_dec_sub21_dec31_dec_sub21_in1_sel), + .dec31_dec_sub21_in2_sel(dec31_dec_sub21_dec31_dec_sub21_in2_sel), + .dec31_dec_sub21_in3_sel(dec31_dec_sub21_dec31_dec_sub21_in3_sel), + .dec31_dec_sub21_internal_op(dec31_dec_sub21_dec31_dec_sub21_internal_op), + .dec31_dec_sub21_inv_a(dec31_dec_sub21_dec31_dec_sub21_inv_a), + .dec31_dec_sub21_inv_out(dec31_dec_sub21_dec31_dec_sub21_inv_out), + .dec31_dec_sub21_is_32b(dec31_dec_sub21_dec31_dec_sub21_is_32b), + .dec31_dec_sub21_ldst_len(dec31_dec_sub21_dec31_dec_sub21_ldst_len), + .dec31_dec_sub21_lk(dec31_dec_sub21_dec31_dec_sub21_lk), + .dec31_dec_sub21_out_sel(dec31_dec_sub21_dec31_dec_sub21_out_sel), + .dec31_dec_sub21_rc_sel(dec31_dec_sub21_dec31_dec_sub21_rc_sel), + .dec31_dec_sub21_rsrv(dec31_dec_sub21_dec31_dec_sub21_rsrv), + .dec31_dec_sub21_sgl_pipe(dec31_dec_sub21_dec31_dec_sub21_sgl_pipe), + .dec31_dec_sub21_sgn(dec31_dec_sub21_dec31_dec_sub21_sgn), + .dec31_dec_sub21_sgn_ext(dec31_dec_sub21_dec31_dec_sub21_sgn_ext), + .dec31_dec_sub21_sv_cr_in(dec31_dec_sub21_dec31_dec_sub21_sv_cr_in), + .dec31_dec_sub21_sv_cr_out(dec31_dec_sub21_dec31_dec_sub21_sv_cr_out), + .dec31_dec_sub21_sv_in1(dec31_dec_sub21_dec31_dec_sub21_sv_in1), + .dec31_dec_sub21_sv_in2(dec31_dec_sub21_dec31_dec_sub21_sv_in2), + .dec31_dec_sub21_sv_in3(dec31_dec_sub21_dec31_dec_sub21_sv_in3), + .dec31_dec_sub21_sv_out(dec31_dec_sub21_dec31_dec_sub21_sv_out), + .dec31_dec_sub21_sv_out2(dec31_dec_sub21_dec31_dec_sub21_sv_out2), + .dec31_dec_sub21_upd(dec31_dec_sub21_dec31_dec_sub21_upd), + .opcode_in(dec31_dec_sub21_opcode_in) + ); + dec31_dec_sub22 dec31_dec_sub22 ( + .dec31_dec_sub22_SV_Etype(dec31_dec_sub22_dec31_dec_sub22_SV_Etype), + .dec31_dec_sub22_SV_Ptype(dec31_dec_sub22_dec31_dec_sub22_SV_Ptype), + .dec31_dec_sub22_asmcode(dec31_dec_sub22_dec31_dec_sub22_asmcode), + .dec31_dec_sub22_br(dec31_dec_sub22_dec31_dec_sub22_br), + .dec31_dec_sub22_cr_in(dec31_dec_sub22_dec31_dec_sub22_cr_in), + .dec31_dec_sub22_cr_out(dec31_dec_sub22_dec31_dec_sub22_cr_out), + .dec31_dec_sub22_cry_in(dec31_dec_sub22_dec31_dec_sub22_cry_in), + .dec31_dec_sub22_cry_out(dec31_dec_sub22_dec31_dec_sub22_cry_out), + .dec31_dec_sub22_form(dec31_dec_sub22_dec31_dec_sub22_form), + .dec31_dec_sub22_function_unit(dec31_dec_sub22_dec31_dec_sub22_function_unit), + .dec31_dec_sub22_in1_sel(dec31_dec_sub22_dec31_dec_sub22_in1_sel), + .dec31_dec_sub22_in2_sel(dec31_dec_sub22_dec31_dec_sub22_in2_sel), + .dec31_dec_sub22_in3_sel(dec31_dec_sub22_dec31_dec_sub22_in3_sel), + .dec31_dec_sub22_internal_op(dec31_dec_sub22_dec31_dec_sub22_internal_op), + .dec31_dec_sub22_inv_a(dec31_dec_sub22_dec31_dec_sub22_inv_a), + .dec31_dec_sub22_inv_out(dec31_dec_sub22_dec31_dec_sub22_inv_out), + .dec31_dec_sub22_is_32b(dec31_dec_sub22_dec31_dec_sub22_is_32b), + .dec31_dec_sub22_ldst_len(dec31_dec_sub22_dec31_dec_sub22_ldst_len), + .dec31_dec_sub22_lk(dec31_dec_sub22_dec31_dec_sub22_lk), + .dec31_dec_sub22_out_sel(dec31_dec_sub22_dec31_dec_sub22_out_sel), + .dec31_dec_sub22_rc_sel(dec31_dec_sub22_dec31_dec_sub22_rc_sel), + .dec31_dec_sub22_rsrv(dec31_dec_sub22_dec31_dec_sub22_rsrv), + .dec31_dec_sub22_sgl_pipe(dec31_dec_sub22_dec31_dec_sub22_sgl_pipe), + .dec31_dec_sub22_sgn(dec31_dec_sub22_dec31_dec_sub22_sgn), + .dec31_dec_sub22_sgn_ext(dec31_dec_sub22_dec31_dec_sub22_sgn_ext), + .dec31_dec_sub22_sv_cr_in(dec31_dec_sub22_dec31_dec_sub22_sv_cr_in), + .dec31_dec_sub22_sv_cr_out(dec31_dec_sub22_dec31_dec_sub22_sv_cr_out), + .dec31_dec_sub22_sv_in1(dec31_dec_sub22_dec31_dec_sub22_sv_in1), + .dec31_dec_sub22_sv_in2(dec31_dec_sub22_dec31_dec_sub22_sv_in2), + .dec31_dec_sub22_sv_in3(dec31_dec_sub22_dec31_dec_sub22_sv_in3), + .dec31_dec_sub22_sv_out(dec31_dec_sub22_dec31_dec_sub22_sv_out), + .dec31_dec_sub22_sv_out2(dec31_dec_sub22_dec31_dec_sub22_sv_out2), + .dec31_dec_sub22_upd(dec31_dec_sub22_dec31_dec_sub22_upd), + .opcode_in(dec31_dec_sub22_opcode_in) + ); + dec31_dec_sub23 dec31_dec_sub23 ( + .dec31_dec_sub23_SV_Etype(dec31_dec_sub23_dec31_dec_sub23_SV_Etype), + .dec31_dec_sub23_SV_Ptype(dec31_dec_sub23_dec31_dec_sub23_SV_Ptype), + .dec31_dec_sub23_asmcode(dec31_dec_sub23_dec31_dec_sub23_asmcode), + .dec31_dec_sub23_br(dec31_dec_sub23_dec31_dec_sub23_br), + .dec31_dec_sub23_cr_in(dec31_dec_sub23_dec31_dec_sub23_cr_in), + .dec31_dec_sub23_cr_out(dec31_dec_sub23_dec31_dec_sub23_cr_out), + .dec31_dec_sub23_cry_in(dec31_dec_sub23_dec31_dec_sub23_cry_in), + .dec31_dec_sub23_cry_out(dec31_dec_sub23_dec31_dec_sub23_cry_out), + .dec31_dec_sub23_form(dec31_dec_sub23_dec31_dec_sub23_form), + .dec31_dec_sub23_function_unit(dec31_dec_sub23_dec31_dec_sub23_function_unit), + .dec31_dec_sub23_in1_sel(dec31_dec_sub23_dec31_dec_sub23_in1_sel), + .dec31_dec_sub23_in2_sel(dec31_dec_sub23_dec31_dec_sub23_in2_sel), + .dec31_dec_sub23_in3_sel(dec31_dec_sub23_dec31_dec_sub23_in3_sel), + .dec31_dec_sub23_internal_op(dec31_dec_sub23_dec31_dec_sub23_internal_op), + .dec31_dec_sub23_inv_a(dec31_dec_sub23_dec31_dec_sub23_inv_a), + .dec31_dec_sub23_inv_out(dec31_dec_sub23_dec31_dec_sub23_inv_out), + .dec31_dec_sub23_is_32b(dec31_dec_sub23_dec31_dec_sub23_is_32b), + .dec31_dec_sub23_ldst_len(dec31_dec_sub23_dec31_dec_sub23_ldst_len), + .dec31_dec_sub23_lk(dec31_dec_sub23_dec31_dec_sub23_lk), + .dec31_dec_sub23_out_sel(dec31_dec_sub23_dec31_dec_sub23_out_sel), + .dec31_dec_sub23_rc_sel(dec31_dec_sub23_dec31_dec_sub23_rc_sel), + .dec31_dec_sub23_rsrv(dec31_dec_sub23_dec31_dec_sub23_rsrv), + .dec31_dec_sub23_sgl_pipe(dec31_dec_sub23_dec31_dec_sub23_sgl_pipe), + .dec31_dec_sub23_sgn(dec31_dec_sub23_dec31_dec_sub23_sgn), + .dec31_dec_sub23_sgn_ext(dec31_dec_sub23_dec31_dec_sub23_sgn_ext), + .dec31_dec_sub23_sv_cr_in(dec31_dec_sub23_dec31_dec_sub23_sv_cr_in), + .dec31_dec_sub23_sv_cr_out(dec31_dec_sub23_dec31_dec_sub23_sv_cr_out), + .dec31_dec_sub23_sv_in1(dec31_dec_sub23_dec31_dec_sub23_sv_in1), + .dec31_dec_sub23_sv_in2(dec31_dec_sub23_dec31_dec_sub23_sv_in2), + .dec31_dec_sub23_sv_in3(dec31_dec_sub23_dec31_dec_sub23_sv_in3), + .dec31_dec_sub23_sv_out(dec31_dec_sub23_dec31_dec_sub23_sv_out), + .dec31_dec_sub23_sv_out2(dec31_dec_sub23_dec31_dec_sub23_sv_out2), + .dec31_dec_sub23_upd(dec31_dec_sub23_dec31_dec_sub23_upd), + .opcode_in(dec31_dec_sub23_opcode_in) + ); + dec31_dec_sub24 dec31_dec_sub24 ( + .dec31_dec_sub24_SV_Etype(dec31_dec_sub24_dec31_dec_sub24_SV_Etype), + .dec31_dec_sub24_SV_Ptype(dec31_dec_sub24_dec31_dec_sub24_SV_Ptype), + .dec31_dec_sub24_asmcode(dec31_dec_sub24_dec31_dec_sub24_asmcode), + .dec31_dec_sub24_br(dec31_dec_sub24_dec31_dec_sub24_br), + .dec31_dec_sub24_cr_in(dec31_dec_sub24_dec31_dec_sub24_cr_in), + .dec31_dec_sub24_cr_out(dec31_dec_sub24_dec31_dec_sub24_cr_out), + .dec31_dec_sub24_cry_in(dec31_dec_sub24_dec31_dec_sub24_cry_in), + .dec31_dec_sub24_cry_out(dec31_dec_sub24_dec31_dec_sub24_cry_out), + .dec31_dec_sub24_form(dec31_dec_sub24_dec31_dec_sub24_form), + .dec31_dec_sub24_function_unit(dec31_dec_sub24_dec31_dec_sub24_function_unit), + .dec31_dec_sub24_in1_sel(dec31_dec_sub24_dec31_dec_sub24_in1_sel), + .dec31_dec_sub24_in2_sel(dec31_dec_sub24_dec31_dec_sub24_in2_sel), + .dec31_dec_sub24_in3_sel(dec31_dec_sub24_dec31_dec_sub24_in3_sel), + .dec31_dec_sub24_internal_op(dec31_dec_sub24_dec31_dec_sub24_internal_op), + .dec31_dec_sub24_inv_a(dec31_dec_sub24_dec31_dec_sub24_inv_a), + .dec31_dec_sub24_inv_out(dec31_dec_sub24_dec31_dec_sub24_inv_out), + .dec31_dec_sub24_is_32b(dec31_dec_sub24_dec31_dec_sub24_is_32b), + .dec31_dec_sub24_ldst_len(dec31_dec_sub24_dec31_dec_sub24_ldst_len), + .dec31_dec_sub24_lk(dec31_dec_sub24_dec31_dec_sub24_lk), + .dec31_dec_sub24_out_sel(dec31_dec_sub24_dec31_dec_sub24_out_sel), + .dec31_dec_sub24_rc_sel(dec31_dec_sub24_dec31_dec_sub24_rc_sel), + .dec31_dec_sub24_rsrv(dec31_dec_sub24_dec31_dec_sub24_rsrv), + .dec31_dec_sub24_sgl_pipe(dec31_dec_sub24_dec31_dec_sub24_sgl_pipe), + .dec31_dec_sub24_sgn(dec31_dec_sub24_dec31_dec_sub24_sgn), + .dec31_dec_sub24_sgn_ext(dec31_dec_sub24_dec31_dec_sub24_sgn_ext), + .dec31_dec_sub24_sv_cr_in(dec31_dec_sub24_dec31_dec_sub24_sv_cr_in), + .dec31_dec_sub24_sv_cr_out(dec31_dec_sub24_dec31_dec_sub24_sv_cr_out), + .dec31_dec_sub24_sv_in1(dec31_dec_sub24_dec31_dec_sub24_sv_in1), + .dec31_dec_sub24_sv_in2(dec31_dec_sub24_dec31_dec_sub24_sv_in2), + .dec31_dec_sub24_sv_in3(dec31_dec_sub24_dec31_dec_sub24_sv_in3), + .dec31_dec_sub24_sv_out(dec31_dec_sub24_dec31_dec_sub24_sv_out), + .dec31_dec_sub24_sv_out2(dec31_dec_sub24_dec31_dec_sub24_sv_out2), + .dec31_dec_sub24_upd(dec31_dec_sub24_dec31_dec_sub24_upd), + .opcode_in(dec31_dec_sub24_opcode_in) + ); + dec31_dec_sub26 dec31_dec_sub26 ( + .dec31_dec_sub26_SV_Etype(dec31_dec_sub26_dec31_dec_sub26_SV_Etype), + .dec31_dec_sub26_SV_Ptype(dec31_dec_sub26_dec31_dec_sub26_SV_Ptype), + .dec31_dec_sub26_asmcode(dec31_dec_sub26_dec31_dec_sub26_asmcode), + .dec31_dec_sub26_br(dec31_dec_sub26_dec31_dec_sub26_br), + .dec31_dec_sub26_cr_in(dec31_dec_sub26_dec31_dec_sub26_cr_in), + .dec31_dec_sub26_cr_out(dec31_dec_sub26_dec31_dec_sub26_cr_out), + .dec31_dec_sub26_cry_in(dec31_dec_sub26_dec31_dec_sub26_cry_in), + .dec31_dec_sub26_cry_out(dec31_dec_sub26_dec31_dec_sub26_cry_out), + .dec31_dec_sub26_form(dec31_dec_sub26_dec31_dec_sub26_form), + .dec31_dec_sub26_function_unit(dec31_dec_sub26_dec31_dec_sub26_function_unit), + .dec31_dec_sub26_in1_sel(dec31_dec_sub26_dec31_dec_sub26_in1_sel), + .dec31_dec_sub26_in2_sel(dec31_dec_sub26_dec31_dec_sub26_in2_sel), + .dec31_dec_sub26_in3_sel(dec31_dec_sub26_dec31_dec_sub26_in3_sel), + .dec31_dec_sub26_internal_op(dec31_dec_sub26_dec31_dec_sub26_internal_op), + .dec31_dec_sub26_inv_a(dec31_dec_sub26_dec31_dec_sub26_inv_a), + .dec31_dec_sub26_inv_out(dec31_dec_sub26_dec31_dec_sub26_inv_out), + .dec31_dec_sub26_is_32b(dec31_dec_sub26_dec31_dec_sub26_is_32b), + .dec31_dec_sub26_ldst_len(dec31_dec_sub26_dec31_dec_sub26_ldst_len), + .dec31_dec_sub26_lk(dec31_dec_sub26_dec31_dec_sub26_lk), + .dec31_dec_sub26_out_sel(dec31_dec_sub26_dec31_dec_sub26_out_sel), + .dec31_dec_sub26_rc_sel(dec31_dec_sub26_dec31_dec_sub26_rc_sel), + .dec31_dec_sub26_rsrv(dec31_dec_sub26_dec31_dec_sub26_rsrv), + .dec31_dec_sub26_sgl_pipe(dec31_dec_sub26_dec31_dec_sub26_sgl_pipe), + .dec31_dec_sub26_sgn(dec31_dec_sub26_dec31_dec_sub26_sgn), + .dec31_dec_sub26_sgn_ext(dec31_dec_sub26_dec31_dec_sub26_sgn_ext), + .dec31_dec_sub26_sv_cr_in(dec31_dec_sub26_dec31_dec_sub26_sv_cr_in), + .dec31_dec_sub26_sv_cr_out(dec31_dec_sub26_dec31_dec_sub26_sv_cr_out), + .dec31_dec_sub26_sv_in1(dec31_dec_sub26_dec31_dec_sub26_sv_in1), + .dec31_dec_sub26_sv_in2(dec31_dec_sub26_dec31_dec_sub26_sv_in2), + .dec31_dec_sub26_sv_in3(dec31_dec_sub26_dec31_dec_sub26_sv_in3), + .dec31_dec_sub26_sv_out(dec31_dec_sub26_dec31_dec_sub26_sv_out), + .dec31_dec_sub26_sv_out2(dec31_dec_sub26_dec31_dec_sub26_sv_out2), + .dec31_dec_sub26_upd(dec31_dec_sub26_dec31_dec_sub26_upd), + .opcode_in(dec31_dec_sub26_opcode_in) + ); + dec31_dec_sub27 dec31_dec_sub27 ( + .dec31_dec_sub27_SV_Etype(dec31_dec_sub27_dec31_dec_sub27_SV_Etype), + .dec31_dec_sub27_SV_Ptype(dec31_dec_sub27_dec31_dec_sub27_SV_Ptype), + .dec31_dec_sub27_asmcode(dec31_dec_sub27_dec31_dec_sub27_asmcode), + .dec31_dec_sub27_br(dec31_dec_sub27_dec31_dec_sub27_br), + .dec31_dec_sub27_cr_in(dec31_dec_sub27_dec31_dec_sub27_cr_in), + .dec31_dec_sub27_cr_out(dec31_dec_sub27_dec31_dec_sub27_cr_out), + .dec31_dec_sub27_cry_in(dec31_dec_sub27_dec31_dec_sub27_cry_in), + .dec31_dec_sub27_cry_out(dec31_dec_sub27_dec31_dec_sub27_cry_out), + .dec31_dec_sub27_form(dec31_dec_sub27_dec31_dec_sub27_form), + .dec31_dec_sub27_function_unit(dec31_dec_sub27_dec31_dec_sub27_function_unit), + .dec31_dec_sub27_in1_sel(dec31_dec_sub27_dec31_dec_sub27_in1_sel), + .dec31_dec_sub27_in2_sel(dec31_dec_sub27_dec31_dec_sub27_in2_sel), + .dec31_dec_sub27_in3_sel(dec31_dec_sub27_dec31_dec_sub27_in3_sel), + .dec31_dec_sub27_internal_op(dec31_dec_sub27_dec31_dec_sub27_internal_op), + .dec31_dec_sub27_inv_a(dec31_dec_sub27_dec31_dec_sub27_inv_a), + .dec31_dec_sub27_inv_out(dec31_dec_sub27_dec31_dec_sub27_inv_out), + .dec31_dec_sub27_is_32b(dec31_dec_sub27_dec31_dec_sub27_is_32b), + .dec31_dec_sub27_ldst_len(dec31_dec_sub27_dec31_dec_sub27_ldst_len), + .dec31_dec_sub27_lk(dec31_dec_sub27_dec31_dec_sub27_lk), + .dec31_dec_sub27_out_sel(dec31_dec_sub27_dec31_dec_sub27_out_sel), + .dec31_dec_sub27_rc_sel(dec31_dec_sub27_dec31_dec_sub27_rc_sel), + .dec31_dec_sub27_rsrv(dec31_dec_sub27_dec31_dec_sub27_rsrv), + .dec31_dec_sub27_sgl_pipe(dec31_dec_sub27_dec31_dec_sub27_sgl_pipe), + .dec31_dec_sub27_sgn(dec31_dec_sub27_dec31_dec_sub27_sgn), + .dec31_dec_sub27_sgn_ext(dec31_dec_sub27_dec31_dec_sub27_sgn_ext), + .dec31_dec_sub27_sv_cr_in(dec31_dec_sub27_dec31_dec_sub27_sv_cr_in), + .dec31_dec_sub27_sv_cr_out(dec31_dec_sub27_dec31_dec_sub27_sv_cr_out), + .dec31_dec_sub27_sv_in1(dec31_dec_sub27_dec31_dec_sub27_sv_in1), + .dec31_dec_sub27_sv_in2(dec31_dec_sub27_dec31_dec_sub27_sv_in2), + .dec31_dec_sub27_sv_in3(dec31_dec_sub27_dec31_dec_sub27_sv_in3), + .dec31_dec_sub27_sv_out(dec31_dec_sub27_dec31_dec_sub27_sv_out), + .dec31_dec_sub27_sv_out2(dec31_dec_sub27_dec31_dec_sub27_sv_out2), + .dec31_dec_sub27_upd(dec31_dec_sub27_dec31_dec_sub27_upd), + .opcode_in(dec31_dec_sub27_opcode_in) + ); + dec31_dec_sub28 dec31_dec_sub28 ( + .dec31_dec_sub28_SV_Etype(dec31_dec_sub28_dec31_dec_sub28_SV_Etype), + .dec31_dec_sub28_SV_Ptype(dec31_dec_sub28_dec31_dec_sub28_SV_Ptype), + .dec31_dec_sub28_asmcode(dec31_dec_sub28_dec31_dec_sub28_asmcode), + .dec31_dec_sub28_br(dec31_dec_sub28_dec31_dec_sub28_br), + .dec31_dec_sub28_cr_in(dec31_dec_sub28_dec31_dec_sub28_cr_in), + .dec31_dec_sub28_cr_out(dec31_dec_sub28_dec31_dec_sub28_cr_out), + .dec31_dec_sub28_cry_in(dec31_dec_sub28_dec31_dec_sub28_cry_in), + .dec31_dec_sub28_cry_out(dec31_dec_sub28_dec31_dec_sub28_cry_out), + .dec31_dec_sub28_form(dec31_dec_sub28_dec31_dec_sub28_form), + .dec31_dec_sub28_function_unit(dec31_dec_sub28_dec31_dec_sub28_function_unit), + .dec31_dec_sub28_in1_sel(dec31_dec_sub28_dec31_dec_sub28_in1_sel), + .dec31_dec_sub28_in2_sel(dec31_dec_sub28_dec31_dec_sub28_in2_sel), + .dec31_dec_sub28_in3_sel(dec31_dec_sub28_dec31_dec_sub28_in3_sel), + .dec31_dec_sub28_internal_op(dec31_dec_sub28_dec31_dec_sub28_internal_op), + .dec31_dec_sub28_inv_a(dec31_dec_sub28_dec31_dec_sub28_inv_a), + .dec31_dec_sub28_inv_out(dec31_dec_sub28_dec31_dec_sub28_inv_out), + .dec31_dec_sub28_is_32b(dec31_dec_sub28_dec31_dec_sub28_is_32b), + .dec31_dec_sub28_ldst_len(dec31_dec_sub28_dec31_dec_sub28_ldst_len), + .dec31_dec_sub28_lk(dec31_dec_sub28_dec31_dec_sub28_lk), + .dec31_dec_sub28_out_sel(dec31_dec_sub28_dec31_dec_sub28_out_sel), + .dec31_dec_sub28_rc_sel(dec31_dec_sub28_dec31_dec_sub28_rc_sel), + .dec31_dec_sub28_rsrv(dec31_dec_sub28_dec31_dec_sub28_rsrv), + .dec31_dec_sub28_sgl_pipe(dec31_dec_sub28_dec31_dec_sub28_sgl_pipe), + .dec31_dec_sub28_sgn(dec31_dec_sub28_dec31_dec_sub28_sgn), + .dec31_dec_sub28_sgn_ext(dec31_dec_sub28_dec31_dec_sub28_sgn_ext), + .dec31_dec_sub28_sv_cr_in(dec31_dec_sub28_dec31_dec_sub28_sv_cr_in), + .dec31_dec_sub28_sv_cr_out(dec31_dec_sub28_dec31_dec_sub28_sv_cr_out), + .dec31_dec_sub28_sv_in1(dec31_dec_sub28_dec31_dec_sub28_sv_in1), + .dec31_dec_sub28_sv_in2(dec31_dec_sub28_dec31_dec_sub28_sv_in2), + .dec31_dec_sub28_sv_in3(dec31_dec_sub28_dec31_dec_sub28_sv_in3), + .dec31_dec_sub28_sv_out(dec31_dec_sub28_dec31_dec_sub28_sv_out), + .dec31_dec_sub28_sv_out2(dec31_dec_sub28_dec31_dec_sub28_sv_out2), + .dec31_dec_sub28_upd(dec31_dec_sub28_dec31_dec_sub28_upd), + .opcode_in(dec31_dec_sub28_opcode_in) + ); + dec31_dec_sub4 dec31_dec_sub4 ( + .dec31_dec_sub4_SV_Etype(dec31_dec_sub4_dec31_dec_sub4_SV_Etype), + .dec31_dec_sub4_SV_Ptype(dec31_dec_sub4_dec31_dec_sub4_SV_Ptype), + .dec31_dec_sub4_asmcode(dec31_dec_sub4_dec31_dec_sub4_asmcode), + .dec31_dec_sub4_br(dec31_dec_sub4_dec31_dec_sub4_br), + .dec31_dec_sub4_cr_in(dec31_dec_sub4_dec31_dec_sub4_cr_in), + .dec31_dec_sub4_cr_out(dec31_dec_sub4_dec31_dec_sub4_cr_out), + .dec31_dec_sub4_cry_in(dec31_dec_sub4_dec31_dec_sub4_cry_in), + .dec31_dec_sub4_cry_out(dec31_dec_sub4_dec31_dec_sub4_cry_out), + .dec31_dec_sub4_form(dec31_dec_sub4_dec31_dec_sub4_form), + .dec31_dec_sub4_function_unit(dec31_dec_sub4_dec31_dec_sub4_function_unit), + .dec31_dec_sub4_in1_sel(dec31_dec_sub4_dec31_dec_sub4_in1_sel), + .dec31_dec_sub4_in2_sel(dec31_dec_sub4_dec31_dec_sub4_in2_sel), + .dec31_dec_sub4_in3_sel(dec31_dec_sub4_dec31_dec_sub4_in3_sel), + .dec31_dec_sub4_internal_op(dec31_dec_sub4_dec31_dec_sub4_internal_op), + .dec31_dec_sub4_inv_a(dec31_dec_sub4_dec31_dec_sub4_inv_a), + .dec31_dec_sub4_inv_out(dec31_dec_sub4_dec31_dec_sub4_inv_out), + .dec31_dec_sub4_is_32b(dec31_dec_sub4_dec31_dec_sub4_is_32b), + .dec31_dec_sub4_ldst_len(dec31_dec_sub4_dec31_dec_sub4_ldst_len), + .dec31_dec_sub4_lk(dec31_dec_sub4_dec31_dec_sub4_lk), + .dec31_dec_sub4_out_sel(dec31_dec_sub4_dec31_dec_sub4_out_sel), + .dec31_dec_sub4_rc_sel(dec31_dec_sub4_dec31_dec_sub4_rc_sel), + .dec31_dec_sub4_rsrv(dec31_dec_sub4_dec31_dec_sub4_rsrv), + .dec31_dec_sub4_sgl_pipe(dec31_dec_sub4_dec31_dec_sub4_sgl_pipe), + .dec31_dec_sub4_sgn(dec31_dec_sub4_dec31_dec_sub4_sgn), + .dec31_dec_sub4_sgn_ext(dec31_dec_sub4_dec31_dec_sub4_sgn_ext), + .dec31_dec_sub4_sv_cr_in(dec31_dec_sub4_dec31_dec_sub4_sv_cr_in), + .dec31_dec_sub4_sv_cr_out(dec31_dec_sub4_dec31_dec_sub4_sv_cr_out), + .dec31_dec_sub4_sv_in1(dec31_dec_sub4_dec31_dec_sub4_sv_in1), + .dec31_dec_sub4_sv_in2(dec31_dec_sub4_dec31_dec_sub4_sv_in2), + .dec31_dec_sub4_sv_in3(dec31_dec_sub4_dec31_dec_sub4_sv_in3), + .dec31_dec_sub4_sv_out(dec31_dec_sub4_dec31_dec_sub4_sv_out), + .dec31_dec_sub4_sv_out2(dec31_dec_sub4_dec31_dec_sub4_sv_out2), + .dec31_dec_sub4_upd(dec31_dec_sub4_dec31_dec_sub4_upd), + .opcode_in(dec31_dec_sub4_opcode_in) + ); + dec31_dec_sub8 dec31_dec_sub8 ( + .dec31_dec_sub8_SV_Etype(dec31_dec_sub8_dec31_dec_sub8_SV_Etype), + .dec31_dec_sub8_SV_Ptype(dec31_dec_sub8_dec31_dec_sub8_SV_Ptype), + .dec31_dec_sub8_asmcode(dec31_dec_sub8_dec31_dec_sub8_asmcode), + .dec31_dec_sub8_br(dec31_dec_sub8_dec31_dec_sub8_br), + .dec31_dec_sub8_cr_in(dec31_dec_sub8_dec31_dec_sub8_cr_in), + .dec31_dec_sub8_cr_out(dec31_dec_sub8_dec31_dec_sub8_cr_out), + .dec31_dec_sub8_cry_in(dec31_dec_sub8_dec31_dec_sub8_cry_in), + .dec31_dec_sub8_cry_out(dec31_dec_sub8_dec31_dec_sub8_cry_out), + .dec31_dec_sub8_form(dec31_dec_sub8_dec31_dec_sub8_form), + .dec31_dec_sub8_function_unit(dec31_dec_sub8_dec31_dec_sub8_function_unit), + .dec31_dec_sub8_in1_sel(dec31_dec_sub8_dec31_dec_sub8_in1_sel), + .dec31_dec_sub8_in2_sel(dec31_dec_sub8_dec31_dec_sub8_in2_sel), + .dec31_dec_sub8_in3_sel(dec31_dec_sub8_dec31_dec_sub8_in3_sel), + .dec31_dec_sub8_internal_op(dec31_dec_sub8_dec31_dec_sub8_internal_op), + .dec31_dec_sub8_inv_a(dec31_dec_sub8_dec31_dec_sub8_inv_a), + .dec31_dec_sub8_inv_out(dec31_dec_sub8_dec31_dec_sub8_inv_out), + .dec31_dec_sub8_is_32b(dec31_dec_sub8_dec31_dec_sub8_is_32b), + .dec31_dec_sub8_ldst_len(dec31_dec_sub8_dec31_dec_sub8_ldst_len), + .dec31_dec_sub8_lk(dec31_dec_sub8_dec31_dec_sub8_lk), + .dec31_dec_sub8_out_sel(dec31_dec_sub8_dec31_dec_sub8_out_sel), + .dec31_dec_sub8_rc_sel(dec31_dec_sub8_dec31_dec_sub8_rc_sel), + .dec31_dec_sub8_rsrv(dec31_dec_sub8_dec31_dec_sub8_rsrv), + .dec31_dec_sub8_sgl_pipe(dec31_dec_sub8_dec31_dec_sub8_sgl_pipe), + .dec31_dec_sub8_sgn(dec31_dec_sub8_dec31_dec_sub8_sgn), + .dec31_dec_sub8_sgn_ext(dec31_dec_sub8_dec31_dec_sub8_sgn_ext), + .dec31_dec_sub8_sv_cr_in(dec31_dec_sub8_dec31_dec_sub8_sv_cr_in), + .dec31_dec_sub8_sv_cr_out(dec31_dec_sub8_dec31_dec_sub8_sv_cr_out), + .dec31_dec_sub8_sv_in1(dec31_dec_sub8_dec31_dec_sub8_sv_in1), + .dec31_dec_sub8_sv_in2(dec31_dec_sub8_dec31_dec_sub8_sv_in2), + .dec31_dec_sub8_sv_in3(dec31_dec_sub8_dec31_dec_sub8_sv_in3), + .dec31_dec_sub8_sv_out(dec31_dec_sub8_dec31_dec_sub8_sv_out), + .dec31_dec_sub8_sv_out2(dec31_dec_sub8_dec31_dec_sub8_sv_out2), + .dec31_dec_sub8_upd(dec31_dec_sub8_dec31_dec_sub8_upd), + .opcode_in(dec31_dec_sub8_opcode_in) + ); + dec31_dec_sub9 dec31_dec_sub9 ( + .dec31_dec_sub9_SV_Etype(dec31_dec_sub9_dec31_dec_sub9_SV_Etype), + .dec31_dec_sub9_SV_Ptype(dec31_dec_sub9_dec31_dec_sub9_SV_Ptype), + .dec31_dec_sub9_asmcode(dec31_dec_sub9_dec31_dec_sub9_asmcode), + .dec31_dec_sub9_br(dec31_dec_sub9_dec31_dec_sub9_br), + .dec31_dec_sub9_cr_in(dec31_dec_sub9_dec31_dec_sub9_cr_in), + .dec31_dec_sub9_cr_out(dec31_dec_sub9_dec31_dec_sub9_cr_out), + .dec31_dec_sub9_cry_in(dec31_dec_sub9_dec31_dec_sub9_cry_in), + .dec31_dec_sub9_cry_out(dec31_dec_sub9_dec31_dec_sub9_cry_out), + .dec31_dec_sub9_form(dec31_dec_sub9_dec31_dec_sub9_form), + .dec31_dec_sub9_function_unit(dec31_dec_sub9_dec31_dec_sub9_function_unit), + .dec31_dec_sub9_in1_sel(dec31_dec_sub9_dec31_dec_sub9_in1_sel), + .dec31_dec_sub9_in2_sel(dec31_dec_sub9_dec31_dec_sub9_in2_sel), + .dec31_dec_sub9_in3_sel(dec31_dec_sub9_dec31_dec_sub9_in3_sel), + .dec31_dec_sub9_internal_op(dec31_dec_sub9_dec31_dec_sub9_internal_op), + .dec31_dec_sub9_inv_a(dec31_dec_sub9_dec31_dec_sub9_inv_a), + .dec31_dec_sub9_inv_out(dec31_dec_sub9_dec31_dec_sub9_inv_out), + .dec31_dec_sub9_is_32b(dec31_dec_sub9_dec31_dec_sub9_is_32b), + .dec31_dec_sub9_ldst_len(dec31_dec_sub9_dec31_dec_sub9_ldst_len), + .dec31_dec_sub9_lk(dec31_dec_sub9_dec31_dec_sub9_lk), + .dec31_dec_sub9_out_sel(dec31_dec_sub9_dec31_dec_sub9_out_sel), + .dec31_dec_sub9_rc_sel(dec31_dec_sub9_dec31_dec_sub9_rc_sel), + .dec31_dec_sub9_rsrv(dec31_dec_sub9_dec31_dec_sub9_rsrv), + .dec31_dec_sub9_sgl_pipe(dec31_dec_sub9_dec31_dec_sub9_sgl_pipe), + .dec31_dec_sub9_sgn(dec31_dec_sub9_dec31_dec_sub9_sgn), + .dec31_dec_sub9_sgn_ext(dec31_dec_sub9_dec31_dec_sub9_sgn_ext), + .dec31_dec_sub9_sv_cr_in(dec31_dec_sub9_dec31_dec_sub9_sv_cr_in), + .dec31_dec_sub9_sv_cr_out(dec31_dec_sub9_dec31_dec_sub9_sv_cr_out), + .dec31_dec_sub9_sv_in1(dec31_dec_sub9_dec31_dec_sub9_sv_in1), + .dec31_dec_sub9_sv_in2(dec31_dec_sub9_dec31_dec_sub9_sv_in2), + .dec31_dec_sub9_sv_in3(dec31_dec_sub9_dec31_dec_sub9_sv_in3), + .dec31_dec_sub9_sv_out(dec31_dec_sub9_dec31_dec_sub9_sv_out), + .dec31_dec_sub9_sv_out2(dec31_dec_sub9_dec31_dec_sub9_sv_out2), + .dec31_dec_sub9_upd(dec31_dec_sub9_dec31_dec_sub9_upd), + .opcode_in(dec31_dec_sub9_opcode_in) + ); + always @* begin + if (\initial ) begin end + dec31_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_function_unit = dec31_dec_sub10_dec31_dec_sub10_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_function_unit = dec31_dec_sub28_dec31_dec_sub28_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_function_unit = dec31_dec_sub0_dec31_dec_sub0_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_function_unit = dec31_dec_sub26_dec31_dec_sub26_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_function_unit = dec31_dec_sub19_dec31_dec_sub19_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_function_unit = dec31_dec_sub22_dec31_dec_sub22_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_function_unit = dec31_dec_sub9_dec31_dec_sub9_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_function_unit = dec31_dec_sub11_dec31_dec_sub11_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_function_unit = dec31_dec_sub27_dec31_dec_sub27_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_function_unit = dec31_dec_sub15_dec31_dec_sub15_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_function_unit = dec31_dec_sub20_dec31_dec_sub20_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_function_unit = dec31_dec_sub21_dec31_dec_sub21_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_function_unit = dec31_dec_sub23_dec31_dec_sub23_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_function_unit = dec31_dec_sub16_dec31_dec_sub16_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_function_unit = dec31_dec_sub18_dec31_dec_sub18_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_function_unit = dec31_dec_sub8_dec31_dec_sub8_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_function_unit = dec31_dec_sub24_dec31_dec_sub24_function_unit; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_function_unit = dec31_dec_sub4_dec31_dec_sub4_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + dec31_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_internal_op = dec31_dec_sub10_dec31_dec_sub10_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_internal_op = dec31_dec_sub28_dec31_dec_sub28_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_internal_op = dec31_dec_sub0_dec31_dec_sub0_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_internal_op = dec31_dec_sub26_dec31_dec_sub26_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_internal_op = dec31_dec_sub19_dec31_dec_sub19_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_internal_op = dec31_dec_sub22_dec31_dec_sub22_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_internal_op = dec31_dec_sub9_dec31_dec_sub9_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_internal_op = dec31_dec_sub11_dec31_dec_sub11_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_internal_op = dec31_dec_sub27_dec31_dec_sub27_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_internal_op = dec31_dec_sub15_dec31_dec_sub15_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_internal_op = dec31_dec_sub20_dec31_dec_sub20_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_internal_op = dec31_dec_sub21_dec31_dec_sub21_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_internal_op = dec31_dec_sub23_dec31_dec_sub23_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_internal_op = dec31_dec_sub16_dec31_dec_sub16_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_internal_op = dec31_dec_sub18_dec31_dec_sub18_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_internal_op = dec31_dec_sub8_dec31_dec_sub8_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_internal_op = dec31_dec_sub24_dec31_dec_sub24_internal_op; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_internal_op = dec31_dec_sub4_dec31_dec_sub4_internal_op; + endcase + end + always @* begin + if (\initial ) begin end + dec31_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_form = dec31_dec_sub10_dec31_dec_sub10_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_form = dec31_dec_sub28_dec31_dec_sub28_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_form = dec31_dec_sub0_dec31_dec_sub0_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_form = dec31_dec_sub26_dec31_dec_sub26_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_form = dec31_dec_sub19_dec31_dec_sub19_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_form = dec31_dec_sub22_dec31_dec_sub22_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_form = dec31_dec_sub9_dec31_dec_sub9_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_form = dec31_dec_sub11_dec31_dec_sub11_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_form = dec31_dec_sub27_dec31_dec_sub27_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_form = dec31_dec_sub15_dec31_dec_sub15_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_form = dec31_dec_sub20_dec31_dec_sub20_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_form = dec31_dec_sub21_dec31_dec_sub21_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_form = dec31_dec_sub23_dec31_dec_sub23_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_form = dec31_dec_sub16_dec31_dec_sub16_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_form = dec31_dec_sub18_dec31_dec_sub18_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_form = dec31_dec_sub8_dec31_dec_sub8_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_form = dec31_dec_sub24_dec31_dec_sub24_form; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_form = dec31_dec_sub4_dec31_dec_sub4_form; + endcase + end + always @* begin + if (\initial ) begin end + dec31_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_asmcode = dec31_dec_sub10_dec31_dec_sub10_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_asmcode = dec31_dec_sub28_dec31_dec_sub28_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_asmcode = dec31_dec_sub0_dec31_dec_sub0_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_asmcode = dec31_dec_sub26_dec31_dec_sub26_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_asmcode = dec31_dec_sub19_dec31_dec_sub19_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_asmcode = dec31_dec_sub22_dec31_dec_sub22_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_asmcode = dec31_dec_sub9_dec31_dec_sub9_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_asmcode = dec31_dec_sub11_dec31_dec_sub11_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_asmcode = dec31_dec_sub27_dec31_dec_sub27_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_asmcode = dec31_dec_sub15_dec31_dec_sub15_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_asmcode = dec31_dec_sub20_dec31_dec_sub20_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_asmcode = dec31_dec_sub21_dec31_dec_sub21_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_asmcode = dec31_dec_sub23_dec31_dec_sub23_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_asmcode = dec31_dec_sub16_dec31_dec_sub16_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_asmcode = dec31_dec_sub18_dec31_dec_sub18_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_asmcode = dec31_dec_sub8_dec31_dec_sub8_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_asmcode = dec31_dec_sub24_dec31_dec_sub24_asmcode; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_asmcode = dec31_dec_sub4_dec31_dec_sub4_asmcode; + endcase + end + always @* begin + if (\initial ) begin end + dec31_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_SV_Etype = dec31_dec_sub10_dec31_dec_sub10_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_SV_Etype = dec31_dec_sub28_dec31_dec_sub28_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_SV_Etype = dec31_dec_sub0_dec31_dec_sub0_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_SV_Etype = dec31_dec_sub26_dec31_dec_sub26_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_SV_Etype = dec31_dec_sub19_dec31_dec_sub19_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_SV_Etype = dec31_dec_sub22_dec31_dec_sub22_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_SV_Etype = dec31_dec_sub9_dec31_dec_sub9_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_SV_Etype = dec31_dec_sub11_dec31_dec_sub11_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_SV_Etype = dec31_dec_sub27_dec31_dec_sub27_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_SV_Etype = dec31_dec_sub15_dec31_dec_sub15_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_SV_Etype = dec31_dec_sub20_dec31_dec_sub20_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_SV_Etype = dec31_dec_sub21_dec31_dec_sub21_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_SV_Etype = dec31_dec_sub23_dec31_dec_sub23_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_SV_Etype = dec31_dec_sub16_dec31_dec_sub16_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_SV_Etype = dec31_dec_sub18_dec31_dec_sub18_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_SV_Etype = dec31_dec_sub8_dec31_dec_sub8_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_SV_Etype = dec31_dec_sub24_dec31_dec_sub24_SV_Etype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_SV_Etype = dec31_dec_sub4_dec31_dec_sub4_SV_Etype; + endcase + end + always @* begin + if (\initial ) begin end + dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_SV_Ptype = dec31_dec_sub10_dec31_dec_sub10_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_SV_Ptype = dec31_dec_sub28_dec31_dec_sub28_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_SV_Ptype = dec31_dec_sub0_dec31_dec_sub0_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_SV_Ptype = dec31_dec_sub26_dec31_dec_sub26_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_SV_Ptype = dec31_dec_sub19_dec31_dec_sub19_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_SV_Ptype = dec31_dec_sub22_dec31_dec_sub22_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_SV_Ptype = dec31_dec_sub9_dec31_dec_sub9_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_SV_Ptype = dec31_dec_sub11_dec31_dec_sub11_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_SV_Ptype = dec31_dec_sub27_dec31_dec_sub27_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_SV_Ptype = dec31_dec_sub15_dec31_dec_sub15_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_SV_Ptype = dec31_dec_sub20_dec31_dec_sub20_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_SV_Ptype = dec31_dec_sub21_dec31_dec_sub21_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_SV_Ptype = dec31_dec_sub23_dec31_dec_sub23_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_SV_Ptype = dec31_dec_sub16_dec31_dec_sub16_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_SV_Ptype = dec31_dec_sub18_dec31_dec_sub18_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_SV_Ptype = dec31_dec_sub8_dec31_dec_sub8_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_SV_Ptype = dec31_dec_sub24_dec31_dec_sub24_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_SV_Ptype = dec31_dec_sub4_dec31_dec_sub4_SV_Ptype; + endcase + end + always @* begin + if (\initial ) begin end + dec31_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_in1_sel = dec31_dec_sub10_dec31_dec_sub10_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_in1_sel = dec31_dec_sub28_dec31_dec_sub28_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_in1_sel = dec31_dec_sub0_dec31_dec_sub0_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_in1_sel = dec31_dec_sub26_dec31_dec_sub26_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_in1_sel = dec31_dec_sub19_dec31_dec_sub19_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_in1_sel = dec31_dec_sub22_dec31_dec_sub22_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_in1_sel = dec31_dec_sub9_dec31_dec_sub9_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_in1_sel = dec31_dec_sub11_dec31_dec_sub11_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_in1_sel = dec31_dec_sub27_dec31_dec_sub27_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_in1_sel = dec31_dec_sub15_dec31_dec_sub15_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_in1_sel = dec31_dec_sub20_dec31_dec_sub20_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_in1_sel = dec31_dec_sub21_dec31_dec_sub21_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_in1_sel = dec31_dec_sub23_dec31_dec_sub23_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_in1_sel = dec31_dec_sub16_dec31_dec_sub16_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_in1_sel = dec31_dec_sub18_dec31_dec_sub18_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_in1_sel = dec31_dec_sub8_dec31_dec_sub8_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_in1_sel = dec31_dec_sub24_dec31_dec_sub24_in1_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_in1_sel = dec31_dec_sub4_dec31_dec_sub4_in1_sel; + endcase + end + always @* begin + if (\initial ) begin end + dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_in2_sel = dec31_dec_sub10_dec31_dec_sub10_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_in2_sel = dec31_dec_sub28_dec31_dec_sub28_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_in2_sel = dec31_dec_sub0_dec31_dec_sub0_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_in2_sel = dec31_dec_sub26_dec31_dec_sub26_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_in2_sel = dec31_dec_sub19_dec31_dec_sub19_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_in2_sel = dec31_dec_sub22_dec31_dec_sub22_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_in2_sel = dec31_dec_sub9_dec31_dec_sub9_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_in2_sel = dec31_dec_sub11_dec31_dec_sub11_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_in2_sel = dec31_dec_sub27_dec31_dec_sub27_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_in2_sel = dec31_dec_sub15_dec31_dec_sub15_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_in2_sel = dec31_dec_sub20_dec31_dec_sub20_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_in2_sel = dec31_dec_sub21_dec31_dec_sub21_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_in2_sel = dec31_dec_sub23_dec31_dec_sub23_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_in2_sel = dec31_dec_sub16_dec31_dec_sub16_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_in2_sel = dec31_dec_sub18_dec31_dec_sub18_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_in2_sel = dec31_dec_sub8_dec31_dec_sub8_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_in2_sel = dec31_dec_sub24_dec31_dec_sub24_in2_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_in2_sel = dec31_dec_sub4_dec31_dec_sub4_in2_sel; + endcase + end + always @* begin + if (\initial ) begin end + dec31_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_in3_sel = dec31_dec_sub10_dec31_dec_sub10_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_in3_sel = dec31_dec_sub28_dec31_dec_sub28_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_in3_sel = dec31_dec_sub0_dec31_dec_sub0_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_in3_sel = dec31_dec_sub26_dec31_dec_sub26_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_in3_sel = dec31_dec_sub19_dec31_dec_sub19_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_in3_sel = dec31_dec_sub22_dec31_dec_sub22_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_in3_sel = dec31_dec_sub9_dec31_dec_sub9_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_in3_sel = dec31_dec_sub11_dec31_dec_sub11_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_in3_sel = dec31_dec_sub27_dec31_dec_sub27_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_in3_sel = dec31_dec_sub15_dec31_dec_sub15_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_in3_sel = dec31_dec_sub20_dec31_dec_sub20_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_in3_sel = dec31_dec_sub21_dec31_dec_sub21_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_in3_sel = dec31_dec_sub23_dec31_dec_sub23_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_in3_sel = dec31_dec_sub16_dec31_dec_sub16_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_in3_sel = dec31_dec_sub18_dec31_dec_sub18_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_in3_sel = dec31_dec_sub8_dec31_dec_sub8_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_in3_sel = dec31_dec_sub24_dec31_dec_sub24_in3_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_in3_sel = dec31_dec_sub4_dec31_dec_sub4_in3_sel; + endcase + end + always @* begin + if (\initial ) begin end + dec31_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_out_sel = dec31_dec_sub10_dec31_dec_sub10_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_out_sel = dec31_dec_sub28_dec31_dec_sub28_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_out_sel = dec31_dec_sub0_dec31_dec_sub0_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_out_sel = dec31_dec_sub26_dec31_dec_sub26_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_out_sel = dec31_dec_sub19_dec31_dec_sub19_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_out_sel = dec31_dec_sub22_dec31_dec_sub22_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_out_sel = dec31_dec_sub9_dec31_dec_sub9_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_out_sel = dec31_dec_sub11_dec31_dec_sub11_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_out_sel = dec31_dec_sub27_dec31_dec_sub27_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_out_sel = dec31_dec_sub15_dec31_dec_sub15_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_out_sel = dec31_dec_sub20_dec31_dec_sub20_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_out_sel = dec31_dec_sub21_dec31_dec_sub21_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_out_sel = dec31_dec_sub23_dec31_dec_sub23_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_out_sel = dec31_dec_sub16_dec31_dec_sub16_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_out_sel = dec31_dec_sub18_dec31_dec_sub18_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_out_sel = dec31_dec_sub8_dec31_dec_sub8_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_out_sel = dec31_dec_sub24_dec31_dec_sub24_out_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_out_sel = dec31_dec_sub4_dec31_dec_sub4_out_sel; + endcase + end + always @* begin + if (\initial ) begin end + dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_cr_in = dec31_dec_sub10_dec31_dec_sub10_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_cr_in = dec31_dec_sub28_dec31_dec_sub28_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_cr_in = dec31_dec_sub0_dec31_dec_sub0_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_cr_in = dec31_dec_sub26_dec31_dec_sub26_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_cr_in = dec31_dec_sub19_dec31_dec_sub19_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_cr_in = dec31_dec_sub22_dec31_dec_sub22_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_cr_in = dec31_dec_sub9_dec31_dec_sub9_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_cr_in = dec31_dec_sub11_dec31_dec_sub11_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_cr_in = dec31_dec_sub27_dec31_dec_sub27_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_cr_in = dec31_dec_sub15_dec31_dec_sub15_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_cr_in = dec31_dec_sub20_dec31_dec_sub20_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_cr_in = dec31_dec_sub21_dec31_dec_sub21_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_cr_in = dec31_dec_sub23_dec31_dec_sub23_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_cr_in = dec31_dec_sub16_dec31_dec_sub16_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_cr_in = dec31_dec_sub18_dec31_dec_sub18_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_cr_in = dec31_dec_sub8_dec31_dec_sub8_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_cr_in = dec31_dec_sub24_dec31_dec_sub24_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_cr_in = dec31_dec_sub4_dec31_dec_sub4_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_cr_out = dec31_dec_sub10_dec31_dec_sub10_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_cr_out = dec31_dec_sub28_dec31_dec_sub28_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_cr_out = dec31_dec_sub0_dec31_dec_sub0_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_cr_out = dec31_dec_sub26_dec31_dec_sub26_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_cr_out = dec31_dec_sub19_dec31_dec_sub19_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_cr_out = dec31_dec_sub22_dec31_dec_sub22_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_cr_out = dec31_dec_sub9_dec31_dec_sub9_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_cr_out = dec31_dec_sub11_dec31_dec_sub11_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_cr_out = dec31_dec_sub27_dec31_dec_sub27_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_cr_out = dec31_dec_sub15_dec31_dec_sub15_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_cr_out = dec31_dec_sub20_dec31_dec_sub20_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_cr_out = dec31_dec_sub21_dec31_dec_sub21_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_cr_out = dec31_dec_sub23_dec31_dec_sub23_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_cr_out = dec31_dec_sub16_dec31_dec_sub16_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_cr_out = dec31_dec_sub18_dec31_dec_sub18_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_cr_out = dec31_dec_sub8_dec31_dec_sub8_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_cr_out = dec31_dec_sub24_dec31_dec_sub24_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_cr_out = dec31_dec_sub4_dec31_dec_sub4_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sv_in1 = dec31_dec_sub10_dec31_dec_sub10_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sv_in1 = dec31_dec_sub28_dec31_dec_sub28_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sv_in1 = dec31_dec_sub0_dec31_dec_sub0_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sv_in1 = dec31_dec_sub26_dec31_dec_sub26_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sv_in1 = dec31_dec_sub19_dec31_dec_sub19_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sv_in1 = dec31_dec_sub22_dec31_dec_sub22_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sv_in1 = dec31_dec_sub9_dec31_dec_sub9_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sv_in1 = dec31_dec_sub11_dec31_dec_sub11_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sv_in1 = dec31_dec_sub27_dec31_dec_sub27_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sv_in1 = dec31_dec_sub15_dec31_dec_sub15_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sv_in1 = dec31_dec_sub20_dec31_dec_sub20_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sv_in1 = dec31_dec_sub21_dec31_dec_sub21_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sv_in1 = dec31_dec_sub23_dec31_dec_sub23_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sv_in1 = dec31_dec_sub16_dec31_dec_sub16_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sv_in1 = dec31_dec_sub18_dec31_dec_sub18_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sv_in1 = dec31_dec_sub8_dec31_dec_sub8_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sv_in1 = dec31_dec_sub24_dec31_dec_sub24_sv_in1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sv_in1 = dec31_dec_sub4_dec31_dec_sub4_sv_in1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sv_in2 = dec31_dec_sub10_dec31_dec_sub10_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sv_in2 = dec31_dec_sub28_dec31_dec_sub28_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sv_in2 = dec31_dec_sub0_dec31_dec_sub0_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sv_in2 = dec31_dec_sub26_dec31_dec_sub26_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sv_in2 = dec31_dec_sub19_dec31_dec_sub19_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sv_in2 = dec31_dec_sub22_dec31_dec_sub22_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sv_in2 = dec31_dec_sub9_dec31_dec_sub9_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sv_in2 = dec31_dec_sub11_dec31_dec_sub11_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sv_in2 = dec31_dec_sub27_dec31_dec_sub27_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sv_in2 = dec31_dec_sub15_dec31_dec_sub15_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sv_in2 = dec31_dec_sub20_dec31_dec_sub20_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sv_in2 = dec31_dec_sub21_dec31_dec_sub21_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sv_in2 = dec31_dec_sub23_dec31_dec_sub23_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sv_in2 = dec31_dec_sub16_dec31_dec_sub16_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sv_in2 = dec31_dec_sub18_dec31_dec_sub18_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sv_in2 = dec31_dec_sub8_dec31_dec_sub8_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sv_in2 = dec31_dec_sub24_dec31_dec_sub24_sv_in2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sv_in2 = dec31_dec_sub4_dec31_dec_sub4_sv_in2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sv_in3 = dec31_dec_sub10_dec31_dec_sub10_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sv_in3 = dec31_dec_sub28_dec31_dec_sub28_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sv_in3 = dec31_dec_sub0_dec31_dec_sub0_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sv_in3 = dec31_dec_sub26_dec31_dec_sub26_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sv_in3 = dec31_dec_sub19_dec31_dec_sub19_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sv_in3 = dec31_dec_sub22_dec31_dec_sub22_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sv_in3 = dec31_dec_sub9_dec31_dec_sub9_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sv_in3 = dec31_dec_sub11_dec31_dec_sub11_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sv_in3 = dec31_dec_sub27_dec31_dec_sub27_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sv_in3 = dec31_dec_sub15_dec31_dec_sub15_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sv_in3 = dec31_dec_sub20_dec31_dec_sub20_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sv_in3 = dec31_dec_sub21_dec31_dec_sub21_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sv_in3 = dec31_dec_sub23_dec31_dec_sub23_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sv_in3 = dec31_dec_sub16_dec31_dec_sub16_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sv_in3 = dec31_dec_sub18_dec31_dec_sub18_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sv_in3 = dec31_dec_sub8_dec31_dec_sub8_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sv_in3 = dec31_dec_sub24_dec31_dec_sub24_sv_in3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sv_in3 = dec31_dec_sub4_dec31_dec_sub4_sv_in3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sv_out = dec31_dec_sub10_dec31_dec_sub10_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sv_out = dec31_dec_sub28_dec31_dec_sub28_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sv_out = dec31_dec_sub0_dec31_dec_sub0_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sv_out = dec31_dec_sub26_dec31_dec_sub26_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sv_out = dec31_dec_sub19_dec31_dec_sub19_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sv_out = dec31_dec_sub22_dec31_dec_sub22_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sv_out = dec31_dec_sub9_dec31_dec_sub9_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sv_out = dec31_dec_sub11_dec31_dec_sub11_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sv_out = dec31_dec_sub27_dec31_dec_sub27_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sv_out = dec31_dec_sub15_dec31_dec_sub15_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sv_out = dec31_dec_sub20_dec31_dec_sub20_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sv_out = dec31_dec_sub21_dec31_dec_sub21_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sv_out = dec31_dec_sub23_dec31_dec_sub23_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sv_out = dec31_dec_sub16_dec31_dec_sub16_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sv_out = dec31_dec_sub18_dec31_dec_sub18_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sv_out = dec31_dec_sub8_dec31_dec_sub8_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sv_out = dec31_dec_sub24_dec31_dec_sub24_sv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sv_out = dec31_dec_sub4_dec31_dec_sub4_sv_out; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sv_out2 = dec31_dec_sub10_dec31_dec_sub10_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sv_out2 = dec31_dec_sub28_dec31_dec_sub28_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sv_out2 = dec31_dec_sub0_dec31_dec_sub0_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sv_out2 = dec31_dec_sub26_dec31_dec_sub26_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sv_out2 = dec31_dec_sub19_dec31_dec_sub19_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sv_out2 = dec31_dec_sub22_dec31_dec_sub22_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sv_out2 = dec31_dec_sub9_dec31_dec_sub9_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sv_out2 = dec31_dec_sub11_dec31_dec_sub11_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sv_out2 = dec31_dec_sub27_dec31_dec_sub27_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sv_out2 = dec31_dec_sub15_dec31_dec_sub15_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sv_out2 = dec31_dec_sub20_dec31_dec_sub20_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sv_out2 = dec31_dec_sub21_dec31_dec_sub21_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sv_out2 = dec31_dec_sub23_dec31_dec_sub23_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sv_out2 = dec31_dec_sub16_dec31_dec_sub16_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sv_out2 = dec31_dec_sub18_dec31_dec_sub18_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sv_out2 = dec31_dec_sub8_dec31_dec_sub8_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sv_out2 = dec31_dec_sub24_dec31_dec_sub24_sv_out2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sv_out2 = dec31_dec_sub4_dec31_dec_sub4_sv_out2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sv_cr_in = dec31_dec_sub10_dec31_dec_sub10_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sv_cr_in = dec31_dec_sub28_dec31_dec_sub28_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sv_cr_in = dec31_dec_sub0_dec31_dec_sub0_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sv_cr_in = dec31_dec_sub26_dec31_dec_sub26_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sv_cr_in = dec31_dec_sub19_dec31_dec_sub19_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sv_cr_in = dec31_dec_sub22_dec31_dec_sub22_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sv_cr_in = dec31_dec_sub9_dec31_dec_sub9_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sv_cr_in = dec31_dec_sub11_dec31_dec_sub11_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sv_cr_in = dec31_dec_sub27_dec31_dec_sub27_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sv_cr_in = dec31_dec_sub15_dec31_dec_sub15_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sv_cr_in = dec31_dec_sub20_dec31_dec_sub20_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sv_cr_in = dec31_dec_sub21_dec31_dec_sub21_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sv_cr_in = dec31_dec_sub23_dec31_dec_sub23_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sv_cr_in = dec31_dec_sub16_dec31_dec_sub16_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sv_cr_in = dec31_dec_sub18_dec31_dec_sub18_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sv_cr_in = dec31_dec_sub8_dec31_dec_sub8_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sv_cr_in = dec31_dec_sub24_dec31_dec_sub24_sv_cr_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sv_cr_in = dec31_dec_sub4_dec31_dec_sub4_sv_cr_in; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sv_cr_out = dec31_dec_sub10_dec31_dec_sub10_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sv_cr_out = dec31_dec_sub28_dec31_dec_sub28_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sv_cr_out = dec31_dec_sub0_dec31_dec_sub0_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sv_cr_out = dec31_dec_sub26_dec31_dec_sub26_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sv_cr_out = dec31_dec_sub19_dec31_dec_sub19_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sv_cr_out = dec31_dec_sub22_dec31_dec_sub22_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sv_cr_out = dec31_dec_sub9_dec31_dec_sub9_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sv_cr_out = dec31_dec_sub11_dec31_dec_sub11_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sv_cr_out = dec31_dec_sub27_dec31_dec_sub27_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sv_cr_out = dec31_dec_sub15_dec31_dec_sub15_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sv_cr_out = dec31_dec_sub20_dec31_dec_sub20_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sv_cr_out = dec31_dec_sub21_dec31_dec_sub21_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sv_cr_out = dec31_dec_sub23_dec31_dec_sub23_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sv_cr_out = dec31_dec_sub16_dec31_dec_sub16_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sv_cr_out = dec31_dec_sub18_dec31_dec_sub18_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sv_cr_out = dec31_dec_sub8_dec31_dec_sub8_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sv_cr_out = dec31_dec_sub24_dec31_dec_sub24_sv_cr_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sv_cr_out = dec31_dec_sub4_dec31_dec_sub4_sv_cr_out; + endcase + end + always @* begin + if (\initial ) begin end + dec31_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_ldst_len = dec31_dec_sub10_dec31_dec_sub10_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_ldst_len = dec31_dec_sub28_dec31_dec_sub28_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_ldst_len = dec31_dec_sub0_dec31_dec_sub0_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_ldst_len = dec31_dec_sub26_dec31_dec_sub26_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_ldst_len = dec31_dec_sub19_dec31_dec_sub19_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_ldst_len = dec31_dec_sub22_dec31_dec_sub22_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_ldst_len = dec31_dec_sub9_dec31_dec_sub9_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_ldst_len = dec31_dec_sub11_dec31_dec_sub11_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_ldst_len = dec31_dec_sub27_dec31_dec_sub27_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_ldst_len = dec31_dec_sub15_dec31_dec_sub15_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_ldst_len = dec31_dec_sub20_dec31_dec_sub20_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_ldst_len = dec31_dec_sub21_dec31_dec_sub21_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_ldst_len = dec31_dec_sub23_dec31_dec_sub23_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_ldst_len = dec31_dec_sub16_dec31_dec_sub16_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_ldst_len = dec31_dec_sub18_dec31_dec_sub18_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_ldst_len = dec31_dec_sub8_dec31_dec_sub8_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_ldst_len = dec31_dec_sub24_dec31_dec_sub24_ldst_len; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_ldst_len = dec31_dec_sub4_dec31_dec_sub4_ldst_len; + endcase + end + always @* begin + if (\initial ) begin end + dec31_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_upd = dec31_dec_sub10_dec31_dec_sub10_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_upd = dec31_dec_sub28_dec31_dec_sub28_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_upd = dec31_dec_sub0_dec31_dec_sub0_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_upd = dec31_dec_sub26_dec31_dec_sub26_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_upd = dec31_dec_sub19_dec31_dec_sub19_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_upd = dec31_dec_sub22_dec31_dec_sub22_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_upd = dec31_dec_sub9_dec31_dec_sub9_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_upd = dec31_dec_sub11_dec31_dec_sub11_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_upd = dec31_dec_sub27_dec31_dec_sub27_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_upd = dec31_dec_sub15_dec31_dec_sub15_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_upd = dec31_dec_sub20_dec31_dec_sub20_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_upd = dec31_dec_sub21_dec31_dec_sub21_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_upd = dec31_dec_sub23_dec31_dec_sub23_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_upd = dec31_dec_sub16_dec31_dec_sub16_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_upd = dec31_dec_sub18_dec31_dec_sub18_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_upd = dec31_dec_sub8_dec31_dec_sub8_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_upd = dec31_dec_sub24_dec31_dec_sub24_upd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_upd = dec31_dec_sub4_dec31_dec_sub4_upd; + endcase + end + always @* begin + if (\initial ) begin end + dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_rc_sel = dec31_dec_sub10_dec31_dec_sub10_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_rc_sel = dec31_dec_sub28_dec31_dec_sub28_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_rc_sel = dec31_dec_sub0_dec31_dec_sub0_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_rc_sel = dec31_dec_sub26_dec31_dec_sub26_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_rc_sel = dec31_dec_sub19_dec31_dec_sub19_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_rc_sel = dec31_dec_sub22_dec31_dec_sub22_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_rc_sel = dec31_dec_sub9_dec31_dec_sub9_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_rc_sel = dec31_dec_sub11_dec31_dec_sub11_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_rc_sel = dec31_dec_sub27_dec31_dec_sub27_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_rc_sel = dec31_dec_sub15_dec31_dec_sub15_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_rc_sel = dec31_dec_sub20_dec31_dec_sub20_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_rc_sel = dec31_dec_sub21_dec31_dec_sub21_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_rc_sel = dec31_dec_sub23_dec31_dec_sub23_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_rc_sel = dec31_dec_sub16_dec31_dec_sub16_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_rc_sel = dec31_dec_sub18_dec31_dec_sub18_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_rc_sel = dec31_dec_sub8_dec31_dec_sub8_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_rc_sel = dec31_dec_sub24_dec31_dec_sub24_rc_sel; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_rc_sel = dec31_dec_sub4_dec31_dec_sub4_rc_sel; + endcase + end + always @* begin + if (\initial ) begin end + dec31_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_cry_in = dec31_dec_sub10_dec31_dec_sub10_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_cry_in = dec31_dec_sub28_dec31_dec_sub28_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_cry_in = dec31_dec_sub0_dec31_dec_sub0_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_cry_in = dec31_dec_sub26_dec31_dec_sub26_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_cry_in = dec31_dec_sub19_dec31_dec_sub19_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_cry_in = dec31_dec_sub22_dec31_dec_sub22_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_cry_in = dec31_dec_sub9_dec31_dec_sub9_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_cry_in = dec31_dec_sub11_dec31_dec_sub11_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_cry_in = dec31_dec_sub27_dec31_dec_sub27_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_cry_in = dec31_dec_sub15_dec31_dec_sub15_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_cry_in = dec31_dec_sub20_dec31_dec_sub20_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_cry_in = dec31_dec_sub21_dec31_dec_sub21_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_cry_in = dec31_dec_sub23_dec31_dec_sub23_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_cry_in = dec31_dec_sub16_dec31_dec_sub16_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_cry_in = dec31_dec_sub18_dec31_dec_sub18_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_cry_in = dec31_dec_sub8_dec31_dec_sub8_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_cry_in = dec31_dec_sub24_dec31_dec_sub24_cry_in; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_cry_in = dec31_dec_sub4_dec31_dec_sub4_cry_in; + endcase + end + always @* begin + if (\initial ) begin end + dec31_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_inv_a = dec31_dec_sub10_dec31_dec_sub10_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_inv_a = dec31_dec_sub28_dec31_dec_sub28_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_inv_a = dec31_dec_sub0_dec31_dec_sub0_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_inv_a = dec31_dec_sub26_dec31_dec_sub26_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_inv_a = dec31_dec_sub19_dec31_dec_sub19_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_inv_a = dec31_dec_sub22_dec31_dec_sub22_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_inv_a = dec31_dec_sub9_dec31_dec_sub9_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_inv_a = dec31_dec_sub11_dec31_dec_sub11_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_inv_a = dec31_dec_sub27_dec31_dec_sub27_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_inv_a = dec31_dec_sub15_dec31_dec_sub15_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_inv_a = dec31_dec_sub20_dec31_dec_sub20_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_inv_a = dec31_dec_sub21_dec31_dec_sub21_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_inv_a = dec31_dec_sub23_dec31_dec_sub23_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_inv_a = dec31_dec_sub16_dec31_dec_sub16_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_inv_a = dec31_dec_sub18_dec31_dec_sub18_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_inv_a = dec31_dec_sub8_dec31_dec_sub8_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_inv_a = dec31_dec_sub24_dec31_dec_sub24_inv_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_inv_a = dec31_dec_sub4_dec31_dec_sub4_inv_a; + endcase + end + always @* begin + if (\initial ) begin end + dec31_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_inv_out = dec31_dec_sub10_dec31_dec_sub10_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_inv_out = dec31_dec_sub28_dec31_dec_sub28_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_inv_out = dec31_dec_sub0_dec31_dec_sub0_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_inv_out = dec31_dec_sub26_dec31_dec_sub26_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_inv_out = dec31_dec_sub19_dec31_dec_sub19_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_inv_out = dec31_dec_sub22_dec31_dec_sub22_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_inv_out = dec31_dec_sub9_dec31_dec_sub9_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_inv_out = dec31_dec_sub11_dec31_dec_sub11_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_inv_out = dec31_dec_sub27_dec31_dec_sub27_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_inv_out = dec31_dec_sub15_dec31_dec_sub15_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_inv_out = dec31_dec_sub20_dec31_dec_sub20_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_inv_out = dec31_dec_sub21_dec31_dec_sub21_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_inv_out = dec31_dec_sub23_dec31_dec_sub23_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_inv_out = dec31_dec_sub16_dec31_dec_sub16_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_inv_out = dec31_dec_sub18_dec31_dec_sub18_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_inv_out = dec31_dec_sub8_dec31_dec_sub8_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_inv_out = dec31_dec_sub24_dec31_dec_sub24_inv_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_inv_out = dec31_dec_sub4_dec31_dec_sub4_inv_out; + endcase + end + always @* begin + if (\initial ) begin end + dec31_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_cry_out = dec31_dec_sub10_dec31_dec_sub10_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_cry_out = dec31_dec_sub28_dec31_dec_sub28_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_cry_out = dec31_dec_sub0_dec31_dec_sub0_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_cry_out = dec31_dec_sub26_dec31_dec_sub26_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_cry_out = dec31_dec_sub19_dec31_dec_sub19_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_cry_out = dec31_dec_sub22_dec31_dec_sub22_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_cry_out = dec31_dec_sub9_dec31_dec_sub9_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_cry_out = dec31_dec_sub11_dec31_dec_sub11_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_cry_out = dec31_dec_sub27_dec31_dec_sub27_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_cry_out = dec31_dec_sub15_dec31_dec_sub15_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_cry_out = dec31_dec_sub20_dec31_dec_sub20_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_cry_out = dec31_dec_sub21_dec31_dec_sub21_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_cry_out = dec31_dec_sub23_dec31_dec_sub23_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_cry_out = dec31_dec_sub16_dec31_dec_sub16_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_cry_out = dec31_dec_sub18_dec31_dec_sub18_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_cry_out = dec31_dec_sub8_dec31_dec_sub8_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_cry_out = dec31_dec_sub24_dec31_dec_sub24_cry_out; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_cry_out = dec31_dec_sub4_dec31_dec_sub4_cry_out; + endcase + end + always @* begin + if (\initial ) begin end + dec31_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_br = dec31_dec_sub10_dec31_dec_sub10_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_br = dec31_dec_sub28_dec31_dec_sub28_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_br = dec31_dec_sub0_dec31_dec_sub0_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_br = dec31_dec_sub26_dec31_dec_sub26_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_br = dec31_dec_sub19_dec31_dec_sub19_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_br = dec31_dec_sub22_dec31_dec_sub22_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_br = dec31_dec_sub9_dec31_dec_sub9_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_br = dec31_dec_sub11_dec31_dec_sub11_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_br = dec31_dec_sub27_dec31_dec_sub27_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_br = dec31_dec_sub15_dec31_dec_sub15_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_br = dec31_dec_sub20_dec31_dec_sub20_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_br = dec31_dec_sub21_dec31_dec_sub21_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_br = dec31_dec_sub23_dec31_dec_sub23_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_br = dec31_dec_sub16_dec31_dec_sub16_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_br = dec31_dec_sub18_dec31_dec_sub18_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_br = dec31_dec_sub8_dec31_dec_sub8_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_br = dec31_dec_sub24_dec31_dec_sub24_br; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_br = dec31_dec_sub4_dec31_dec_sub4_br; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sgn_ext = dec31_dec_sub10_dec31_dec_sub10_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sgn_ext = dec31_dec_sub28_dec31_dec_sub28_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sgn_ext = dec31_dec_sub0_dec31_dec_sub0_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sgn_ext = dec31_dec_sub26_dec31_dec_sub26_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sgn_ext = dec31_dec_sub19_dec31_dec_sub19_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sgn_ext = dec31_dec_sub22_dec31_dec_sub22_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sgn_ext = dec31_dec_sub9_dec31_dec_sub9_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sgn_ext = dec31_dec_sub11_dec31_dec_sub11_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sgn_ext = dec31_dec_sub27_dec31_dec_sub27_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sgn_ext = dec31_dec_sub15_dec31_dec_sub15_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sgn_ext = dec31_dec_sub20_dec31_dec_sub20_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sgn_ext = dec31_dec_sub21_dec31_dec_sub21_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sgn_ext = dec31_dec_sub23_dec31_dec_sub23_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sgn_ext = dec31_dec_sub16_dec31_dec_sub16_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sgn_ext = dec31_dec_sub18_dec31_dec_sub18_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sgn_ext = dec31_dec_sub8_dec31_dec_sub8_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sgn_ext = dec31_dec_sub24_dec31_dec_sub24_sgn_ext; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sgn_ext = dec31_dec_sub4_dec31_dec_sub4_sgn_ext; + endcase + end + always @* begin + if (\initial ) begin end + dec31_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_rsrv = dec31_dec_sub10_dec31_dec_sub10_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_rsrv = dec31_dec_sub28_dec31_dec_sub28_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_rsrv = dec31_dec_sub0_dec31_dec_sub0_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_rsrv = dec31_dec_sub26_dec31_dec_sub26_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_rsrv = dec31_dec_sub19_dec31_dec_sub19_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_rsrv = dec31_dec_sub22_dec31_dec_sub22_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_rsrv = dec31_dec_sub9_dec31_dec_sub9_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_rsrv = dec31_dec_sub11_dec31_dec_sub11_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_rsrv = dec31_dec_sub27_dec31_dec_sub27_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_rsrv = dec31_dec_sub15_dec31_dec_sub15_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_rsrv = dec31_dec_sub20_dec31_dec_sub20_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_rsrv = dec31_dec_sub21_dec31_dec_sub21_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_rsrv = dec31_dec_sub23_dec31_dec_sub23_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_rsrv = dec31_dec_sub16_dec31_dec_sub16_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_rsrv = dec31_dec_sub18_dec31_dec_sub18_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_rsrv = dec31_dec_sub8_dec31_dec_sub8_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_rsrv = dec31_dec_sub24_dec31_dec_sub24_rsrv; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_rsrv = dec31_dec_sub4_dec31_dec_sub4_rsrv; + endcase + end + always @* begin + if (\initial ) begin end + dec31_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_is_32b = dec31_dec_sub10_dec31_dec_sub10_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_is_32b = dec31_dec_sub28_dec31_dec_sub28_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_is_32b = dec31_dec_sub0_dec31_dec_sub0_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_is_32b = dec31_dec_sub26_dec31_dec_sub26_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_is_32b = dec31_dec_sub19_dec31_dec_sub19_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_is_32b = dec31_dec_sub22_dec31_dec_sub22_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_is_32b = dec31_dec_sub9_dec31_dec_sub9_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_is_32b = dec31_dec_sub11_dec31_dec_sub11_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_is_32b = dec31_dec_sub27_dec31_dec_sub27_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_is_32b = dec31_dec_sub15_dec31_dec_sub15_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_is_32b = dec31_dec_sub20_dec31_dec_sub20_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_is_32b = dec31_dec_sub21_dec31_dec_sub21_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_is_32b = dec31_dec_sub23_dec31_dec_sub23_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_is_32b = dec31_dec_sub16_dec31_dec_sub16_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_is_32b = dec31_dec_sub18_dec31_dec_sub18_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_is_32b = dec31_dec_sub8_dec31_dec_sub8_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_is_32b = dec31_dec_sub24_dec31_dec_sub24_is_32b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_is_32b = dec31_dec_sub4_dec31_dec_sub4_is_32b; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sgn = dec31_dec_sub10_dec31_dec_sub10_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sgn = dec31_dec_sub28_dec31_dec_sub28_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sgn = dec31_dec_sub0_dec31_dec_sub0_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sgn = dec31_dec_sub26_dec31_dec_sub26_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sgn = dec31_dec_sub19_dec31_dec_sub19_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sgn = dec31_dec_sub22_dec31_dec_sub22_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sgn = dec31_dec_sub9_dec31_dec_sub9_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sgn = dec31_dec_sub11_dec31_dec_sub11_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sgn = dec31_dec_sub27_dec31_dec_sub27_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sgn = dec31_dec_sub15_dec31_dec_sub15_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sgn = dec31_dec_sub20_dec31_dec_sub20_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sgn = dec31_dec_sub21_dec31_dec_sub21_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sgn = dec31_dec_sub23_dec31_dec_sub23_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sgn = dec31_dec_sub16_dec31_dec_sub16_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sgn = dec31_dec_sub18_dec31_dec_sub18_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sgn = dec31_dec_sub8_dec31_dec_sub8_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sgn = dec31_dec_sub24_dec31_dec_sub24_sgn; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sgn = dec31_dec_sub4_dec31_dec_sub4_sgn; + endcase + end + always @* begin + if (\initial ) begin end + dec31_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_lk = dec31_dec_sub10_dec31_dec_sub10_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_lk = dec31_dec_sub28_dec31_dec_sub28_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_lk = dec31_dec_sub0_dec31_dec_sub0_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_lk = dec31_dec_sub26_dec31_dec_sub26_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_lk = dec31_dec_sub19_dec31_dec_sub19_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_lk = dec31_dec_sub22_dec31_dec_sub22_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_lk = dec31_dec_sub9_dec31_dec_sub9_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_lk = dec31_dec_sub11_dec31_dec_sub11_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_lk = dec31_dec_sub27_dec31_dec_sub27_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_lk = dec31_dec_sub15_dec31_dec_sub15_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_lk = dec31_dec_sub20_dec31_dec_sub20_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_lk = dec31_dec_sub21_dec31_dec_sub21_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_lk = dec31_dec_sub23_dec31_dec_sub23_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_lk = dec31_dec_sub16_dec31_dec_sub16_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_lk = dec31_dec_sub18_dec31_dec_sub18_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_lk = dec31_dec_sub8_dec31_dec_sub8_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_lk = dec31_dec_sub24_dec31_dec_sub24_lk; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_lk = dec31_dec_sub4_dec31_dec_sub4_lk; + endcase + end + always @* begin + if (\initial ) begin end + dec31_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_sgl_pipe = dec31_dec_sub10_dec31_dec_sub10_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_sgl_pipe = dec31_dec_sub28_dec31_dec_sub28_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_sgl_pipe = dec31_dec_sub0_dec31_dec_sub0_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_sgl_pipe = dec31_dec_sub26_dec31_dec_sub26_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_sgl_pipe = dec31_dec_sub19_dec31_dec_sub19_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_sgl_pipe = dec31_dec_sub22_dec31_dec_sub22_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_sgl_pipe = dec31_dec_sub9_dec31_dec_sub9_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_sgl_pipe = dec31_dec_sub11_dec31_dec_sub11_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_sgl_pipe = dec31_dec_sub27_dec31_dec_sub27_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_sgl_pipe = dec31_dec_sub15_dec31_dec_sub15_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_sgl_pipe = dec31_dec_sub20_dec31_dec_sub20_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_sgl_pipe = dec31_dec_sub21_dec31_dec_sub21_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_sgl_pipe = dec31_dec_sub23_dec31_dec_sub23_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_sgl_pipe = dec31_dec_sub16_dec31_dec_sub16_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_sgl_pipe = dec31_dec_sub18_dec31_dec_sub18_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_sgl_pipe = dec31_dec_sub8_dec31_dec_sub8_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_sgl_pipe = dec31_dec_sub24_dec31_dec_sub24_sgl_pipe; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_sgl_pipe = dec31_dec_sub4_dec31_dec_sub4_sgl_pipe; + endcase + end + assign dec31_dec_sub4_opcode_in = opcode_in; + assign dec31_dec_sub24_opcode_in = opcode_in; + assign dec31_dec_sub8_opcode_in = opcode_in; + assign dec31_dec_sub18_opcode_in = opcode_in; + assign dec31_dec_sub16_opcode_in = opcode_in; + assign dec31_dec_sub23_opcode_in = opcode_in; + assign dec31_dec_sub21_opcode_in = opcode_in; + assign dec31_dec_sub20_opcode_in = opcode_in; + assign dec31_dec_sub15_opcode_in = opcode_in; + assign dec31_dec_sub27_opcode_in = opcode_in; + assign dec31_dec_sub11_opcode_in = opcode_in; + assign dec31_dec_sub9_opcode_in = opcode_in; + assign dec31_dec_sub22_opcode_in = opcode_in; + assign dec31_dec_sub19_opcode_in = opcode_in; + assign dec31_dec_sub26_opcode_in = opcode_in; + assign dec31_dec_sub0_opcode_in = opcode_in; + assign dec31_dec_sub28_opcode_in = opcode_in; + assign dec31_dec_sub10_opcode_in = opcode_in; + assign opc_in = opcode_switch[4:0]; + assign opcode_switch = opcode_in[10:1]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" *) +(* generator = "nMigen" *) +module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, dec31_dec_sub0_form, dec31_dec_sub0_asmcode, dec31_dec_sub0_SV_Etype, dec31_dec_sub0_SV_Ptype, dec31_dec_sub0_in1_sel, dec31_dec_sub0_in2_sel, dec31_dec_sub0_in3_sel, dec31_dec_sub0_out_sel, dec31_dec_sub0_cr_in, dec31_dec_sub0_cr_out, dec31_dec_sub0_sv_in1, dec31_dec_sub0_sv_in2, dec31_dec_sub0_sv_in3, dec31_dec_sub0_sv_out, dec31_dec_sub0_sv_out2, dec31_dec_sub0_sv_cr_in, dec31_dec_sub0_sv_cr_out, dec31_dec_sub0_ldst_len, dec31_dec_sub0_upd, dec31_dec_sub0_rc_sel, dec31_dec_sub0_cry_in, dec31_dec_sub0_inv_a, dec31_dec_sub0_inv_out, dec31_dec_sub0_cry_out, dec31_dec_sub0_br, dec31_dec_sub0_sgn_ext, dec31_dec_sub0_rsrv, dec31_dec_sub0_is_32b, dec31_dec_sub0_sgn, dec31_dec_sub0_lk, dec31_dec_sub0_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub0_SV_Etype; + reg [1:0] dec31_dec_sub0_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub0_SV_Ptype; + reg [1:0] dec31_dec_sub0_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub0_asmcode; + reg [7:0] dec31_dec_sub0_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_br; + reg dec31_dec_sub0_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_cr_in; + reg [2:0] dec31_dec_sub0_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_cr_out; + reg [2:0] dec31_dec_sub0_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub0_cry_in; + reg [1:0] dec31_dec_sub0_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_cry_out; + reg dec31_dec_sub0_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub0_form; + reg [4:0] dec31_dec_sub0_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub0_function_unit; + reg [13:0] dec31_dec_sub0_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_in1_sel; + reg [2:0] dec31_dec_sub0_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub0_in2_sel; + reg [3:0] dec31_dec_sub0_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub0_in3_sel; + reg [1:0] dec31_dec_sub0_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub0_internal_op; + reg [6:0] dec31_dec_sub0_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_inv_a; + reg dec31_dec_sub0_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_inv_out; + reg dec31_dec_sub0_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_is_32b; + reg dec31_dec_sub0_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub0_ldst_len; + reg [3:0] dec31_dec_sub0_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_lk; + reg dec31_dec_sub0_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_out_sel; + reg [2:0] dec31_dec_sub0_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub0_rc_sel; + reg [1:0] dec31_dec_sub0_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_rsrv; + reg dec31_dec_sub0_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_sgl_pipe; + reg dec31_dec_sub0_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_sgn; + reg dec31_dec_sub0_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub0_sgn_ext; + reg dec31_dec_sub0_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_sv_cr_in; + reg [2:0] dec31_dec_sub0_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_sv_cr_out; + reg [2:0] dec31_dec_sub0_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_sv_in1; + reg [2:0] dec31_dec_sub0_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_sv_in2; + reg [2:0] dec31_dec_sub0_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_sv_in3; + reg [2:0] dec31_dec_sub0_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_sv_out; + reg [2:0] dec31_dec_sub0_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_sv_out2; + reg [2:0] dec31_dec_sub0_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub0_upd; + reg [1:0] dec31_dec_sub0_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub0_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_function_unit = 14'h0040; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_cr_in = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_cr_out = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sv_cr_in = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_internal_op = 7'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_internal_op = 7'h0c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_internal_op = 7'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_internal_op = 7'h3b; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_asmcode = 8'h1a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_asmcode = 8'h1c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_asmcode = 8'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_asmcode = 8'h9b; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_form = 5'h18; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub0_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub0_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub0_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub0_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub0_out_sel = 3'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" *) +(* generator = "nMigen" *) +module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_op, dec31_dec_sub10_form, dec31_dec_sub10_asmcode, dec31_dec_sub10_SV_Etype, dec31_dec_sub10_SV_Ptype, dec31_dec_sub10_in1_sel, dec31_dec_sub10_in2_sel, dec31_dec_sub10_in3_sel, dec31_dec_sub10_out_sel, dec31_dec_sub10_cr_in, dec31_dec_sub10_cr_out, dec31_dec_sub10_sv_in1, dec31_dec_sub10_sv_in2, dec31_dec_sub10_sv_in3, dec31_dec_sub10_sv_out, dec31_dec_sub10_sv_out2, dec31_dec_sub10_sv_cr_in, dec31_dec_sub10_sv_cr_out, dec31_dec_sub10_ldst_len, dec31_dec_sub10_upd, dec31_dec_sub10_rc_sel, dec31_dec_sub10_cry_in, dec31_dec_sub10_inv_a, dec31_dec_sub10_inv_out, dec31_dec_sub10_cry_out, dec31_dec_sub10_br, dec31_dec_sub10_sgn_ext, dec31_dec_sub10_rsrv, dec31_dec_sub10_is_32b, dec31_dec_sub10_sgn, dec31_dec_sub10_lk, dec31_dec_sub10_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub10_SV_Etype; + reg [1:0] dec31_dec_sub10_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub10_SV_Ptype; + reg [1:0] dec31_dec_sub10_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub10_asmcode; + reg [7:0] dec31_dec_sub10_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_br; + reg dec31_dec_sub10_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_cr_in; + reg [2:0] dec31_dec_sub10_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_cr_out; + reg [2:0] dec31_dec_sub10_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub10_cry_in; + reg [1:0] dec31_dec_sub10_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_cry_out; + reg dec31_dec_sub10_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub10_form; + reg [4:0] dec31_dec_sub10_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub10_function_unit; + reg [13:0] dec31_dec_sub10_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_in1_sel; + reg [2:0] dec31_dec_sub10_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub10_in2_sel; + reg [3:0] dec31_dec_sub10_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub10_in3_sel; + reg [1:0] dec31_dec_sub10_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub10_internal_op; + reg [6:0] dec31_dec_sub10_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_inv_a; + reg dec31_dec_sub10_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_inv_out; + reg dec31_dec_sub10_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_is_32b; + reg dec31_dec_sub10_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub10_ldst_len; + reg [3:0] dec31_dec_sub10_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_lk; + reg dec31_dec_sub10_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_out_sel; + reg [2:0] dec31_dec_sub10_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub10_rc_sel; + reg [1:0] dec31_dec_sub10_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_rsrv; + reg dec31_dec_sub10_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_sgl_pipe; + reg dec31_dec_sub10_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_sgn; + reg dec31_dec_sub10_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub10_sgn_ext; + reg dec31_dec_sub10_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_sv_cr_in; + reg [2:0] dec31_dec_sub10_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_sv_cr_out; + reg [2:0] dec31_dec_sub10_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_sv_in1; + reg [2:0] dec31_dec_sub10_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_sv_in2; + reg [2:0] dec31_dec_sub10_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_sv_in3; + reg [2:0] dec31_dec_sub10_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_sv_out; + reg [2:0] dec31_dec_sub10_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_sv_out2; + reg [2:0] dec31_dec_sub10_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub10_upd; + reg [1:0] dec31_dec_sub10_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub10_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_internal_op = 7'h02; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_cry_in = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_asmcode = 8'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_asmcode = 8'h0c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_asmcode = 8'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_asmcode = 8'h03; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_asmcode = 8'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_asmcode = 8'h05; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_asmcode = 8'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_asmcode = 8'h0b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_asmcode = 8'h0d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_asmcode = 8'h0e; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_cry_out = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_form = 5'h11; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_in2_sel = 4'h9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_in2_sel = 4'h9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub10_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub10_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub10_out_sel = 3'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" *) +(* generator = "nMigen" *) +module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_op, dec31_dec_sub11_form, dec31_dec_sub11_asmcode, dec31_dec_sub11_SV_Etype, dec31_dec_sub11_SV_Ptype, dec31_dec_sub11_in1_sel, dec31_dec_sub11_in2_sel, dec31_dec_sub11_in3_sel, dec31_dec_sub11_out_sel, dec31_dec_sub11_cr_in, dec31_dec_sub11_cr_out, dec31_dec_sub11_sv_in1, dec31_dec_sub11_sv_in2, dec31_dec_sub11_sv_in3, dec31_dec_sub11_sv_out, dec31_dec_sub11_sv_out2, dec31_dec_sub11_sv_cr_in, dec31_dec_sub11_sv_cr_out, dec31_dec_sub11_ldst_len, dec31_dec_sub11_upd, dec31_dec_sub11_rc_sel, dec31_dec_sub11_cry_in, dec31_dec_sub11_inv_a, dec31_dec_sub11_inv_out, dec31_dec_sub11_cry_out, dec31_dec_sub11_br, dec31_dec_sub11_sgn_ext, dec31_dec_sub11_rsrv, dec31_dec_sub11_is_32b, dec31_dec_sub11_sgn, dec31_dec_sub11_lk, dec31_dec_sub11_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub11_SV_Etype; + reg [1:0] dec31_dec_sub11_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub11_SV_Ptype; + reg [1:0] dec31_dec_sub11_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub11_asmcode; + reg [7:0] dec31_dec_sub11_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_br; + reg dec31_dec_sub11_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_cr_in; + reg [2:0] dec31_dec_sub11_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_cr_out; + reg [2:0] dec31_dec_sub11_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub11_cry_in; + reg [1:0] dec31_dec_sub11_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_cry_out; + reg dec31_dec_sub11_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub11_form; + reg [4:0] dec31_dec_sub11_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub11_function_unit; + reg [13:0] dec31_dec_sub11_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_in1_sel; + reg [2:0] dec31_dec_sub11_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub11_in2_sel; + reg [3:0] dec31_dec_sub11_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub11_in3_sel; + reg [1:0] dec31_dec_sub11_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub11_internal_op; + reg [6:0] dec31_dec_sub11_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_inv_a; + reg dec31_dec_sub11_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_inv_out; + reg dec31_dec_sub11_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_is_32b; + reg dec31_dec_sub11_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub11_ldst_len; + reg [3:0] dec31_dec_sub11_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_lk; + reg dec31_dec_sub11_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_out_sel; + reg [2:0] dec31_dec_sub11_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub11_rc_sel; + reg [1:0] dec31_dec_sub11_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_rsrv; + reg dec31_dec_sub11_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_sgl_pipe; + reg dec31_dec_sub11_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_sgn; + reg dec31_dec_sub11_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub11_sgn_ext; + reg dec31_dec_sub11_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_sv_cr_in; + reg [2:0] dec31_dec_sub11_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_sv_cr_out; + reg [2:0] dec31_dec_sub11_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_sv_in1; + reg [2:0] dec31_dec_sub11_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_sv_in2; + reg [2:0] dec31_dec_sub11_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_sv_in3; + reg [2:0] dec31_dec_sub11_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_sv_out; + reg [2:0] dec31_dec_sub11_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_sv_out2; + reg [2:0] dec31_dec_sub11_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub11_upd; + reg [1:0] dec31_dec_sub11_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub11_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_function_unit = 14'h0100; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sv_in2 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_internal_op = 7'h2f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_internal_op = 7'h2f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_internal_op = 7'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_internal_op = 7'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_internal_op = 7'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_internal_op = 7'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_internal_op = 7'h32; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_internal_op = 7'h32; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_asmcode = 8'h3e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_asmcode = 8'h3f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_asmcode = 8'h3c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_asmcode = 8'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_asmcode = 8'h41; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_asmcode = 8'h42; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_asmcode = 8'h3b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_asmcode = 8'h40; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_asmcode = 8'h75; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_asmcode = 8'h73; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_asmcode = 8'h7c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_asmcode = 8'h7d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_asmcode = 8'h7c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_asmcode = 8'h7d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_asmcode = 8'h81; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_asmcode = 8'h82; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_form = 5'h11; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_is_32b = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sgn = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_SV_Ptype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub11_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub11_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub11_out_sel = 3'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" *) +(* generator = "nMigen" *) +module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_op, dec31_dec_sub15_form, dec31_dec_sub15_asmcode, dec31_dec_sub15_SV_Etype, dec31_dec_sub15_SV_Ptype, dec31_dec_sub15_in1_sel, dec31_dec_sub15_in2_sel, dec31_dec_sub15_in3_sel, dec31_dec_sub15_out_sel, dec31_dec_sub15_cr_in, dec31_dec_sub15_cr_out, dec31_dec_sub15_sv_in1, dec31_dec_sub15_sv_in2, dec31_dec_sub15_sv_in3, dec31_dec_sub15_sv_out, dec31_dec_sub15_sv_out2, dec31_dec_sub15_sv_cr_in, dec31_dec_sub15_sv_cr_out, dec31_dec_sub15_ldst_len, dec31_dec_sub15_upd, dec31_dec_sub15_rc_sel, dec31_dec_sub15_cry_in, dec31_dec_sub15_inv_a, dec31_dec_sub15_inv_out, dec31_dec_sub15_cry_out, dec31_dec_sub15_br, dec31_dec_sub15_sgn_ext, dec31_dec_sub15_rsrv, dec31_dec_sub15_is_32b, dec31_dec_sub15_sgn, dec31_dec_sub15_lk, dec31_dec_sub15_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub15_SV_Etype; + reg [1:0] dec31_dec_sub15_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub15_SV_Ptype; + reg [1:0] dec31_dec_sub15_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub15_asmcode; + reg [7:0] dec31_dec_sub15_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_br; + reg dec31_dec_sub15_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_cr_in; + reg [2:0] dec31_dec_sub15_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_cr_out; + reg [2:0] dec31_dec_sub15_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub15_cry_in; + reg [1:0] dec31_dec_sub15_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_cry_out; + reg dec31_dec_sub15_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub15_form; + reg [4:0] dec31_dec_sub15_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub15_function_unit; + reg [13:0] dec31_dec_sub15_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_in1_sel; + reg [2:0] dec31_dec_sub15_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub15_in2_sel; + reg [3:0] dec31_dec_sub15_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub15_in3_sel; + reg [1:0] dec31_dec_sub15_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub15_internal_op; + reg [6:0] dec31_dec_sub15_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_inv_a; + reg dec31_dec_sub15_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_inv_out; + reg dec31_dec_sub15_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_is_32b; + reg dec31_dec_sub15_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub15_ldst_len; + reg [3:0] dec31_dec_sub15_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_lk; + reg dec31_dec_sub15_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_out_sel; + reg [2:0] dec31_dec_sub15_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub15_rc_sel; + reg [1:0] dec31_dec_sub15_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_rsrv; + reg dec31_dec_sub15_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_sgl_pipe; + reg dec31_dec_sub15_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_sgn; + reg dec31_dec_sub15_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub15_sgn_ext; + reg dec31_dec_sub15_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_sv_cr_in; + reg [2:0] dec31_dec_sub15_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_sv_cr_out; + reg [2:0] dec31_dec_sub15_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_sv_in1; + reg [2:0] dec31_dec_sub15_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_sv_in2; + reg [2:0] dec31_dec_sub15_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_sv_in3; + reg [2:0] dec31_dec_sub15_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_sv_out; + reg [2:0] dec31_dec_sub15_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_sv_out2; + reg [2:0] dec31_dec_sub15_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub15_upd; + reg [1:0] dec31_dec_sub15_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_function_unit = 14'h0040; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_cr_in = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_cr_in = 3'h5; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sv_in2 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sv_cr_in = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sv_cr_in = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_internal_op = 7'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_internal_op = 7'h23; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_asmcode = 8'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_asmcode = 8'h4b; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_form = 5'h12; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_form = 5'h12; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_SV_Etype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_SV_Ptype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub15_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub15_out_sel = 3'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" *) +(* generator = "nMigen" *) +module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_op, dec31_dec_sub16_form, dec31_dec_sub16_asmcode, dec31_dec_sub16_SV_Etype, dec31_dec_sub16_SV_Ptype, dec31_dec_sub16_in1_sel, dec31_dec_sub16_in2_sel, dec31_dec_sub16_in3_sel, dec31_dec_sub16_out_sel, dec31_dec_sub16_cr_in, dec31_dec_sub16_cr_out, dec31_dec_sub16_sv_in1, dec31_dec_sub16_sv_in2, dec31_dec_sub16_sv_in3, dec31_dec_sub16_sv_out, dec31_dec_sub16_sv_out2, dec31_dec_sub16_sv_cr_in, dec31_dec_sub16_sv_cr_out, dec31_dec_sub16_ldst_len, dec31_dec_sub16_upd, dec31_dec_sub16_rc_sel, dec31_dec_sub16_cry_in, dec31_dec_sub16_inv_a, dec31_dec_sub16_inv_out, dec31_dec_sub16_cry_out, dec31_dec_sub16_br, dec31_dec_sub16_sgn_ext, dec31_dec_sub16_rsrv, dec31_dec_sub16_is_32b, dec31_dec_sub16_sgn, dec31_dec_sub16_lk, dec31_dec_sub16_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub16_SV_Etype; + reg [1:0] dec31_dec_sub16_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub16_SV_Ptype; + reg [1:0] dec31_dec_sub16_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub16_asmcode; + reg [7:0] dec31_dec_sub16_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_br; + reg dec31_dec_sub16_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_cr_in; + reg [2:0] dec31_dec_sub16_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_cr_out; + reg [2:0] dec31_dec_sub16_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub16_cry_in; + reg [1:0] dec31_dec_sub16_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_cry_out; + reg dec31_dec_sub16_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub16_form; + reg [4:0] dec31_dec_sub16_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub16_function_unit; + reg [13:0] dec31_dec_sub16_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_in1_sel; + reg [2:0] dec31_dec_sub16_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub16_in2_sel; + reg [3:0] dec31_dec_sub16_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub16_in3_sel; + reg [1:0] dec31_dec_sub16_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub16_internal_op; + reg [6:0] dec31_dec_sub16_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_inv_a; + reg dec31_dec_sub16_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_inv_out; + reg dec31_dec_sub16_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_is_32b; + reg dec31_dec_sub16_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub16_ldst_len; + reg [3:0] dec31_dec_sub16_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_lk; + reg dec31_dec_sub16_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_out_sel; + reg [2:0] dec31_dec_sub16_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub16_rc_sel; + reg [1:0] dec31_dec_sub16_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_rsrv; + reg dec31_dec_sub16_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_sgl_pipe; + reg dec31_dec_sub16_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_sgn; + reg dec31_dec_sub16_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub16_sgn_ext; + reg dec31_dec_sub16_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_sv_cr_in; + reg [2:0] dec31_dec_sub16_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_sv_cr_out; + reg [2:0] dec31_dec_sub16_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_sv_in1; + reg [2:0] dec31_dec_sub16_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_sv_in2; + reg [2:0] dec31_dec_sub16_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_sv_in3; + reg [2:0] dec31_dec_sub16_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_sv_out; + reg [2:0] dec31_dec_sub16_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_sv_out2; + reg [2:0] dec31_dec_sub16_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub16_upd; + reg [1:0] dec31_dec_sub16_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub16_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_function_unit = 14'h0040; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_cr_in = 3'h6; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_cr_out = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_internal_op = 7'h30; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_asmcode = 8'h76; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_form = 5'h0a; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_SV_Etype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_in1_sel = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub16_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub16_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" *) +(* generator = "nMigen" *) +module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_op, dec31_dec_sub18_form, dec31_dec_sub18_asmcode, dec31_dec_sub18_SV_Etype, dec31_dec_sub18_SV_Ptype, dec31_dec_sub18_in1_sel, dec31_dec_sub18_in2_sel, dec31_dec_sub18_in3_sel, dec31_dec_sub18_out_sel, dec31_dec_sub18_cr_in, dec31_dec_sub18_cr_out, dec31_dec_sub18_sv_in1, dec31_dec_sub18_sv_in2, dec31_dec_sub18_sv_in3, dec31_dec_sub18_sv_out, dec31_dec_sub18_sv_out2, dec31_dec_sub18_sv_cr_in, dec31_dec_sub18_sv_cr_out, dec31_dec_sub18_ldst_len, dec31_dec_sub18_upd, dec31_dec_sub18_rc_sel, dec31_dec_sub18_cry_in, dec31_dec_sub18_inv_a, dec31_dec_sub18_inv_out, dec31_dec_sub18_cry_out, dec31_dec_sub18_br, dec31_dec_sub18_sgn_ext, dec31_dec_sub18_rsrv, dec31_dec_sub18_is_32b, dec31_dec_sub18_sgn, dec31_dec_sub18_lk, dec31_dec_sub18_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub18_SV_Etype; + reg [1:0] dec31_dec_sub18_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub18_SV_Ptype; + reg [1:0] dec31_dec_sub18_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub18_asmcode; + reg [7:0] dec31_dec_sub18_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_br; + reg dec31_dec_sub18_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_cr_in; + reg [2:0] dec31_dec_sub18_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_cr_out; + reg [2:0] dec31_dec_sub18_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub18_cry_in; + reg [1:0] dec31_dec_sub18_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_cry_out; + reg dec31_dec_sub18_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub18_form; + reg [4:0] dec31_dec_sub18_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub18_function_unit; + reg [13:0] dec31_dec_sub18_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_in1_sel; + reg [2:0] dec31_dec_sub18_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub18_in2_sel; + reg [3:0] dec31_dec_sub18_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub18_in3_sel; + reg [1:0] dec31_dec_sub18_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub18_internal_op; + reg [6:0] dec31_dec_sub18_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_inv_a; + reg dec31_dec_sub18_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_inv_out; + reg dec31_dec_sub18_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_is_32b; + reg dec31_dec_sub18_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub18_ldst_len; + reg [3:0] dec31_dec_sub18_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_lk; + reg dec31_dec_sub18_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_out_sel; + reg [2:0] dec31_dec_sub18_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub18_rc_sel; + reg [1:0] dec31_dec_sub18_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_rsrv; + reg dec31_dec_sub18_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_sgl_pipe; + reg dec31_dec_sub18_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_sgn; + reg dec31_dec_sub18_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub18_sgn_ext; + reg dec31_dec_sub18_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_sv_cr_in; + reg [2:0] dec31_dec_sub18_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_sv_cr_out; + reg [2:0] dec31_dec_sub18_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_sv_in1; + reg [2:0] dec31_dec_sub18_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_sv_in2; + reg [2:0] dec31_dec_sub18_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_sv_in3; + reg [2:0] dec31_dec_sub18_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_sv_out; + reg [2:0] dec31_dec_sub18_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_sv_out2; + reg [2:0] dec31_dec_sub18_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub18_upd; + reg [1:0] dec31_dec_sub18_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub18_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_function_unit = 14'h0080; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_function_unit = 14'h0080; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_function_unit = 14'h0800; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_function_unit = 14'h0800; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_function_unit = 14'h0800; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_internal_op = 7'h48; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_internal_op = 7'h4a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_internal_op = 7'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_internal_op = 7'h4b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_internal_op = 7'h4b; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_asmcode = 8'h78; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_asmcode = 8'h77; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_asmcode = 8'h9e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_asmcode = 8'hcd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_asmcode = 8'hce; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_SV_Etype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_SV_Ptype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub18_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub18_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub18_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub18_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub18_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub18_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" *) +(* generator = "nMigen" *) +module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_op, dec31_dec_sub19_form, dec31_dec_sub19_asmcode, dec31_dec_sub19_SV_Etype, dec31_dec_sub19_SV_Ptype, dec31_dec_sub19_in1_sel, dec31_dec_sub19_in2_sel, dec31_dec_sub19_in3_sel, dec31_dec_sub19_out_sel, dec31_dec_sub19_cr_in, dec31_dec_sub19_cr_out, dec31_dec_sub19_sv_in1, dec31_dec_sub19_sv_in2, dec31_dec_sub19_sv_in3, dec31_dec_sub19_sv_out, dec31_dec_sub19_sv_out2, dec31_dec_sub19_sv_cr_in, dec31_dec_sub19_sv_cr_out, dec31_dec_sub19_ldst_len, dec31_dec_sub19_upd, dec31_dec_sub19_rc_sel, dec31_dec_sub19_cry_in, dec31_dec_sub19_inv_a, dec31_dec_sub19_inv_out, dec31_dec_sub19_cry_out, dec31_dec_sub19_br, dec31_dec_sub19_sgn_ext, dec31_dec_sub19_rsrv, dec31_dec_sub19_is_32b, dec31_dec_sub19_sgn, dec31_dec_sub19_lk, dec31_dec_sub19_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub19_SV_Etype; + reg [1:0] dec31_dec_sub19_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub19_SV_Ptype; + reg [1:0] dec31_dec_sub19_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub19_asmcode; + reg [7:0] dec31_dec_sub19_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_br; + reg dec31_dec_sub19_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_cr_in; + reg [2:0] dec31_dec_sub19_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_cr_out; + reg [2:0] dec31_dec_sub19_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub19_cry_in; + reg [1:0] dec31_dec_sub19_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_cry_out; + reg dec31_dec_sub19_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub19_form; + reg [4:0] dec31_dec_sub19_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub19_function_unit; + reg [13:0] dec31_dec_sub19_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_in1_sel; + reg [2:0] dec31_dec_sub19_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub19_in2_sel; + reg [3:0] dec31_dec_sub19_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub19_in3_sel; + reg [1:0] dec31_dec_sub19_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub19_internal_op; + reg [6:0] dec31_dec_sub19_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_inv_a; + reg dec31_dec_sub19_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_inv_out; + reg dec31_dec_sub19_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_is_32b; + reg dec31_dec_sub19_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub19_ldst_len; + reg [3:0] dec31_dec_sub19_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_lk; + reg dec31_dec_sub19_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_out_sel; + reg [2:0] dec31_dec_sub19_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub19_rc_sel; + reg [1:0] dec31_dec_sub19_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_rsrv; + reg dec31_dec_sub19_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_sgl_pipe; + reg dec31_dec_sub19_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_sgn; + reg dec31_dec_sub19_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub19_sgn_ext; + reg dec31_dec_sub19_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_sv_cr_in; + reg [2:0] dec31_dec_sub19_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_sv_cr_out; + reg [2:0] dec31_dec_sub19_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_sv_in1; + reg [2:0] dec31_dec_sub19_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_sv_in2; + reg [2:0] dec31_dec_sub19_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_sv_in3; + reg [2:0] dec31_dec_sub19_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_sv_out; + reg [2:0] dec31_dec_sub19_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_sv_out2; + reg [2:0] dec31_dec_sub19_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub19_upd; + reg [1:0] dec31_dec_sub19_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub19_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_function_unit = 14'h0040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_function_unit = 14'h0080; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_function_unit = 14'h0400; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_function_unit = 14'h0400; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_cr_in = 3'h6; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_internal_op = 7'h2d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_internal_op = 7'h47; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_internal_op = 7'h2e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_internal_op = 7'h31; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_asmcode = 8'h6f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_asmcode = 8'h70; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_asmcode = 8'h71; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_asmcode = 8'h79; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_form = 5'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_form = 5'h0a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_form = 5'h0a; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_in1_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_in1_sel = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub19_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub19_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub19_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub19_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub19_out_sel = 3'h3; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" *) +(* generator = "nMigen" *) +module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_op, dec31_dec_sub20_form, dec31_dec_sub20_asmcode, dec31_dec_sub20_SV_Etype, dec31_dec_sub20_SV_Ptype, dec31_dec_sub20_in1_sel, dec31_dec_sub20_in2_sel, dec31_dec_sub20_in3_sel, dec31_dec_sub20_out_sel, dec31_dec_sub20_cr_in, dec31_dec_sub20_cr_out, dec31_dec_sub20_sv_in1, dec31_dec_sub20_sv_in2, dec31_dec_sub20_sv_in3, dec31_dec_sub20_sv_out, dec31_dec_sub20_sv_out2, dec31_dec_sub20_sv_cr_in, dec31_dec_sub20_sv_cr_out, dec31_dec_sub20_ldst_len, dec31_dec_sub20_upd, dec31_dec_sub20_rc_sel, dec31_dec_sub20_cry_in, dec31_dec_sub20_inv_a, dec31_dec_sub20_inv_out, dec31_dec_sub20_cry_out, dec31_dec_sub20_br, dec31_dec_sub20_sgn_ext, dec31_dec_sub20_rsrv, dec31_dec_sub20_is_32b, dec31_dec_sub20_sgn, dec31_dec_sub20_lk, dec31_dec_sub20_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub20_SV_Etype; + reg [1:0] dec31_dec_sub20_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub20_SV_Ptype; + reg [1:0] dec31_dec_sub20_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub20_asmcode; + reg [7:0] dec31_dec_sub20_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_br; + reg dec31_dec_sub20_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_cr_in; + reg [2:0] dec31_dec_sub20_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_cr_out; + reg [2:0] dec31_dec_sub20_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub20_cry_in; + reg [1:0] dec31_dec_sub20_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_cry_out; + reg dec31_dec_sub20_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub20_form; + reg [4:0] dec31_dec_sub20_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub20_function_unit; + reg [13:0] dec31_dec_sub20_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_in1_sel; + reg [2:0] dec31_dec_sub20_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub20_in2_sel; + reg [3:0] dec31_dec_sub20_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub20_in3_sel; + reg [1:0] dec31_dec_sub20_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub20_internal_op; + reg [6:0] dec31_dec_sub20_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_inv_a; + reg dec31_dec_sub20_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_inv_out; + reg dec31_dec_sub20_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_is_32b; + reg dec31_dec_sub20_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub20_ldst_len; + reg [3:0] dec31_dec_sub20_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_lk; + reg dec31_dec_sub20_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_out_sel; + reg [2:0] dec31_dec_sub20_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub20_rc_sel; + reg [1:0] dec31_dec_sub20_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_rsrv; + reg dec31_dec_sub20_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_sgl_pipe; + reg dec31_dec_sub20_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_sgn; + reg dec31_dec_sub20_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub20_sgn_ext; + reg dec31_dec_sub20_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_sv_cr_in; + reg [2:0] dec31_dec_sub20_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_sv_cr_out; + reg [2:0] dec31_dec_sub20_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_sv_in1; + reg [2:0] dec31_dec_sub20_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_sv_in2; + reg [2:0] dec31_dec_sub20_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_sv_in3; + reg [2:0] dec31_dec_sub20_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_sv_out; + reg [2:0] dec31_dec_sub20_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_sv_out2; + reg [2:0] dec31_dec_sub20_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub20_upd; + reg [1:0] dec31_dec_sub20_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub20_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sv_in2 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sv_in3 = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_ldst_len = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_asmcode = 8'h4d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_asmcode = 8'h53; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_asmcode = 8'h54; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_asmcode = 8'h59; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_asmcode = 8'h63; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_asmcode = 8'hae; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_br = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_rsrv = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_rsrv = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_rsrv = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_rsrv = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_SV_Etype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_in3_sel = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub20_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub20_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub20_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub20_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub20_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub20_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub20_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" *) +(* generator = "nMigen" *) +module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_op, dec31_dec_sub21_form, dec31_dec_sub21_asmcode, dec31_dec_sub21_SV_Etype, dec31_dec_sub21_SV_Ptype, dec31_dec_sub21_in1_sel, dec31_dec_sub21_in2_sel, dec31_dec_sub21_in3_sel, dec31_dec_sub21_out_sel, dec31_dec_sub21_cr_in, dec31_dec_sub21_cr_out, dec31_dec_sub21_sv_in1, dec31_dec_sub21_sv_in2, dec31_dec_sub21_sv_in3, dec31_dec_sub21_sv_out, dec31_dec_sub21_sv_out2, dec31_dec_sub21_sv_cr_in, dec31_dec_sub21_sv_cr_out, dec31_dec_sub21_ldst_len, dec31_dec_sub21_upd, dec31_dec_sub21_rc_sel, dec31_dec_sub21_cry_in, dec31_dec_sub21_inv_a, dec31_dec_sub21_inv_out, dec31_dec_sub21_cry_out, dec31_dec_sub21_br, dec31_dec_sub21_sgn_ext, dec31_dec_sub21_rsrv, dec31_dec_sub21_is_32b, dec31_dec_sub21_sgn, dec31_dec_sub21_lk, dec31_dec_sub21_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub21_SV_Etype; + reg [1:0] dec31_dec_sub21_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub21_SV_Ptype; + reg [1:0] dec31_dec_sub21_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub21_asmcode; + reg [7:0] dec31_dec_sub21_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_br; + reg dec31_dec_sub21_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_cr_in; + reg [2:0] dec31_dec_sub21_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_cr_out; + reg [2:0] dec31_dec_sub21_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub21_cry_in; + reg [1:0] dec31_dec_sub21_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_cry_out; + reg dec31_dec_sub21_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub21_form; + reg [4:0] dec31_dec_sub21_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub21_function_unit; + reg [13:0] dec31_dec_sub21_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_in1_sel; + reg [2:0] dec31_dec_sub21_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub21_in2_sel; + reg [3:0] dec31_dec_sub21_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub21_in3_sel; + reg [1:0] dec31_dec_sub21_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub21_internal_op; + reg [6:0] dec31_dec_sub21_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_inv_a; + reg dec31_dec_sub21_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_inv_out; + reg dec31_dec_sub21_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_is_32b; + reg dec31_dec_sub21_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub21_ldst_len; + reg [3:0] dec31_dec_sub21_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_lk; + reg dec31_dec_sub21_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_out_sel; + reg [2:0] dec31_dec_sub21_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub21_rc_sel; + reg [1:0] dec31_dec_sub21_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_rsrv; + reg dec31_dec_sub21_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_sgl_pipe; + reg dec31_dec_sub21_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_sgn; + reg dec31_dec_sub21_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub21_sgn_ext; + reg dec31_dec_sub21_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_sv_cr_in; + reg [2:0] dec31_dec_sub21_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_sv_cr_out; + reg [2:0] dec31_dec_sub21_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_sv_in1; + reg [2:0] dec31_dec_sub21_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_sv_in2; + reg [2:0] dec31_dec_sub21_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_sv_in3; + reg [2:0] dec31_dec_sub21_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_sv_out; + reg [2:0] dec31_dec_sub21_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_sv_out2; + reg [2:0] dec31_dec_sub21_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub21_upd; + reg [1:0] dec31_dec_sub21_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub21_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sv_in2 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sv_in3 = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_upd = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_upd = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_asmcode = 8'h56; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_asmcode = 8'h57; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_asmcode = 8'h64; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_asmcode = 8'h65; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_asmcode = 8'h68; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_asmcode = 8'ha8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_asmcode = 8'hb1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_asmcode = 8'hb2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_SV_Etype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_in3_sel = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub21_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1a: + dec31_dec_sub21_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub21_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub21_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub21_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub21_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub21_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub21_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub21_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub21_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub21_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub21_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub21_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub21_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub21_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" *) +(* generator = "nMigen" *) +module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_op, dec31_dec_sub22_form, dec31_dec_sub22_asmcode, dec31_dec_sub22_SV_Etype, dec31_dec_sub22_SV_Ptype, dec31_dec_sub22_in1_sel, dec31_dec_sub22_in2_sel, dec31_dec_sub22_in3_sel, dec31_dec_sub22_out_sel, dec31_dec_sub22_cr_in, dec31_dec_sub22_cr_out, dec31_dec_sub22_sv_in1, dec31_dec_sub22_sv_in2, dec31_dec_sub22_sv_in3, dec31_dec_sub22_sv_out, dec31_dec_sub22_sv_out2, dec31_dec_sub22_sv_cr_in, dec31_dec_sub22_sv_cr_out, dec31_dec_sub22_ldst_len, dec31_dec_sub22_upd, dec31_dec_sub22_rc_sel, dec31_dec_sub22_cry_in, dec31_dec_sub22_inv_a, dec31_dec_sub22_inv_out, dec31_dec_sub22_cry_out, dec31_dec_sub22_br, dec31_dec_sub22_sgn_ext, dec31_dec_sub22_rsrv, dec31_dec_sub22_is_32b, dec31_dec_sub22_sgn, dec31_dec_sub22_lk, dec31_dec_sub22_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub22_SV_Etype; + reg [1:0] dec31_dec_sub22_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub22_SV_Ptype; + reg [1:0] dec31_dec_sub22_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub22_asmcode; + reg [7:0] dec31_dec_sub22_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_br; + reg dec31_dec_sub22_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_cr_in; + reg [2:0] dec31_dec_sub22_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_cr_out; + reg [2:0] dec31_dec_sub22_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub22_cry_in; + reg [1:0] dec31_dec_sub22_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_cry_out; + reg dec31_dec_sub22_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub22_form; + reg [4:0] dec31_dec_sub22_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub22_function_unit; + reg [13:0] dec31_dec_sub22_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_in1_sel; + reg [2:0] dec31_dec_sub22_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub22_in2_sel; + reg [3:0] dec31_dec_sub22_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub22_in3_sel; + reg [1:0] dec31_dec_sub22_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub22_internal_op; + reg [6:0] dec31_dec_sub22_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_inv_a; + reg dec31_dec_sub22_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_inv_out; + reg dec31_dec_sub22_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_is_32b; + reg dec31_dec_sub22_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub22_ldst_len; + reg [3:0] dec31_dec_sub22_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_lk; + reg dec31_dec_sub22_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_out_sel; + reg [2:0] dec31_dec_sub22_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub22_rc_sel; + reg [1:0] dec31_dec_sub22_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_rsrv; + reg dec31_dec_sub22_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_sgl_pipe; + reg dec31_dec_sub22_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_sgn; + reg dec31_dec_sub22_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub22_sgn_ext; + reg dec31_dec_sub22_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_sv_cr_in; + reg [2:0] dec31_dec_sub22_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_sv_cr_out; + reg [2:0] dec31_dec_sub22_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_sv_in1; + reg [2:0] dec31_dec_sub22_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_sv_in2; + reg [2:0] dec31_dec_sub22_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_sv_in3; + reg [2:0] dec31_dec_sub22_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_sv_out; + reg [2:0] dec31_dec_sub22_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_sv_out2; + reg [2:0] dec31_dec_sub22_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub22_upd; + reg [1:0] dec31_dec_sub22_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub22_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_function_unit = 14'h0800; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_internal_op = 7'h1c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_internal_op = 7'h21; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_internal_op = 7'h01; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_internal_op = 7'h01; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_asmcode = 8'h2e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_asmcode = 8'h2f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_asmcode = 8'h30; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_asmcode = 8'h31; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_asmcode = 8'h32; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_asmcode = 8'h49; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_asmcode = 8'h4a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_asmcode = 8'h5d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_asmcode = 8'h66; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_asmcode = 8'ha9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_asmcode = 8'haf; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_asmcode = 8'hb4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_asmcode = 8'hb5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_asmcode = 8'hba; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_asmcode = 8'hbb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_asmcode = 8'hca; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_br = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_rsrv = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_rsrv = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_rsrv = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_rsrv = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_SV_Etype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_SV_Ptype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub22_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub22_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub22_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h15: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub22_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub22_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" *) +(* generator = "nMigen" *) +module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_op, dec31_dec_sub23_form, dec31_dec_sub23_asmcode, dec31_dec_sub23_SV_Etype, dec31_dec_sub23_SV_Ptype, dec31_dec_sub23_in1_sel, dec31_dec_sub23_in2_sel, dec31_dec_sub23_in3_sel, dec31_dec_sub23_out_sel, dec31_dec_sub23_cr_in, dec31_dec_sub23_cr_out, dec31_dec_sub23_sv_in1, dec31_dec_sub23_sv_in2, dec31_dec_sub23_sv_in3, dec31_dec_sub23_sv_out, dec31_dec_sub23_sv_out2, dec31_dec_sub23_sv_cr_in, dec31_dec_sub23_sv_cr_out, dec31_dec_sub23_ldst_len, dec31_dec_sub23_upd, dec31_dec_sub23_rc_sel, dec31_dec_sub23_cry_in, dec31_dec_sub23_inv_a, dec31_dec_sub23_inv_out, dec31_dec_sub23_cry_out, dec31_dec_sub23_br, dec31_dec_sub23_sgn_ext, dec31_dec_sub23_rsrv, dec31_dec_sub23_is_32b, dec31_dec_sub23_sgn, dec31_dec_sub23_lk, dec31_dec_sub23_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub23_SV_Etype; + reg [1:0] dec31_dec_sub23_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub23_SV_Ptype; + reg [1:0] dec31_dec_sub23_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub23_asmcode; + reg [7:0] dec31_dec_sub23_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_br; + reg dec31_dec_sub23_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_cr_in; + reg [2:0] dec31_dec_sub23_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_cr_out; + reg [2:0] dec31_dec_sub23_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub23_cry_in; + reg [1:0] dec31_dec_sub23_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_cry_out; + reg dec31_dec_sub23_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub23_form; + reg [4:0] dec31_dec_sub23_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub23_function_unit; + reg [13:0] dec31_dec_sub23_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_in1_sel; + reg [2:0] dec31_dec_sub23_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub23_in2_sel; + reg [3:0] dec31_dec_sub23_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub23_in3_sel; + reg [1:0] dec31_dec_sub23_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub23_internal_op; + reg [6:0] dec31_dec_sub23_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_inv_a; + reg dec31_dec_sub23_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_inv_out; + reg dec31_dec_sub23_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_is_32b; + reg dec31_dec_sub23_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub23_ldst_len; + reg [3:0] dec31_dec_sub23_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_lk; + reg dec31_dec_sub23_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_out_sel; + reg [2:0] dec31_dec_sub23_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub23_rc_sel; + reg [1:0] dec31_dec_sub23_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_rsrv; + reg dec31_dec_sub23_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_sgl_pipe; + reg dec31_dec_sub23_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_sgn; + reg dec31_dec_sub23_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub23_sgn_ext; + reg dec31_dec_sub23_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_sv_cr_in; + reg [2:0] dec31_dec_sub23_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_sv_cr_out; + reg [2:0] dec31_dec_sub23_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_sv_in1; + reg [2:0] dec31_dec_sub23_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_sv_in2; + reg [2:0] dec31_dec_sub23_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_sv_in3; + reg [2:0] dec31_dec_sub23_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_sv_out; + reg [2:0] dec31_dec_sub23_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_sv_out2; + reg [2:0] dec31_dec_sub23_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub23_upd; + reg [1:0] dec31_dec_sub23_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub23_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sv_in2 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sv_in3 = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_asmcode = 8'h50; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_asmcode = 8'h51; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_asmcode = 8'h5b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_asmcode = 8'h5c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_asmcode = 8'h60; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_asmcode = 8'h6a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_asmcode = 8'h6b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_asmcode = 8'hab; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_asmcode = 8'hac; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_asmcode = 8'hb7; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_asmcode = 8'hb8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_asmcode = 8'hbd; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_asmcode = 8'hbe; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_SV_Etype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_in3_sel = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub23_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub23_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub23_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub23_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0a: + dec31_dec_sub23_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub23_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub23_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub23_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub23_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub23_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" *) +(* generator = "nMigen" *) +module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_op, dec31_dec_sub24_form, dec31_dec_sub24_asmcode, dec31_dec_sub24_SV_Etype, dec31_dec_sub24_SV_Ptype, dec31_dec_sub24_in1_sel, dec31_dec_sub24_in2_sel, dec31_dec_sub24_in3_sel, dec31_dec_sub24_out_sel, dec31_dec_sub24_cr_in, dec31_dec_sub24_cr_out, dec31_dec_sub24_sv_in1, dec31_dec_sub24_sv_in2, dec31_dec_sub24_sv_in3, dec31_dec_sub24_sv_out, dec31_dec_sub24_sv_out2, dec31_dec_sub24_sv_cr_in, dec31_dec_sub24_sv_cr_out, dec31_dec_sub24_ldst_len, dec31_dec_sub24_upd, dec31_dec_sub24_rc_sel, dec31_dec_sub24_cry_in, dec31_dec_sub24_inv_a, dec31_dec_sub24_inv_out, dec31_dec_sub24_cry_out, dec31_dec_sub24_br, dec31_dec_sub24_sgn_ext, dec31_dec_sub24_rsrv, dec31_dec_sub24_is_32b, dec31_dec_sub24_sgn, dec31_dec_sub24_lk, dec31_dec_sub24_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub24_SV_Etype; + reg [1:0] dec31_dec_sub24_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub24_SV_Ptype; + reg [1:0] dec31_dec_sub24_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub24_asmcode; + reg [7:0] dec31_dec_sub24_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_br; + reg dec31_dec_sub24_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_cr_in; + reg [2:0] dec31_dec_sub24_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_cr_out; + reg [2:0] dec31_dec_sub24_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub24_cry_in; + reg [1:0] dec31_dec_sub24_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_cry_out; + reg dec31_dec_sub24_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub24_form; + reg [4:0] dec31_dec_sub24_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub24_function_unit; + reg [13:0] dec31_dec_sub24_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_in1_sel; + reg [2:0] dec31_dec_sub24_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub24_in2_sel; + reg [3:0] dec31_dec_sub24_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub24_in3_sel; + reg [1:0] dec31_dec_sub24_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub24_internal_op; + reg [6:0] dec31_dec_sub24_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_inv_a; + reg dec31_dec_sub24_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_inv_out; + reg dec31_dec_sub24_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_is_32b; + reg dec31_dec_sub24_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub24_ldst_len; + reg [3:0] dec31_dec_sub24_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_lk; + reg dec31_dec_sub24_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_out_sel; + reg [2:0] dec31_dec_sub24_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub24_rc_sel; + reg [1:0] dec31_dec_sub24_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_rsrv; + reg dec31_dec_sub24_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_sgl_pipe; + reg dec31_dec_sub24_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_sgn; + reg dec31_dec_sub24_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub24_sgn_ext; + reg dec31_dec_sub24_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_sv_cr_in; + reg [2:0] dec31_dec_sub24_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_sv_cr_out; + reg [2:0] dec31_dec_sub24_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_sv_in1; + reg [2:0] dec31_dec_sub24_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_sv_in2; + reg [2:0] dec31_dec_sub24_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_sv_in3; + reg [2:0] dec31_dec_sub24_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_sv_out; + reg [2:0] dec31_dec_sub24_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_sv_out2; + reg [2:0] dec31_dec_sub24_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub24_upd; + reg [1:0] dec31_dec_sub24_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub24_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sv_in2 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sv_in3 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_internal_op = 7'h3c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_internal_op = 7'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_internal_op = 7'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_internal_op = 7'h3d; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_asmcode = 8'ha0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_asmcode = 8'ha3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_asmcode = 8'ha4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_asmcode = 8'ha6; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_is_32b = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_SV_Ptype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_in2_sel = 4'hb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_in3_sel = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub24_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub24_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub24_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub24_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub24_out_sel = 3'h2; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" *) +(* generator = "nMigen" *) +module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_op, dec31_dec_sub26_form, dec31_dec_sub26_asmcode, dec31_dec_sub26_SV_Etype, dec31_dec_sub26_SV_Ptype, dec31_dec_sub26_in1_sel, dec31_dec_sub26_in2_sel, dec31_dec_sub26_in3_sel, dec31_dec_sub26_out_sel, dec31_dec_sub26_cr_in, dec31_dec_sub26_cr_out, dec31_dec_sub26_sv_in1, dec31_dec_sub26_sv_in2, dec31_dec_sub26_sv_in3, dec31_dec_sub26_sv_out, dec31_dec_sub26_sv_out2, dec31_dec_sub26_sv_cr_in, dec31_dec_sub26_sv_cr_out, dec31_dec_sub26_ldst_len, dec31_dec_sub26_upd, dec31_dec_sub26_rc_sel, dec31_dec_sub26_cry_in, dec31_dec_sub26_inv_a, dec31_dec_sub26_inv_out, dec31_dec_sub26_cry_out, dec31_dec_sub26_br, dec31_dec_sub26_sgn_ext, dec31_dec_sub26_rsrv, dec31_dec_sub26_is_32b, dec31_dec_sub26_sgn, dec31_dec_sub26_lk, dec31_dec_sub26_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub26_SV_Etype; + reg [1:0] dec31_dec_sub26_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub26_SV_Ptype; + reg [1:0] dec31_dec_sub26_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub26_asmcode; + reg [7:0] dec31_dec_sub26_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_br; + reg dec31_dec_sub26_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_cr_in; + reg [2:0] dec31_dec_sub26_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_cr_out; + reg [2:0] dec31_dec_sub26_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub26_cry_in; + reg [1:0] dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_cry_out; + reg dec31_dec_sub26_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub26_form; + reg [4:0] dec31_dec_sub26_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub26_function_unit; + reg [13:0] dec31_dec_sub26_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_in1_sel; + reg [2:0] dec31_dec_sub26_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub26_in2_sel; + reg [3:0] dec31_dec_sub26_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub26_in3_sel; + reg [1:0] dec31_dec_sub26_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub26_internal_op; + reg [6:0] dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_inv_a; + reg dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_inv_out; + reg dec31_dec_sub26_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_is_32b; + reg dec31_dec_sub26_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub26_ldst_len; + reg [3:0] dec31_dec_sub26_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_lk; + reg dec31_dec_sub26_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_out_sel; + reg [2:0] dec31_dec_sub26_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub26_rc_sel; + reg [1:0] dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_rsrv; + reg dec31_dec_sub26_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_sgl_pipe; + reg dec31_dec_sub26_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_sgn; + reg dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub26_sgn_ext; + reg dec31_dec_sub26_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_sv_cr_in; + reg [2:0] dec31_dec_sub26_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_sv_cr_out; + reg [2:0] dec31_dec_sub26_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_sv_in1; + reg [2:0] dec31_dec_sub26_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_sv_in2; + reg [2:0] dec31_dec_sub26_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_sv_in3; + reg [2:0] dec31_dec_sub26_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_sv_out; + reg [2:0] dec31_dec_sub26_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_sv_out2; + reg [2:0] dec31_dec_sub26_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub26_upd; + reg [1:0] dec31_dec_sub26_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub26_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sv_in3 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_ldst_len = 4'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_ldst_len = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_internal_op = 7'h0e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_internal_op = 7'h0e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_internal_op = 7'h0e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_internal_op = 7'h0e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_internal_op = 7'h1f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_internal_op = 7'h1f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_internal_op = 7'h1f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_internal_op = 7'h20; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_internal_op = 7'h36; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_internal_op = 7'h36; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_internal_op = 7'h36; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_internal_op = 7'h37; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_internal_op = 7'h37; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_internal_op = 7'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_internal_op = 7'h3d; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_asmcode = 8'h21; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_asmcode = 8'h22; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_asmcode = 8'h23; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_asmcode = 8'h24; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_asmcode = 8'h44; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_asmcode = 8'h45; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_asmcode = 8'h46; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_asmcode = 8'h47; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_asmcode = 8'h8c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_asmcode = 8'h8d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_asmcode = 8'h8e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_asmcode = 8'h8f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_asmcode = 8'h90; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_asmcode = 8'ha1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_asmcode = 8'ha2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_cry_out = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_form = 5'h10; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_form = 5'h10; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sgn = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_in2_sel = 4'ha; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_in3_sel = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub26_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0b: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h05: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub26_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub26_out_sel = 3'h2; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" *) +(* generator = "nMigen" *) +module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_op, dec31_dec_sub27_form, dec31_dec_sub27_asmcode, dec31_dec_sub27_SV_Etype, dec31_dec_sub27_SV_Ptype, dec31_dec_sub27_in1_sel, dec31_dec_sub27_in2_sel, dec31_dec_sub27_in3_sel, dec31_dec_sub27_out_sel, dec31_dec_sub27_cr_in, dec31_dec_sub27_cr_out, dec31_dec_sub27_sv_in1, dec31_dec_sub27_sv_in2, dec31_dec_sub27_sv_in3, dec31_dec_sub27_sv_out, dec31_dec_sub27_sv_out2, dec31_dec_sub27_sv_cr_in, dec31_dec_sub27_sv_cr_out, dec31_dec_sub27_ldst_len, dec31_dec_sub27_upd, dec31_dec_sub27_rc_sel, dec31_dec_sub27_cry_in, dec31_dec_sub27_inv_a, dec31_dec_sub27_inv_out, dec31_dec_sub27_cry_out, dec31_dec_sub27_br, dec31_dec_sub27_sgn_ext, dec31_dec_sub27_rsrv, dec31_dec_sub27_is_32b, dec31_dec_sub27_sgn, dec31_dec_sub27_lk, dec31_dec_sub27_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub27_SV_Etype; + reg [1:0] dec31_dec_sub27_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub27_SV_Ptype; + reg [1:0] dec31_dec_sub27_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub27_asmcode; + reg [7:0] dec31_dec_sub27_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_br; + reg dec31_dec_sub27_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_cr_in; + reg [2:0] dec31_dec_sub27_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_cr_out; + reg [2:0] dec31_dec_sub27_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub27_cry_in; + reg [1:0] dec31_dec_sub27_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_cry_out; + reg dec31_dec_sub27_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub27_form; + reg [4:0] dec31_dec_sub27_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub27_function_unit; + reg [13:0] dec31_dec_sub27_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_in1_sel; + reg [2:0] dec31_dec_sub27_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub27_in2_sel; + reg [3:0] dec31_dec_sub27_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub27_in3_sel; + reg [1:0] dec31_dec_sub27_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub27_internal_op; + reg [6:0] dec31_dec_sub27_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_inv_a; + reg dec31_dec_sub27_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_inv_out; + reg dec31_dec_sub27_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_is_32b; + reg dec31_dec_sub27_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub27_ldst_len; + reg [3:0] dec31_dec_sub27_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_lk; + reg dec31_dec_sub27_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_out_sel; + reg [2:0] dec31_dec_sub27_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub27_rc_sel; + reg [1:0] dec31_dec_sub27_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_rsrv; + reg dec31_dec_sub27_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_sgl_pipe; + reg dec31_dec_sub27_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_sgn; + reg dec31_dec_sub27_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub27_sgn_ext; + reg dec31_dec_sub27_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_sv_cr_in; + reg [2:0] dec31_dec_sub27_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_sv_cr_out; + reg [2:0] dec31_dec_sub27_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_sv_in1; + reg [2:0] dec31_dec_sub27_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_sv_in2; + reg [2:0] dec31_dec_sub27_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_sv_in3; + reg [2:0] dec31_dec_sub27_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_sv_out; + reg [2:0] dec31_dec_sub27_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_sv_out2; + reg [2:0] dec31_dec_sub27_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub27_upd; + reg [1:0] dec31_dec_sub27_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub27_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_function_unit = 14'h0008; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_function_unit = 14'h0008; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sv_in2 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sv_in3 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sv_in3 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_internal_op = 7'h20; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_internal_op = 7'h3c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_internal_op = 7'h3d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_internal_op = 7'h3d; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_asmcode = 8'h47; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_asmcode = 8'h9f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_asmcode = 8'ha2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_asmcode = 8'ha5; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_form = 5'h10; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_form = 5'h10; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_SV_Ptype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_in1_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_in1_sel = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_in2_sel = 4'ha; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_in3_sel = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub27_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1b: + dec31_dec_sub27_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub27_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h19: + dec31_dec_sub27_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub27_out_sel = 3'h2; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" *) +(* generator = "nMigen" *) +module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_op, dec31_dec_sub28_form, dec31_dec_sub28_asmcode, dec31_dec_sub28_SV_Etype, dec31_dec_sub28_SV_Ptype, dec31_dec_sub28_in1_sel, dec31_dec_sub28_in2_sel, dec31_dec_sub28_in3_sel, dec31_dec_sub28_out_sel, dec31_dec_sub28_cr_in, dec31_dec_sub28_cr_out, dec31_dec_sub28_sv_in1, dec31_dec_sub28_sv_in2, dec31_dec_sub28_sv_in3, dec31_dec_sub28_sv_out, dec31_dec_sub28_sv_out2, dec31_dec_sub28_sv_cr_in, dec31_dec_sub28_sv_cr_out, dec31_dec_sub28_ldst_len, dec31_dec_sub28_upd, dec31_dec_sub28_rc_sel, dec31_dec_sub28_cry_in, dec31_dec_sub28_inv_a, dec31_dec_sub28_inv_out, dec31_dec_sub28_cry_out, dec31_dec_sub28_br, dec31_dec_sub28_sgn_ext, dec31_dec_sub28_rsrv, dec31_dec_sub28_is_32b, dec31_dec_sub28_sgn, dec31_dec_sub28_lk, dec31_dec_sub28_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub28_SV_Etype; + reg [1:0] dec31_dec_sub28_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub28_SV_Ptype; + reg [1:0] dec31_dec_sub28_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub28_asmcode; + reg [7:0] dec31_dec_sub28_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_br; + reg dec31_dec_sub28_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_cr_in; + reg [2:0] dec31_dec_sub28_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_cr_out; + reg [2:0] dec31_dec_sub28_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub28_cry_in; + reg [1:0] dec31_dec_sub28_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_cry_out; + reg dec31_dec_sub28_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub28_form; + reg [4:0] dec31_dec_sub28_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub28_function_unit; + reg [13:0] dec31_dec_sub28_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_in1_sel; + reg [2:0] dec31_dec_sub28_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub28_in2_sel; + reg [3:0] dec31_dec_sub28_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub28_in3_sel; + reg [1:0] dec31_dec_sub28_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub28_internal_op; + reg [6:0] dec31_dec_sub28_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_inv_a; + reg dec31_dec_sub28_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_inv_out; + reg dec31_dec_sub28_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_is_32b; + reg dec31_dec_sub28_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub28_ldst_len; + reg [3:0] dec31_dec_sub28_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_lk; + reg dec31_dec_sub28_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_out_sel; + reg [2:0] dec31_dec_sub28_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub28_rc_sel; + reg [1:0] dec31_dec_sub28_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_rsrv; + reg dec31_dec_sub28_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_sgl_pipe; + reg dec31_dec_sub28_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_sgn; + reg dec31_dec_sub28_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub28_sgn_ext; + reg dec31_dec_sub28_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_sv_cr_in; + reg [2:0] dec31_dec_sub28_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_sv_cr_out; + reg [2:0] dec31_dec_sub28_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_sv_in1; + reg [2:0] dec31_dec_sub28_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_sv_in2; + reg [2:0] dec31_dec_sub28_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_sv_in3; + reg [2:0] dec31_dec_sub28_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_sv_out; + reg [2:0] dec31_dec_sub28_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_sv_out2; + reg [2:0] dec31_dec_sub28_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub28_upd; + reg [1:0] dec31_dec_sub28_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub28_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_function_unit = 14'h0010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_function_unit = 14'h0010; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sv_in1 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sv_in2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sv_in2 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_internal_op = 7'h09; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_internal_op = 7'h0b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_internal_op = 7'h43; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_internal_op = 7'h04; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_internal_op = 7'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_internal_op = 7'h43; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_asmcode = 8'h0f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_asmcode = 8'h10; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_asmcode = 8'h19; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_asmcode = 8'h1b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_asmcode = 8'h43; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_asmcode = 8'h83; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_asmcode = 8'h87; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_asmcode = 8'h88; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_asmcode = 8'h89; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_asmcode = 8'hd1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_inv_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_inv_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_inv_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_SV_Ptype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_in1_sel = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_in1_sel = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub28_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub28_out_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h09: + dec31_dec_sub28_out_sel = 3'h2; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" *) +(* generator = "nMigen" *) +module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, dec31_dec_sub4_form, dec31_dec_sub4_asmcode, dec31_dec_sub4_SV_Etype, dec31_dec_sub4_SV_Ptype, dec31_dec_sub4_in1_sel, dec31_dec_sub4_in2_sel, dec31_dec_sub4_in3_sel, dec31_dec_sub4_out_sel, dec31_dec_sub4_cr_in, dec31_dec_sub4_cr_out, dec31_dec_sub4_sv_in1, dec31_dec_sub4_sv_in2, dec31_dec_sub4_sv_in3, dec31_dec_sub4_sv_out, dec31_dec_sub4_sv_out2, dec31_dec_sub4_sv_cr_in, dec31_dec_sub4_sv_cr_out, dec31_dec_sub4_ldst_len, dec31_dec_sub4_upd, dec31_dec_sub4_rc_sel, dec31_dec_sub4_cry_in, dec31_dec_sub4_inv_a, dec31_dec_sub4_inv_out, dec31_dec_sub4_cry_out, dec31_dec_sub4_br, dec31_dec_sub4_sgn_ext, dec31_dec_sub4_rsrv, dec31_dec_sub4_is_32b, dec31_dec_sub4_sgn, dec31_dec_sub4_lk, dec31_dec_sub4_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub4_SV_Etype; + reg [1:0] dec31_dec_sub4_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub4_SV_Ptype; + reg [1:0] dec31_dec_sub4_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub4_asmcode; + reg [7:0] dec31_dec_sub4_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_br; + reg dec31_dec_sub4_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_cr_in; + reg [2:0] dec31_dec_sub4_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_cr_out; + reg [2:0] dec31_dec_sub4_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub4_cry_in; + reg [1:0] dec31_dec_sub4_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_cry_out; + reg dec31_dec_sub4_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub4_form; + reg [4:0] dec31_dec_sub4_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub4_function_unit; + reg [13:0] dec31_dec_sub4_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_in1_sel; + reg [2:0] dec31_dec_sub4_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub4_in2_sel; + reg [3:0] dec31_dec_sub4_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub4_in3_sel; + reg [1:0] dec31_dec_sub4_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub4_internal_op; + reg [6:0] dec31_dec_sub4_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_inv_a; + reg dec31_dec_sub4_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_inv_out; + reg dec31_dec_sub4_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_is_32b; + reg dec31_dec_sub4_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub4_ldst_len; + reg [3:0] dec31_dec_sub4_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_lk; + reg dec31_dec_sub4_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_out_sel; + reg [2:0] dec31_dec_sub4_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub4_rc_sel; + reg [1:0] dec31_dec_sub4_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_rsrv; + reg dec31_dec_sub4_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_sgl_pipe; + reg dec31_dec_sub4_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_sgn; + reg dec31_dec_sub4_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub4_sgn_ext; + reg dec31_dec_sub4_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_sv_cr_in; + reg [2:0] dec31_dec_sub4_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_sv_cr_out; + reg [2:0] dec31_dec_sub4_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_sv_in1; + reg [2:0] dec31_dec_sub4_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_sv_in2; + reg [2:0] dec31_dec_sub4_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_sv_in3; + reg [2:0] dec31_dec_sub4_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_sv_out; + reg [2:0] dec31_dec_sub4_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_sv_out2; + reg [2:0] dec31_dec_sub4_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub4_upd; + reg [1:0] dec31_dec_sub4_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub4_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_function_unit = 14'h0080; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_function_unit = 14'h0080; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sv_in1 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_internal_op = 7'h3f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_internal_op = 7'h3f; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_asmcode = 8'hcb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_asmcode = 8'hcf; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_form = 5'h08; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_is_32b = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_SV_Etype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_SV_Etype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_SV_Ptype = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub4_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub4_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub4_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" *) +(* generator = "nMigen" *) +module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, dec31_dec_sub8_form, dec31_dec_sub8_asmcode, dec31_dec_sub8_SV_Etype, dec31_dec_sub8_SV_Ptype, dec31_dec_sub8_in1_sel, dec31_dec_sub8_in2_sel, dec31_dec_sub8_in3_sel, dec31_dec_sub8_out_sel, dec31_dec_sub8_cr_in, dec31_dec_sub8_cr_out, dec31_dec_sub8_sv_in1, dec31_dec_sub8_sv_in2, dec31_dec_sub8_sv_in3, dec31_dec_sub8_sv_out, dec31_dec_sub8_sv_out2, dec31_dec_sub8_sv_cr_in, dec31_dec_sub8_sv_cr_out, dec31_dec_sub8_ldst_len, dec31_dec_sub8_upd, dec31_dec_sub8_rc_sel, dec31_dec_sub8_cry_in, dec31_dec_sub8_inv_a, dec31_dec_sub8_inv_out, dec31_dec_sub8_cry_out, dec31_dec_sub8_br, dec31_dec_sub8_sgn_ext, dec31_dec_sub8_rsrv, dec31_dec_sub8_is_32b, dec31_dec_sub8_sgn, dec31_dec_sub8_lk, dec31_dec_sub8_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub8_SV_Etype; + reg [1:0] dec31_dec_sub8_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub8_SV_Ptype; + reg [1:0] dec31_dec_sub8_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub8_asmcode; + reg [7:0] dec31_dec_sub8_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_br; + reg dec31_dec_sub8_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_cr_in; + reg [2:0] dec31_dec_sub8_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_cr_out; + reg [2:0] dec31_dec_sub8_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub8_cry_in; + reg [1:0] dec31_dec_sub8_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_cry_out; + reg dec31_dec_sub8_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub8_form; + reg [4:0] dec31_dec_sub8_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub8_function_unit; + reg [13:0] dec31_dec_sub8_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_in1_sel; + reg [2:0] dec31_dec_sub8_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub8_in2_sel; + reg [3:0] dec31_dec_sub8_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub8_in3_sel; + reg [1:0] dec31_dec_sub8_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub8_internal_op; + reg [6:0] dec31_dec_sub8_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_inv_a; + reg dec31_dec_sub8_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_inv_out; + reg dec31_dec_sub8_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_is_32b; + reg dec31_dec_sub8_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub8_ldst_len; + reg [3:0] dec31_dec_sub8_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_lk; + reg dec31_dec_sub8_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_out_sel; + reg [2:0] dec31_dec_sub8_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub8_rc_sel; + reg [1:0] dec31_dec_sub8_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_rsrv; + reg dec31_dec_sub8_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_sgl_pipe; + reg dec31_dec_sub8_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_sgn; + reg dec31_dec_sub8_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub8_sgn_ext; + reg dec31_dec_sub8_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_sv_cr_in; + reg [2:0] dec31_dec_sub8_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_sv_cr_out; + reg [2:0] dec31_dec_sub8_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_sv_in1; + reg [2:0] dec31_dec_sub8_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_sv_in2; + reg [2:0] dec31_dec_sub8_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_sv_in3; + reg [2:0] dec31_dec_sub8_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_sv_out; + reg [2:0] dec31_dec_sub8_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_sv_out2; + reg [2:0] dec31_dec_sub8_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub8_upd; + reg [1:0] dec31_dec_sub8_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub8_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_function_unit = 14'h0002; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_function_unit = 14'h0002; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_internal_op = 7'h02; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_internal_op = 7'h02; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_cry_in = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_asmcode = 8'h84; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_asmcode = 8'h85; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_asmcode = 8'hbf; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_asmcode = 8'hc7; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_asmcode = 8'hc0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_asmcode = 8'hc1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_asmcode = 8'hc2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_asmcode = 8'hc3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_asmcode = 8'hc5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_asmcode = 8'hc6; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_asmcode = 8'hc8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_asmcode = 8'hc9; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_inv_a = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_inv_a = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_cry_out = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_form = 5'h11; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_in2_sel = 4'h9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_in2_sel = 4'h9; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_in2_sel = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_in2_sel = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub8_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h03: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h13: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h01: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h11: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h04: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h14: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h06: + dec31_dec_sub8_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h16: + dec31_dec_sub8_out_sel = 3'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" *) +(* generator = "nMigen" *) +module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, dec31_dec_sub9_form, dec31_dec_sub9_asmcode, dec31_dec_sub9_SV_Etype, dec31_dec_sub9_SV_Ptype, dec31_dec_sub9_in1_sel, dec31_dec_sub9_in2_sel, dec31_dec_sub9_in3_sel, dec31_dec_sub9_out_sel, dec31_dec_sub9_cr_in, dec31_dec_sub9_cr_out, dec31_dec_sub9_sv_in1, dec31_dec_sub9_sv_in2, dec31_dec_sub9_sv_in3, dec31_dec_sub9_sv_out, dec31_dec_sub9_sv_out2, dec31_dec_sub9_sv_cr_in, dec31_dec_sub9_sv_cr_out, dec31_dec_sub9_ldst_len, dec31_dec_sub9_upd, dec31_dec_sub9_rc_sel, dec31_dec_sub9_cry_in, dec31_dec_sub9_inv_a, dec31_dec_sub9_inv_out, dec31_dec_sub9_cry_out, dec31_dec_sub9_br, dec31_dec_sub9_sgn_ext, dec31_dec_sub9_rsrv, dec31_dec_sub9_is_32b, dec31_dec_sub9_sgn, dec31_dec_sub9_lk, dec31_dec_sub9_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub9_SV_Etype; + reg [1:0] dec31_dec_sub9_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub9_SV_Ptype; + reg [1:0] dec31_dec_sub9_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec31_dec_sub9_asmcode; + reg [7:0] dec31_dec_sub9_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_br; + reg dec31_dec_sub9_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_cr_in; + reg [2:0] dec31_dec_sub9_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_cr_out; + reg [2:0] dec31_dec_sub9_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub9_cry_in; + reg [1:0] dec31_dec_sub9_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_cry_out; + reg dec31_dec_sub9_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec31_dec_sub9_form; + reg [4:0] dec31_dec_sub9_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec31_dec_sub9_function_unit; + reg [13:0] dec31_dec_sub9_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_in1_sel; + reg [2:0] dec31_dec_sub9_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub9_in2_sel; + reg [3:0] dec31_dec_sub9_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub9_in3_sel; + reg [1:0] dec31_dec_sub9_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec31_dec_sub9_internal_op; + reg [6:0] dec31_dec_sub9_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_inv_a; + reg dec31_dec_sub9_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_inv_out; + reg dec31_dec_sub9_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_is_32b; + reg dec31_dec_sub9_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec31_dec_sub9_ldst_len; + reg [3:0] dec31_dec_sub9_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_lk; + reg dec31_dec_sub9_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_out_sel; + reg [2:0] dec31_dec_sub9_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub9_rc_sel; + reg [1:0] dec31_dec_sub9_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_rsrv; + reg dec31_dec_sub9_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_sgl_pipe; + reg dec31_dec_sub9_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_sgn; + reg dec31_dec_sub9_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec31_dec_sub9_sgn_ext; + reg dec31_dec_sub9_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_sv_cr_in; + reg [2:0] dec31_dec_sub9_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_sv_cr_out; + reg [2:0] dec31_dec_sub9_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_sv_in1; + reg [2:0] dec31_dec_sub9_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_sv_in2; + reg [2:0] dec31_dec_sub9_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_sv_in3; + reg [2:0] dec31_dec_sub9_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_sv_out; + reg [2:0] dec31_dec_sub9_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_sv_out2; + reg [2:0] dec31_dec_sub9_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec31_dec_sub9_upd; + reg [1:0] dec31_dec_sub9_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [4:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec31_dec_sub9_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_function_unit = 14'h0200; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_function_unit = 14'h0100; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_function_unit = 14'h0100; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sv_in2 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sv_cr_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sv_cr_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_ldst_len = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_internal_op = 7'h1e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_internal_op = 7'h1d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_internal_op = 7'h2f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_internal_op = 7'h2f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_internal_op = 7'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_internal_op = 7'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_internal_op = 7'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_internal_op = 7'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_internal_op = 7'h32; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_internal_op = 7'h32; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_rc_sel = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_asmcode = 8'h36; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_asmcode = 8'h37; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_asmcode = 8'h34; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_asmcode = 8'h35; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_asmcode = 8'h39; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_asmcode = 8'h3a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_asmcode = 8'h33; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_asmcode = 8'h38; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_asmcode = 8'h74; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_asmcode = 8'h72; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_asmcode = 8'h7a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_asmcode = 8'h7b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_asmcode = 8'h7a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_asmcode = 8'h7b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_asmcode = 8'h7e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_asmcode = 8'h7f; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_form = 5'h11; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_form = 5'h11; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sgn = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sgn = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_sgl_pipe = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_SV_Ptype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_in1_sel = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_in2_sel = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec31_dec_sub9_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0c: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1c: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0d: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1d: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0e: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1e: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h0f: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h1f: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h08: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h18: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h02: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h00: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h12: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h10: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h07: + dec31_dec_sub9_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 5'h17: + dec31_dec_sub9_out_sel = 3'h1; + endcase + end + assign opcode_switch = opcode_in[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec58" *) +(* generator = "nMigen" *) +module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, dec58_SV_Etype, dec58_SV_Ptype, dec58_in1_sel, dec58_in2_sel, dec58_in3_sel, dec58_out_sel, dec58_cr_in, dec58_cr_out, dec58_sv_in1, dec58_sv_in2, dec58_sv_in3, dec58_sv_out, dec58_sv_out2, dec58_sv_cr_in, dec58_sv_cr_out, dec58_ldst_len, dec58_upd, dec58_rc_sel, dec58_cry_in, dec58_inv_a, dec58_inv_out, dec58_cry_out, dec58_br, dec58_sgn_ext, dec58_rsrv, dec58_is_32b, dec58_sgn, dec58_lk, dec58_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec58_SV_Etype; + reg [1:0] dec58_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec58_SV_Ptype; + reg [1:0] dec58_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec58_asmcode; + reg [7:0] dec58_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_br; + reg dec58_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_cr_in; + reg [2:0] dec58_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_cr_out; + reg [2:0] dec58_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec58_cry_in; + reg [1:0] dec58_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_cry_out; + reg dec58_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec58_form; + reg [4:0] dec58_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec58_function_unit; + reg [13:0] dec58_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_in1_sel; + reg [2:0] dec58_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec58_in2_sel; + reg [3:0] dec58_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec58_in3_sel; + reg [1:0] dec58_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec58_internal_op; + reg [6:0] dec58_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_inv_a; + reg dec58_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_inv_out; + reg dec58_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_is_32b; + reg dec58_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec58_ldst_len; + reg [3:0] dec58_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_lk; + reg dec58_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_out_sel; + reg [2:0] dec58_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec58_rc_sel; + reg [1:0] dec58_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_rsrv; + reg dec58_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_sgl_pipe; + reg dec58_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_sgn; + reg dec58_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec58_sgn_ext; + reg dec58_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_sv_cr_in; + reg [2:0] dec58_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_sv_cr_out; + reg [2:0] dec58_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_sv_in1; + reg [2:0] dec58_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_sv_in2; + reg [2:0] dec58_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_sv_in3; + reg [2:0] dec58_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_sv_out; + reg [2:0] dec58_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec58_sv_out2; + reg [2:0] dec58_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec58_upd; + reg [1:0] dec58_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [1:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec58_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + dec58_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sv_in1 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sv_in3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sv_out = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sv_out2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_ldst_len = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + dec58_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_internal_op = 7'h25; + endcase + end + always @* begin + if (\initial ) begin end + dec58_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_upd = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_asmcode = 8'h52; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_asmcode = 8'h55; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_asmcode = 8'h62; + endcase + end + always @* begin + if (\initial ) begin end + dec58_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sgn_ext = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec58_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_form = 5'h05; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_form = 5'h05; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_form = 5'h05; + endcase + end + always @* begin + if (\initial ) begin end + dec58_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec58_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_SV_Etype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec58_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec58_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec58_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_in2_sel = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_in2_sel = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_in2_sel = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + dec58_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_in3_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_in3_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec58_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec58_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec58_out_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h2: + dec58_out_sel = 3'h1; + endcase + end + assign opcode_switch = opcode_in[1:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec.dec62" *) +(* generator = "nMigen" *) +module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, dec62_SV_Etype, dec62_SV_Ptype, dec62_in1_sel, dec62_in2_sel, dec62_in3_sel, dec62_out_sel, dec62_cr_in, dec62_cr_out, dec62_sv_in1, dec62_sv_in2, dec62_sv_in3, dec62_sv_out, dec62_sv_out2, dec62_sv_cr_in, dec62_sv_cr_out, dec62_ldst_len, dec62_upd, dec62_rc_sel, dec62_cry_in, dec62_inv_a, dec62_inv_out, dec62_cry_out, dec62_br, dec62_sgn_ext, dec62_rsrv, dec62_is_32b, dec62_sgn, dec62_lk, dec62_sgl_pipe, opcode_in); + reg \initial = 0; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec62_SV_Etype; + reg [1:0] dec62_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec62_SV_Ptype; + reg [1:0] dec62_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [7:0] dec62_asmcode; + reg [7:0] dec62_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_br; + reg dec62_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_cr_in; + reg [2:0] dec62_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_cr_out; + reg [2:0] dec62_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec62_cry_in; + reg [1:0] dec62_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_cry_out; + reg dec62_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [4:0] dec62_form; + reg [4:0] dec62_form; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [13:0] dec62_function_unit; + reg [13:0] dec62_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_in1_sel; + reg [2:0] dec62_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec62_in2_sel; + reg [3:0] dec62_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec62_in3_sel; + reg [1:0] dec62_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [6:0] dec62_internal_op; + reg [6:0] dec62_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_inv_a; + reg dec62_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_inv_out; + reg dec62_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_is_32b; + reg dec62_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [3:0] dec62_ldst_len; + reg [3:0] dec62_ldst_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_lk; + reg dec62_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_out_sel; + reg [2:0] dec62_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec62_rc_sel; + reg [1:0] dec62_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_rsrv; + reg dec62_rsrv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_sgl_pipe; + reg dec62_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_sgn; + reg dec62_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + output dec62_sgn_ext; + reg dec62_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_sv_cr_in; + reg [2:0] dec62_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_sv_cr_out; + reg [2:0] dec62_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_sv_in1; + reg [2:0] dec62_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_sv_in2; + reg [2:0] dec62_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_sv_in3; + reg [2:0] dec62_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_sv_out; + reg [2:0] dec62_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [2:0] dec62_sv_out2; + reg [2:0] dec62_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + output [1:0] dec62_upd; + reg [1:0] dec62_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + input [31:0] opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + wire [1:0] opcode_switch; + always @* begin + if (\initial ) begin end + dec62_function_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_function_unit = 14'h0004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_function_unit = 14'h0004; + endcase + end + always @* begin + if (\initial ) begin end + dec62_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sv_in1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sv_in1 = 3'h3; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sv_in2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sv_in2 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sv_in3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sv_in3 = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sv_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sv_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sv_out2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sv_out2 = 3'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sv_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sv_cr_in = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sv_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sv_cr_out = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_ldst_len = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + dec62_internal_op = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_internal_op = 7'h26; + endcase + end + always @* begin + if (\initial ) begin end + dec62_upd = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_upd = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec62_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_rc_sel = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_cry_in = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_asmcode = 8'had; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_asmcode = 8'hb0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_inv_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_inv_a = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_inv_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_inv_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_cry_out = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_br = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_br = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sgn_ext = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sgn_ext = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_rsrv = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_rsrv = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_form = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_form = 5'h05; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_form = 5'h05; + endcase + end + always @* begin + if (\initial ) begin end + dec62_is_32b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_is_32b = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sgn = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_lk = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dec62_sgl_pipe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_sgl_pipe = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec62_SV_Etype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_SV_Etype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec62_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_SV_Ptype = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec62_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_in1_sel = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + dec62_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_in2_sel = 4'h8; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_in2_sel = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + dec62_in3_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_in3_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_in3_sel = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + dec62_out_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h0: + dec62_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + 2'h1: + dec62_out_sel = 3'h0; + endcase + end + assign opcode_switch = opcode_in[1:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU" *) +(* generator = "nMigen" *) +module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__data, ALU__imm_data__ok, ALU__rc__rc, ALU__rc__ok, ALU__oe__oe, ALU__oe__ok, ALU__invert_in, ALU__zero_a, ALU__invert_out, ALU__write_cr0, ALU__input_carry, ALU__output_carry, ALU__is_32bit, ALU__is_signed, ALU__data_len, ALU__insn, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] ALU__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] ALU__fn_unit; + reg [13:0] ALU__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] ALU__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] ALU__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] ALU__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] ALU__insn_type; + reg [6:0] ALU__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__write_cr0; + reg ALU__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output ALU__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_ALU_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_ALU_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] dec_ALU_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_ALU_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_ALU_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_ALU_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_ALU_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_ALU_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_ALU_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_ALU_UI; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_ALU_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_ALU_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_ALU_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_ALU_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_ALU_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_ALU_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_ALU_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_ALU_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_ALU_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_ALU_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_ALU_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_ALU_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_ALU_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] dec_ALU_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + wire dec_ai_immz_out; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + wire [2:0] dec_ai_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + wire dec_ai_sv_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] dec_bi_imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_bi_imm_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + wire [3:0] dec_bi_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + input sv_a_nz; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + dec dec ( + .ALU_BD(dec_ALU_BD), + .ALU_DS(dec_ALU_DS), + .ALU_LI(dec_ALU_LI), + .ALU_OE(dec_ALU_OE), + .ALU_RA(dec_ALU_RA), + .ALU_Rc(dec_ALU_Rc), + .ALU_SH32(dec_ALU_SH32), + .ALU_SI(dec_ALU_SI), + .ALU_SPR(dec_ALU_SPR), + .ALU_UI(dec_ALU_UI), + .ALU_cr_out(dec_ALU_cr_out), + .ALU_cry_in(dec_ALU_cry_in), + .ALU_cry_out(dec_ALU_cry_out), + .ALU_function_unit(dec_ALU_function_unit), + .ALU_in1_sel(dec_ALU_in1_sel), + .ALU_in2_sel(dec_ALU_in2_sel), + .ALU_internal_op(dec_ALU_internal_op), + .ALU_inv_a(dec_ALU_inv_a), + .ALU_inv_out(dec_ALU_inv_out), + .ALU_is_32b(dec_ALU_is_32b), + .ALU_ldst_len(dec_ALU_ldst_len), + .ALU_rc_sel(dec_ALU_rc_sel), + .ALU_sgn(dec_ALU_sgn), + .ALU_sh(dec_ALU_sh), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + dec_ai dec_ai ( + .ALU_RA(dec_ALU_RA), + .immz_out(dec_ai_immz_out), + .sel_in(dec_ai_sel_in), + .sv_nz(dec_ai_sv_nz) + ); + dec_bi dec_bi ( + .ALU_BD(dec_ALU_BD), + .ALU_DS(dec_ALU_DS), + .ALU_LI(dec_ALU_LI), + .ALU_SH32(dec_ALU_SH32), + .ALU_SI(dec_ALU_SI), + .ALU_UI(dec_ALU_UI), + .ALU_sh(dec_ALU_sh), + .imm_b(dec_bi_imm_b), + .imm_b_ok(dec_bi_imm_b_ok), + .sel_in(dec_bi_sel_in) + ); + dec_oe dec_oe ( + .ALU_OE(dec_ALU_OE), + .ALU_internal_op(dec_ALU_internal_op), + .oe(dec_oe_oe), + .oe_ok(dec_oe_oe_ok), + .sel_in(dec_oe_sel_in) + ); + dec_rc dec_rc ( + .ALU_Rc(dec_ALU_Rc), + .rc(dec_rc_rc), + .rc_ok(dec_rc_rc_ok), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + ALU__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + casez (dec_ALU_cr_out) + /* \nmigen.decoding = "CR0/1|CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + 3'h1, 3'h5: + ALU__write_cr0 = dec_rc_rc; + /* \nmigen.decoding = "BF/2|BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + 3'h2, 3'h3: + ALU__write_cr0 = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ALU__insn_type = dec_ALU_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + ALU__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + ALU__insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + ALU__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + ALU__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + ALU__fn_unit = dec_ALU_function_unit; + endcase + end + assign ALU__is_signed = dec_ALU_sgn; + assign ALU__is_32bit = dec_ALU_is_32b; + assign ALU__output_carry = dec_ALU_cry_out; + assign ALU__input_carry = dec_ALU_cry_in; + assign ALU__invert_out = dec_ALU_inv_out; + assign ALU__invert_in = dec_ALU_inv_a; + assign ALU__data_len = dec_ALU_ldst_len; + assign { ALU__oe__ok, ALU__oe__oe } = { dec_oe_oe_ok, dec_oe_oe }; + assign { ALU__rc__ok, ALU__rc__rc } = { dec_rc_rc_ok, dec_rc_rc }; + assign { ALU__imm_data__ok, ALU__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b }; + assign dec_bi_sel_in = dec_ALU_in2_sel; + assign ALU__zero_a = dec_ai_immz_out; + assign dec_ai_sel_in = dec_ALU_in1_sel; + assign dec_ai_sv_nz = sv_a_nz; + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_ALU_SPR[4:0], dec_ALU_SPR[9:5] }; + assign dec_oe_sel_in = dec_ALU_rc_sel; + assign dec_rc_sel_in = dec_ALU_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign ALU__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_BRANCH" *) +(* generator = "nMigen" *) +module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRANCH__fn_unit, BRANCH__insn, BRANCH__imm_data__data, BRANCH__imm_data__ok, BRANCH__lk, BRANCH__is_32bit, core_pc); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] BRANCH__cia; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] BRANCH__fn_unit; + reg [13:0] BRANCH__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] BRANCH__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output BRANCH__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] BRANCH__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] BRANCH__insn_type; + reg [6:0] BRANCH__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output BRANCH__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output BRANCH__lk; + reg BRANCH__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + input [63:0] core_pc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_BRANCH_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_BRANCH_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] dec_BRANCH_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_BRANCH_LK; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_BRANCH_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_BRANCH_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_BRANCH_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_BRANCH_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_BRANCH_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_BRANCH_UI; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_BRANCH_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_BRANCH_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_BRANCH_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_BRANCH_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_BRANCH_is_32b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_BRANCH_lk; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_BRANCH_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] dec_BRANCH_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] dec_bi_imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_bi_imm_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + wire [3:0] dec_bi_sel_in; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + \dec$141 dec ( + .BRANCH_BD(dec_BRANCH_BD), + .BRANCH_DS(dec_BRANCH_DS), + .BRANCH_LI(dec_BRANCH_LI), + .BRANCH_LK(dec_BRANCH_LK), + .BRANCH_OE(dec_BRANCH_OE), + .BRANCH_Rc(dec_BRANCH_Rc), + .BRANCH_SH32(dec_BRANCH_SH32), + .BRANCH_SI(dec_BRANCH_SI), + .BRANCH_SPR(dec_BRANCH_SPR), + .BRANCH_UI(dec_BRANCH_UI), + .BRANCH_cr_out(dec_BRANCH_cr_out), + .BRANCH_function_unit(dec_BRANCH_function_unit), + .BRANCH_in2_sel(dec_BRANCH_in2_sel), + .BRANCH_internal_op(dec_BRANCH_internal_op), + .BRANCH_is_32b(dec_BRANCH_is_32b), + .BRANCH_lk(dec_BRANCH_lk), + .BRANCH_rc_sel(dec_BRANCH_rc_sel), + .BRANCH_sh(dec_BRANCH_sh), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + \dec_bi$144 dec_bi ( + .BRANCH_BD(dec_BRANCH_BD), + .BRANCH_DS(dec_BRANCH_DS), + .BRANCH_LI(dec_BRANCH_LI), + .BRANCH_SH32(dec_BRANCH_SH32), + .BRANCH_SI(dec_BRANCH_SI), + .BRANCH_UI(dec_BRANCH_UI), + .BRANCH_sh(dec_BRANCH_sh), + .imm_b(dec_bi_imm_b), + .imm_b_ok(dec_bi_imm_b_ok), + .sel_in(dec_bi_sel_in) + ); + \dec_oe$143 dec_oe ( + .BRANCH_OE(dec_BRANCH_OE), + .BRANCH_internal_op(dec_BRANCH_internal_op), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$142 dec_rc ( + .BRANCH_Rc(dec_BRANCH_Rc), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + BRANCH__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + BRANCH__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + BRANCH__fn_unit = dec_BRANCH_function_unit; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH__lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" *) + casez (dec_BRANCH_lk) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" */ + 1'h1: + BRANCH__lk = dec_BRANCH_LK; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH__insn_type = dec_BRANCH_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + BRANCH__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + BRANCH__insn_type = 7'h00; + endcase + end + assign BRANCH__is_32bit = dec_BRANCH_is_32b; + assign { BRANCH__imm_data__ok, BRANCH__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b }; + assign dec_bi_sel_in = dec_BRANCH_in2_sel; + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_BRANCH_SPR[4:0], dec_BRANCH_SPR[9:5] }; + assign BRANCH__cia = core_pc; + assign dec_oe_sel_in = dec_BRANCH_rc_sel; + assign dec_rc_sel_in = dec_BRANCH_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign BRANCH__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR" *) +(* generator = "nMigen" *) +module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] CR__fn_unit; + reg [13:0] CR__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] CR__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] CR__insn_type; + reg [6:0] CR__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_CR_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_CR_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_CR_SPR; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_CR_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_CR_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_CR_internal_op; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_CR_rc_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + \dec$138 dec ( + .CR_OE(dec_CR_OE), + .CR_Rc(dec_CR_Rc), + .CR_SPR(dec_CR_SPR), + .CR_cr_out(dec_CR_cr_out), + .CR_function_unit(dec_CR_function_unit), + .CR_internal_op(dec_CR_internal_op), + .CR_rc_sel(dec_CR_rc_sel), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + \dec_oe$140 dec_oe ( + .CR_OE(dec_CR_OE), + .CR_internal_op(dec_CR_internal_op), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$139 dec_rc ( + .CR_Rc(dec_CR_Rc), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + CR__insn_type = dec_CR_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + CR__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + CR__insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + CR__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + CR__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + CR__fn_unit = dec_CR_function_unit; + endcase + end + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_CR_SPR[4:0], dec_CR_SPR[9:5] }; + assign dec_oe_sel_in = dec_CR_rc_sel; + assign dec_rc_sel_in = dec_CR_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign CR__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV" *) +(* generator = "nMigen" *) +module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__data, DIV__imm_data__ok, DIV__rc__rc, DIV__rc__ok, DIV__oe__oe, DIV__oe__ok, DIV__invert_in, DIV__zero_a, DIV__input_carry, DIV__invert_out, DIV__write_cr0, DIV__output_carry, DIV__is_32bit, DIV__is_signed, DIV__data_len, DIV__insn, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] DIV__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] DIV__fn_unit; + reg [13:0] DIV__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] DIV__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] DIV__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] DIV__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] DIV__insn_type; + reg [6:0] DIV__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__write_cr0; + reg DIV__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output DIV__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_DIV_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_DIV_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] dec_DIV_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_DIV_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_DIV_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_DIV_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_DIV_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_DIV_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_DIV_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_DIV_UI; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_DIV_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_DIV_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_DIV_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_DIV_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_DIV_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_DIV_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_DIV_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_DIV_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_DIV_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_DIV_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_DIV_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_DIV_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_DIV_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] dec_DIV_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + wire dec_ai_immz_out; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + wire [2:0] dec_ai_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + wire dec_ai_sv_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] dec_bi_imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_bi_imm_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + wire [3:0] dec_bi_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + input sv_a_nz; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + \dec$153 dec ( + .DIV_BD(dec_DIV_BD), + .DIV_DS(dec_DIV_DS), + .DIV_LI(dec_DIV_LI), + .DIV_OE(dec_DIV_OE), + .DIV_RA(dec_DIV_RA), + .DIV_Rc(dec_DIV_Rc), + .DIV_SH32(dec_DIV_SH32), + .DIV_SI(dec_DIV_SI), + .DIV_SPR(dec_DIV_SPR), + .DIV_UI(dec_DIV_UI), + .DIV_cr_out(dec_DIV_cr_out), + .DIV_cry_in(dec_DIV_cry_in), + .DIV_cry_out(dec_DIV_cry_out), + .DIV_function_unit(dec_DIV_function_unit), + .DIV_in1_sel(dec_DIV_in1_sel), + .DIV_in2_sel(dec_DIV_in2_sel), + .DIV_internal_op(dec_DIV_internal_op), + .DIV_inv_a(dec_DIV_inv_a), + .DIV_inv_out(dec_DIV_inv_out), + .DIV_is_32b(dec_DIV_is_32b), + .DIV_ldst_len(dec_DIV_ldst_len), + .DIV_rc_sel(dec_DIV_rc_sel), + .DIV_sgn(dec_DIV_sgn), + .DIV_sh(dec_DIV_sh), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + \dec_ai$156 dec_ai ( + .DIV_RA(dec_DIV_RA), + .immz_out(dec_ai_immz_out), + .sel_in(dec_ai_sel_in), + .sv_nz(dec_ai_sv_nz) + ); + \dec_bi$157 dec_bi ( + .DIV_BD(dec_DIV_BD), + .DIV_DS(dec_DIV_DS), + .DIV_LI(dec_DIV_LI), + .DIV_SH32(dec_DIV_SH32), + .DIV_SI(dec_DIV_SI), + .DIV_UI(dec_DIV_UI), + .DIV_sh(dec_DIV_sh), + .imm_b(dec_bi_imm_b), + .imm_b_ok(dec_bi_imm_b_ok), + .sel_in(dec_bi_sel_in) + ); + \dec_oe$155 dec_oe ( + .DIV_OE(dec_DIV_OE), + .DIV_internal_op(dec_DIV_internal_op), + .oe(dec_oe_oe), + .oe_ok(dec_oe_oe_ok), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$154 dec_rc ( + .DIV_Rc(dec_DIV_Rc), + .rc(dec_rc_rc), + .rc_ok(dec_rc_rc_ok), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + DIV__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + casez (dec_DIV_cr_out) + /* \nmigen.decoding = "CR0/1|CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + 3'h1, 3'h5: + DIV__write_cr0 = dec_rc_rc; + /* \nmigen.decoding = "BF/2|BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + 3'h2, 3'h3: + DIV__write_cr0 = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + DIV__insn_type = dec_DIV_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + DIV__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + DIV__insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + DIV__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + DIV__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + DIV__fn_unit = dec_DIV_function_unit; + endcase + end + assign DIV__is_signed = dec_DIV_sgn; + assign DIV__is_32bit = dec_DIV_is_32b; + assign DIV__output_carry = dec_DIV_cry_out; + assign DIV__input_carry = dec_DIV_cry_in; + assign DIV__invert_out = dec_DIV_inv_out; + assign DIV__invert_in = dec_DIV_inv_a; + assign DIV__data_len = dec_DIV_ldst_len; + assign { DIV__oe__ok, DIV__oe__oe } = { dec_oe_oe_ok, dec_oe_oe }; + assign { DIV__rc__ok, DIV__rc__rc } = { dec_rc_rc_ok, dec_rc_rc }; + assign { DIV__imm_data__ok, DIV__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b }; + assign dec_bi_sel_in = dec_DIV_in2_sel; + assign DIV__zero_a = dec_ai_immz_out; + assign dec_ai_sel_in = dec_DIV_in1_sel; + assign dec_ai_sv_nz = sv_a_nz; + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_DIV_SPR[4:0], dec_DIV_SPR[9:5] }; + assign dec_oe_sel_in = dec_DIV_rc_sel; + assign dec_rc_sel_in = dec_DIV_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign DIV__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST" *) +(* generator = "nMigen" *) +module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_data__data, LDST__imm_data__ok, LDST__zero_a, LDST__rc__rc, LDST__rc__ok, LDST__oe__oe, LDST__oe__ok, LDST__is_32bit, LDST__is_signed, LDST__data_len, LDST__byte_reverse, LDST__sign_extend, LDST__ldst_mode, LDST__insn, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__byte_reverse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] LDST__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] LDST__fn_unit; + reg [13:0] LDST__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] LDST__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] LDST__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] LDST__insn_type; + reg [6:0] LDST__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__is_signed; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] LDST__ldst_mode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__sign_extend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LDST__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_LDST_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_LDST_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] dec_LDST_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_LDST_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_LDST_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_LDST_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_LDST_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_LDST_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_LDST_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_LDST_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LDST_br; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_LDST_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_LDST_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_LDST_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_LDST_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_LDST_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LDST_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_LDST_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_LDST_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LDST_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LDST_sgn_ext; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] dec_LDST_sh; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_LDST_upd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + wire dec_ai_immz_out; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + wire [2:0] dec_ai_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + wire dec_ai_sv_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] dec_bi_imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_bi_imm_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + wire [3:0] dec_bi_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + input sv_a_nz; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + \dec$166 dec ( + .LDST_BD(dec_LDST_BD), + .LDST_DS(dec_LDST_DS), + .LDST_LI(dec_LDST_LI), + .LDST_OE(dec_LDST_OE), + .LDST_RA(dec_LDST_RA), + .LDST_Rc(dec_LDST_Rc), + .LDST_SH32(dec_LDST_SH32), + .LDST_SI(dec_LDST_SI), + .LDST_SPR(dec_LDST_SPR), + .LDST_UI(dec_LDST_UI), + .LDST_br(dec_LDST_br), + .LDST_cr_out(dec_LDST_cr_out), + .LDST_function_unit(dec_LDST_function_unit), + .LDST_in1_sel(dec_LDST_in1_sel), + .LDST_in2_sel(dec_LDST_in2_sel), + .LDST_internal_op(dec_LDST_internal_op), + .LDST_is_32b(dec_LDST_is_32b), + .LDST_ldst_len(dec_LDST_ldst_len), + .LDST_rc_sel(dec_LDST_rc_sel), + .LDST_sgn(dec_LDST_sgn), + .LDST_sgn_ext(dec_LDST_sgn_ext), + .LDST_sh(dec_LDST_sh), + .LDST_upd(dec_LDST_upd), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + \dec_ai$169 dec_ai ( + .LDST_RA(dec_LDST_RA), + .immz_out(dec_ai_immz_out), + .sel_in(dec_ai_sel_in), + .sv_nz(dec_ai_sv_nz) + ); + \dec_bi$170 dec_bi ( + .LDST_BD(dec_LDST_BD), + .LDST_DS(dec_LDST_DS), + .LDST_LI(dec_LDST_LI), + .LDST_SH32(dec_LDST_SH32), + .LDST_SI(dec_LDST_SI), + .LDST_UI(dec_LDST_UI), + .LDST_sh(dec_LDST_sh), + .imm_b(dec_bi_imm_b), + .imm_b_ok(dec_bi_imm_b_ok), + .sel_in(dec_bi_sel_in) + ); + \dec_oe$168 dec_oe ( + .LDST_OE(dec_LDST_OE), + .LDST_internal_op(dec_LDST_internal_op), + .oe(dec_oe_oe), + .oe_ok(dec_oe_oe_ok), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$167 dec_rc ( + .LDST_Rc(dec_LDST_Rc), + .rc(dec_rc_rc), + .rc_ok(dec_rc_rc_ok), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + LDST__insn_type = dec_LDST_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + LDST__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + LDST__insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + LDST__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + LDST__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + LDST__fn_unit = dec_LDST_function_unit; + endcase + end + assign LDST__ldst_mode = dec_LDST_upd; + assign LDST__sign_extend = dec_LDST_sgn_ext; + assign LDST__byte_reverse = dec_LDST_br; + assign LDST__is_signed = dec_LDST_sgn; + assign LDST__is_32bit = dec_LDST_is_32b; + assign LDST__data_len = dec_LDST_ldst_len; + assign { LDST__oe__ok, LDST__oe__oe } = { dec_oe_oe_ok, dec_oe_oe }; + assign { LDST__rc__ok, LDST__rc__rc } = { dec_rc_rc_ok, dec_rc_rc }; + assign { LDST__imm_data__ok, LDST__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b }; + assign dec_bi_sel_in = dec_LDST_in2_sel; + assign LDST__zero_a = dec_ai_immz_out; + assign dec_ai_sel_in = dec_LDST_in1_sel; + assign dec_ai_sv_nz = sv_a_nz; + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_LDST_SPR[4:0], dec_LDST_SPR[9:5] }; + assign dec_oe_sel_in = dec_LDST_rc_sel; + assign dec_rc_sel_in = dec_LDST_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign LDST__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL" *) +(* generator = "nMigen" *) +module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOGICAL__imm_data__data, LOGICAL__imm_data__ok, LOGICAL__rc__rc, LOGICAL__rc__ok, LOGICAL__oe__oe, LOGICAL__oe__ok, LOGICAL__invert_in, LOGICAL__zero_a, LOGICAL__input_carry, LOGICAL__invert_out, LOGICAL__write_cr0, LOGICAL__output_carry, LOGICAL__is_32bit, LOGICAL__is_signed, LOGICAL__data_len, LOGICAL__insn, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] LOGICAL__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] LOGICAL__fn_unit; + reg [13:0] LOGICAL__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] LOGICAL__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] LOGICAL__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] LOGICAL__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] LOGICAL__insn_type; + reg [6:0] LOGICAL__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__write_cr0; + reg LOGICAL__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output LOGICAL__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_LOGICAL_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_LOGICAL_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] dec_LOGICAL_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_LOGICAL_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_LOGICAL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_LOGICAL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_LOGICAL_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_LOGICAL_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_LOGICAL_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_LOGICAL_UI; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_LOGICAL_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_LOGICAL_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LOGICAL_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_LOGICAL_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_LOGICAL_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_LOGICAL_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_LOGICAL_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LOGICAL_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LOGICAL_inv_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LOGICAL_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_LOGICAL_ldst_len; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_LOGICAL_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_LOGICAL_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] dec_LOGICAL_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + wire dec_ai_immz_out; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + wire [2:0] dec_ai_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + wire dec_ai_sv_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] dec_bi_imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_bi_imm_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + wire [3:0] dec_bi_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + input sv_a_nz; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + \dec$145 dec ( + .LOGICAL_BD(dec_LOGICAL_BD), + .LOGICAL_DS(dec_LOGICAL_DS), + .LOGICAL_LI(dec_LOGICAL_LI), + .LOGICAL_OE(dec_LOGICAL_OE), + .LOGICAL_RA(dec_LOGICAL_RA), + .LOGICAL_Rc(dec_LOGICAL_Rc), + .LOGICAL_SH32(dec_LOGICAL_SH32), + .LOGICAL_SI(dec_LOGICAL_SI), + .LOGICAL_SPR(dec_LOGICAL_SPR), + .LOGICAL_UI(dec_LOGICAL_UI), + .LOGICAL_cr_out(dec_LOGICAL_cr_out), + .LOGICAL_cry_in(dec_LOGICAL_cry_in), + .LOGICAL_cry_out(dec_LOGICAL_cry_out), + .LOGICAL_function_unit(dec_LOGICAL_function_unit), + .LOGICAL_in1_sel(dec_LOGICAL_in1_sel), + .LOGICAL_in2_sel(dec_LOGICAL_in2_sel), + .LOGICAL_internal_op(dec_LOGICAL_internal_op), + .LOGICAL_inv_a(dec_LOGICAL_inv_a), + .LOGICAL_inv_out(dec_LOGICAL_inv_out), + .LOGICAL_is_32b(dec_LOGICAL_is_32b), + .LOGICAL_ldst_len(dec_LOGICAL_ldst_len), + .LOGICAL_rc_sel(dec_LOGICAL_rc_sel), + .LOGICAL_sgn(dec_LOGICAL_sgn), + .LOGICAL_sh(dec_LOGICAL_sh), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + \dec_ai$148 dec_ai ( + .LOGICAL_RA(dec_LOGICAL_RA), + .immz_out(dec_ai_immz_out), + .sel_in(dec_ai_sel_in), + .sv_nz(dec_ai_sv_nz) + ); + \dec_bi$149 dec_bi ( + .LOGICAL_BD(dec_LOGICAL_BD), + .LOGICAL_DS(dec_LOGICAL_DS), + .LOGICAL_LI(dec_LOGICAL_LI), + .LOGICAL_SH32(dec_LOGICAL_SH32), + .LOGICAL_SI(dec_LOGICAL_SI), + .LOGICAL_UI(dec_LOGICAL_UI), + .LOGICAL_sh(dec_LOGICAL_sh), + .imm_b(dec_bi_imm_b), + .imm_b_ok(dec_bi_imm_b_ok), + .sel_in(dec_bi_sel_in) + ); + \dec_oe$147 dec_oe ( + .LOGICAL_OE(dec_LOGICAL_OE), + .LOGICAL_internal_op(dec_LOGICAL_internal_op), + .oe(dec_oe_oe), + .oe_ok(dec_oe_oe_ok), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$146 dec_rc ( + .LOGICAL_Rc(dec_LOGICAL_Rc), + .rc(dec_rc_rc), + .rc_ok(dec_rc_rc_ok), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + LOGICAL__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + casez (dec_LOGICAL_cr_out) + /* \nmigen.decoding = "CR0/1|CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + 3'h1, 3'h5: + LOGICAL__write_cr0 = dec_rc_rc; + /* \nmigen.decoding = "BF/2|BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + 3'h2, 3'h3: + LOGICAL__write_cr0 = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL__insn_type = dec_LOGICAL_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + LOGICAL__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + LOGICAL__insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + LOGICAL__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + LOGICAL__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + LOGICAL__fn_unit = dec_LOGICAL_function_unit; + endcase + end + assign LOGICAL__is_signed = dec_LOGICAL_sgn; + assign LOGICAL__is_32bit = dec_LOGICAL_is_32b; + assign LOGICAL__output_carry = dec_LOGICAL_cry_out; + assign LOGICAL__input_carry = dec_LOGICAL_cry_in; + assign LOGICAL__invert_out = dec_LOGICAL_inv_out; + assign LOGICAL__invert_in = dec_LOGICAL_inv_a; + assign LOGICAL__data_len = dec_LOGICAL_ldst_len; + assign { LOGICAL__oe__ok, LOGICAL__oe__oe } = { dec_oe_oe_ok, dec_oe_oe }; + assign { LOGICAL__rc__ok, LOGICAL__rc__rc } = { dec_rc_rc_ok, dec_rc_rc }; + assign { LOGICAL__imm_data__ok, LOGICAL__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b }; + assign dec_bi_sel_in = dec_LOGICAL_in2_sel; + assign LOGICAL__zero_a = dec_ai_immz_out; + assign dec_ai_sel_in = dec_LOGICAL_in1_sel; + assign dec_ai_sv_nz = sv_a_nz; + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_LOGICAL_SPR[4:0], dec_LOGICAL_SPR[9:5] }; + assign dec_oe_sel_in = dec_LOGICAL_rc_sel; + assign dec_rc_sel_in = dec_LOGICAL_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign LOGICAL__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL" *) +(* generator = "nMigen" *) +module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL__imm_data__ok, MUL__rc__rc, MUL__rc__ok, MUL__oe__oe, MUL__oe__ok, MUL__write_cr0, MUL__is_32bit, MUL__is_signed, MUL__insn, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] MUL__fn_unit; + reg [13:0] MUL__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] MUL__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output MUL__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] MUL__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] MUL__insn_type; + reg [6:0] MUL__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output MUL__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output MUL__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output MUL__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output MUL__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output MUL__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output MUL__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output MUL__write_cr0; + reg MUL__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_MUL_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_MUL_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] dec_MUL_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_MUL_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_MUL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_MUL_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_MUL_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_MUL_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_MUL_UI; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_MUL_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_MUL_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_MUL_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_MUL_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_MUL_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_MUL_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_MUL_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] dec_MUL_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] dec_bi_imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_bi_imm_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + wire [3:0] dec_bi_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + \dec$158 dec ( + .MUL_BD(dec_MUL_BD), + .MUL_DS(dec_MUL_DS), + .MUL_LI(dec_MUL_LI), + .MUL_OE(dec_MUL_OE), + .MUL_Rc(dec_MUL_Rc), + .MUL_SH32(dec_MUL_SH32), + .MUL_SI(dec_MUL_SI), + .MUL_SPR(dec_MUL_SPR), + .MUL_UI(dec_MUL_UI), + .MUL_cr_out(dec_MUL_cr_out), + .MUL_function_unit(dec_MUL_function_unit), + .MUL_in2_sel(dec_MUL_in2_sel), + .MUL_internal_op(dec_MUL_internal_op), + .MUL_is_32b(dec_MUL_is_32b), + .MUL_rc_sel(dec_MUL_rc_sel), + .MUL_sgn(dec_MUL_sgn), + .MUL_sh(dec_MUL_sh), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + \dec_bi$161 dec_bi ( + .MUL_BD(dec_MUL_BD), + .MUL_DS(dec_MUL_DS), + .MUL_LI(dec_MUL_LI), + .MUL_SH32(dec_MUL_SH32), + .MUL_SI(dec_MUL_SI), + .MUL_UI(dec_MUL_UI), + .MUL_sh(dec_MUL_sh), + .imm_b(dec_bi_imm_b), + .imm_b_ok(dec_bi_imm_b_ok), + .sel_in(dec_bi_sel_in) + ); + \dec_oe$160 dec_oe ( + .MUL_OE(dec_MUL_OE), + .MUL_internal_op(dec_MUL_internal_op), + .oe(dec_oe_oe), + .oe_ok(dec_oe_oe_ok), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$159 dec_rc ( + .MUL_Rc(dec_MUL_Rc), + .rc(dec_rc_rc), + .rc_ok(dec_rc_rc_ok), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + MUL__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + casez (dec_MUL_cr_out) + /* \nmigen.decoding = "CR0/1|CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + 3'h1, 3'h5: + MUL__write_cr0 = dec_rc_rc; + /* \nmigen.decoding = "BF/2|BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + 3'h2, 3'h3: + MUL__write_cr0 = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + MUL__insn_type = dec_MUL_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + MUL__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + MUL__insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + MUL__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + MUL__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + MUL__fn_unit = dec_MUL_function_unit; + endcase + end + assign MUL__is_signed = dec_MUL_sgn; + assign MUL__is_32bit = dec_MUL_is_32b; + assign { MUL__oe__ok, MUL__oe__oe } = { dec_oe_oe_ok, dec_oe_oe }; + assign { MUL__rc__ok, MUL__rc__rc } = { dec_rc_rc_ok, dec_rc_rc }; + assign { MUL__imm_data__ok, MUL__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b }; + assign dec_bi_sel_in = dec_MUL_in2_sel; + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_MUL_SPR[4:0], dec_MUL_SPR[9:5] }; + assign dec_oe_sel_in = dec_MUL_rc_sel; + assign dec_rc_sel_in = dec_MUL_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign MUL__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT" *) +(* generator = "nMigen" *) +module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ROT__imm_data__data, SHIFT_ROT__imm_data__ok, SHIFT_ROT__rc__rc, SHIFT_ROT__rc__ok, SHIFT_ROT__oe__oe, SHIFT_ROT__oe__ok, SHIFT_ROT__write_cr0, SHIFT_ROT__invert_in, SHIFT_ROT__input_carry, SHIFT_ROT__output_carry, SHIFT_ROT__input_cr, SHIFT_ROT__output_cr, SHIFT_ROT__is_32bit, SHIFT_ROT__is_signed, SHIFT_ROT__insn, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] SHIFT_ROT__fn_unit; + reg [13:0] SHIFT_ROT__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] SHIFT_ROT__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] SHIFT_ROT__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] SHIFT_ROT__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] SHIFT_ROT__insn_type; + reg [6:0] SHIFT_ROT__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SHIFT_ROT__write_cr0; + reg SHIFT_ROT__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_SHIFT_ROT_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [13:0] dec_SHIFT_ROT_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [23:0] dec_SHIFT_ROT_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_SHIFT_ROT_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_SHIFT_ROT_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [4:0] dec_SHIFT_ROT_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_SHIFT_ROT_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_SHIFT_ROT_SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [15:0] dec_SHIFT_ROT_UI; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_SHIFT_ROT_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_SHIFT_ROT_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_SHIFT_ROT_cry_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_SHIFT_ROT_cry_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_SHIFT_ROT_function_unit; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [3:0] dec_SHIFT_ROT_in2_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_SHIFT_ROT_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_SHIFT_ROT_inv_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_SHIFT_ROT_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_SHIFT_ROT_rc_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_SHIFT_ROT_sgn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [5:0] dec_SHIFT_ROT_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] dec_bi_imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_bi_imm_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + wire [3:0] dec_bi_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_oe_oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec_rc_rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + \dec$162 dec ( + .SHIFT_ROT_BD(dec_SHIFT_ROT_BD), + .SHIFT_ROT_DS(dec_SHIFT_ROT_DS), + .SHIFT_ROT_LI(dec_SHIFT_ROT_LI), + .SHIFT_ROT_OE(dec_SHIFT_ROT_OE), + .SHIFT_ROT_Rc(dec_SHIFT_ROT_Rc), + .SHIFT_ROT_SH32(dec_SHIFT_ROT_SH32), + .SHIFT_ROT_SI(dec_SHIFT_ROT_SI), + .SHIFT_ROT_SPR(dec_SHIFT_ROT_SPR), + .SHIFT_ROT_UI(dec_SHIFT_ROT_UI), + .SHIFT_ROT_cr_in(dec_SHIFT_ROT_cr_in), + .SHIFT_ROT_cr_out(dec_SHIFT_ROT_cr_out), + .SHIFT_ROT_cry_in(dec_SHIFT_ROT_cry_in), + .SHIFT_ROT_cry_out(dec_SHIFT_ROT_cry_out), + .SHIFT_ROT_function_unit(dec_SHIFT_ROT_function_unit), + .SHIFT_ROT_in2_sel(dec_SHIFT_ROT_in2_sel), + .SHIFT_ROT_internal_op(dec_SHIFT_ROT_internal_op), + .SHIFT_ROT_inv_a(dec_SHIFT_ROT_inv_a), + .SHIFT_ROT_is_32b(dec_SHIFT_ROT_is_32b), + .SHIFT_ROT_rc_sel(dec_SHIFT_ROT_rc_sel), + .SHIFT_ROT_sgn(dec_SHIFT_ROT_sgn), + .SHIFT_ROT_sh(dec_SHIFT_ROT_sh), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + \dec_bi$165 dec_bi ( + .SHIFT_ROT_BD(dec_SHIFT_ROT_BD), + .SHIFT_ROT_DS(dec_SHIFT_ROT_DS), + .SHIFT_ROT_LI(dec_SHIFT_ROT_LI), + .SHIFT_ROT_SH32(dec_SHIFT_ROT_SH32), + .SHIFT_ROT_SI(dec_SHIFT_ROT_SI), + .SHIFT_ROT_UI(dec_SHIFT_ROT_UI), + .SHIFT_ROT_sh(dec_SHIFT_ROT_sh), + .imm_b(dec_bi_imm_b), + .imm_b_ok(dec_bi_imm_b_ok), + .sel_in(dec_bi_sel_in) + ); + \dec_oe$164 dec_oe ( + .SHIFT_ROT_OE(dec_SHIFT_ROT_OE), + .SHIFT_ROT_internal_op(dec_SHIFT_ROT_internal_op), + .oe(dec_oe_oe), + .oe_ok(dec_oe_oe_ok), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$163 dec_rc ( + .SHIFT_ROT_Rc(dec_SHIFT_ROT_Rc), + .rc(dec_rc_rc), + .rc_ok(dec_rc_rc_ok), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + SHIFT_ROT__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + casez (dec_SHIFT_ROT_cr_out) + /* \nmigen.decoding = "CR0/1|CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + 3'h1, 3'h5: + SHIFT_ROT__write_cr0 = dec_rc_rc; + /* \nmigen.decoding = "BF/2|BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + 3'h2, 3'h3: + SHIFT_ROT__write_cr0 = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT__insn_type = dec_SHIFT_ROT_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + SHIFT_ROT__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + SHIFT_ROT__insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + SHIFT_ROT__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + SHIFT_ROT__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + SHIFT_ROT__fn_unit = dec_SHIFT_ROT_function_unit; + endcase + end + assign SHIFT_ROT__is_signed = dec_SHIFT_ROT_sgn; + assign SHIFT_ROT__is_32bit = dec_SHIFT_ROT_is_32b; + assign SHIFT_ROT__output_carry = dec_SHIFT_ROT_cry_out; + assign SHIFT_ROT__input_carry = dec_SHIFT_ROT_cry_in; + assign SHIFT_ROT__invert_in = dec_SHIFT_ROT_inv_a; + assign SHIFT_ROT__output_cr = dec_SHIFT_ROT_cr_out[0]; + assign SHIFT_ROT__input_cr = dec_SHIFT_ROT_cr_in[0]; + assign { SHIFT_ROT__oe__ok, SHIFT_ROT__oe__oe } = { dec_oe_oe_ok, dec_oe_oe }; + assign { SHIFT_ROT__rc__ok, SHIFT_ROT__rc__rc } = { dec_rc_rc_ok, dec_rc_rc }; + assign { SHIFT_ROT__imm_data__ok, SHIFT_ROT__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b }; + assign dec_bi_sel_in = dec_SHIFT_ROT_in2_sel; + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_SHIFT_ROT_SPR[4:0], dec_SHIFT_ROT_SPR[9:5] }; + assign dec_oe_sel_in = dec_SHIFT_ROT_rc_sel; + assign dec_rc_sel_in = dec_SHIFT_ROT_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign SHIFT_ROT__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SPR" *) +(* generator = "nMigen" *) +module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit, raw_opcode_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + wire \$8 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] SPR__fn_unit; + reg [13:0] SPR__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] SPR__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] SPR__insn_type; + reg [6:0] SPR__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output SPR__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + input bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_SPR_OE; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire dec_SPR_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [9:0] dec_SPR_SPR; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [2:0] dec_SPR_cr_out; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [13:0] dec_SPR_function_unit; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [6:0] dec_SPR_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + wire dec_SPR_is_32b; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + wire [1:0] dec_SPR_rc_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + wire [1:0] dec_oe_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + wire [31:0] dec_opcode_in; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + wire [1:0] dec_rc_sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + wire [31:0] insn_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + wire [31:0] \insn_in$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + wire is_mmu_spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + wire is_spr_mv; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + input [31:0] raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + wire [9:0] spr; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; + assign \$16 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; + assign \$18 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; + assign \$2 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; + assign \$36 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$42 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; + assign \$8 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + \dec$150 dec ( + .SPR_OE(dec_SPR_OE), + .SPR_Rc(dec_SPR_Rc), + .SPR_SPR(dec_SPR_SPR), + .SPR_cr_out(dec_SPR_cr_out), + .SPR_function_unit(dec_SPR_function_unit), + .SPR_internal_op(dec_SPR_internal_op), + .SPR_is_32b(dec_SPR_is_32b), + .SPR_rc_sel(dec_SPR_rc_sel), + .bigendian(bigendian), + .opcode_in(dec_opcode_in), + .raw_opcode_in(raw_opcode_in) + ); + \dec_oe$152 dec_oe ( + .SPR_OE(dec_SPR_OE), + .SPR_internal_op(dec_SPR_internal_op), + .sel_in(dec_oe_sel_in) + ); + \dec_rc$151 dec_rc ( + .SPR_Rc(dec_SPR_Rc), + .sel_in(dec_rc_sel_in) + ); + always @* begin + if (\initial ) begin end + SPR__insn_type = dec_SPR_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + SPR__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + SPR__insn_type = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + 2'b?1: + SPR__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + 2'b1?: + SPR__fn_unit = 14'h0000; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + default: + SPR__fn_unit = dec_SPR_function_unit; + endcase + end + assign SPR__is_32bit = dec_SPR_is_32b; + assign is_mmu_spr = \$34 ; + assign is_spr_mv = \$20 ; + assign spr = { dec_SPR_SPR[4:0], dec_SPR_SPR[9:5] }; + assign dec_oe_sel_in = dec_SPR_rc_sel; + assign dec_rc_sel_in = dec_SPR_rc_sel; + assign \insn_in$1 = dec_opcode_in; + assign insn_in = dec_opcode_in; + assign SPR__insn = dec_opcode_in; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_a" *) +(* generator = "nMigen" *) +module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_a_ok, RS, RA, BO, XL_XO, internal_op); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [9:0] SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + input [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fast_a; + reg [2:0] fast_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast_a_ok; + reg fast_a_ok; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" *) + wire [4:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [4:0] reg_a; + reg [4:0] reg_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output reg_a_ok; + reg reg_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" *) + wire [4:0] rs; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" *) + input [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" *) + reg [9:0] spr; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [9:0] spr_a; + reg [9:0] spr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr_a_ok; + reg spr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] sprmap_fast_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire sprmap_fast_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + reg [9:0] sprmap_spr_i; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [9:0] sprmap_spr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire sprmap_spr_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" *) + input sv_nz; + assign \$9 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$7 ; + assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$9 ; + assign \$13 = \$1 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$11 ; + assign \$15 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) 3'h4; + assign \$17 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) 3'h1; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) 3'h1; + assign \$19 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) 3'h2; + assign \$21 = ra != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 5'h00; + assign \$23 = sv_nz != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 1'h0; + assign \$25 = \$21 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$23 ; + assign \$27 = \$19 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$25 ; + assign \$29 = \$17 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$27 ; + assign \$31 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) 3'h4; + assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) BO[2]; + assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) XL_XO[5]; + assign \$37 = XL_XO[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) \$35 ; + assign \$3 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) 3'h2; + assign \$5 = ra != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 5'h00; + assign \$7 = sv_nz != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 1'h0; + sprmap sprmap ( + .fast_o(sprmap_fast_o), + .fast_o_ok(sprmap_fast_o_ok), + .spr_i(sprmap_spr_i), + .spr_o(sprmap_spr_o), + .spr_o_ok(sprmap_spr_o_ok) + ); + always @* begin + if (\initial ) begin end + reg_a = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" */ + 1'h1: + reg_a = ra; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" */ + 1'h1: + reg_a = rs; + endcase + end + always @* begin + if (\initial ) begin end + reg_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" */ + 1'h1: + reg_a_ok = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" */ + 1'h1: + reg_a_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + fast_a = 3'h0; + fast_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + 7'h07: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) + casez (\$33 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" */ + 1'h1: + begin + fast_a = 3'h0; + fast_a_ok = 1'h1; + end + endcase + /* \nmigen.decoding = "OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + 7'h08: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) + casez (\$37 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" */ + 1'h1: + begin + fast_a = 3'h0; + fast_a_ok = 1'h1; + end + endcase + /* \nmigen.decoding = "OP_MFSPR/46" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + 7'h2e: + { fast_a_ok, fast_a } = { sprmap_fast_o_ok, sprmap_fast_o }; + endcase + end + always @* begin + if (\initial ) begin end + spr = 10'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + 7'h07: + /* empty */; + /* \nmigen.decoding = "OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + 7'h08: + /* empty */; + /* \nmigen.decoding = "OP_MFSPR/46" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + 7'h2e: + spr = { SPR[4:0], SPR[9:5] }; + endcase + end + always @* begin + if (\initial ) begin end + sprmap_spr_i = 10'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + 7'h07: + /* empty */; + /* \nmigen.decoding = "OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + 7'h08: + /* empty */; + /* \nmigen.decoding = "OP_MFSPR/46" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + 7'h2e: + sprmap_spr_i = spr; + endcase + end + always @* begin + if (\initial ) begin end + spr_a = 10'h000; + spr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + 7'h07: + /* empty */; + /* \nmigen.decoding = "OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + 7'h08: + /* empty */; + /* \nmigen.decoding = "OP_MFSPR/46" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + 7'h2e: + { spr_a_ok, spr_a } = { sprmap_spr_o_ok, sprmap_spr_o }; + endcase + end + assign rs = RS; + assign ra = RA; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec_ai" *) +(* generator = "nMigen" *) +module dec_ai(sel_in, immz_out, ALU_RA, sv_nz); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] ALU_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + output immz_out; + reg immz_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + wire [4:0] ra; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + input [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + input sv_nz; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + always @* begin + if (\initial ) begin end + immz_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + 1'h1: + immz_out = 1'h1; + endcase + end + assign ra = ALU_RA; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec_ai" *) +(* generator = "nMigen" *) +module \dec_ai$148 (sel_in, immz_out, LOGICAL_RA, sv_nz); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] LOGICAL_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + output immz_out; + reg immz_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + wire [4:0] ra; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + input [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + input sv_nz; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + always @* begin + if (\initial ) begin end + immz_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + 1'h1: + immz_out = 1'h1; + endcase + end + assign ra = LOGICAL_RA; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec_ai" *) +(* generator = "nMigen" *) +module \dec_ai$156 (sel_in, immz_out, DIV_RA, sv_nz); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] DIV_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + output immz_out; + reg immz_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + wire [4:0] ra; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + input [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + input sv_nz; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + always @* begin + if (\initial ) begin end + immz_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + 1'h1: + immz_out = 1'h1; + endcase + end + assign ra = DIV_RA; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec_ai" *) +(* generator = "nMigen" *) +module \dec_ai$169 (sel_in, immz_out, LDST_RA, sv_nz); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] LDST_RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + output immz_out; + reg immz_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + wire [4:0] ra; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + input [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + input sv_nz; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + always @* begin + if (\initial ) begin end + immz_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + 1'h1: + immz_out = 1'h1; + endcase + end + assign ra = LDST_RA; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_b" *) +(* generator = "nMigen" *) +module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal_op); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [6:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [6:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + input [9:0] XL_XO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fast_b; + reg [2:0] fast_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast_b_ok; + reg fast_b_ok; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [6:0] reg_b; + reg [6:0] reg_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output reg_b_ok; + reg reg_b_ok; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" *) + input [3:0] sel_in; + assign \$9 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) 7'h08; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) XL_XO[9]; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) RB; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) RS; + assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) 7'h08; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) XL_XO[9]; + always @* begin + if (\initial ) begin end + reg_b = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" *) + casez (sel_in) + /* \nmigen.decoding = "RB/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" */ + 4'h1: + reg_b = \$1 ; + /* \nmigen.decoding = "RS/13" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" */ + 4'hd: + reg_b = \$3 ; + endcase + end + always @* begin + if (\initial ) begin end + reg_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" *) + casez (sel_in) + /* \nmigen.decoding = "RB/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" */ + 4'h1: + reg_b_ok = 1'h1; + /* \nmigen.decoding = "RS/13" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" */ + 4'hd: + reg_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + fast_b = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + casez (\$5 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + casez ({ XL_XO[5], \$7 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" */ + 2'b?1: + fast_b = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:240" */ + 2'b1?: + fast_b = 3'h2; + endcase + endcase + end + always @* begin + if (\initial ) begin end + fast_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + casez ({ XL_XO[5], \$11 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" */ + 2'b?1: + fast_b_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:240" */ + 2'b1?: + fast_b_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec_bi" *) +(* generator = "nMigen" *) +module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, ALU_DS, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [63:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [46:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + wire [63:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] ALU_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] ALU_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [23:0] ALU_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] ALU_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] ALU_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] ALU_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [5:0] ALU_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + reg [15:0] bd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + reg [15:0] ds; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] imm_b; + reg [63:0] imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output imm_b_ok; + reg imm_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + reg [25:0] li; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + input [3:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + reg [15:0] si; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + reg [31:0] si_hi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + reg [15:0] ui; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_SH32; + assign \$14 = ALU_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; + assign \$17 = ALU_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_UI; + assign \$20 = ALU_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; + assign \$23 = ALU_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + always @* begin + if (\initial ) begin end + imm_b = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b = \$1 ; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b = \$3 ; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b = \$7 ; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b = \$9 ; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b = \$11 ; + endcase + end + always @* begin + if (\initial ) begin end + imm_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + si = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + si = ALU_SI; + endcase + end + always @* begin + if (\initial ) begin end + si_hi = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + si_hi = \$13 [31:0]; + endcase + end + always @* begin + if (\initial ) begin end + ui = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + ui = ALU_UI; + endcase + end + always @* begin + if (\initial ) begin end + li = 26'h0000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + li = \$16 [25:0]; + endcase + end + always @* begin + if (\initial ) begin end + bd = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + bd = \$19 [15:0]; + endcase + end + always @* begin + if (\initial ) begin end + ds = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + ds = \$22 [15:0]; + endcase + end + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign \$22 = \$23 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_BRANCH.dec_bi" *) +(* generator = "nMigen" *) +module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_sh, BRANCH_LI, BRANCH_BD, BRANCH_DS, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [63:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [46:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + wire [63:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] BRANCH_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] BRANCH_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [23:0] BRANCH_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] BRANCH_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] BRANCH_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] BRANCH_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [5:0] BRANCH_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + reg [15:0] bd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + reg [15:0] ds; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] imm_b; + reg [63:0] imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output imm_b_ok; + reg imm_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + reg [25:0] li; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + input [3:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + reg [15:0] si; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + reg [31:0] si_hi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + reg [15:0] ui; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_SH32; + assign \$14 = BRANCH_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; + assign \$17 = BRANCH_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_UI; + assign \$20 = BRANCH_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; + assign \$23 = BRANCH_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + always @* begin + if (\initial ) begin end + imm_b = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b = \$1 ; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b = \$3 ; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b = \$7 ; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b = \$9 ; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b = \$11 ; + endcase + end + always @* begin + if (\initial ) begin end + imm_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + si = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + si = BRANCH_SI; + endcase + end + always @* begin + if (\initial ) begin end + si_hi = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + si_hi = \$13 [31:0]; + endcase + end + always @* begin + if (\initial ) begin end + ui = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + ui = BRANCH_UI; + endcase + end + always @* begin + if (\initial ) begin end + li = 26'h0000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + li = \$16 [25:0]; + endcase + end + always @* begin + if (\initial ) begin end + bd = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + bd = \$19 [15:0]; + endcase + end + always @* begin + if (\initial ) begin end + ds = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + ds = \$22 [15:0]; + endcase + end + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign \$22 = \$23 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec_bi" *) +(* generator = "nMigen" *) +module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGICAL_sh, LOGICAL_LI, LOGICAL_BD, LOGICAL_DS, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [63:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [46:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + wire [63:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] LOGICAL_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] LOGICAL_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [23:0] LOGICAL_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] LOGICAL_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] LOGICAL_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] LOGICAL_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [5:0] LOGICAL_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + reg [15:0] bd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + reg [15:0] ds; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] imm_b; + reg [63:0] imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output imm_b_ok; + reg imm_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + reg [25:0] li; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + input [3:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + reg [15:0] si; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + reg [31:0] si_hi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + reg [15:0] ui; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_SH32; + assign \$14 = LOGICAL_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; + assign \$17 = LOGICAL_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_UI; + assign \$20 = LOGICAL_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; + assign \$23 = LOGICAL_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + always @* begin + if (\initial ) begin end + imm_b = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b = \$1 ; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b = \$3 ; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b = \$7 ; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b = \$9 ; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b = \$11 ; + endcase + end + always @* begin + if (\initial ) begin end + imm_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + si = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + si = LOGICAL_SI; + endcase + end + always @* begin + if (\initial ) begin end + si_hi = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + si_hi = \$13 [31:0]; + endcase + end + always @* begin + if (\initial ) begin end + ui = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + ui = LOGICAL_UI; + endcase + end + always @* begin + if (\initial ) begin end + li = 26'h0000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + li = \$16 [25:0]; + endcase + end + always @* begin + if (\initial ) begin end + bd = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + bd = \$19 [15:0]; + endcase + end + always @* begin + if (\initial ) begin end + ds = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + ds = \$22 [15:0]; + endcase + end + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign \$22 = \$23 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec_bi" *) +(* generator = "nMigen" *) +module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, DIV_BD, DIV_DS, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [63:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [46:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + wire [63:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] DIV_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] DIV_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [23:0] DIV_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] DIV_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] DIV_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] DIV_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [5:0] DIV_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + reg [15:0] bd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + reg [15:0] ds; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] imm_b; + reg [63:0] imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output imm_b_ok; + reg imm_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + reg [25:0] li; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + input [3:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + reg [15:0] si; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + reg [31:0] si_hi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + reg [15:0] ui; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_SH32; + assign \$14 = DIV_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; + assign \$17 = DIV_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_UI; + assign \$20 = DIV_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; + assign \$23 = DIV_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + always @* begin + if (\initial ) begin end + imm_b = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b = \$1 ; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b = \$3 ; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b = \$7 ; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b = \$9 ; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b = \$11 ; + endcase + end + always @* begin + if (\initial ) begin end + imm_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + si = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + si = DIV_SI; + endcase + end + always @* begin + if (\initial ) begin end + si_hi = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + si_hi = \$13 [31:0]; + endcase + end + always @* begin + if (\initial ) begin end + ui = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + ui = DIV_UI; + endcase + end + always @* begin + if (\initial ) begin end + li = 26'h0000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + li = \$16 [25:0]; + endcase + end + always @* begin + if (\initial ) begin end + bd = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + bd = \$19 [15:0]; + endcase + end + always @* begin + if (\initial ) begin end + ds = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + ds = \$22 [15:0]; + endcase + end + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign \$22 = \$23 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec_bi" *) +(* generator = "nMigen" *) +module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, MUL_BD, MUL_DS, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [63:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [46:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + wire [63:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] MUL_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] MUL_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [23:0] MUL_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] MUL_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] MUL_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] MUL_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [5:0] MUL_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + reg [15:0] bd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + reg [15:0] ds; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] imm_b; + reg [63:0] imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output imm_b_ok; + reg imm_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + reg [25:0] li; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + input [3:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + reg [15:0] si; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + reg [31:0] si_hi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + reg [15:0] ui; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_SH32; + assign \$14 = MUL_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; + assign \$17 = MUL_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_UI; + assign \$20 = MUL_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; + assign \$23 = MUL_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + always @* begin + if (\initial ) begin end + imm_b = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b = \$1 ; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b = \$3 ; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b = \$7 ; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b = \$9 ; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b = \$11 ; + endcase + end + always @* begin + if (\initial ) begin end + imm_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + si = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + si = MUL_SI; + endcase + end + always @* begin + if (\initial ) begin end + si_hi = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + si_hi = \$13 [31:0]; + endcase + end + always @* begin + if (\initial ) begin end + ui = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + ui = MUL_UI; + endcase + end + always @* begin + if (\initial ) begin end + li = 26'h0000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + li = \$16 [25:0]; + endcase + end + always @* begin + if (\initial ) begin end + bd = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + bd = \$19 [15:0]; + endcase + end + always @* begin + if (\initial ) begin end + ds = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + ds = \$22 [15:0]; + endcase + end + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign \$22 = \$23 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" *) +(* generator = "nMigen" *) +module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, SHIFT_ROT_sh, SHIFT_ROT_LI, SHIFT_ROT_BD, SHIFT_ROT_DS, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [63:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [46:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + wire [63:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] SHIFT_ROT_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] SHIFT_ROT_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [23:0] SHIFT_ROT_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] SHIFT_ROT_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] SHIFT_ROT_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] SHIFT_ROT_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [5:0] SHIFT_ROT_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + reg [15:0] bd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + reg [15:0] ds; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] imm_b; + reg [63:0] imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output imm_b_ok; + reg imm_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + reg [25:0] li; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + input [3:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + reg [15:0] si; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + reg [31:0] si_hi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + reg [15:0] ui; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_SH32; + assign \$14 = SHIFT_ROT_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; + assign \$17 = SHIFT_ROT_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_UI; + assign \$20 = SHIFT_ROT_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; + assign \$23 = SHIFT_ROT_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + always @* begin + if (\initial ) begin end + imm_b = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b = \$1 ; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b = \$3 ; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b = \$7 ; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b = \$9 ; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b = \$11 ; + endcase + end + always @* begin + if (\initial ) begin end + imm_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + si = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + si = SHIFT_ROT_SI; + endcase + end + always @* begin + if (\initial ) begin end + si_hi = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + si_hi = \$13 [31:0]; + endcase + end + always @* begin + if (\initial ) begin end + ui = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + ui = SHIFT_ROT_UI; + endcase + end + always @* begin + if (\initial ) begin end + li = 26'h0000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + li = \$16 [25:0]; + endcase + end + always @* begin + if (\initial ) begin end + bd = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + bd = \$19 [15:0]; + endcase + end + always @* begin + if (\initial ) begin end + ds = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + ds = \$22 [15:0]; + endcase + end + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign \$22 = \$23 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec_bi" *) +(* generator = "nMigen" *) +module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_LI, LDST_BD, LDST_DS, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + wire [46:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + wire [26:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + wire [16:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + wire [16:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [63:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + wire [46:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + wire [63:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + wire [63:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] LDST_BD; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [13:0] LDST_DS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [23:0] LDST_LI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] LDST_SH32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] LDST_SI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [15:0] LDST_UI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [5:0] LDST_sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + reg [15:0] bd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + reg [15:0] ds; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] imm_b; + reg [63:0] imm_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output imm_b_ok; + reg imm_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + reg [25:0] li; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + input [3:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + reg [15:0] si; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + reg [31:0] si_hi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + reg [15:0] ui; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_SH32; + assign \$14 = LDST_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; + assign \$17 = LDST_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_UI; + assign \$20 = LDST_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; + assign \$23 = LDST_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + always @* begin + if (\initial ) begin end + imm_b = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b = \$1 ; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b = \$3 ; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b = \$7 ; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b = \$9 ; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b = \$11 ; + endcase + end + always @* begin + if (\initial ) begin end + imm_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_M1/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + 4'h9: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + 4'ha: + imm_b_ok = 1'h1; + /* \nmigen.decoding = "CONST_SH32/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + 4'hb: + imm_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + si = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + si = LDST_SI; + endcase + end + always @* begin + if (\initial ) begin end + si_hi = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + si_hi = \$13 [31:0]; + endcase + end + always @* begin + if (\initial ) begin end + ui = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + ui = LDST_UI; + endcase + end + always @* begin + if (\initial ) begin end + li = 26'h0000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + li = \$16 [25:0]; + endcase + end + always @* begin + if (\initial ) begin end + bd = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + bd = \$19 [15:0]; + endcase + end + always @* begin + if (\initial ) begin end + ds = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + casez (sel_in) + /* \nmigen.decoding = "CONST_UI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "CONST_SI/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "CONST_SI_HI/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "CONST_UI_HI/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CONST_LI/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "CONST_BD/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "CONST_DS/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + 4'h8: + ds = \$22 [15:0]; + endcase + end + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign \$22 = \$23 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_c" *) +(* generator = "nMigen" *) +module dec_c(reg_c, reg_c_ok, RS, RB, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RS; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [4:0] reg_c; + reg [4:0] reg_c; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output reg_c_ok; + reg reg_c_ok; + (* enum_base_type = "In3Sel" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "RS" *) + (* enum_value_10 = "RB" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + reg_c = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" *) + casez (sel_in) + /* \nmigen.decoding = "RB/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327" */ + 2'h2: + reg_c = RB; + /* \nmigen.decoding = "RS/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" */ + 2'h1: + reg_c = RS; + endcase + end + always @* begin + if (\initial ) begin end + reg_c_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" *) + casez (sel_in) + /* \nmigen.decoding = "RB/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327" */ + 2'h2: + reg_c_ok = 1'h1; + /* \nmigen.decoding = "RS/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" */ + 2'h1: + reg_c_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_cr_in" *) +(* generator = "nMigen" *) +module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok, cr_bitfield_b, cr_bitfield_b_ok, cr_bitfield_o, cr_bitfield_o_ok, BB, BA, BT, FXM, BI, BC, X_BFA, internal_op); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] BA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] BB; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] BI; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [7:0] FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + input [2:0] X_BFA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] cr_bitfield; + reg [2:0] cr_bitfield; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] cr_bitfield_b; + reg [2:0] cr_bitfield_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_bitfield_b_ok; + reg cr_bitfield_b_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] cr_bitfield_o; + reg [2:0] cr_bitfield_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_bitfield_o_ok; + reg cr_bitfield_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_bitfield_ok; + reg cr_bitfield_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [7:0] cr_fxm; + reg [7:0] cr_fxm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_fxm_ok; + reg cr_fxm_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" *) + input [31:0] insn_in; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" *) + reg move_one; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + reg [7:0] ppick_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [7:0] ppick_o; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" *) + input [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" *) + reg [1:0] sv_override; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) 7'h2d; + assign \$3 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) move_one; + assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) 7'h2d; + assign \$7 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) move_one; + ppick ppick ( + .i(ppick_i), + .o(ppick_o) + ); + always @* begin + if (\initial ) begin end + cr_bitfield_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + cr_bitfield_ok = 1'h1; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + cr_bitfield_ok = 1'h1; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + cr_bitfield_ok = 1'h1; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + cr_bitfield_ok = 1'h1; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + cr_bitfield_ok = 1'h1; + /* \nmigen.decoding = "BC/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + 3'h5: + cr_bitfield_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + cr_bitfield_b_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + /* empty */; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + cr_bitfield_b_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + cr_fxm = 8'h00; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + /* empty */; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "BC/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "WHOLE_REG/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + 3'h6: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + casez (\$7 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" */ + 1'h1: + cr_fxm = ppick_o; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600" */ + default: + cr_fxm = 8'hff; + endcase + endcase + end + always @* begin + if (\initial ) begin end + cr_bitfield_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + /* empty */; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + cr_bitfield_o_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + cr_fxm_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + /* empty */; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "BC/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "WHOLE_REG/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + 3'h6: + cr_fxm_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + sv_override = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + sv_override = 2'h1; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + sv_override = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + cr_bitfield = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + cr_bitfield = 3'h0; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + cr_bitfield = 3'h1; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + cr_bitfield = BI[4:2]; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + cr_bitfield = X_BFA; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + cr_bitfield = BA[4:2]; + /* \nmigen.decoding = "BC/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + 3'h5: + cr_bitfield = BC[4:2]; + endcase + end + always @* begin + if (\initial ) begin end + cr_bitfield_b = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + /* empty */; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + cr_bitfield_b = BB[4:2]; + endcase + end + always @* begin + if (\initial ) begin end + cr_bitfield_o = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + /* empty */; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + cr_bitfield_o = BT[4:2]; + endcase + end + always @* begin + if (\initial ) begin end + move_one = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + /* empty */; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "BC/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "WHOLE_REG/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + 3'h6: + move_one = insn_in[20]; + endcase + end + always @* begin + if (\initial ) begin end + ppick_i = 8'h00; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + 3'h7: + /* empty */; + /* \nmigen.decoding = "BI/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BFA/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "BA_BB/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "BC/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "WHOLE_REG/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + 3'h6: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" */ + 1'h1: + ppick_i = FXM; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_cr_out" *) +(* generator = "nMigen" *) +module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok, FXM, X_BF, XL_BT, internal_op); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [7:0] FXM; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + input [4:0] XL_BT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + input [2:0] X_BF; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] cr_bitfield; + reg [2:0] cr_bitfield; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_bitfield_ok; + reg cr_bitfield_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [7:0] cr_fxm; + reg [7:0] cr_fxm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_fxm_ok; + reg cr_fxm_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" *) + input [31:0] insn_in; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:659" *) + reg move_one; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire ppick_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + reg [7:0] ppick_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire [7:0] ppick_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" *) + input rc_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" *) + input [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:621" *) + reg [1:0] sv_override; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) 7'h30; + assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) 7'h30; + \ppick$175 ppick ( + .en_o(ppick_en_o), + .i(ppick_i), + .o(ppick_o) + ); + always @* begin + if (\initial ) begin end + cr_bitfield_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + 3'h1: + cr_bitfield_ok = rc_in; + /* \nmigen.decoding = "CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + 3'h5: + cr_bitfield_ok = rc_in; + /* \nmigen.decoding = "BF/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + 3'h2: + cr_bitfield_ok = 1'h1; + /* \nmigen.decoding = "BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + 3'h3: + cr_bitfield_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + cr_fxm_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "BF/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "WHOLE_REG/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + 3'h4: + cr_fxm_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + sv_override = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + 3'h1: + sv_override = 2'h1; + /* \nmigen.decoding = "CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + 3'h5: + sv_override = 2'h2; + endcase + end + always @* begin + if (\initial ) begin end + cr_bitfield = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + 3'h1: + cr_bitfield = 3'h0; + /* \nmigen.decoding = "CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + 3'h5: + cr_bitfield = 3'h1; + /* \nmigen.decoding = "BF/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + 3'h2: + cr_bitfield = X_BF; + /* \nmigen.decoding = "BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + 3'h3: + cr_bitfield = XL_BT[4:2]; + endcase + end + always @* begin + if (\initial ) begin end + move_one = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "BF/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "WHOLE_REG/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + 3'h4: + move_one = insn_in[20]; + endcase + end + always @* begin + if (\initial ) begin end + ppick_i = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "BF/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "WHOLE_REG/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + 3'h4: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *) + casez (move_one) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" */ + 1'h1: + ppick_i = FXM; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + cr_fxm = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + casez (sel_in) + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "CR0/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "CR1/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "BF/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "BT/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "WHOLE_REG/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + 3'h4: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *) + casez (move_one) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" *) + casez (ppick_en_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" */ + 1'h1: + cr_fxm = ppick_o; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:667" */ + default: + cr_fxm = 8'h01; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:669" */ + default: + cr_fxm = FXM; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" */ + default: + cr_fxm = 8'hff; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_o" *) +(* generator = "nMigen" *) +module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, RT, RA, BO, internal_op); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] BO; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RT; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [9:0] SPR; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fast_o; + reg [2:0] fast_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast_o_ok; + reg fast_o_ok; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [4:0] reg_o; + reg [4:0] reg_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output reg_o_ok; + reg reg_o_ok; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" *) + input [2:0] sel_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" *) + reg [9:0] spr; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [9:0] spr_o; + reg [9:0] spr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr_o_ok; + reg spr_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] sprmap_fast_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire sprmap_fast_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + reg [9:0] sprmap_spr_i; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [9:0] sprmap_spr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire sprmap_spr_o_ok; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; + assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; + assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) BO[2]; + \sprmap$174 sprmap ( + .fast_o(sprmap_fast_o), + .fast_o_ok(sprmap_fast_o_ok), + .spr_i(sprmap_spr_i), + .spr_o(sprmap_spr_o), + .spr_o_ok(sprmap_spr_o_ok) + ); + always @* begin + if (\initial ) begin end + reg_o = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + casez (sel_in) + /* \nmigen.decoding = "RT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + 3'h1: + reg_o = RT; + /* \nmigen.decoding = "RA/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + 3'h2: + reg_o = RA; + endcase + end + always @* begin + if (\initial ) begin end + reg_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + casez (sel_in) + /* \nmigen.decoding = "RT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + 3'h1: + reg_o_ok = 1'h1; + /* \nmigen.decoding = "RA/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + 3'h2: + reg_o_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + spr = 10'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + casez (sel_in) + /* \nmigen.decoding = "RT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "RA/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "SPR/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + 3'h3: + spr = { SPR[4:0], SPR[9:5] }; + endcase + end + always @* begin + if (\initial ) begin end + sprmap_spr_i = 10'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + casez (sel_in) + /* \nmigen.decoding = "RT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "RA/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "SPR/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + 3'h3: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + 1'h1: + sprmap_spr_i = spr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + spr_o = 10'h000; + spr_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + casez (sel_in) + /* \nmigen.decoding = "RT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "RA/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "SPR/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + 3'h3: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + 1'h1: + { spr_o_ok, spr_o } = { sprmap_spr_o_ok, sprmap_spr_o }; + endcase + endcase + end + always @* begin + if (\initial ) begin end + fast_o = 3'h0; + fast_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + casez (sel_in) + /* \nmigen.decoding = "RT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "RA/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "SPR/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + 3'h3: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + casez (\$5 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + 1'h1: + { fast_o_ok, fast_o } = { sprmap_fast_o_ok, sprmap_fast_o }; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:382" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7|OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" */ + 7'h07, 7'h08: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) + casez (\$7 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" */ + 1'h1: + begin + fast_o = 3'h0; + fast_o_ok = 1'h1; + end + endcase + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:392" */ + 7'h46: + begin + fast_o = 3'h3; + fast_o_ok = 1'h1; + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_o2" *) +(* generator = "nMigen" *) +module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input [4:0] RA; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fast_o2; + reg [2:0] fast_o2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast_o2_ok; + reg fast_o2_ok; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" *) + input lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [4:0] reg_o2; + reg [4:0] reg_o2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output reg_o2_ok; + reg reg_o2_ok; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [1:0] upd; + assign \$1 = upd == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) 2'h1; + assign \$3 = upd == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) 2'h1; + always @* begin + if (\initial ) begin end + reg_o2 = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" */ + 1'h1: + reg_o2 = RA; + endcase + end + always @* begin + if (\initial ) begin end + reg_o2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" */ + 1'h1: + reg_o2_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + fast_o2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7|OP_B/6|OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" */ + 7'h07, 7'h06, 7'h08: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" *) + casez (lk) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" */ + 1'h1: + fast_o2 = 3'h1; + endcase + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447" */ + 7'h46: + fast_o2 = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + fast_o2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7|OP_B/6|OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" */ + 7'h07, 7'h06, 7'h08: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" *) + casez (lk) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" */ + 1'h1: + fast_o2_ok = 1'h1; + endcase + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447" */ + 7'h46: + fast_o2_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec_oe" *) +(* generator = "nMigen" *) +module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input ALU_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] ALU_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe; + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe_ok; + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (ALU_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = ALU_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (ALU_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input CR_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] CR_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (CR_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = CR_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (CR_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_BRANCH.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input BRANCH_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] BRANCH_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (BRANCH_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = BRANCH_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (BRANCH_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input LOGICAL_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] LOGICAL_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe; + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe_ok; + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (LOGICAL_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = LOGICAL_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (LOGICAL_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SPR.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input SPR_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] SPR_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (SPR_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = SPR_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (SPR_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input DIV_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] DIV_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe; + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe_ok; + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (DIV_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = DIV_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (DIV_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input MUL_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] MUL_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe; + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe_ok; + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (MUL_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = MUL_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (MUL_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input SHIFT_ROT_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] SHIFT_ROT_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe; + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe_ok; + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (SHIFT_ROT_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = SHIFT_ROT_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (SHIFT_ROT_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input LDST_OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] LDST_internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe; + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe_ok; + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (LDST_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = LDST_OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (LDST_internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_oe" *) +(* generator = "nMigen" *) +module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input OE; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + input [6:0] internal_op; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe; + reg oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output oe_ok; + reg oe_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + oe = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe = OE; + endcase + endcase + end + always @* begin + if (\initial ) begin end + oe_ok = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + casez (internal_op) + /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + 2'h2: + oe_ok = 1'h1; + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec_rc" *) +(* generator = "nMigen" *) +module dec_rc(rc, rc_ok, ALU_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input ALU_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc; + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc_ok; + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = ALU_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$139 (CR_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input CR_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = CR_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_BRANCH.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$142 (BRANCH_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input BRANCH_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = BRANCH_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$146 (rc, rc_ok, LOGICAL_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input LOGICAL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc; + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc_ok; + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = LOGICAL_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SPR.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$151 (SPR_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input SPR_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = SPR_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$154 (rc, rc_ok, DIV_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input DIV_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc; + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc_ok; + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = DIV_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$159 (rc, rc_ok, MUL_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input MUL_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc; + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc_ok; + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = MUL_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$163 (rc, rc_ok, SHIFT_ROT_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input SHIFT_ROT_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc; + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc_ok; + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = SHIFT_ROT_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$167 (rc, rc_ok, LDST_Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input LDST_Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc; + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc_ok; + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = LDST_Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_rc" *) +(* generator = "nMigen" *) +module \dec_rc$172 (rc, rc_ok, Rc, sel_in); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + input Rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc; + reg rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output rc_ok; + reg rc_ok; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + input [1:0] sel_in; + always @* begin + if (\initial ) begin end + rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc = Rc; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + casez (sel_in) + /* \nmigen.decoding = "RC/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + 2'h2: + rc_ok = 1'h1; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + 2'h1: + rc_ok = 1'h1; + /* \nmigen.decoding = "NONE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + 2'h0: + rc_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0" *) +(* generator = "nMigen" *) +module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$114 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [3:0] \$118 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [3:0] \$120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$122 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$126 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$128 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [3:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [3:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [3:0] \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [3:0] \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [3:0] \$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [2:0] \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [3:0] \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [3:0] \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$86 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$88 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$90 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire \$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] alu_div0_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] alu_div0_logical_op__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \alu_div0_logical_op__data_len$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_div0_logical_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_div0_logical_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_div0_logical_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_div0_logical_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__imm_data__ok$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] alu_div0_logical_op__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \alu_div0_logical_op__input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_div0_logical_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_div0_logical_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_div0_logical_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_div0_logical_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__invert_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__invert_out$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__output_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_div0_logical_op__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_div0_logical_op__zero_a$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_div0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_div0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_div0_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_div0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_div0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_div0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_div0_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] alu_div0_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire alu_div0_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \alu_div0_xer_so$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [3:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [3:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [3:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [3:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] data_r1__cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] \data_r1__cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] data_r2__xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] \data_r2__xer_ov$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r2__xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r2__xer_ov_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__xer_so$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__xer_so_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] dest2_o; + reg [3:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest3_o; + reg [1:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output dest4_o; + reg dest4_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] oper_i_alu_div0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_div0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_div0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_alu_div0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_div0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_div0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [3:0] prev_wr_go = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [3:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [3:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [3:0] req_l_r_req = 4'hf; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [3:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [3:0] req_l_s_req = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [3:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [2:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [3:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input src3_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [2:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] src_l_r_src = 3'h7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] src_l_s_src = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] src_or_imm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] \src_or_imm$85 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg src_r2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire src_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire \src_sel$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + assign \$100 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_div0_logical_op__zero_a; + assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_div0_logical_op__imm_data__ok; + assign \$104 = \$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 1'h1, \$102 , \$100 }; + assign \$106 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + assign \$108 = \$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$106 ; + assign \$10 = \$2 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$4 ; + assign \$110 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$112 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$114 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$116 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$118 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$110 , \$112 , \$114 , \$116 }; + assign \$120 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$122 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$124 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$126 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$128 = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$14 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$12 ; + assign \$16 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$18 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$16 ; + assign \$20 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$26 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; + assign \$23 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ; + assign \$22 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; + assign \$2 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$30 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$22 ; + assign \$32 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$36 = \$32 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$34 ; + assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_div0_n_ready_i; + assign \$40 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$38 ; + assign \$42 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$44 = \$42 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$46 = \$40 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$44 ; + assign \$48 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$50 = \$48 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_div0_n_ready_i; + assign \$52 = \$50 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_div0_n_valid_o; + assign \$54 = \$52 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$56 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$58 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$60 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$62 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$64 = alu_div0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$66 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$68 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$70 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$72 = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$74 = xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$76 = xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$78 = alu_div0_logical_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[0]; + assign \$7 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$80 = alu_div0_logical_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) 64'h0000000000000000 : src1_i; + assign \$83 = alu_div0_logical_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1]; + assign \$86 = alu_div0_logical_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_div0_logical_op__imm_data__data : src2_i; + assign \$88 = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r0; + assign \$4 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$7 ; + assign \$90 = \src_sel$82 ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) \src_or_imm$85 : src_r1; + assign \$92 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$94 = alu_div0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$96 = alu_div0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$98 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r3__xer_so <= \data_r3__xer_so$next ; + always @(posedge coresync_clk) + data_r3__xer_so_ok <= \data_r3__xer_so_ok$next ; + always @(posedge coresync_clk) + data_r2__xer_ov <= \data_r2__xer_ov$next ; + always @(posedge coresync_clk) + data_r2__xer_ov_ok <= \data_r2__xer_ov_ok$next ; + always @(posedge coresync_clk) + data_r1__cr_a <= \data_r1__cr_a$next ; + always @(posedge coresync_clk) + data_r1__cr_a_ok <= \data_r1__cr_a_ok$next ; + always @(posedge coresync_clk) + data_r0__o <= \data_r0__o$next ; + always @(posedge coresync_clk) + data_r0__o_ok <= \data_r0__o_ok$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__insn_type <= \alu_div0_logical_op__insn_type$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__fn_unit <= \alu_div0_logical_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__imm_data__data <= \alu_div0_logical_op__imm_data__data$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__imm_data__ok <= \alu_div0_logical_op__imm_data__ok$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__rc__rc <= \alu_div0_logical_op__rc__rc$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__rc__ok <= \alu_div0_logical_op__rc__ok$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__oe__oe <= \alu_div0_logical_op__oe__oe$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__oe__ok <= \alu_div0_logical_op__oe__ok$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__invert_in <= \alu_div0_logical_op__invert_in$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__zero_a <= \alu_div0_logical_op__zero_a$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__input_carry <= \alu_div0_logical_op__input_carry$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__invert_out <= \alu_div0_logical_op__invert_out$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__write_cr0 <= \alu_div0_logical_op__write_cr0$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__output_carry <= \alu_div0_logical_op__output_carry$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__is_32bit <= \alu_div0_logical_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__is_signed <= \alu_div0_logical_op__is_signed$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__data_len <= \alu_div0_logical_op__data_len$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__insn <= \alu_div0_logical_op__insn$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_div0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$10 ; + alu_div0 alu_div0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(alu_div0_cr_a), + .cr_a_ok(cr_a_ok), + .logical_op__data_len(alu_div0_logical_op__data_len), + .logical_op__fn_unit(alu_div0_logical_op__fn_unit), + .logical_op__imm_data__data(alu_div0_logical_op__imm_data__data), + .logical_op__imm_data__ok(alu_div0_logical_op__imm_data__ok), + .logical_op__input_carry(alu_div0_logical_op__input_carry), + .logical_op__insn(alu_div0_logical_op__insn), + .logical_op__insn_type(alu_div0_logical_op__insn_type), + .logical_op__invert_in(alu_div0_logical_op__invert_in), + .logical_op__invert_out(alu_div0_logical_op__invert_out), + .logical_op__is_32bit(alu_div0_logical_op__is_32bit), + .logical_op__is_signed(alu_div0_logical_op__is_signed), + .logical_op__oe__oe(alu_div0_logical_op__oe__oe), + .logical_op__oe__ok(alu_div0_logical_op__oe__ok), + .logical_op__output_carry(alu_div0_logical_op__output_carry), + .logical_op__rc__ok(alu_div0_logical_op__rc__ok), + .logical_op__rc__rc(alu_div0_logical_op__rc__rc), + .logical_op__write_cr0(alu_div0_logical_op__write_cr0), + .logical_op__zero_a(alu_div0_logical_op__zero_a), + .n_ready_i(alu_div0_n_ready_i), + .n_valid_o(alu_div0_n_valid_o), + .o(alu_div0_o), + .o_ok(o_ok), + .p_ready_o(alu_div0_p_ready_o), + .p_valid_i(alu_div0_p_valid_i), + .ra(alu_div0_ra), + .rb(alu_div0_rb), + .xer_ov(alu_div0_xer_ov), + .xer_ov_ok(xer_ov_ok), + .xer_so(alu_div0_xer_so), + .\xer_so$1 (\alu_div0_xer_so$1 ), + .xer_so_ok(xer_so_ok) + ); + \alu_l$90 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + \alui_l$89 alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + \opc_l$85 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \req_l$86 req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + \rok_l$88 rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + \rst_l$87 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$84 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$54 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$64 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$66 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$68 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 4'hf; + endcase + end + always @* begin + if (\initial ) begin end + \alu_div0_logical_op__insn_type$next = alu_div0_logical_op__insn_type; + \alu_div0_logical_op__fn_unit$next = alu_div0_logical_op__fn_unit; + \alu_div0_logical_op__imm_data__data$next = alu_div0_logical_op__imm_data__data; + \alu_div0_logical_op__imm_data__ok$next = alu_div0_logical_op__imm_data__ok; + \alu_div0_logical_op__rc__rc$next = alu_div0_logical_op__rc__rc; + \alu_div0_logical_op__rc__ok$next = alu_div0_logical_op__rc__ok; + \alu_div0_logical_op__oe__oe$next = alu_div0_logical_op__oe__oe; + \alu_div0_logical_op__oe__ok$next = alu_div0_logical_op__oe__ok; + \alu_div0_logical_op__invert_in$next = alu_div0_logical_op__invert_in; + \alu_div0_logical_op__zero_a$next = alu_div0_logical_op__zero_a; + \alu_div0_logical_op__input_carry$next = alu_div0_logical_op__input_carry; + \alu_div0_logical_op__invert_out$next = alu_div0_logical_op__invert_out; + \alu_div0_logical_op__write_cr0$next = alu_div0_logical_op__write_cr0; + \alu_div0_logical_op__output_carry$next = alu_div0_logical_op__output_carry; + \alu_div0_logical_op__is_32bit$next = alu_div0_logical_op__is_32bit; + \alu_div0_logical_op__is_signed$next = alu_div0_logical_op__is_signed; + \alu_div0_logical_op__data_len$next = alu_div0_logical_op__data_len; + \alu_div0_logical_op__insn$next = alu_div0_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_div0_logical_op__insn$next , \alu_div0_logical_op__data_len$next , \alu_div0_logical_op__is_signed$next , \alu_div0_logical_op__is_32bit$next , \alu_div0_logical_op__output_carry$next , \alu_div0_logical_op__write_cr0$next , \alu_div0_logical_op__invert_out$next , \alu_div0_logical_op__input_carry$next , \alu_div0_logical_op__zero_a$next , \alu_div0_logical_op__invert_in$next , \alu_div0_logical_op__oe__ok$next , \alu_div0_logical_op__oe__oe$next , \alu_div0_logical_op__rc__ok$next , \alu_div0_logical_op__rc__rc$next , \alu_div0_logical_op__imm_data__ok$next , \alu_div0_logical_op__imm_data__data$next , \alu_div0_logical_op__fn_unit$next , \alu_div0_logical_op__insn_type$next } = { oper_i_alu_div0__insn, oper_i_alu_div0__data_len, oper_i_alu_div0__is_signed, oper_i_alu_div0__is_32bit, oper_i_alu_div0__output_carry, oper_i_alu_div0__write_cr0, oper_i_alu_div0__invert_out, oper_i_alu_div0__input_carry, oper_i_alu_div0__zero_a, oper_i_alu_div0__invert_in, oper_i_alu_div0__oe__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__rc__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__fn_unit, oper_i_alu_div0__insn_type }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \alu_div0_logical_op__imm_data__data$next = 64'h0000000000000000; + \alu_div0_logical_op__imm_data__ok$next = 1'h0; + \alu_div0_logical_op__rc__rc$next = 1'h0; + \alu_div0_logical_op__rc__ok$next = 1'h0; + \alu_div0_logical_op__oe__oe$next = 1'h0; + \alu_div0_logical_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__o$next = data_r0__o; + \data_r0__o_ok$next = data_r0__o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = { o_ok, alu_div0_o }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__cr_a$next = data_r1__cr_a; + \data_r1__cr_a_ok$next = data_r1__cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = { cr_a_ok, alu_div0_cr_a }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r2__xer_ov$next = data_r2__xer_ov; + \data_r2__xer_ov_ok$next = data_r2__xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = { xer_ov_ok, alu_div0_xer_ov }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r2__xer_ov_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r3__xer_so$next = data_r3__xer_so; + \data_r3__xer_so_ok$next = data_r3__xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = { xer_so_ok, alu_div0_xer_so }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r3__xer_so_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_sel) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src_or_imm; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (\src_sel$82 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = \src_or_imm$85 ; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$94 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$96 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$122 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__o; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$124 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__cr_a; + endcase + end + always @* begin + if (\initial ) begin end + dest3_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$126 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest3_o = data_r2__xer_ov; + endcase + end + always @* begin + if (\initial ) begin end + dest4_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$128 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest4_o = data_r3__xer_so; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$20 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 4'h0; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$120 ; + assign cu_rd__rel_o = \$108 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_div0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_div0_p_valid_i = alui_l_q_alui; + assign \alu_div0_xer_so$1 = \$92 ; + assign alu_div0_rb = \$90 ; + assign alu_div0_ra = \$88 ; + assign \src_or_imm$85 = \$86 ; + assign \src_sel$82 = \$83 ; + assign src_or_imm = \$80 ; + assign src_sel = \$78 ; + assign cu_wrmask_o = { \$76 , \$74 , \$72 , \$70 }; + assign reset_r = \$62 ; + assign reset_w = \$60 ; + assign rst_r = \$58 ; + assign reset = \$56 ; + assign wr_any = \$36 ; + assign cu_done_o = \$30 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$18 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_div0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$14 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$10 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" *) +(* generator = "nMigen" *) +module div_state_init(o_q_bits_known, o_dividend_quotient, dividend); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" *) + input [127:0] dividend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) + output [127:0] o_dividend_quotient; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) + output [6:0] o_q_bits_known; + assign o_dividend_quotient = dividend; + assign o_q_bits_known = 7'h00; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" *) +(* generator = "nMigen" *) +module div_state_next(o_q_bits_known, i_q_bits_known, i_dividend_quotient, divisor, o_dividend_quotient); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *) + wire [128:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" *) + wire [7:0] \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" *) + wire [7:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *) + wire [126:0] \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *) + wire [128:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" *) + wire [127:0] difference; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" *) + input [63:0] divisor; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) + input [127:0] i_dividend_quotient; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) + input [6:0] i_q_bits_known; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" *) + wire next_quotient_bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) + output [127:0] o_dividend_quotient; + reg [127:0] o_dividend_quotient; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) + output [6:0] o_q_bits_known; + reg [6:0] o_q_bits_known; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" *) + reg [127:0] value; + assign \$11 = i_q_bits_known + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" *) 1'h1; + assign \$13 = i_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 7'h40; + assign \$2 = divisor <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *) 6'h3f; + assign \$4 = i_dividend_quotient - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *) \$2 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" *) difference[127]; + assign \$8 = i_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 7'h40; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" *) + casez (next_quotient_bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" */ + 1'h1: + value = difference; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:74" */ + default: + value = i_dividend_quotient; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" *) + casez (\$8 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" */ + 1'h1: + o_q_bits_known = i_q_bits_known; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:79" */ + default: + o_q_bits_known = \$10 [6:0]; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" */ + 1'h1: + o_dividend_quotient = i_dividend_quotient; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:79" */ + default: + o_dividend_quotient = { value[126:0], next_quotient_bit }; + endcase + end + assign \$1 = \$4 ; + assign \$10 = \$11 ; + assign next_quotient_bit = \$6 ; + assign difference = \$4 [127:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" *) +(* generator = "nMigen" *) +module dummy(trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , \ra$11 , \rb$12 , \fast1$13 , \fast2$14 , muxid); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \fast1$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \fast2$14 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \ra$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rb$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] trap_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \trap_op__cia$6 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] trap_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \trap_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] trap_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \trap_op__insn$4 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] trap_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \trap_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input trap_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \trap_op__is_32bit$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [7:0] \trap_op__ldst_exc$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] trap_op__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \trap_op__msr$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [12:0] trap_op__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [12:0] \trap_op__trapaddr$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] trap_op__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [7:0] \trap_op__traptype$8 ; + assign \fast2$14 = fast2; + assign \fast1$13 = fast1; + assign \rb$12 = rb; + assign \ra$11 = ra; + assign { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; + assign \muxid$1 = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fast" *) +(* generator = "nMigen" *) +module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] dest1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] dest1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] issue__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] \issue__addr$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] issue__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] issue__data_o; + reg [63:0] issue__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input issue__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input issue__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [2:0] memory_r_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [2:0] \memory_r_addr$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [63:0] memory_r_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [63:0] \memory_r_data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire [2:0] memory_w_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire [2:0] \memory_w_addr$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire [63:0] memory_w_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire [63:0] \memory_w_data$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire memory_w_en; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire \memory_w_en$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg ren_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg \ren_delay$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg \ren_delay$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg \ren_delay$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] src1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] src1__data_o; + reg [63:0] src1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src1__ren; + reg [63:0] memory [7:0]; + initial begin + memory[0] = 64'h0000000000000000; + memory[1] = 64'h0000000000000000; + memory[2] = 64'h0000000000000000; + memory[3] = 64'h0000000000000000; + memory[4] = 64'h0000000000000000; + memory[5] = 64'h0000000000000000; + memory[6] = 64'h0000000000000000; + memory[7] = 64'h0000000000000000; + end + reg [2:0] _0_; + reg [2:0] _1_; + always @(posedge coresync_clk) begin + _0_ <= memory_r_addr; + _1_ <= \memory_r_addr$3 ; + if (memory_w_en) memory[memory_w_addr] <= memory_w_data; + if (\memory_w_en$5 ) memory[\memory_w_addr$6 ] <= \memory_w_data$7 ; + end + assign memory_r_data = memory[_0_]; + assign \memory_r_data$4 = memory[_1_]; + always @(posedge coresync_clk) + \ren_delay$8 <= \ren_delay$8$next ; + always @(posedge coresync_clk) + ren_delay <= \ren_delay$next ; + always @* begin + if (\initial ) begin end + \ren_delay$next = src1__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + src1__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + casez (ren_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + 1'h1: + src1__data_o = memory_r_data; + endcase + end + always @* begin + if (\initial ) begin end + \ren_delay$8$next = issue__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$8$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + issue__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + casez (\ren_delay$8 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + 1'h1: + issue__data_o = \memory_r_data$4 ; + endcase + end + assign \memory_w_data$7 = issue__data_i; + assign \memory_w_en$5 = issue__wen; + assign \memory_w_addr$6 = \issue__addr$1 ; + assign memory_w_data = dest1__data_i; + assign memory_w_en = dest1__wen; + assign memory_w_addr = dest1__addr; + assign \memory_r_addr$3 = issue__addr; + assign memory_r_addr = src1__addr; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.jtag.fsm" *) +(* generator = "nMigen" *) +module fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, negjtag_clk, TAP_bus__tck, TAP_bus__tms, isdr); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tck; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tms; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) + output capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) + reg [3:0] fsm_state = 4'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) + reg [3:0] \fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) + output isdr; + reg isdr = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) + reg \isdr$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) + output isir; + reg isir = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) + reg \isir$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:50" *) + wire local_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *) + output negjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *) + output negjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + output posjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + output posjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:37" *) + wire rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) + output shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) + output update; + assign \$9 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) 1'h0; + assign \$11 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) 1'h0; + assign \$13 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" *) 1'h0; + assign \$15 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" *) 1'h1; + assign \$17 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) 1'h0; + assign \$1 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) 1'h0; + assign \$19 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) 1'h0; + assign \$21 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" *) 1'h0; + assign \$23 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" *) 1'h1; + assign \$25 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" *) 1'h0; + assign \$27 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" *) 1'h1; + assign \$29 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" *) 1'h0; + assign \$31 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" *) 1'h0; + assign \$3 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) 2'h3; + assign \$5 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) 3'h5; + assign \$7 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" *) 4'h8; + always @(posedge local_clk) + fsm_state <= \fsm_state$next ; + always @(posedge local_clk) + isdr <= \isdr$next ; + always @(posedge local_clk) + isir <= \isir$next ; + always @* begin + if (\initial ) begin end + \isdr$next = isdr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) + casez (fsm_state) + /* \nmigen.decoding = "TestLogicReset/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:54" */ + 4'h0: + \isdr$next = 1'h0; + /* \nmigen.decoding = "RunTestIdle/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:62" */ + 4'h1: + \isdr$next = 1'h0; + /* \nmigen.decoding = "SelectDRScan/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ + 4'h2: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) + casez (\$11 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" */ + 1'h1: + \isdr$next = 1'h1; + endcase + /* \nmigen.decoding = "SelectIRScan/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CaptureState/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "ShiftState/5" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "Exit1/6" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "Pause/7" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "Exit2/9" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "UpdateState/8" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:103" */ + 4'h8: + \isdr$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fsm_state$next = fsm_state; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) + casez (fsm_state) + /* \nmigen.decoding = "TestLogicReset/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:54" */ + 4'h0: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" */ + 1'h1: + \fsm_state$next = 4'h1; + endcase + /* \nmigen.decoding = "RunTestIdle/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:62" */ + 4'h1: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" */ + 1'h1: + \fsm_state$next = 4'h2; + endcase + /* \nmigen.decoding = "SelectDRScan/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ + 4'h2: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" *) + casez (\$17 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" */ + 1'h1: + \fsm_state$next = 4'h3; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:74" */ + default: + \fsm_state$next = 4'h4; + endcase + /* \nmigen.decoding = "SelectIRScan/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ + 4'h4: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" */ + 1'h1: + \fsm_state$next = 4'h3; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:80" */ + default: + \fsm_state$next = 4'h0; + endcase + /* \nmigen.decoding = "CaptureState/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ + 4'h3: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" *) + casez (\$21 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" */ + 1'h1: + \fsm_state$next = 4'h5; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:85" */ + default: + \fsm_state$next = 4'h6; + endcase + /* \nmigen.decoding = "ShiftState/5" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ + 4'h5: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" *) + casez (\$23 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" */ + 1'h1: + \fsm_state$next = 4'h6; + endcase + /* \nmigen.decoding = "Exit1/6" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ + 4'h6: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" */ + 1'h1: + \fsm_state$next = 4'h7; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:93" */ + default: + \fsm_state$next = 4'h8; + endcase + /* \nmigen.decoding = "Pause/7" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ + 4'h7: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" */ + 1'h1: + \fsm_state$next = 4'h9; + endcase + /* \nmigen.decoding = "Exit2/9" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ + 4'h9: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" */ + 1'h1: + \fsm_state$next = 4'h5; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:101" */ + default: + \fsm_state$next = 4'h8; + endcase + /* \nmigen.decoding = "UpdateState/8" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:103" */ + 4'h8: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" */ + 1'h1: + \fsm_state$next = 4'h1; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:110" */ + default: + \fsm_state$next = 4'h2; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \isir$next = isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" *) + casez (fsm_state) + /* \nmigen.decoding = "TestLogicReset/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:54" */ + 4'h0: + \isir$next = 1'h0; + /* \nmigen.decoding = "RunTestIdle/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:62" */ + 4'h1: + \isir$next = 1'h0; + /* \nmigen.decoding = "SelectDRScan/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "SelectIRScan/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ + 4'h4: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" */ + 1'h1: + \isir$next = 1'h1; + endcase + /* \nmigen.decoding = "CaptureState/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "ShiftState/5" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "Exit1/6" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "Pause/7" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "Exit2/9" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "UpdateState/8" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:103" */ + 4'h8: + \isir$next = 1'h0; + endcase + end + assign update = \$7 ; + assign shift = \$5 ; + assign capture = \$3 ; + assign rst = \$1 ; + assign local_clk = TAP_bus__tck; + assign negjtag_rst = rst; + assign negjtag_clk = TAP_bus__tck; + assign posjtag_rst = rst; + assign posjtag_clk = TAP_bus__tck; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus" *) +(* generator = "nMigen" *) +module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src2_i$79 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$80 , \cu_wr__rel_o$81 , \cu_wr__go_i$82 , \o_ok$83 , \cu_wr__rel_o$84 , \cu_wr__go_i$85 , \o_ok$86 , \cu_wr__rel_o$87 , \cu_wr__go_i$88 , \o_ok$89 , \cu_wr__rel_o$90 , \cu_wr__go_i$91 , \o_ok$92 , \cu_wr__rel_o$93 , \cu_wr__go_i$94 , \o_ok$95 , \cu_wr__rel_o$96 , \cu_wr__go_i$97 , \o_ok$98 , \cu_wr__rel_o$99 , \cu_wr__go_i$100 , \cu_wr__rel_o$101 , \cu_wr__go_i$102 , dest1_o, \dest1_o$103 , \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$110 , \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \dest2_o$115 , dest3_o, \dest2_o$116 , \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , xer_ca_ok, \xer_ca_ok$120 , \xer_ca_ok$121 , \dest3_o$122 , dest6_o, \dest3_o$123 , xer_ov_ok, \xer_ov_ok$124 , \xer_ov_ok$125 , \xer_ov_ok$126 , dest4_o, dest5_o, \dest3_o$127 , \dest3_o$128 , xer_so_ok, \xer_so_ok$129 , \xer_so_ok$130 , \xer_so_ok$131 , \dest5_o$132 , \dest4_o$133 , \dest4_o$134 , \dest4_o$135 , fast1_ok, \cu_wr__rel_o$136 , \cu_wr__go_i$137 , \fast1_ok$138 , \fast1_ok$139 , fast2_ok, \fast2_ok$140 , \dest1_o$141 , \dest2_o$142 , \dest3_o$143 , \dest2_o$144 , \dest3_o$145 , nia_ok, \nia_ok$146 , \dest3_o$147 , \dest4_o$148 , msr_ok, \dest5_o$149 , spr1_ok, \dest2_o$150 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$151 , \ldst_port0_exc_$signal$152 , \ldst_port0_exc_$signal$153 , \ldst_port0_exc_$signal$154 , \ldst_port0_exc_$signal$155 , \ldst_port0_exc_$signal$156 , \ldst_port0_exc_$signal$157 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_a_ok$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_a_ok$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_a_ok$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_a_ok$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_a_ok$114 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input cu_ad__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output cu_ad__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output \cu_busy_o$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input \cu_issue_i$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [3:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [5:0] \cu_rd__go_i$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [3:0] \cu_rd__go_i$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] \cu_rd__go_i$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] \cu_rd__go_i$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] \cu_rd__go_i$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [4:0] \cu_rd__go_i$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] \cu_rd__go_i$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [5:0] \cu_rd__go_i$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] \cu_rd__go_i$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [3:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [5:0] \cu_rd__rel_o$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [3:0] \cu_rd__rel_o$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] \cu_rd__rel_o$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] \cu_rd__rel_o$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] \cu_rd__rel_o$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [4:0] \cu_rd__rel_o$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] \cu_rd__rel_o$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [5:0] \cu_rd__rel_o$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] \cu_rd__rel_o$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [3:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] \cu_rdmaskn_i$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [5:0] \cu_rdmaskn_i$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] \cu_rdmaskn_i$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] \cu_rdmaskn_i$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [4:0] \cu_rdmaskn_i$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] \cu_rdmaskn_i$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [5:0] \cu_rdmaskn_i$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] \cu_rdmaskn_i$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [3:0] \cu_rdmaskn_i$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input cu_st__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output cu_st__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [4:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] \cu_wr__go_i$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [1:0] \cu_wr__go_i$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] \cu_wr__go_i$137 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] \cu_wr__go_i$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [4:0] \cu_wr__go_i$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [1:0] \cu_wr__go_i$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [5:0] \cu_wr__go_i$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [3:0] \cu_wr__go_i$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [3:0] \cu_wr__go_i$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [4:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [1:0] \cu_wr__rel_o$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] \cu_wr__rel_o$136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] \cu_wr__rel_o$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [4:0] \cu_wr__rel_o$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [1:0] \cu_wr__rel_o$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [5:0] \cu_wr__rel_o$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [3:0] \cu_wr__rel_o$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [3:0] \cu_wr__rel_o$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] \cu_wr__rel_o$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest1_o$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest1_o$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest1_o$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest1_o$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest1_o$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest1_o$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest1_o$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest1_o$141 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [31:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] \dest2_o$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] \dest2_o$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] \dest2_o$117 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] \dest2_o$118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] \dest2_o$119 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest2_o$142 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest2_o$144 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest2_o$150 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] \dest3_o$122 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] \dest3_o$123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] \dest3_o$127 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] \dest3_o$128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest3_o$143 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest3_o$145 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest3_o$147 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest4_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output \dest4_o$133 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output \dest4_o$134 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output \dest4_o$135 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest4_o$148 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest5_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output \dest5_o$132 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest5_o$149 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest6_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] ea; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \fast1_ok$138 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \fast1_ok$139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \fast2_ok$140 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output full_cr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [95:0] ldst_port0_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output ldst_port0_addr_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + input ldst_port0_addr_ok_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + input ldst_port0_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + output [3:0] ldst_port0_data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$151 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$152 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$153 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$154 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$155 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$156 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$157 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + output ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + output ldst_port0_is_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] ldst_port0_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input ldst_port0_ld_data_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] ldst_port0_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output ldst_port0_st_data_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output msr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \nia_ok$146 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] oper_i_alu_alu0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_alu0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_alu0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_alu_alu0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_alu0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_alu0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_alu0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_branch0__cia; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_branch0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_branch0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_branch0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_branch0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_branch0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_branch0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_branch0__lk; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_cr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_cr0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_cr0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] oper_i_alu_div0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_div0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_div0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_alu_div0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_div0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_div0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_div0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] oper_i_alu_logical0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_logical0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_logical0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_alu_logical0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_logical0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_logical0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__zero_a; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_mul0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_mul0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_mul0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_mul0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__write_cr0; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_shift_rot0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_shift_rot0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_alu_shift_rot0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_shift_rot0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_shift_rot0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__write_cr0; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_spr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_spr0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_spr0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_spr0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_trap0__cia; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_trap0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_trap0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_trap0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_trap0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] oper_i_alu_trap0__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_trap0__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [12:0] oper_i_alu_trap0__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] oper_i_alu_trap0__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__byte_reverse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] oper_i_ldst_ldst0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_ldst_ldst0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_ldst_ldst0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_ldst_ldst0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_ldst_ldst0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__is_signed; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_ldst_ldst0__ldst_mode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__sign_extend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src1_i$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src2_i$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src3_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src3_i$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input \src3_i$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input \src3_i$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input \src3_i$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input \src3_i$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [31:0] \src3_i$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [3:0] \src3_i$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src3_i$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src3_i$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input src4_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input \src4_i$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [1:0] \src4_i$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [3:0] \src4_i$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src4_i$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [1:0] src5_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [1:0] \src5_i$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [3:0] \src5_i$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [1:0] src6_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [3:0] \src6_i$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_ca_ok$120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_ca_ok$121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_ov_ok$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_ov_ok$125 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_ov_ok$126 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so_ok$129 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so_ok$130 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so_ok$131 ; + alu0 alu0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a_ok(cr_a_ok), + .cu_busy_o(cu_busy_o), + .cu_issue_i(cu_issue_i), + .cu_rd__go_i(cu_rd__go_i), + .cu_rd__rel_o(cu_rd__rel_o), + .cu_rdmaskn_i(cu_rdmaskn_i), + .cu_wr__go_i(cu_wr__go_i), + .cu_wr__rel_o(cu_wr__rel_o), + .dest1_o(dest1_o), + .dest2_o(\dest2_o$115 ), + .dest3_o(\dest3_o$122 ), + .dest4_o(dest4_o), + .dest5_o(\dest5_o$132 ), + .o_ok(o_ok), + .oper_i_alu_alu0__data_len(oper_i_alu_alu0__data_len), + .oper_i_alu_alu0__fn_unit(oper_i_alu_alu0__fn_unit), + .oper_i_alu_alu0__imm_data__data(oper_i_alu_alu0__imm_data__data), + .oper_i_alu_alu0__imm_data__ok(oper_i_alu_alu0__imm_data__ok), + .oper_i_alu_alu0__input_carry(oper_i_alu_alu0__input_carry), + .oper_i_alu_alu0__insn(oper_i_alu_alu0__insn), + .oper_i_alu_alu0__insn_type(oper_i_alu_alu0__insn_type), + .oper_i_alu_alu0__invert_in(oper_i_alu_alu0__invert_in), + .oper_i_alu_alu0__invert_out(oper_i_alu_alu0__invert_out), + .oper_i_alu_alu0__is_32bit(oper_i_alu_alu0__is_32bit), + .oper_i_alu_alu0__is_signed(oper_i_alu_alu0__is_signed), + .oper_i_alu_alu0__oe__oe(oper_i_alu_alu0__oe__oe), + .oper_i_alu_alu0__oe__ok(oper_i_alu_alu0__oe__ok), + .oper_i_alu_alu0__output_carry(oper_i_alu_alu0__output_carry), + .oper_i_alu_alu0__rc__ok(oper_i_alu_alu0__rc__ok), + .oper_i_alu_alu0__rc__rc(oper_i_alu_alu0__rc__rc), + .oper_i_alu_alu0__write_cr0(oper_i_alu_alu0__write_cr0), + .oper_i_alu_alu0__zero_a(oper_i_alu_alu0__zero_a), + .src1_i(src1_i), + .src2_i(src2_i), + .src3_i(\src3_i$60 ), + .src4_i(\src4_i$65 ), + .xer_ca_ok(xer_ca_ok), + .xer_ov_ok(xer_ov_ok), + .xer_so_ok(xer_so_ok) + ); + branch0 branch0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cu_busy_o(\cu_busy_o$5 ), + .cu_issue_i(\cu_issue_i$4 ), + .cu_rd__go_i(\cu_rd__go_i$70 ), + .cu_rd__rel_o(\cu_rd__rel_o$69 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$6 ), + .cu_wr__go_i(\cu_wr__go_i$137 ), + .cu_wr__rel_o(\cu_wr__rel_o$136 ), + .dest1_o(\dest1_o$141 ), + .dest2_o(\dest2_o$144 ), + .dest3_o(\dest3_o$147 ), + .fast1_ok(fast1_ok), + .fast2_ok(fast2_ok), + .nia_ok(nia_ok), + .oper_i_alu_branch0__cia(oper_i_alu_branch0__cia), + .oper_i_alu_branch0__fn_unit(oper_i_alu_branch0__fn_unit), + .oper_i_alu_branch0__imm_data__data(oper_i_alu_branch0__imm_data__data), + .oper_i_alu_branch0__imm_data__ok(oper_i_alu_branch0__imm_data__ok), + .oper_i_alu_branch0__insn(oper_i_alu_branch0__insn), + .oper_i_alu_branch0__insn_type(oper_i_alu_branch0__insn_type), + .oper_i_alu_branch0__is_32bit(oper_i_alu_branch0__is_32bit), + .oper_i_alu_branch0__lk(oper_i_alu_branch0__lk), + .src1_i(\src1_i$74 ), + .src2_i(\src2_i$77 ), + .src3_i(\src3_i$71 ) + ); + cr0 cr0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a_ok(\cr_a_ok$110 ), + .cu_busy_o(\cu_busy_o$2 ), + .cu_issue_i(\cu_issue_i$1 ), + .cu_rd__go_i(\cu_rd__go_i$29 ), + .cu_rd__rel_o(\cu_rd__rel_o$28 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$3 ), + .cu_wr__go_i(\cu_wr__go_i$82 ), + .cu_wr__rel_o(\cu_wr__rel_o$81 ), + .dest1_o(\dest1_o$103 ), + .dest2_o(dest2_o), + .dest3_o(dest3_o), + .full_cr_ok(full_cr_ok), + .o_ok(\o_ok$80 ), + .oper_i_alu_cr0__fn_unit(oper_i_alu_cr0__fn_unit), + .oper_i_alu_cr0__insn(oper_i_alu_cr0__insn), + .oper_i_alu_cr0__insn_type(oper_i_alu_cr0__insn_type), + .src1_i(\src1_i$50 ), + .src2_i(\src2_i$30 ), + .src3_i(\src3_i$67 ), + .src4_i(\src4_i$68 ), + .src5_i(\src5_i$72 ), + .src6_i(\src6_i$73 ) + ); + div0 div0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a_ok(\cr_a_ok$112 ), + .cu_busy_o(\cu_busy_o$17 ), + .cu_issue_i(\cu_issue_i$16 ), + .cu_rd__go_i(\cu_rd__go_i$38 ), + .cu_rd__rel_o(\cu_rd__rel_o$37 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$18 ), + .cu_wr__go_i(\cu_wr__go_i$94 ), + .cu_wr__rel_o(\cu_wr__rel_o$93 ), + .dest1_o(\dest1_o$107 ), + .dest2_o(\dest2_o$117 ), + .dest3_o(\dest3_o$127 ), + .dest4_o(\dest4_o$134 ), + .o_ok(\o_ok$92 ), + .oper_i_alu_div0__data_len(oper_i_alu_div0__data_len), + .oper_i_alu_div0__fn_unit(oper_i_alu_div0__fn_unit), + .oper_i_alu_div0__imm_data__data(oper_i_alu_div0__imm_data__data), + .oper_i_alu_div0__imm_data__ok(oper_i_alu_div0__imm_data__ok), + .oper_i_alu_div0__input_carry(oper_i_alu_div0__input_carry), + .oper_i_alu_div0__insn(oper_i_alu_div0__insn), + .oper_i_alu_div0__insn_type(oper_i_alu_div0__insn_type), + .oper_i_alu_div0__invert_in(oper_i_alu_div0__invert_in), + .oper_i_alu_div0__invert_out(oper_i_alu_div0__invert_out), + .oper_i_alu_div0__is_32bit(oper_i_alu_div0__is_32bit), + .oper_i_alu_div0__is_signed(oper_i_alu_div0__is_signed), + .oper_i_alu_div0__oe__oe(oper_i_alu_div0__oe__oe), + .oper_i_alu_div0__oe__ok(oper_i_alu_div0__oe__ok), + .oper_i_alu_div0__output_carry(oper_i_alu_div0__output_carry), + .oper_i_alu_div0__rc__ok(oper_i_alu_div0__rc__ok), + .oper_i_alu_div0__rc__rc(oper_i_alu_div0__rc__rc), + .oper_i_alu_div0__write_cr0(oper_i_alu_div0__write_cr0), + .oper_i_alu_div0__zero_a(oper_i_alu_div0__zero_a), + .src1_i(\src1_i$56 ), + .src2_i(\src2_i$39 ), + .src3_i(\src3_i$62 ), + .xer_ov_ok(\xer_ov_ok$125 ), + .xer_so_ok(\xer_so_ok$130 ) + ); + ldst0 ldst0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cu_ad__go_i(cu_ad__go_i), + .cu_ad__rel_o(cu_ad__rel_o), + .cu_busy_o(\cu_busy_o$26 ), + .cu_issue_i(\cu_issue_i$25 ), + .cu_rd__go_i(\cu_rd__go_i$47 ), + .cu_rd__rel_o(\cu_rd__rel_o$46 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$27 ), + .cu_st__go_i(cu_st__go_i), + .cu_st__rel_o(cu_st__rel_o), + .cu_wr__go_i(\cu_wr__go_i$102 ), + .cu_wr__rel_o(\cu_wr__rel_o$101 ), + .ea(ea), + .ldst_port0_addr_i(ldst_port0_addr_i), + .ldst_port0_addr_i_ok(ldst_port0_addr_i_ok), + .ldst_port0_addr_ok_o(ldst_port0_addr_ok_o), + .ldst_port0_busy_o(ldst_port0_busy_o), + .ldst_port0_data_len(ldst_port0_data_len), + .\ldst_port0_exc_$signal (\ldst_port0_exc_$signal ), + .\ldst_port0_exc_$signal$1 (\ldst_port0_exc_$signal$151 ), + .\ldst_port0_exc_$signal$2 (\ldst_port0_exc_$signal$152 ), + .\ldst_port0_exc_$signal$3 (\ldst_port0_exc_$signal$153 ), + .\ldst_port0_exc_$signal$4 (\ldst_port0_exc_$signal$154 ), + .\ldst_port0_exc_$signal$5 (\ldst_port0_exc_$signal$155 ), + .\ldst_port0_exc_$signal$6 (\ldst_port0_exc_$signal$156 ), + .\ldst_port0_exc_$signal$7 (\ldst_port0_exc_$signal$157 ), + .ldst_port0_is_ld_i(ldst_port0_is_ld_i), + .ldst_port0_is_st_i(ldst_port0_is_st_i), + .ldst_port0_ld_data_o(ldst_port0_ld_data_o), + .ldst_port0_ld_data_o_ok(ldst_port0_ld_data_o_ok), + .ldst_port0_st_data_i(ldst_port0_st_data_i), + .ldst_port0_st_data_i_ok(ldst_port0_st_data_i_ok), + .o(o), + .oper_i_ldst_ldst0__byte_reverse(oper_i_ldst_ldst0__byte_reverse), + .oper_i_ldst_ldst0__data_len(oper_i_ldst_ldst0__data_len), + .oper_i_ldst_ldst0__fn_unit(oper_i_ldst_ldst0__fn_unit), + .oper_i_ldst_ldst0__imm_data__data(oper_i_ldst_ldst0__imm_data__data), + .oper_i_ldst_ldst0__imm_data__ok(oper_i_ldst_ldst0__imm_data__ok), + .oper_i_ldst_ldst0__insn(oper_i_ldst_ldst0__insn), + .oper_i_ldst_ldst0__insn_type(oper_i_ldst_ldst0__insn_type), + .oper_i_ldst_ldst0__is_32bit(oper_i_ldst_ldst0__is_32bit), + .oper_i_ldst_ldst0__is_signed(oper_i_ldst_ldst0__is_signed), + .oper_i_ldst_ldst0__ldst_mode(oper_i_ldst_ldst0__ldst_mode), + .oper_i_ldst_ldst0__oe__oe(oper_i_ldst_ldst0__oe__oe), + .oper_i_ldst_ldst0__oe__ok(oper_i_ldst_ldst0__oe__ok), + .oper_i_ldst_ldst0__rc__ok(oper_i_ldst_ldst0__rc__ok), + .oper_i_ldst_ldst0__rc__rc(oper_i_ldst_ldst0__rc__rc), + .oper_i_ldst_ldst0__sign_extend(oper_i_ldst_ldst0__sign_extend), + .oper_i_ldst_ldst0__zero_a(oper_i_ldst_ldst0__zero_a), + .src1_i(\src1_i$59 ), + .src2_i(\src2_i$48 ), + .src3_i(\src3_i$49 ) + ); + logical0 logical0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a_ok(\cr_a_ok$111 ), + .cu_busy_o(\cu_busy_o$11 ), + .cu_issue_i(\cu_issue_i$10 ), + .cu_rd__go_i(\cu_rd__go_i$35 ), + .cu_rd__rel_o(\cu_rd__rel_o$34 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$12 ), + .cu_wr__go_i(\cu_wr__go_i$88 ), + .cu_wr__rel_o(\cu_wr__rel_o$87 ), + .dest1_o(\dest1_o$105 ), + .dest2_o(\dest2_o$116 ), + .o_ok(\o_ok$86 ), + .oper_i_alu_logical0__data_len(oper_i_alu_logical0__data_len), + .oper_i_alu_logical0__fn_unit(oper_i_alu_logical0__fn_unit), + .oper_i_alu_logical0__imm_data__data(oper_i_alu_logical0__imm_data__data), + .oper_i_alu_logical0__imm_data__ok(oper_i_alu_logical0__imm_data__ok), + .oper_i_alu_logical0__input_carry(oper_i_alu_logical0__input_carry), + .oper_i_alu_logical0__insn(oper_i_alu_logical0__insn), + .oper_i_alu_logical0__insn_type(oper_i_alu_logical0__insn_type), + .oper_i_alu_logical0__invert_in(oper_i_alu_logical0__invert_in), + .oper_i_alu_logical0__invert_out(oper_i_alu_logical0__invert_out), + .oper_i_alu_logical0__is_32bit(oper_i_alu_logical0__is_32bit), + .oper_i_alu_logical0__is_signed(oper_i_alu_logical0__is_signed), + .oper_i_alu_logical0__oe__oe(oper_i_alu_logical0__oe__oe), + .oper_i_alu_logical0__oe__ok(oper_i_alu_logical0__oe__ok), + .oper_i_alu_logical0__output_carry(oper_i_alu_logical0__output_carry), + .oper_i_alu_logical0__rc__ok(oper_i_alu_logical0__rc__ok), + .oper_i_alu_logical0__rc__rc(oper_i_alu_logical0__rc__rc), + .oper_i_alu_logical0__write_cr0(oper_i_alu_logical0__write_cr0), + .oper_i_alu_logical0__zero_a(oper_i_alu_logical0__zero_a), + .src1_i(\src1_i$52 ), + .src2_i(\src2_i$36 ), + .src3_i(\src3_i$61 ) + ); + mul0 mul0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a_ok(\cr_a_ok$113 ), + .cu_busy_o(\cu_busy_o$20 ), + .cu_issue_i(\cu_issue_i$19 ), + .cu_rd__go_i(\cu_rd__go_i$41 ), + .cu_rd__rel_o(\cu_rd__rel_o$40 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$21 ), + .cu_wr__go_i(\cu_wr__go_i$97 ), + .cu_wr__rel_o(\cu_wr__rel_o$96 ), + .dest1_o(\dest1_o$108 ), + .dest2_o(\dest2_o$118 ), + .dest3_o(\dest3_o$128 ), + .dest4_o(\dest4_o$135 ), + .o_ok(\o_ok$95 ), + .oper_i_alu_mul0__fn_unit(oper_i_alu_mul0__fn_unit), + .oper_i_alu_mul0__imm_data__data(oper_i_alu_mul0__imm_data__data), + .oper_i_alu_mul0__imm_data__ok(oper_i_alu_mul0__imm_data__ok), + .oper_i_alu_mul0__insn(oper_i_alu_mul0__insn), + .oper_i_alu_mul0__insn_type(oper_i_alu_mul0__insn_type), + .oper_i_alu_mul0__is_32bit(oper_i_alu_mul0__is_32bit), + .oper_i_alu_mul0__is_signed(oper_i_alu_mul0__is_signed), + .oper_i_alu_mul0__oe__oe(oper_i_alu_mul0__oe__oe), + .oper_i_alu_mul0__oe__ok(oper_i_alu_mul0__oe__ok), + .oper_i_alu_mul0__rc__ok(oper_i_alu_mul0__rc__ok), + .oper_i_alu_mul0__rc__rc(oper_i_alu_mul0__rc__rc), + .oper_i_alu_mul0__write_cr0(oper_i_alu_mul0__write_cr0), + .src1_i(\src1_i$57 ), + .src2_i(\src2_i$42 ), + .src3_i(\src3_i$63 ), + .xer_ov_ok(\xer_ov_ok$126 ), + .xer_so_ok(\xer_so_ok$131 ) + ); + shiftrot0 shiftrot0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a_ok(\cr_a_ok$114 ), + .cu_busy_o(\cu_busy_o$23 ), + .cu_issue_i(\cu_issue_i$22 ), + .cu_rd__go_i(\cu_rd__go_i$44 ), + .cu_rd__rel_o(\cu_rd__rel_o$43 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$24 ), + .cu_wr__go_i(\cu_wr__go_i$100 ), + .cu_wr__rel_o(\cu_wr__rel_o$99 ), + .dest1_o(\dest1_o$109 ), + .dest2_o(\dest2_o$119 ), + .dest3_o(\dest3_o$123 ), + .o_ok(\o_ok$98 ), + .oper_i_alu_shift_rot0__fn_unit(oper_i_alu_shift_rot0__fn_unit), + .oper_i_alu_shift_rot0__imm_data__data(oper_i_alu_shift_rot0__imm_data__data), + .oper_i_alu_shift_rot0__imm_data__ok(oper_i_alu_shift_rot0__imm_data__ok), + .oper_i_alu_shift_rot0__input_carry(oper_i_alu_shift_rot0__input_carry), + .oper_i_alu_shift_rot0__input_cr(oper_i_alu_shift_rot0__input_cr), + .oper_i_alu_shift_rot0__insn(oper_i_alu_shift_rot0__insn), + .oper_i_alu_shift_rot0__insn_type(oper_i_alu_shift_rot0__insn_type), + .oper_i_alu_shift_rot0__invert_in(oper_i_alu_shift_rot0__invert_in), + .oper_i_alu_shift_rot0__is_32bit(oper_i_alu_shift_rot0__is_32bit), + .oper_i_alu_shift_rot0__is_signed(oper_i_alu_shift_rot0__is_signed), + .oper_i_alu_shift_rot0__oe__oe(oper_i_alu_shift_rot0__oe__oe), + .oper_i_alu_shift_rot0__oe__ok(oper_i_alu_shift_rot0__oe__ok), + .oper_i_alu_shift_rot0__output_carry(oper_i_alu_shift_rot0__output_carry), + .oper_i_alu_shift_rot0__output_cr(oper_i_alu_shift_rot0__output_cr), + .oper_i_alu_shift_rot0__rc__ok(oper_i_alu_shift_rot0__rc__ok), + .oper_i_alu_shift_rot0__rc__rc(oper_i_alu_shift_rot0__rc__rc), + .oper_i_alu_shift_rot0__write_cr0(oper_i_alu_shift_rot0__write_cr0), + .src1_i(\src1_i$58 ), + .src2_i(\src2_i$45 ), + .src3_i(src3_i), + .src4_i(\src4_i$64 ), + .src5_i(src5_i), + .xer_ca_ok(\xer_ca_ok$121 ) + ); + spr0 spr0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cu_busy_o(\cu_busy_o$14 ), + .cu_issue_i(\cu_issue_i$13 ), + .cu_rd__go_i(\cu_rd__go_i$54 ), + .cu_rd__rel_o(\cu_rd__rel_o$53 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$15 ), + .cu_wr__go_i(\cu_wr__go_i$91 ), + .cu_wr__rel_o(\cu_wr__rel_o$90 ), + .dest1_o(\dest1_o$106 ), + .dest2_o(\dest2_o$150 ), + .dest3_o(\dest3_o$143 ), + .dest4_o(\dest4_o$133 ), + .dest5_o(dest5_o), + .dest6_o(dest6_o), + .fast1_ok(\fast1_ok$139 ), + .o_ok(\o_ok$89 ), + .oper_i_alu_spr0__fn_unit(oper_i_alu_spr0__fn_unit), + .oper_i_alu_spr0__insn(oper_i_alu_spr0__insn), + .oper_i_alu_spr0__insn_type(oper_i_alu_spr0__insn_type), + .oper_i_alu_spr0__is_32bit(oper_i_alu_spr0__is_32bit), + .spr1_ok(spr1_ok), + .src1_i(\src1_i$55 ), + .src2_i(\src2_i$79 ), + .src3_i(\src3_i$76 ), + .src4_i(src4_i), + .src5_i(\src5_i$66 ), + .src6_i(src6_i), + .xer_ca_ok(\xer_ca_ok$120 ), + .xer_ov_ok(\xer_ov_ok$124 ), + .xer_so_ok(\xer_so_ok$129 ) + ); + trap0 trap0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cu_busy_o(\cu_busy_o$8 ), + .cu_issue_i(\cu_issue_i$7 ), + .cu_rd__go_i(\cu_rd__go_i$32 ), + .cu_rd__rel_o(\cu_rd__rel_o$31 ), + .cu_rdmaskn_i(\cu_rdmaskn_i$9 ), + .cu_wr__go_i(\cu_wr__go_i$85 ), + .cu_wr__rel_o(\cu_wr__rel_o$84 ), + .dest1_o(\dest1_o$104 ), + .dest2_o(\dest2_o$142 ), + .dest3_o(\dest3_o$145 ), + .dest4_o(\dest4_o$148 ), + .dest5_o(\dest5_o$149 ), + .fast1_ok(\fast1_ok$138 ), + .fast2_ok(\fast2_ok$140 ), + .msr_ok(msr_ok), + .nia_ok(\nia_ok$146 ), + .o_ok(\o_ok$83 ), + .oper_i_alu_trap0__cia(oper_i_alu_trap0__cia), + .oper_i_alu_trap0__fn_unit(oper_i_alu_trap0__fn_unit), + .oper_i_alu_trap0__insn(oper_i_alu_trap0__insn), + .oper_i_alu_trap0__insn_type(oper_i_alu_trap0__insn_type), + .oper_i_alu_trap0__is_32bit(oper_i_alu_trap0__is_32bit), + .oper_i_alu_trap0__ldst_exc(oper_i_alu_trap0__ldst_exc), + .oper_i_alu_trap0__msr(oper_i_alu_trap0__msr), + .oper_i_alu_trap0__trapaddr(oper_i_alu_trap0__trapaddr), + .oper_i_alu_trap0__traptype(oper_i_alu_trap0__traptype), + .src1_i(\src1_i$51 ), + .src2_i(\src2_i$33 ), + .src3_i(\src3_i$75 ), + .src4_i(\src4_i$78 ) + ); +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.jtag.idblock" *) +(* generator = "nMigen" *) +module idblock(id_bypass, capture, shift, update, TAP_bus__tdi, TAP_id_tdo, posjtag_rst, posjtag_clk, select_id); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:389" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:390" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tdi; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *) + reg [31:0] TAP_id_sr = 32'd0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *) + reg [31:0] \TAP_id_sr$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" *) + output TAP_id_tdo; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:248" *) + wire _bypass; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:245" *) + wire _capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:246" *) + wire _shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:244" *) + wire _tdi; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:247" *) + wire _update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) + input capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:381" *) + input id_bypass; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + input posjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + input posjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" *) + input select_id; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) + input shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) + input update; + assign \$1 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:389" *) capture; + assign \$3 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:390" *) shift; + assign \$5 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" *) update; + always @(posedge posjtag_clk) + TAP_id_sr <= \TAP_id_sr$next ; + always @* begin + if (\initial ) begin end + \TAP_id_sr$next = TAP_id_sr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:259" *) + casez ({ _shift, _capture }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:259" */ + 2'b?1: + \TAP_id_sr$next = 32'd6399; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:261" */ + 2'b1?: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:262" *) + casez (_bypass) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:262" */ + 1'h1: + \TAP_id_sr$next [0] = _tdi; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:264" */ + default: + \TAP_id_sr$next = { _tdi, TAP_id_sr[31:1] }; + endcase + endcase + end + assign TAP_id_tdo = TAP_id_sr[0]; + assign _bypass = id_bypass; + assign _update = \$5 ; + assign _shift = \$3 ; + assign _capture = \$1 ; + assign _tdi = TAP_bus__tdi; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.l0.idx_l" *) +(* generator = "nMigen" *) +module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_idx_l; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_idx_l; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_idx_l; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_idx_l; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_idx_l; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_idx_l; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_idx_l; + assign \$15 = q_idx_l | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_idx_l; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_idx_l; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_idx_l; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_idx_l = \$15 ; + assign qn_idx_l = \$13 ; + assign q_idx_l = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.imem" *) +(* generator = "nMigen" *) +module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" *) + reg a_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" *) + input [47:0] a_pc_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" *) + wire a_stall_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *) + input a_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *) + reg [44:0] f_badaddr_o = 45'h000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *) + reg [44:0] \f_badaddr_o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" *) + output f_busy_o; + reg f_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" *) + reg f_fetch_err_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" *) + reg \f_fetch_err_o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" *) + output [63:0] f_instr_o; + reg [63:0] f_instr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" *) + wire f_stall_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" *) + input f_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input ibus__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output [44:0] ibus__adr; + reg [44:0] ibus__adr = 45'h000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + reg [44:0] \ibus__adr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output ibus__cyc; + reg ibus__cyc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + reg \ibus__cyc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input [63:0] ibus__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input ibus__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output [7:0] ibus__sel; + reg [7:0] ibus__sel = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + reg [7:0] \ibus__sel$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output ibus__stb; + reg ibus__stb = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + reg \ibus__stb$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *) + reg [63:0] ibus_rdata = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *) + reg [63:0] \ibus_rdata$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + input wb_icache_en; + assign \$9 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$7 ; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i; + assign \$13 = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$11 ; + assign \$15 = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err; + assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i; + assign \$19 = \$15 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$17 ; + assign \$21 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i; + assign \$23 = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$21 ; + assign \$25 = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err; + assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i; + assign \$29 = \$25 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$27 ; + assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i; + assign \$33 = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$31 ; + assign \$35 = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err; + assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i; + assign \$3 = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$1 ; + assign \$39 = \$35 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$37 ; + assign \$41 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i; + assign \$43 = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$41 ; + assign \$45 = ibus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *) ibus__err; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *) f_stall_i; + assign \$49 = ibus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *) ibus__err; + assign \$51 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *) f_stall_i; + assign \$5 = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i; + always @(posedge clk) + f_badaddr_o <= \f_badaddr_o$next ; + always @(posedge clk) + f_fetch_err_o <= \f_fetch_err_o$next ; + always @(posedge clk) + ibus__adr <= \ibus__adr$next ; + always @(posedge clk) + ibus_rdata <= \ibus_rdata$next ; + always @(posedge clk) + ibus__sel <= \ibus__sel$next ; + always @(posedge clk) + ibus__stb <= \ibus__stb$next ; + always @(posedge clk) + ibus__cyc <= \ibus__cyc$next ; + always @* begin + if (\initial ) begin end + \ibus__cyc$next = ibus__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *) + casez ({ \$3 , ibus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" */ + 1'h1: + \ibus__cyc$next = 1'h0; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" */ + 2'b1?: + \ibus__cyc$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ibus__cyc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \ibus__stb$next = ibus__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *) + casez ({ \$13 , ibus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" */ + 1'h1: + \ibus__stb$next = 1'h0; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" */ + 2'b1?: + \ibus__stb$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ibus__stb$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \ibus__sel$next = ibus__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *) + casez ({ \$23 , ibus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" */ + 1'h1: + \ibus__sel$next = 8'h00; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" */ + 2'b1?: + \ibus__sel$next = 8'hff; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ibus__sel$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \ibus_rdata$next = ibus_rdata; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *) + casez ({ \$33 , ibus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) + casez (\$39 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" */ + 1'h1: + \ibus_rdata$next = ibus__dat_r; + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ibus_rdata$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \ibus__adr$next = ibus__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *) + casez ({ \$43 , ibus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" */ + 2'b?1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" */ + 2'b1?: + \ibus__adr$next = a_pc_i[47:3]; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ibus__adr$next = 45'h000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \f_fetch_err_o$next = f_fetch_err_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *) + casez ({ \$47 , \$45 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" */ + 2'b?1: + \f_fetch_err_o$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" */ + 2'b1?: + \f_fetch_err_o$next = 1'h0; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \f_fetch_err_o$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \f_badaddr_o$next = f_badaddr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *) + casez ({ \$51 , \$49 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" */ + 2'b?1: + \f_badaddr_o$next = ibus__adr; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \f_badaddr_o$next = 45'h000000000000; + endcase + end + always @* begin + if (\initial ) begin end + a_busy_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + a_busy_o = ibus__cyc; + endcase + end + always @* begin + if (\initial ) begin end + f_busy_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" *) + casez (f_fetch_err_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" */ + 1'h1: + f_busy_o = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:98" */ + default: + f_busy_o = ibus__cyc; + endcase + endcase + end + always @* begin + if (\initial ) begin end + f_instr_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *) + casez (wb_icache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" *) + casez (f_fetch_err_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:98" */ + default: + f_instr_o = ibus_rdata; + endcase + endcase + end + assign a_stall_i = 1'h0; + assign f_stall_i = 1'h0; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" *) +(* generator = "nMigen" *) +module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , \xer_ca$23 , muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) + wire [63:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) + reg [63:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \alu_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \alu_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \alu_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \alu_op__input_carry$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \alu_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \alu_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__invert_out$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__write_cr0$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + wire [63:0] b; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \ra$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rb$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [1:0] \xer_ca$23 ; + reg [1:0] \xer_ca$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$22 ; + assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *) + casez (alu_op__invert_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ + 1'h1: + a = \$24 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */ + default: + a = ra; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$23 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" *) + casez (alu_op__input_carry) + /* \nmigen.decoding = "ZERO/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:56" */ + 2'h0: + \xer_ca$23 = 2'h0; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:58" */ + 2'h1: + \xer_ca$23 = 2'h3; + /* \nmigen.decoding = "CA/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" */ + 2'h2: + \xer_ca$23 = xer_ca; + endcase + end + assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$22 = xer_so; + assign \rb$21 = rb; + assign b = rb; + assign \ra$20 = a; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" *) +(* generator = "nMigen" *) +module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, ra, rb, rc, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \ra$19 , \rb$20 , \rc$21 , \xer_so$22 , \xer_ca$23 , muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) + wire [63:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) + reg [63:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + wire [63:0] b; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \ra$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rb$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rc$21 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \sr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \sr_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \sr_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__input_cr$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \sr_op__insn$18 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \sr_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__invert_in$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__output_carry$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__output_cr$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [1:0] \xer_ca$23 ; + reg [1:0] \xer_ca$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$22 ; + assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *) + casez (sr_op__invert_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ + 1'h1: + a = \$24 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */ + default: + a = ra; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$23 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" *) + casez (sr_op__input_carry) + /* \nmigen.decoding = "ZERO/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:56" */ + 2'h0: + \xer_ca$23 = 2'h0; + /* \nmigen.decoding = "ONE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:58" */ + 2'h1: + \xer_ca$23 = 2'h3; + /* \nmigen.decoding = "CA/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" */ + 2'h2: + \xer_ca$23 = xer_ca; + endcase + end + assign \rc$21 = rc; + assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$22 = xer_so; + assign \rb$20 = b; + assign b = rb; + assign \ra$19 = a; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" *) +(* generator = "nMigen" *) +module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" *) + wire [63:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) + wire [63:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + reg [63:0] b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \ra$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rb$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$22 ; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" *) rb; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" *) + casez (logical_op__invert_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" */ + 1'h1: + b = \$23 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:44" */ + default: + b = rb; + endcase + end + assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$22 = xer_so; + assign \rb$21 = b; + assign \ra$20 = a; + assign a = ra; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" *) +(* generator = "nMigen" *) +module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) + wire [63:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) + reg [63:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + wire [63:0] b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \ra$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rb$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$22 ; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *) + casez (logical_op__invert_in) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ + 1'h1: + a = \$23 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */ + default: + a = ra; + endcase + end + assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$22 = xer_so; + assign \rb$21 = rb; + assign b = rb; + assign \ra$20 = a; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" *) +(* generator = "nMigen" *) +module \input$95 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , muxid); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) + wire [63:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + wire [63:0] b; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \mul_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \mul_op__insn$13 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \mul_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_32bit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_signed$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \ra$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rb$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$16 ; + assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$16 = xer_so; + assign \rb$15 = rb; + assign b = rb; + assign \ra$14 = a; + assign a = ra; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.int" *) +(* generator = "nMigen" *) +module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [4:0] dest1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] dest1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [4:0] dmi__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] dmi__data_o; + reg [63:0] dmi__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dmi__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [4:0] memory_r_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [4:0] \memory_r_addr$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [63:0] memory_r_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [63:0] \memory_r_data$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire [4:0] memory_w_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire [63:0] memory_w_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire memory_w_en; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg ren_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg \ren_delay$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg \ren_delay$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg \ren_delay$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [4:0] src1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] src1__data_o; + reg [63:0] src1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src1__ren; + reg [63:0] memory [31:0]; + initial begin + memory[0] = 64'h0000000000000000; + memory[1] = 64'h0000000000000000; + memory[2] = 64'h0000000000000000; + memory[3] = 64'h0000000000000000; + memory[4] = 64'h0000000000000000; + memory[5] = 64'h0000000000000000; + memory[6] = 64'h0000000000000000; + memory[7] = 64'h0000000000000000; + memory[8] = 64'h0000000000000000; + memory[9] = 64'h0000000000000000; + memory[10] = 64'h0000000000000000; + memory[11] = 64'h0000000000000000; + memory[12] = 64'h0000000000000000; + memory[13] = 64'h0000000000000000; + memory[14] = 64'h0000000000000000; + memory[15] = 64'h0000000000000000; + memory[16] = 64'h0000000000000000; + memory[17] = 64'h0000000000000000; + memory[18] = 64'h0000000000000000; + memory[19] = 64'h0000000000000000; + memory[20] = 64'h0000000000000000; + memory[21] = 64'h0000000000000000; + memory[22] = 64'h0000000000000000; + memory[23] = 64'h0000000000000000; + memory[24] = 64'h0000000000000000; + memory[25] = 64'h0000000000000000; + memory[26] = 64'h0000000000000000; + memory[27] = 64'h0000000000000000; + memory[28] = 64'h0000000000000000; + memory[29] = 64'h0000000000000000; + memory[30] = 64'h0000000000000000; + memory[31] = 64'h0000000000000000; + end + reg [4:0] _0_; + reg [4:0] _1_; + always @(posedge coresync_clk) begin + _0_ <= memory_r_addr; + _1_ <= \memory_r_addr$2 ; + if (memory_w_en) memory[memory_w_addr] <= memory_w_data; + end + assign memory_r_data = memory[_0_]; + assign \memory_r_data$3 = memory[_1_]; + always @(posedge coresync_clk) + \ren_delay$4 <= \ren_delay$4$next ; + always @(posedge coresync_clk) + ren_delay <= \ren_delay$next ; + always @* begin + if (\initial ) begin end + \ren_delay$next = dmi__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dmi__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + casez (ren_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + 1'h1: + dmi__data_o = memory_r_data; + endcase + end + always @* begin + if (\initial ) begin end + \ren_delay$4$next = src1__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$4$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + src1__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + casez (\ren_delay$4 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + 1'h1: + src1__data_o = \memory_r_data$3 ; + endcase + end + assign memory_w_data = dest1__data_i; + assign memory_w_en = dest1__wen; + assign memory_w_addr = dest1__addr; + assign \memory_r_addr$2 = src1__addr; + assign memory_r_addr = dmi__addr; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.jtag.irblock" *) +(* generator = "nMigen" *) +module irblock(capture, shift, update, TAP_bus__tdi, isir, tdo, posjtag_rst, posjtag_clk, ir); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:372" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:372" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tdi; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) + input capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" *) + output [3:0] ir; + reg [3:0] ir = 4'h1; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" *) + reg [3:0] \ir$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) + input isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + input posjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + input posjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) + input shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:140" *) + reg [3:0] shift_ir = 4'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:140" *) + reg [3:0] \shift_ir$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:130" *) + output tdo; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) + input update; + assign \$9 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *) shift; + assign \$11 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) update; + assign \$1 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:372" *) capture; + assign \$3 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *) shift; + assign \$5 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) update; + assign \$7 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:372" *) capture; + always @(posedge posjtag_clk) + ir <= \ir$next ; + always @(posedge posjtag_clk) + shift_ir <= \shift_ir$next ; + always @* begin + if (\initial ) begin end + \shift_ir$next = shift_ir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" *) + casez ({ \$5 , \$3 , \$1 }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ + 3'b??1: + \shift_ir$next = ir; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:145" */ + 3'b?1?: + \shift_ir$next = { TAP_bus__tdi, shift_ir[3:1] }; + endcase + end + always @* begin + if (\initial ) begin end + \ir$next = ir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" *) + casez ({ \$11 , \$9 , \$7 }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ + 3'b??1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:145" */ + 3'b?1?: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:147" */ + 3'b1??: + \ir$next = shift_ir; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \ir$next = 4'h1; + endcase + end + assign tdo = ir[0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.jtag" *) +(* generator = "nMigen" *) +module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, wb_sram_en, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$117 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$119 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$125 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$127 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$129 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$131 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$133 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$135 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$137 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$139 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$141 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$143 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$145 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$147 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$149 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$151 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$153 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$155 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$157 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$159 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$161 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$163 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$165 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$167 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$169 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:406" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$171 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$173 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$175 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$177 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$179 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$181 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$183 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$185 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$187 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$189 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$191 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$193 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$195 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$197 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$199 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$201 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$203 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$205 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$207 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$209 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$211 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$213 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$215 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$217 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$219 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$221 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$223 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$225 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$227 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$229 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$231 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$233 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$235 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$237 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$239 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$241 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$243 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$245 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$247 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$249 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$251 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$253 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$255 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$257 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$259 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$261 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$263 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$265 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$267 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$269 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$271 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$273 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$275 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$277 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$279 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$281 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$283 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$285 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$287 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$289 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$291 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$293 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$295 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$297 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$299 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$301 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$303 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) + wire \$305 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) + wire \$307 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) + wire \$309 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:408" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$311 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$313 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$315 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) + wire \$317 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) + wire \$319 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) + wire \$321 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) + wire \$323 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$325 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$327 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$329 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$331 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$333 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$335 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$337 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$339 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) + wire \$341 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$343 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$345 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$347 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$349 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$351 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$353 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$355 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$357 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) + wire \$359 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) + wire \$361 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$363 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$365 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$367 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$369 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$371 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$373 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$375 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$377 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) + wire \$379 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$381 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$383 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$385 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$387 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$389 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$391 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$393 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$395 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) + wire \$397 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) + wire \$399 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$401 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$403 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$405 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$407 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$409 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$411 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$413 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$415 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) + wire \$417 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$419 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) + wire \$421 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$423 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) + wire \$425 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$427 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) + wire \$429 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$431 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + wire \$433 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) + wire \$435 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) + wire \$437 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) + wire \$439 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) + wire \$441 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) + wire \$443 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:808" *) + wire \$445 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:808" *) + wire \$447 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:809" *) + wire \$449 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:409" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:810" *) + wire \$451 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:810" *) + wire \$453 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:811" *) + wire \$455 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:811" *) + wire \$456 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:770" *) + wire [30:0] \$459 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:770" *) + wire [30:0] \$460 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:795" *) + wire [30:0] \$462 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:795" *) + wire [30:0] \$463 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + wire [7:0] \$465 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) + wire \$468 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:410" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) + wire \$470 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) + wire \$472 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:531" *) + wire \$474 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:500" *) + wire [4:0] \$476 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:500" *) + wire [4:0] \$477 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:525" *) + wire [4:0] \$479 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:525" *) + wire [4:0] \$480 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:411" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tck; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tdi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + output TAP_bus__tdo; + reg TAP_bus__tdo; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tms; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" *) + reg TAP_tdo; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + input dmi0__ack_o; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + output [3:0] dmi0__addr_i; + reg [3:0] dmi0__addr_i = 4'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + reg [3:0] \dmi0__addr_i$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + output [63:0] dmi0__din; + reg [63:0] dmi0__din = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + reg [63:0] \dmi0__din$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + input [63:0] dmi0__dout; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + output dmi0__req_i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + output dmi0__we_i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:477" *) + wire [7:0] dmi0_addrsr__i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:477" *) + wire [7:0] dmi0_addrsr__o; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:477" *) + reg dmi0_addrsr__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:477" *) + reg \dmi0_addrsr__oe$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + wire dmi0_addrsr_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + wire dmi0_addrsr_isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [7:0] dmi0_addrsr_reg = 8'h00; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [7:0] \dmi0_addrsr_reg$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) + wire dmi0_addrsr_shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) + wire dmi0_addrsr_update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg dmi0_addrsr_update_core = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg \dmi0_addrsr_update_core$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg dmi0_addrsr_update_core_prev = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg \dmi0_addrsr_update_core_prev$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) + reg [63:0] dmi0_datasr__i = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) + reg [63:0] \dmi0_datasr__i$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) + wire [63:0] dmi0_datasr__o; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) + reg [1:0] dmi0_datasr__oe = 2'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:479" *) + reg [1:0] \dmi0_datasr__oe$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + wire dmi0_datasr_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + wire [1:0] dmi0_datasr_isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [63:0] dmi0_datasr_reg = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [63:0] \dmi0_datasr_reg$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) + wire dmi0_datasr_shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) + wire dmi0_datasr_update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg dmi0_datasr_update_core = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg \dmi0_datasr_update_core$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg dmi0_datasr_update_core_prev = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg \dmi0_datasr_update_core_prev$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_2__pad__i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) + wire fsm_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) + wire fsm_isdr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) + wire fsm_isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) + wire fsm_shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) + reg [2:0] fsm_state = 3'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) + reg [2:0] \fsm_state$467 = 3'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) + reg [2:0] \fsm_state$467$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) + reg [2:0] \fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) + wire fsm_update; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__pad__oe; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" *) + wire idblock_TAP_id_tdo; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:381" *) + wire idblock_id_bypass; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" *) + wire idblock_select_id; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:556" *) + reg [129:0] io_bd = 130'h000000000000000000000000000000000; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:556" *) + reg [129:0] \io_bd$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:401" *) + wire io_bd2core; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" *) + wire io_bd2io; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) + wire io_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) + wire io_shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:555" *) + reg [129:0] io_sr = 130'h000000000000000000000000000000000; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:555" *) + reg [129:0] \io_sr$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:399" *) + wire io_update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" *) + wire [3:0] irblock_ir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:130" *) + wire irblock_tdo; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + input jtag_wb__ack; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [29:0] jtag_wb__adr; + reg [29:0] jtag_wb__adr = 30'h00000000; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + reg [29:0] \jtag_wb__adr$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__cyc; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + input [31:0] jtag_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [31:0] jtag_wb__dat_w; + reg [31:0] jtag_wb__dat_w = 32'd0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + reg [31:0] \jtag_wb__dat_w$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [3:0] jtag_wb__sel; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__stb; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__we; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + wire [29:0] jtag_wb_addrsr__i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + wire [29:0] jtag_wb_addrsr__o; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + reg jtag_wb_addrsr__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) + reg \jtag_wb_addrsr__oe$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + wire jtag_wb_addrsr_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + wire jtag_wb_addrsr_isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [29:0] jtag_wb_addrsr_reg = 30'h00000000; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [29:0] \jtag_wb_addrsr_reg$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) + wire jtag_wb_addrsr_shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) + wire jtag_wb_addrsr_update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg jtag_wb_addrsr_update_core = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg \jtag_wb_addrsr_update_core$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg jtag_wb_addrsr_update_core_prev = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg \jtag_wb_addrsr_update_core_prev$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) + reg [31:0] jtag_wb_datasr__i = 32'd0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) + reg [31:0] \jtag_wb_datasr__i$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) + wire [31:0] jtag_wb_datasr__o; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) + reg [1:0] jtag_wb_datasr__oe = 2'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:744" *) + reg [1:0] \jtag_wb_datasr__oe$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + wire jtag_wb_datasr_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + wire [1:0] jtag_wb_datasr_isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [31:0] jtag_wb_datasr_reg = 32'd0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [31:0] \jtag_wb_datasr_reg$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) + wire jtag_wb_datasr_shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) + wire jtag_wb_datasr_update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg jtag_wb_datasr_update_core = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg \jtag_wb_datasr_update_core$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg jtag_wb_datasr_update_core_prev = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg \jtag_wb_datasr_update_core_prev$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_clk__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_clk__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_cs_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_cs_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_miso__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_miso__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_mosi__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_mosi__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_scl__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_scl__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__pad__oe; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *) + wire negjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *) + wire negjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + wire posjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + wire posjtag_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ba_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ba_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ba_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ba_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cas_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cas_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cke__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cke__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_clock__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_clock__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cs_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cs_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dm_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dm_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dm_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dm_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ras_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ras_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_we_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_we_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *) + wire [2:0] sr0__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *) + wire [2:0] sr0__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *) + reg sr0__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *) + reg \sr0__oe$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + wire sr0_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + wire sr0_isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [2:0] sr0_reg = 3'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [2:0] \sr0_reg$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) + wire sr0_shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) + wire sr0_update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg sr0_update_core = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg \sr0_update_core$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg sr0_update_core_prev = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg \sr0_update_core_prev$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) + reg [2:0] sr5__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) + wire sr5__ie; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) + wire [2:0] sr5__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) + reg sr5__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) + reg \sr5__oe$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) + wire sr5_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) + wire sr5_isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [2:0] sr5_reg = 3'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:649" *) + reg [2:0] \sr5_reg$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:654" *) + wire sr5_shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:655" *) + wire sr5_update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg sr5_update_core = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:668" *) + reg \sr5_update_core$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg sr5_update_core_prev = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *) + reg \sr5_update_core_prev$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + output wb_dcache_en; + reg wb_dcache_en = 1'h1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + reg \wb_dcache_en$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + output wb_icache_en; + reg wb_icache_en = 1'h1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + reg \wb_icache_en$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + output wb_sram_en; + reg wb_sram_en = 1'h1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + reg \wb_sram_en$next ; + assign \$9 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) 4'hf; + assign \$99 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[24] : sdr_dq_6__core__o; + assign \$101 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[25] : sdr_dq_6__core__oe; + assign \$103 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[26] : sdr_dq_7__pad__i; + assign \$105 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[27] : sdr_dq_7__core__o; + assign \$107 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[28] : sdr_dq_7__core__oe; + assign \$109 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[29] : sdr_a_0__core__o; + assign \$111 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[30] : sdr_a_1__core__o; + assign \$113 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[31] : sdr_a_2__core__o; + assign \$115 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[32] : sdr_a_3__core__o; + assign \$117 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[33] : sdr_a_4__core__o; + assign \$11 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 1'h0; + assign \$119 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[34] : sdr_a_5__core__o; + assign \$121 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[35] : sdr_a_6__core__o; + assign \$123 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[36] : sdr_a_7__core__o; + assign \$125 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[37] : sdr_a_8__core__o; + assign \$127 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[38] : sdr_a_9__core__o; + assign \$129 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[39] : sdr_ba_0__core__o; + assign \$131 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[40] : sdr_ba_1__core__o; + assign \$133 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[41] : sdr_clock__core__o; + assign \$135 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[42] : sdr_cke__core__o; + assign \$137 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[43] : sdr_ras_n__core__o; + assign \$13 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 2'h2; + assign \$139 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[44] : sdr_cas_n__core__o; + assign \$141 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[45] : sdr_we_n__core__o; + assign \$143 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[46] : sdr_cs_n__core__o; + assign \$145 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[47] : sdr_a_10__core__o; + assign \$147 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[48] : sdr_a_11__core__o; + assign \$149 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[49] : sdr_a_12__core__o; + assign \$151 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[50] : sdr_dm_1__core__o; + assign \$153 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[51] : sdr_dq_8__pad__i; + assign \$155 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[52] : sdr_dq_8__core__o; + assign \$157 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[53] : sdr_dq_8__core__oe; + assign \$15 = \$11 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) \$13 ; + assign \$159 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[54] : sdr_dq_9__pad__i; + assign \$161 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[55] : sdr_dq_9__core__o; + assign \$163 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[56] : sdr_dq_9__core__oe; + assign \$165 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[57] : sdr_dq_10__pad__i; + assign \$167 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[58] : sdr_dq_10__core__o; + assign \$169 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[59] : sdr_dq_10__core__oe; + assign \$171 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[60] : sdr_dq_11__pad__i; + assign \$173 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[61] : sdr_dq_11__core__o; + assign \$175 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[62] : sdr_dq_11__core__oe; + assign \$177 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[63] : sdr_dq_12__pad__i; + assign \$17 = \$15 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:406" *) fsm_capture; + assign \$179 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[64] : sdr_dq_12__core__o; + assign \$181 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[65] : sdr_dq_12__core__oe; + assign \$183 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[66] : sdr_dq_13__pad__i; + assign \$185 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[67] : sdr_dq_13__core__o; + assign \$187 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[68] : sdr_dq_13__core__oe; + assign \$189 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[69] : sdr_dq_14__pad__i; + assign \$191 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[70] : sdr_dq_14__core__o; + assign \$193 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[71] : sdr_dq_14__core__oe; + assign \$195 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[72] : sdr_dq_15__pad__i; + assign \$197 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[73] : sdr_dq_15__core__o; + assign \$1 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) 1'h1; + assign \$19 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 1'h0; + assign \$199 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[74] : sdr_dq_15__core__oe; + assign \$201 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[75] : gpio_e8__pad__i; + assign \$203 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[76] : gpio_e8__core__o; + assign \$205 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[77] : gpio_e8__core__oe; + assign \$207 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[78] : gpio_e9__pad__i; + assign \$209 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[79] : gpio_e9__core__o; + assign \$211 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[80] : gpio_e9__core__oe; + assign \$213 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[81] : gpio_e10__pad__i; + assign \$215 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[82] : gpio_e10__core__o; + assign \$217 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[83] : gpio_e10__core__oe; + assign \$21 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 2'h2; + assign \$219 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[84] : gpio_e11__pad__i; + assign \$221 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[85] : gpio_e11__core__o; + assign \$223 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[86] : gpio_e11__core__oe; + assign \$225 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[87] : gpio_e12__pad__i; + assign \$227 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[88] : gpio_e12__core__o; + assign \$229 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[89] : gpio_e12__core__oe; + assign \$231 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[90] : gpio_e13__pad__i; + assign \$233 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[91] : gpio_e13__core__o; + assign \$235 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[92] : gpio_e13__core__oe; + assign \$237 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[93] : gpio_e14__pad__i; + assign \$23 = \$19 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) \$21 ; + assign \$239 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[94] : gpio_e14__core__o; + assign \$241 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[95] : gpio_e14__core__oe; + assign \$243 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[96] : gpio_e15__pad__i; + assign \$245 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[97] : gpio_e15__core__o; + assign \$247 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[98] : gpio_e15__core__oe; + assign \$249 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[99] : gpio_s0__pad__i; + assign \$251 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[100] : gpio_s0__core__o; + assign \$253 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[101] : gpio_s0__core__oe; + assign \$255 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[102] : gpio_s1__pad__i; + assign \$257 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[103] : gpio_s1__core__o; + assign \$25 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) 2'h2; + assign \$259 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[104] : gpio_s1__core__oe; + assign \$261 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[105] : gpio_s2__pad__i; + assign \$263 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[106] : gpio_s2__core__o; + assign \$265 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[107] : gpio_s2__core__oe; + assign \$267 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[108] : gpio_s3__pad__i; + assign \$269 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[109] : gpio_s3__core__o; + assign \$271 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[110] : gpio_s3__core__oe; + assign \$273 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[111] : gpio_s4__pad__i; + assign \$275 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[112] : gpio_s4__core__o; + assign \$277 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[113] : gpio_s4__core__oe; + assign \$27 = \$23 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$25 ; + assign \$279 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[114] : gpio_s5__pad__i; + assign \$281 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[115] : gpio_s5__core__o; + assign \$283 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[116] : gpio_s5__core__oe; + assign \$285 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[117] : gpio_s6__pad__i; + assign \$287 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[118] : gpio_s6__core__o; + assign \$289 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[119] : gpio_s6__core__oe; + assign \$291 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[120] : gpio_s7__pad__i; + assign \$293 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[121] : gpio_s7__core__o; + assign \$295 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[122] : gpio_s7__core__oe; + assign \$297 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[123] : mtwi_sda__pad__i; + assign \$29 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$27 ; + assign \$299 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[124] : mtwi_sda__core__o; + assign \$301 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[125] : mtwi_sda__core__oe; + assign \$303 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[126] : mtwi_scl__core__o; + assign \$305 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) io_bd[127] : eint_0__pad__i; + assign \$307 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) io_bd[128] : eint_1__pad__i; + assign \$309 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) io_bd[129] : eint_2__pad__i; + assign \$311 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 1'h0; + assign \$313 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 2'h2; + assign \$315 = \$311 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) \$313 ; + assign \$317 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) 2'h2; + assign \$31 = \$29 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:408" *) fsm_shift; + assign \$319 = \$315 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$317 ; + assign \$321 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$319 ; + assign \$323 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 3'h4; + assign \$325 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$327 = \$325 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$329 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$331 = \$329 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$333 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$335 = \$333 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$337 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) sr0_update_core; + assign \$33 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 1'h0; + assign \$339 = sr0_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$337 ; + assign \$341 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 3'h5; + assign \$343 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$345 = \$343 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$347 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$349 = \$347 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$351 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$353 = \$351 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$355 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) jtag_wb_addrsr_update_core; + assign \$357 = jtag_wb_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$355 ; + assign \$35 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) 2'h2; + assign \$359 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 3'h6; + assign \$361 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 3'h7; + assign \$363 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$365 = \$363 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$367 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$369 = \$367 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$371 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$373 = \$371 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$375 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) jtag_wb_datasr_update_core; + assign \$377 = jtag_wb_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$375 ; + assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) \$35 ; + assign \$379 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 4'h8; + assign \$381 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$383 = \$381 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$385 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$387 = \$385 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$389 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$391 = \$389 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$393 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) dmi0_addrsr_update_core; + assign \$395 = dmi0_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$393 ; + assign \$397 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 4'h9; + assign \$3 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) 4'hf; + assign \$39 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) 2'h2; + assign \$399 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 4'ha; + assign \$401 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$403 = \$401 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$405 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$407 = \$405 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$409 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$411 = \$409 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$413 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) dmi0_datasr_update_core; + assign \$415 = dmi0_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$413 ; + assign \$417 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:657" *) 4'hb; + assign \$41 = \$37 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$39 ; + assign \$419 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) 1'h0; + assign \$421 = \$419 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:658" *) fsm_capture; + assign \$423 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) 1'h0; + assign \$425 = \$423 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:659" *) fsm_shift; + assign \$427 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) 1'h0; + assign \$429 = \$427 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *) fsm_update; + assign \$431 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) sr5_update_core; + assign \$433 = sr5_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) \$431 ; + assign \$435 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) 1'h1; + assign \$437 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) 2'h2; + assign \$43 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) \$41 ; + assign \$439 = \$435 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) \$437 ; + assign \$441 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) 2'h3; + assign \$443 = \$439 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:807" *) \$441 ; + assign \$445 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:808" *) 3'h4; + assign \$447 = \$443 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:808" *) \$445 ; + assign \$449 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:809" *) 2'h2; + assign \$451 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:810" *) 3'h4; + assign \$453 = \$449 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:810" *) \$451 ; + assign \$456 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:811" *) 1'h0; + assign \$455 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:811" *) \$456 ; + assign \$45 = \$43 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:409" *) fsm_update; + assign \$460 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:770" *) 1'h1; + assign \$463 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:795" *) 1'h1; + assign \$465 = + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) dmi0__addr_i; + assign \$468 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) 1'h1; + assign \$470 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) 2'h2; + assign \$472 = \$468 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" *) \$470 ; + assign \$474 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:531" *) 2'h2; + assign \$477 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:500" *) 1'h1; + assign \$47 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:410" *) 1'h0; + assign \$480 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:525" *) 1'h1; + assign \$49 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:411" *) 1'h0; + assign \$51 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[0] : mspi0_clk__core__o; + assign \$53 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[1] : mspi0_cs_n__core__o; + assign \$55 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[2] : mspi0_mosi__core__o; + assign \$57 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:589" *) io_bd[3] : mspi0_miso__pad__i; + assign \$5 = \$1 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) \$3 ; + assign \$59 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:592" *) io_bd[4] : sdr_dm_0__core__o; + assign \$61 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[5] : sdr_dq_0__pad__i; + assign \$63 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[6] : sdr_dq_0__core__o; + assign \$65 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[7] : sdr_dq_0__core__oe; + assign \$67 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[8] : sdr_dq_1__pad__i; + assign \$69 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[9] : sdr_dq_1__core__o; + assign \$71 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[10] : sdr_dq_1__core__oe; + assign \$73 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[11] : sdr_dq_2__pad__i; + assign \$75 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[12] : sdr_dq_2__core__o; + assign \$77 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[13] : sdr_dq_2__core__oe; + assign \$7 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) \$5 ; + assign \$79 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[14] : sdr_dq_3__pad__i; + assign \$81 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[15] : sdr_dq_3__core__o; + assign \$83 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[16] : sdr_dq_3__core__oe; + assign \$85 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[17] : sdr_dq_4__pad__i; + assign \$87 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[18] : sdr_dq_4__core__o; + assign \$89 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[19] : sdr_dq_4__core__oe; + assign \$91 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[20] : sdr_dq_5__pad__i; + assign \$93 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[21] : sdr_dq_5__core__o; + assign \$95 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:604" *) io_bd[22] : sdr_dq_5__core__oe; + assign \$97 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:602" *) io_bd[23] : sdr_dq_6__pad__i; + always @(posedge clk) + wb_icache_en <= \wb_icache_en$next ; + always @(posedge clk) + wb_dcache_en <= \wb_dcache_en$next ; + always @(posedge clk) + wb_sram_en <= \wb_sram_en$next ; + always @(posedge clk) + dmi0_datasr__i <= \dmi0_datasr__i$next ; + always @(posedge clk) + dmi0__din <= \dmi0__din$next ; + always @(posedge clk) + \fsm_state$467 <= \fsm_state$467$next ; + always @(posedge clk) + dmi0__addr_i <= \dmi0__addr_i$next ; + always @(posedge clk) + jtag_wb_datasr__i <= \jtag_wb_datasr__i$next ; + always @(posedge clk) + jtag_wb__dat_w <= \jtag_wb__dat_w$next ; + always @(posedge clk) + fsm_state <= \fsm_state$next ; + always @(posedge clk) + jtag_wb__adr <= \jtag_wb__adr$next ; + always @(posedge posjtag_clk) + sr5_reg <= \sr5_reg$next ; + always @(posedge clk) + sr5__oe <= \sr5__oe$next ; + always @(posedge clk) + sr5_update_core_prev <= \sr5_update_core_prev$next ; + always @(posedge clk) + sr5_update_core <= \sr5_update_core$next ; + always @(posedge posjtag_clk) + dmi0_datasr_reg <= \dmi0_datasr_reg$next ; + always @(posedge clk) + dmi0_datasr__oe <= \dmi0_datasr__oe$next ; + always @(posedge clk) + dmi0_datasr_update_core_prev <= \dmi0_datasr_update_core_prev$next ; + always @(posedge clk) + dmi0_datasr_update_core <= \dmi0_datasr_update_core$next ; + always @(posedge posjtag_clk) + dmi0_addrsr_reg <= \dmi0_addrsr_reg$next ; + always @(posedge clk) + dmi0_addrsr__oe <= \dmi0_addrsr__oe$next ; + always @(posedge clk) + dmi0_addrsr_update_core_prev <= \dmi0_addrsr_update_core_prev$next ; + always @(posedge clk) + dmi0_addrsr_update_core <= \dmi0_addrsr_update_core$next ; + always @(posedge posjtag_clk) + jtag_wb_datasr_reg <= \jtag_wb_datasr_reg$next ; + always @(posedge clk) + jtag_wb_datasr__oe <= \jtag_wb_datasr__oe$next ; + always @(posedge clk) + jtag_wb_datasr_update_core_prev <= \jtag_wb_datasr_update_core_prev$next ; + always @(posedge clk) + jtag_wb_datasr_update_core <= \jtag_wb_datasr_update_core$next ; + always @(posedge posjtag_clk) + jtag_wb_addrsr_reg <= \jtag_wb_addrsr_reg$next ; + always @(posedge clk) + jtag_wb_addrsr__oe <= \jtag_wb_addrsr__oe$next ; + always @(posedge clk) + jtag_wb_addrsr_update_core_prev <= \jtag_wb_addrsr_update_core_prev$next ; + always @(posedge clk) + jtag_wb_addrsr_update_core <= \jtag_wb_addrsr_update_core$next ; + always @(posedge posjtag_clk) + sr0_reg <= \sr0_reg$next ; + always @(posedge clk) + sr0__oe <= \sr0__oe$next ; + always @(posedge clk) + sr0_update_core_prev <= \sr0_update_core_prev$next ; + always @(posedge clk) + sr0_update_core <= \sr0_update_core$next ; + always @(negedge negjtag_clk) + io_bd <= \io_bd$next ; + always @(posedge posjtag_clk) + io_sr <= \io_sr$next ; + fsm fsm ( + .TAP_bus__tck(TAP_bus__tck), + .TAP_bus__tms(TAP_bus__tms), + .capture(fsm_capture), + .isdr(fsm_isdr), + .isir(fsm_isir), + .negjtag_clk(negjtag_clk), + .negjtag_rst(negjtag_rst), + .posjtag_clk(posjtag_clk), + .posjtag_rst(posjtag_rst), + .shift(fsm_shift), + .update(fsm_update) + ); + idblock idblock ( + .TAP_bus__tdi(TAP_bus__tdi), + .TAP_id_tdo(idblock_TAP_id_tdo), + .capture(fsm_capture), + .id_bypass(idblock_id_bypass), + .posjtag_clk(posjtag_clk), + .posjtag_rst(posjtag_rst), + .select_id(idblock_select_id), + .shift(fsm_shift), + .update(fsm_update) + ); + irblock irblock ( + .TAP_bus__tdi(TAP_bus__tdi), + .capture(fsm_capture), + .ir(irblock_ir), + .isir(fsm_isir), + .posjtag_clk(posjtag_clk), + .posjtag_rst(posjtag_rst), + .shift(fsm_shift), + .tdo(irblock_tdo), + .update(fsm_update) + ); + always @* begin + if (\initial ) begin end + TAP_tdo = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:421" *) + casez ({ \$321 , idblock_select_id, fsm_isir }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:421" */ + 3'b??1: + TAP_tdo = irblock_tdo; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:423" */ + 3'b?1?: + TAP_tdo = idblock_TAP_id_tdo; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:426" */ + 3'b1??: + TAP_tdo = io_sr[129]; + endcase + end + always @* begin + if (\initial ) begin end + \sr0_update_core$next = sr0_update; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sr0_update_core$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \sr0_update_core_prev$next = sr0_update_core; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sr0_update_core_prev$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + casez (\$339 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + 1'h1: + \sr0__oe$next = sr0_isir; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ + default: + \sr0__oe$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sr0__oe$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \sr0_reg$next = sr0_reg; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) + casez (sr0_shift) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ + 1'h1: + \sr0_reg$next = { TAP_bus__tdi, sr0_reg[2:1] }; + endcase + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) + casez (sr0_capture) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ + 1'h1: + \sr0_reg$next = sr0__i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \sr0_reg$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb_addrsr_update_core$next = jtag_wb_addrsr_update; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb_addrsr_update_core$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb_addrsr_update_core_prev$next = jtag_wb_addrsr_update_core; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb_addrsr_update_core_prev$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + casez (\$357 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + 1'h1: + \jtag_wb_addrsr__oe$next = jtag_wb_addrsr_isir; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ + default: + \jtag_wb_addrsr__oe$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb_addrsr__oe$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb_addrsr_reg$next = jtag_wb_addrsr_reg; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) + casez (jtag_wb_addrsr_shift) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ + 1'h1: + \jtag_wb_addrsr_reg$next = { TAP_bus__tdi, jtag_wb_addrsr_reg[29:1] }; + endcase + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) + casez (jtag_wb_addrsr_capture) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ + 1'h1: + \jtag_wb_addrsr_reg$next = jtag_wb_addrsr__i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \jtag_wb_addrsr_reg$next = 30'h00000000; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb_datasr_update_core$next = jtag_wb_datasr_update; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb_datasr_update_core$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb_datasr_update_core_prev$next = jtag_wb_datasr_update_core; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb_datasr_update_core_prev$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + casez (\$377 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + 1'h1: + \jtag_wb_datasr__oe$next = jtag_wb_datasr_isir; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ + default: + \jtag_wb_datasr__oe$next = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb_datasr__oe$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb_datasr_reg$next = jtag_wb_datasr_reg; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) + casez (jtag_wb_datasr_shift) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ + 1'h1: + \jtag_wb_datasr_reg$next = { TAP_bus__tdi, jtag_wb_datasr_reg[31:1] }; + endcase + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) + casez (jtag_wb_datasr_capture) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ + 1'h1: + \jtag_wb_datasr_reg$next = jtag_wb_datasr__i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \jtag_wb_datasr_reg$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0_addrsr_update_core$next = dmi0_addrsr_update; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0_addrsr_update_core$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0_addrsr_update_core_prev$next = dmi0_addrsr_update_core; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0_addrsr_update_core_prev$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + casez (\$395 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + 1'h1: + \dmi0_addrsr__oe$next = dmi0_addrsr_isir; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ + default: + \dmi0_addrsr__oe$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0_addrsr__oe$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0_addrsr_reg$next = dmi0_addrsr_reg; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) + casez (dmi0_addrsr_shift) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ + 1'h1: + \dmi0_addrsr_reg$next = { TAP_bus__tdi, dmi0_addrsr_reg[7:1] }; + endcase + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) + casez (dmi0_addrsr_capture) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ + 1'h1: + \dmi0_addrsr_reg$next = dmi0_addrsr__i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \dmi0_addrsr_reg$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0_datasr_update_core$next = dmi0_datasr_update; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0_datasr_update_core$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0_datasr_update_core_prev$next = dmi0_datasr_update_core; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0_datasr_update_core_prev$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + casez (\$415 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + 1'h1: + \dmi0_datasr__oe$next = dmi0_datasr_isir; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ + default: + \dmi0_datasr__oe$next = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0_datasr__oe$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0_datasr_reg$next = dmi0_datasr_reg; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) + casez (dmi0_datasr_shift) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ + 1'h1: + \dmi0_datasr_reg$next = { TAP_bus__tdi, dmi0_datasr_reg[63:1] }; + endcase + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) + casez (dmi0_datasr_capture) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ + 1'h1: + \dmi0_datasr_reg$next = dmi0_datasr__i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \dmi0_datasr_reg$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \sr5_update_core$next = sr5_update; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sr5_update_core$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \sr5_update_core_prev$next = sr5_update_core; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sr5_update_core_prev$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *) + casez (\$433 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" */ + 1'h1: + \sr5__oe$next = sr5_isir; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:678" */ + default: + \sr5__oe$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sr5__oe$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \sr5_reg$next = sr5_reg; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" *) + casez (sr5_shift) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:681" */ + 1'h1: + \sr5_reg$next = { TAP_bus__tdi, sr5_reg[2:1] }; + endcase + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" *) + casez (sr5_capture) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:683" */ + 1'h1: + \sr5_reg$next = sr5__i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \sr5_reg$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:694" *) + casez ({ sr5_shift, dmi0_datasr_shift, dmi0_addrsr_shift, jtag_wb_datasr_shift, jtag_wb_addrsr_shift, sr0_shift }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:694" */ + 6'b?????1: + TAP_bus__tdo = sr0_reg[0]; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ + 6'b????1?: + TAP_bus__tdo = jtag_wb_addrsr_reg[0]; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ + 6'b???1??: + TAP_bus__tdo = jtag_wb_datasr_reg[0]; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ + 6'b??1???: + TAP_bus__tdo = dmi0_addrsr_reg[0]; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ + 6'b?1????: + TAP_bus__tdo = dmi0_datasr_reg[0]; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:697" */ + 6'b1?????: + TAP_bus__tdo = sr5_reg[0]; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:701" */ + default: + TAP_bus__tdo = TAP_tdo; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb__adr$next = jtag_wb__adr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:764" */ + 3'h0: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" *) + casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" */ + 3'b??1: + \jtag_wb__adr$next = jtag_wb_addrsr__o; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:768" */ + 3'b?1?: + \jtag_wb__adr$next = \$459 [29:0]; + endcase + /* \nmigen.decoding = "READ/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:775" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "READACK/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:781" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "WRITEREAD/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:787" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "WRITEREADACK/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:793" */ + 3'h4: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:794" *) + casez (jtag_wb__ack) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:794" */ + 1'h1: + \jtag_wb__adr$next = \$462 [29:0]; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb__adr$next = 30'h00000000; + endcase + end + always @* begin + if (\initial ) begin end + \fsm_state$next = fsm_state; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:764" */ + 3'h0: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" *) + casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" */ + 3'b??1: + \fsm_state$next = 3'h1; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:768" */ + 3'b?1?: + \fsm_state$next = 3'h1; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:772" */ + 3'b1??: + \fsm_state$next = 3'h2; + endcase + /* \nmigen.decoding = "READ/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:775" */ + 3'h1: + \fsm_state$next = 3'h3; + /* \nmigen.decoding = "READACK/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:781" */ + 3'h3: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:782" *) + casez (jtag_wb__ack) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:782" */ + 1'h1: + \fsm_state$next = 3'h0; + endcase + /* \nmigen.decoding = "WRITEREAD/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:787" */ + 3'h2: + \fsm_state$next = 3'h4; + /* \nmigen.decoding = "WRITEREADACK/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:793" */ + 3'h4: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:794" *) + casez (jtag_wb__ack) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:794" */ + 1'h1: + \fsm_state$next = 3'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \fsm_state$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb__dat_w$next = jtag_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:764" */ + 3'h0: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" *) + casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:765" */ + 3'b??1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:768" */ + 3'b?1?: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:772" */ + 3'b1??: + \jtag_wb__dat_w$next = jtag_wb_datasr__o; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb__dat_w$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \jtag_wb_datasr__i$next = jtag_wb_datasr__i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:763" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:764" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "READ/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:775" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "READACK/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:781" */ + 3'h3: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:782" *) + casez (jtag_wb__ack) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:782" */ + 1'h1: + \jtag_wb_datasr__i$next = jtag_wb__dat_r; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_wb_datasr__i$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0__addr_i$next = dmi0__addr_i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) + casez (\fsm_state$467 ) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" */ + 3'h0: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" *) + casez ({ dmi0_datasr__oe, dmi0_addrsr__oe }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" */ + 3'b??1: + \dmi0__addr_i$next = dmi0_addrsr__o[3:0]; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:498" */ + 3'b?1?: + \dmi0__addr_i$next = \$476 [3:0]; + endcase + /* \nmigen.decoding = "READ/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:507" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "READACK/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:511" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "WRRD/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:519" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "WRRDACK/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" */ + 3'h4: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) + casez (dmi0__ack_o) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" */ + 1'h1: + \dmi0__addr_i$next = \$479 [3:0]; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0__addr_i$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fsm_state$467$next = \fsm_state$467 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) + casez (\fsm_state$467 ) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" */ + 3'h0: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" *) + casez ({ dmi0_datasr__oe, dmi0_addrsr__oe }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" */ + 3'b??1: + \fsm_state$467$next = 3'h1; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:498" */ + 3'b?1?: + \fsm_state$467$next = 3'h1; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:502" */ + 3'b1??: + \fsm_state$467$next = 3'h2; + endcase + /* \nmigen.decoding = "READ/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:507" */ + 3'h1: + \fsm_state$467$next = 3'h3; + /* \nmigen.decoding = "READACK/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:511" */ + 3'h3: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" *) + casez (dmi0__ack_o) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" */ + 1'h1: + \fsm_state$467$next = 3'h0; + endcase + /* \nmigen.decoding = "WRRD/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:519" */ + 3'h2: + \fsm_state$467$next = 3'h4; + /* \nmigen.decoding = "WRRDACK/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" */ + 3'h4: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) + casez (dmi0__ack_o) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" */ + 1'h1: + \fsm_state$467$next = 3'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \fsm_state$467$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0__din$next = dmi0__din; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) + casez (\fsm_state$467 ) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" */ + 3'h0: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" *) + casez ({ dmi0_datasr__oe, dmi0_addrsr__oe }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:495" */ + 3'b??1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:498" */ + 3'b?1?: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:502" */ + 3'b1??: + \dmi0__din$next = dmi0_datasr__o; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0__din$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \dmi0_datasr__i$next = dmi0_datasr__i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:491" *) + casez (\fsm_state$467 ) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "READ/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:507" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "READACK/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:511" */ + 3'h3: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" *) + casez (dmi0__ack_o) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" */ + 1'h1: + \dmi0_datasr__i$next = dmi0__dout; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dmi0_datasr__i$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \wb_icache_en$next = wb_icache_en; + \wb_dcache_en$next = wb_dcache_en; + \wb_sram_en$next = wb_sram_en; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:108" *) + casez (sr5__oe) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:108" */ + 1'h1: + { \wb_sram_en$next , \wb_dcache_en$next , \wb_icache_en$next } = sr5__o; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + begin + \wb_icache_en$next = 1'h1; + \wb_dcache_en$next = 1'h1; + \wb_sram_en$next = 1'h1; + end + endcase + end + always @* begin + if (\initial ) begin end + sr5__i = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:111" *) + casez (sr5__ie) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:111" */ + 1'h1: + sr5__i = { wb_sram_en, wb_dcache_en, wb_icache_en }; + endcase + end + always @* begin + if (\initial ) begin end + \io_sr$next = io_sr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" *) + casez ({ io_update, io_shift, io_capture }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" */ + 3'b??1: + \io_sr$next = { eint_2__pad__i, eint_1__pad__i, eint_0__pad__i, mtwi_scl__core__o, mtwi_sda__core__oe, mtwi_sda__core__o, mtwi_sda__pad__i, gpio_s7__core__oe, gpio_s7__core__o, gpio_s7__pad__i, gpio_s6__core__oe, gpio_s6__core__o, gpio_s6__pad__i, gpio_s5__core__oe, gpio_s5__core__o, gpio_s5__pad__i, gpio_s4__core__oe, gpio_s4__core__o, gpio_s4__pad__i, gpio_s3__core__oe, gpio_s3__core__o, gpio_s3__pad__i, gpio_s2__core__oe, gpio_s2__core__o, gpio_s2__pad__i, gpio_s1__core__oe, gpio_s1__core__o, gpio_s1__pad__i, gpio_s0__core__oe, gpio_s0__core__o, gpio_s0__pad__i, gpio_e15__core__oe, gpio_e15__core__o, gpio_e15__pad__i, gpio_e14__core__oe, gpio_e14__core__o, gpio_e14__pad__i, gpio_e13__core__oe, gpio_e13__core__o, gpio_e13__pad__i, gpio_e12__core__oe, gpio_e12__core__o, gpio_e12__pad__i, gpio_e11__core__oe, gpio_e11__core__o, gpio_e11__pad__i, gpio_e10__core__oe, gpio_e10__core__o, gpio_e10__pad__i, gpio_e9__core__oe, gpio_e9__core__o, gpio_e9__pad__i, gpio_e8__core__oe, gpio_e8__core__o, gpio_e8__pad__i, sdr_dq_15__core__oe, sdr_dq_15__core__o, sdr_dq_15__pad__i, sdr_dq_14__core__oe, sdr_dq_14__core__o, sdr_dq_14__pad__i, sdr_dq_13__core__oe, sdr_dq_13__core__o, sdr_dq_13__pad__i, sdr_dq_12__core__oe, sdr_dq_12__core__o, sdr_dq_12__pad__i, sdr_dq_11__core__oe, sdr_dq_11__core__o, sdr_dq_11__pad__i, sdr_dq_10__core__oe, sdr_dq_10__core__o, sdr_dq_10__pad__i, sdr_dq_9__core__oe, sdr_dq_9__core__o, sdr_dq_9__pad__i, sdr_dq_8__core__oe, sdr_dq_8__core__o, sdr_dq_8__pad__i, sdr_dm_1__core__o, sdr_a_12__core__o, sdr_a_11__core__o, sdr_a_10__core__o, sdr_cs_n__core__o, sdr_we_n__core__o, sdr_cas_n__core__o, sdr_ras_n__core__o, sdr_cke__core__o, sdr_clock__core__o, sdr_ba_1__core__o, sdr_ba_0__core__o, sdr_a_9__core__o, sdr_a_8__core__o, sdr_a_7__core__o, sdr_a_6__core__o, sdr_a_5__core__o, sdr_a_4__core__o, sdr_a_3__core__o, sdr_a_2__core__o, sdr_a_1__core__o, sdr_a_0__core__o, sdr_dq_7__core__oe, sdr_dq_7__core__o, sdr_dq_7__pad__i, sdr_dq_6__core__oe, sdr_dq_6__core__o, sdr_dq_6__pad__i, sdr_dq_5__core__oe, sdr_dq_5__core__o, sdr_dq_5__pad__i, sdr_dq_4__core__oe, sdr_dq_4__core__o, sdr_dq_4__pad__i, sdr_dq_3__core__oe, sdr_dq_3__core__o, sdr_dq_3__pad__i, sdr_dq_2__core__oe, sdr_dq_2__core__o, sdr_dq_2__pad__i, sdr_dq_1__core__oe, sdr_dq_1__core__o, sdr_dq_1__pad__i, sdr_dq_0__core__oe, sdr_dq_0__core__o, sdr_dq_0__pad__i, sdr_dm_0__core__o, mspi0_miso__pad__i, mspi0_mosi__core__o, mspi0_cs_n__core__o, mspi0_clk__core__o }; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:577" */ + 3'b?1?: + \io_sr$next = { io_sr[128:0], TAP_bus__tdi }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \io_sr$next = 130'h000000000000000000000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \io_bd$next = io_bd; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" *) + casez ({ io_update, io_shift, io_capture }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" */ + 3'b??1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:577" */ + 3'b?1?: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:581" */ + 3'b1??: + \io_bd$next = io_sr; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (negjtag_rst) + 1'h1: + \io_bd$next = 130'h000000000000000000000000000000000; + endcase + end + assign \$459 = \$460 ; + assign \$462 = \$463 ; + assign \$476 = \$477 ; + assign \$479 = \$480 ; + assign sr5__ie = 1'h0; + assign sr0__i = sr0__o; + assign dmi0__we_i = \$474 ; + assign dmi0__req_i = \$472 ; + assign dmi0_addrsr__i = \$465 ; + assign jtag_wb__cyc = \$455 ; + assign jtag_wb__we = \$453 ; + assign jtag_wb__stb = \$447 ; + assign jtag_wb__sel[3] = 1'h1; + assign jtag_wb__sel[2] = 1'h1; + assign jtag_wb__sel[1] = 1'h1; + assign jtag_wb__sel[0] = 1'h1; + assign jtag_wb_addrsr__i = jtag_wb__adr; + assign sr5_update = \$429 ; + assign sr5_shift = \$425 ; + assign sr5_capture = \$421 ; + assign sr5_isir = \$417 ; + assign sr5__o = sr5_reg; + assign dmi0_datasr_update = \$411 ; + assign dmi0_datasr_shift = \$407 ; + assign dmi0_datasr_capture = \$403 ; + assign dmi0_datasr_isir = { \$399 , \$397 }; + assign dmi0_datasr__o = dmi0_datasr_reg; + assign dmi0_addrsr_update = \$391 ; + assign dmi0_addrsr_shift = \$387 ; + assign dmi0_addrsr_capture = \$383 ; + assign dmi0_addrsr_isir = \$379 ; + assign dmi0_addrsr__o = dmi0_addrsr_reg; + assign jtag_wb_datasr_update = \$373 ; + assign jtag_wb_datasr_shift = \$369 ; + assign jtag_wb_datasr_capture = \$365 ; + assign jtag_wb_datasr_isir = { \$361 , \$359 }; + assign jtag_wb_datasr__o = jtag_wb_datasr_reg; + assign jtag_wb_addrsr_update = \$353 ; + assign jtag_wb_addrsr_shift = \$349 ; + assign jtag_wb_addrsr_capture = \$345 ; + assign jtag_wb_addrsr_isir = \$341 ; + assign jtag_wb_addrsr__o = jtag_wb_addrsr_reg; + assign sr0_update = \$335 ; + assign sr0_shift = \$331 ; + assign sr0_capture = \$327 ; + assign sr0_isir = \$323 ; + assign sr0__o = sr0_reg; + assign eint_2__core__i = \$309 ; + assign eint_1__core__i = \$307 ; + assign eint_0__core__i = \$305 ; + assign mtwi_scl__pad__o = \$303 ; + assign mtwi_sda__pad__oe = \$301 ; + assign mtwi_sda__pad__o = \$299 ; + assign mtwi_sda__core__i = \$297 ; + assign gpio_s7__pad__oe = \$295 ; + assign gpio_s7__pad__o = \$293 ; + assign gpio_s7__core__i = \$291 ; + assign gpio_s6__pad__oe = \$289 ; + assign gpio_s6__pad__o = \$287 ; + assign gpio_s6__core__i = \$285 ; + assign gpio_s5__pad__oe = \$283 ; + assign gpio_s5__pad__o = \$281 ; + assign gpio_s5__core__i = \$279 ; + assign gpio_s4__pad__oe = \$277 ; + assign gpio_s4__pad__o = \$275 ; + assign gpio_s4__core__i = \$273 ; + assign gpio_s3__pad__oe = \$271 ; + assign gpio_s3__pad__o = \$269 ; + assign gpio_s3__core__i = \$267 ; + assign gpio_s2__pad__oe = \$265 ; + assign gpio_s2__pad__o = \$263 ; + assign gpio_s2__core__i = \$261 ; + assign gpio_s1__pad__oe = \$259 ; + assign gpio_s1__pad__o = \$257 ; + assign gpio_s1__core__i = \$255 ; + assign gpio_s0__pad__oe = \$253 ; + assign gpio_s0__pad__o = \$251 ; + assign gpio_s0__core__i = \$249 ; + assign gpio_e15__pad__oe = \$247 ; + assign gpio_e15__pad__o = \$245 ; + assign gpio_e15__core__i = \$243 ; + assign gpio_e14__pad__oe = \$241 ; + assign gpio_e14__pad__o = \$239 ; + assign gpio_e14__core__i = \$237 ; + assign gpio_e13__pad__oe = \$235 ; + assign gpio_e13__pad__o = \$233 ; + assign gpio_e13__core__i = \$231 ; + assign gpio_e12__pad__oe = \$229 ; + assign gpio_e12__pad__o = \$227 ; + assign gpio_e12__core__i = \$225 ; + assign gpio_e11__pad__oe = \$223 ; + assign gpio_e11__pad__o = \$221 ; + assign gpio_e11__core__i = \$219 ; + assign gpio_e10__pad__oe = \$217 ; + assign gpio_e10__pad__o = \$215 ; + assign gpio_e10__core__i = \$213 ; + assign gpio_e9__pad__oe = \$211 ; + assign gpio_e9__pad__o = \$209 ; + assign gpio_e9__core__i = \$207 ; + assign gpio_e8__pad__oe = \$205 ; + assign gpio_e8__pad__o = \$203 ; + assign gpio_e8__core__i = \$201 ; + assign sdr_dq_15__pad__oe = \$199 ; + assign sdr_dq_15__pad__o = \$197 ; + assign sdr_dq_15__core__i = \$195 ; + assign sdr_dq_14__pad__oe = \$193 ; + assign sdr_dq_14__pad__o = \$191 ; + assign sdr_dq_14__core__i = \$189 ; + assign sdr_dq_13__pad__oe = \$187 ; + assign sdr_dq_13__pad__o = \$185 ; + assign sdr_dq_13__core__i = \$183 ; + assign sdr_dq_12__pad__oe = \$181 ; + assign sdr_dq_12__pad__o = \$179 ; + assign sdr_dq_12__core__i = \$177 ; + assign sdr_dq_11__pad__oe = \$175 ; + assign sdr_dq_11__pad__o = \$173 ; + assign sdr_dq_11__core__i = \$171 ; + assign sdr_dq_10__pad__oe = \$169 ; + assign sdr_dq_10__pad__o = \$167 ; + assign sdr_dq_10__core__i = \$165 ; + assign sdr_dq_9__pad__oe = \$163 ; + assign sdr_dq_9__pad__o = \$161 ; + assign sdr_dq_9__core__i = \$159 ; + assign sdr_dq_8__pad__oe = \$157 ; + assign sdr_dq_8__pad__o = \$155 ; + assign sdr_dq_8__core__i = \$153 ; + assign sdr_dm_1__pad__o = \$151 ; + assign sdr_a_12__pad__o = \$149 ; + assign sdr_a_11__pad__o = \$147 ; + assign sdr_a_10__pad__o = \$145 ; + assign sdr_cs_n__pad__o = \$143 ; + assign sdr_we_n__pad__o = \$141 ; + assign sdr_cas_n__pad__o = \$139 ; + assign sdr_ras_n__pad__o = \$137 ; + assign sdr_cke__pad__o = \$135 ; + assign sdr_clock__pad__o = \$133 ; + assign sdr_ba_1__pad__o = \$131 ; + assign sdr_ba_0__pad__o = \$129 ; + assign sdr_a_9__pad__o = \$127 ; + assign sdr_a_8__pad__o = \$125 ; + assign sdr_a_7__pad__o = \$123 ; + assign sdr_a_6__pad__o = \$121 ; + assign sdr_a_5__pad__o = \$119 ; + assign sdr_a_4__pad__o = \$117 ; + assign sdr_a_3__pad__o = \$115 ; + assign sdr_a_2__pad__o = \$113 ; + assign sdr_a_1__pad__o = \$111 ; + assign sdr_a_0__pad__o = \$109 ; + assign sdr_dq_7__pad__oe = \$107 ; + assign sdr_dq_7__pad__o = \$105 ; + assign sdr_dq_7__core__i = \$103 ; + assign sdr_dq_6__pad__oe = \$101 ; + assign sdr_dq_6__pad__o = \$99 ; + assign sdr_dq_6__core__i = \$97 ; + assign sdr_dq_5__pad__oe = \$95 ; + assign sdr_dq_5__pad__o = \$93 ; + assign sdr_dq_5__core__i = \$91 ; + assign sdr_dq_4__pad__oe = \$89 ; + assign sdr_dq_4__pad__o = \$87 ; + assign sdr_dq_4__core__i = \$85 ; + assign sdr_dq_3__pad__oe = \$83 ; + assign sdr_dq_3__pad__o = \$81 ; + assign sdr_dq_3__core__i = \$79 ; + assign sdr_dq_2__pad__oe = \$77 ; + assign sdr_dq_2__pad__o = \$75 ; + assign sdr_dq_2__core__i = \$73 ; + assign sdr_dq_1__pad__oe = \$71 ; + assign sdr_dq_1__pad__o = \$69 ; + assign sdr_dq_1__core__i = \$67 ; + assign sdr_dq_0__pad__oe = \$65 ; + assign sdr_dq_0__pad__o = \$63 ; + assign sdr_dq_0__core__i = \$61 ; + assign sdr_dm_0__pad__o = \$59 ; + assign mspi0_miso__core__i = \$57 ; + assign mspi0_mosi__pad__o = \$55 ; + assign mspi0_cs_n__pad__o = \$53 ; + assign mspi0_clk__pad__o = \$51 ; + assign io_bd2core = \$49 ; + assign io_bd2io = \$47 ; + assign io_update = \$45 ; + assign io_shift = \$31 ; + assign io_capture = \$17 ; + assign idblock_id_bypass = \$9 ; + assign idblock_select_id = \$7 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0" *) +(* generator = "nMigen" *) +module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [44:0] dbus__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input [63:0] dbus__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [63:0] dbus__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [7:0] dbus__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [95:0] ldst_port0_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input ldst_port0_addr_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + output ldst_port0_addr_ok_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + output ldst_port0_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + input [3:0] ldst_port0_data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + input ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + input ldst_port0_is_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] ldst_port0_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output ldst_port0_ld_data_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] ldst_port0_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input ldst_port0_st_data_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [47:0] pimem_ldst_port0_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pimem_ldst_port0_addr_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + wire pimem_ldst_port0_addr_ok_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + wire pimem_ldst_port0_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + wire [3:0] pimem_ldst_port0_data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \pimem_ldst_port0_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + wire pimem_ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + wire pimem_ldst_port0_is_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pimem_ldst_port0_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pimem_ldst_port0_ld_data_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] pimem_ldst_port0_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire pimem_ldst_port0_st_data_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *) + wire [63:0] pimem_m_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *) + wire pimem_m_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" *) + wire [47:0] pimem_x_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" *) + wire pimem_x_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" *) + wire pimem_x_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" *) + wire [7:0] pimem_x_mask_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" *) + wire [63:0] pimem_x_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" *) + wire pimem_x_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *) + wire pimem_x_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + input wb_dcache_en; + \l0$130 l0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .ldst_port0_addr_i(ldst_port0_addr_i), + .\ldst_port0_addr_i$12 (pimem_ldst_port0_addr_i), + .ldst_port0_addr_i_ok(ldst_port0_addr_i_ok), + .\ldst_port0_addr_i_ok$13 (pimem_ldst_port0_addr_i_ok), + .ldst_port0_addr_ok_o(ldst_port0_addr_ok_o), + .\ldst_port0_addr_ok_o$14 (pimem_ldst_port0_addr_ok_o), + .ldst_port0_busy_o(ldst_port0_busy_o), + .\ldst_port0_busy_o$10 (pimem_ldst_port0_busy_o), + .ldst_port0_data_len(ldst_port0_data_len), + .\ldst_port0_data_len$11 (pimem_ldst_port0_data_len), + .\ldst_port0_exc_$signal (\ldst_port0_exc_$signal ), + .\ldst_port0_exc_$signal$1 (\ldst_port0_exc_$signal$1 ), + .\ldst_port0_exc_$signal$19 (\pimem_ldst_port0_exc_$signal ), + .\ldst_port0_exc_$signal$2 (\ldst_port0_exc_$signal$2 ), + .\ldst_port0_exc_$signal$3 (\ldst_port0_exc_$signal$3 ), + .\ldst_port0_exc_$signal$4 (\ldst_port0_exc_$signal$4 ), + .\ldst_port0_exc_$signal$5 (\ldst_port0_exc_$signal$5 ), + .\ldst_port0_exc_$signal$6 (\ldst_port0_exc_$signal$6 ), + .\ldst_port0_exc_$signal$7 (\ldst_port0_exc_$signal$7 ), + .ldst_port0_is_ld_i(ldst_port0_is_ld_i), + .\ldst_port0_is_ld_i$8 (pimem_ldst_port0_is_ld_i), + .ldst_port0_is_st_i(ldst_port0_is_st_i), + .\ldst_port0_is_st_i$9 (pimem_ldst_port0_is_st_i), + .ldst_port0_ld_data_o(ldst_port0_ld_data_o), + .\ldst_port0_ld_data_o$15 (pimem_ldst_port0_ld_data_o), + .ldst_port0_ld_data_o_ok(ldst_port0_ld_data_o_ok), + .\ldst_port0_ld_data_o_ok$16 (pimem_ldst_port0_ld_data_o_ok), + .ldst_port0_st_data_i(ldst_port0_st_data_i), + .\ldst_port0_st_data_i$18 (pimem_ldst_port0_st_data_i), + .ldst_port0_st_data_i_ok(ldst_port0_st_data_i_ok), + .\ldst_port0_st_data_i_ok$17 (pimem_ldst_port0_st_data_i_ok) + ); + lsmem lsmem ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dbus__ack(dbus__ack), + .dbus__adr(dbus__adr), + .dbus__cyc(dbus__cyc), + .dbus__dat_r(dbus__dat_r), + .dbus__dat_w(dbus__dat_w), + .dbus__err(dbus__err), + .dbus__sel(dbus__sel), + .dbus__stb(dbus__stb), + .dbus__we(dbus__we), + .m_ld_data_o(pimem_m_ld_data_o), + .m_valid_i(pimem_m_valid_i), + .wb_dcache_en(wb_dcache_en), + .x_addr_i(pimem_x_addr_i), + .x_busy_o(pimem_x_busy_o), + .x_ld_i(pimem_x_ld_i), + .x_mask_i(pimem_x_mask_i), + .x_st_data_i(pimem_x_st_data_i), + .x_st_i(pimem_x_st_i), + .x_valid_i(pimem_x_valid_i) + ); + pimem pimem ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .ldst_port0_addr_i(pimem_ldst_port0_addr_i), + .ldst_port0_addr_i_ok(pimem_ldst_port0_addr_i_ok), + .ldst_port0_addr_ok_o(pimem_ldst_port0_addr_ok_o), + .ldst_port0_busy_o(pimem_ldst_port0_busy_o), + .ldst_port0_data_len(pimem_ldst_port0_data_len), + .\ldst_port0_exc_$signal (\pimem_ldst_port0_exc_$signal ), + .ldst_port0_is_ld_i(pimem_ldst_port0_is_ld_i), + .ldst_port0_is_st_i(pimem_ldst_port0_is_st_i), + .ldst_port0_ld_data_o(pimem_ldst_port0_ld_data_o), + .ldst_port0_ld_data_o_ok(pimem_ldst_port0_ld_data_o_ok), + .ldst_port0_st_data_i(pimem_ldst_port0_st_data_i), + .ldst_port0_st_data_i_ok(pimem_ldst_port0_st_data_i_ok), + .m_ld_data_o(pimem_m_ld_data_o), + .m_valid_i(pimem_m_valid_i), + .x_addr_i(pimem_x_addr_i), + .x_busy_o(pimem_x_busy_o), + .x_ld_i(pimem_x_ld_i), + .x_mask_i(pimem_x_mask_i), + .x_st_data_i(pimem_x_st_data_i), + .x_st_i(pimem_x_st_i), + .x_valid_i(pimem_x_valid_i) + ); + assign \pimem_ldst_port0_exc_$signal = 1'h0; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.l0" *) +(* generator = "nMigen" *) +module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, \ldst_port0_is_ld_i$8 , \ldst_port0_is_st_i$9 , \ldst_port0_busy_o$10 , \ldst_port0_data_len$11 , \ldst_port0_addr_i$12 , \ldst_port0_addr_i_ok$13 , \ldst_port0_addr_ok_o$14 , \ldst_port0_ld_data_o$15 , \ldst_port0_ld_data_o_ok$16 , \ldst_port0_st_data_i_ok$17 , \ldst_port0_st_data_i$18 , \ldst_port0_exc_$signal$19 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *) + wire [95:0] \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *) + wire [95:0] \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg \idx_l$23 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg \idx_l$23$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire idx_l_q_idx_l; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg idx_l_r_idx_l; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg idx_l_s_idx_l; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [95:0] ldst_port0_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [47:0] \ldst_port0_addr_i$12 ; + reg [47:0] \ldst_port0_addr_i$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input ldst_port0_addr_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \ldst_port0_addr_i_ok$13 ; + reg \ldst_port0_addr_i_ok$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + output ldst_port0_addr_ok_o; + reg ldst_port0_addr_ok_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + input \ldst_port0_addr_ok_o$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + output ldst_port0_busy_o; + reg ldst_port0_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + input \ldst_port0_busy_o$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" *) + reg ldst_port0_cache_paradox; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" *) + wire \ldst_port0_cache_paradox$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + input [3:0] ldst_port0_data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + output [3:0] \ldst_port0_data_len$11 ; + reg [3:0] \ldst_port0_data_len$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal ; + reg \ldst_port0_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$1 ; + reg \ldst_port0_exc_$signal$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$2 ; + reg \ldst_port0_exc_$signal$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$3 ; + reg \ldst_port0_exc_$signal$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \ldst_port0_exc_$signal$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \ldst_port0_exc_$signal$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \ldst_port0_exc_$signal$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \ldst_port0_exc_$signal$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \ldst_port0_exc_$signal$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \ldst_port0_exc_$signal$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \ldst_port0_exc_$signal$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$4 ; + reg \ldst_port0_exc_$signal$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$5 ; + reg \ldst_port0_exc_$signal$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$6 ; + reg \ldst_port0_exc_$signal$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + output \ldst_port0_exc_$signal$7 ; + reg \ldst_port0_exc_$signal$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) + reg ldst_port0_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) + wire \ldst_port0_go_die_i$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + input ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + output \ldst_port0_is_ld_i$8 ; + reg \ldst_port0_is_ld_i$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + input ldst_port0_is_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + output \ldst_port0_is_st_i$9 ; + reg \ldst_port0_is_st_i$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] ldst_port0_ld_data_o; + reg [63:0] ldst_port0_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] \ldst_port0_ld_data_o$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output ldst_port0_ld_data_o_ok; + reg ldst_port0_ld_data_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input \ldst_port0_ld_data_o_ok$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *) + reg ldst_port0_ldst_error; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *) + wire \ldst_port0_ldst_error$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *) + reg ldst_port0_mmu_done; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *) + wire \ldst_port0_mmu_done$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] ldst_port0_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \ldst_port0_st_data_i$18 ; + reg [63:0] \ldst_port0_st_data_i$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input ldst_port0_st_data_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \ldst_port0_st_data_i_ok$17 ; + reg \ldst_port0_st_data_i_ok$17 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" *) + wire pick_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" *) + wire pick_n; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" *) + wire pick_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" *) + reg reset_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" *) + wire \reset_delay$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire reset_l_q_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg reset_l_r_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg reset_l_s_reset; + assign \$20 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" *) ldst_port0_is_st_i; + assign \$24 = idx_l_q_idx_l ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) pick_o : \idx_l$23 ; + assign \$26 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *) pick_n; + assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *) \ldst_port0_busy_o$10 ; + always @(posedge coresync_clk) + reset_delay <= reset_l_q_reset; + always @(posedge coresync_clk) + \idx_l$23 <= \idx_l$23$next ; + idx_l idx_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_idx_l(idx_l_q_idx_l), + .r_idx_l(idx_l_r_idx_l), + .s_idx_l(idx_l_s_idx_l) + ); + pick pick ( + .i(pick_i), + .n(pick_n), + .o(pick_o) + ); + \reset_l$131 reset_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_reset(reset_l_q_reset), + .r_reset(reset_l_r_reset), + .s_reset(reset_l_s_reset) + ); + always @* begin + if (\initial ) begin end + \ldst_port0_addr_i$12 = 48'h000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + \ldst_port0_addr_i$12 = \$32 [47:0]; + endcase + end + always @* begin + if (\initial ) begin end + \ldst_port0_addr_i_ok$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + \ldst_port0_addr_i_ok$13 = ldst_port0_addr_i_ok; + endcase + end + always @* begin + if (\initial ) begin end + \ldst_port0_st_data_i$18 = 64'h0000000000000000; + \ldst_port0_st_data_i_ok$17 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + { \ldst_port0_st_data_i_ok$17 , \ldst_port0_st_data_i$18 } = { ldst_port0_st_data_i_ok, ldst_port0_st_data_i }; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_ld_data_o = 64'h0000000000000000; + ldst_port0_ld_data_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + { ldst_port0_ld_data_o_ok, ldst_port0_ld_data_o } = { \ldst_port0_ld_data_o_ok$16 , \ldst_port0_ld_data_o$15 }; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_busy_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + ldst_port0_busy_o = \ldst_port0_busy_o$10 ; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_addr_ok_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + ldst_port0_addr_ok_o = \ldst_port0_addr_ok_o$14 ; + endcase + end + always @* begin + if (\initial ) begin end + \ldst_port0_exc_$signal = 1'h0; + \ldst_port0_exc_$signal$1 = 1'h0; + \ldst_port0_exc_$signal$2 = 1'h0; + \ldst_port0_exc_$signal$3 = 1'h0; + \ldst_port0_exc_$signal$4 = 1'h0; + \ldst_port0_exc_$signal$5 = 1'h0; + \ldst_port0_exc_$signal$6 = 1'h0; + \ldst_port0_exc_$signal$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal } = { \ldst_port0_exc_$signal$39 , \ldst_port0_exc_$signal$38 , \ldst_port0_exc_$signal$37 , \ldst_port0_exc_$signal$36 , \ldst_port0_exc_$signal$35 , \ldst_port0_exc_$signal$34 , \ldst_port0_exc_$signal$33 , \ldst_port0_exc_$signal$19 }; + endcase + end + always @* begin + if (\initial ) begin end + \idx_l$23$next = \idx_l$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \idx_l$23$next = pick_o; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \idx_l$23$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_mmu_done = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + ldst_port0_mmu_done = \ldst_port0_mmu_done$40 ; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_ldst_error = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + ldst_port0_ldst_error = \ldst_port0_ldst_error$41 ; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_cache_paradox = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + ldst_port0_cache_paradox = \ldst_port0_cache_paradox$42 ; + endcase + end + always @* begin + if (\initial ) begin end + idx_l_s_idx_l = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *) + casez (\$26 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" */ + 1'h1: + idx_l_s_idx_l = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + idx_l_r_idx_l = 1'h1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" *) + casez (reset_l_q_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" */ + 1'h1: + idx_l_r_idx_l = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + reset_l_s_reset = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *) + casez (\$28 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" */ + 1'h1: + reset_l_s_reset = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + reset_l_r_reset = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" *) + casez (reset_l_q_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" */ + 1'h1: + reset_l_r_reset = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \ldst_port0_is_ld_i$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + \ldst_port0_is_ld_i$8 = ldst_port0_is_ld_i; + endcase + end + always @* begin + if (\initial ) begin end + \ldst_port0_is_st_i$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + \ldst_port0_is_st_i$9 = ldst_port0_is_st_i; + endcase + end + always @* begin + if (\initial ) begin end + \ldst_port0_data_len$11 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + \ldst_port0_data_len$11 = ldst_port0_data_len; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_go_die_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + ldst_port0_go_die_i = \ldst_port0_go_die_i$30 ; + endcase + end + assign \$22 = \$24 ; + assign \$32 = ldst_port0_addr_i; + assign \ldst_port0_go_die_i$30 = 1'h0; + assign \ldst_port0_exc_$signal$33 = 1'h0; + assign \ldst_port0_exc_$signal$34 = 1'h0; + assign \ldst_port0_exc_$signal$35 = 1'h0; + assign \ldst_port0_exc_$signal$36 = 1'h0; + assign \ldst_port0_exc_$signal$37 = 1'h0; + assign \ldst_port0_exc_$signal$38 = 1'h0; + assign \ldst_port0_exc_$signal$39 = 1'h0; + assign \ldst_port0_mmu_done$40 = 1'h0; + assign \ldst_port0_ldst_error$41 = 1'h0; + assign \ldst_port0_cache_paradox$42 = 1'h0; + assign \reset_delay$next = reset_l_q_reset; + assign pick_i = \$20 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.ld_active" *) +(* generator = "nMigen" *) +module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_ld_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_ld_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_ld_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_ld_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_ld_active; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_ld_active; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_ld_active; + assign \$15 = q_ld_active | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_ld_active; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_ld_active; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_ld_active; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_ld_active = \$15 ; + assign qn_ld_active = \$13 ; + assign q_ld_active = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0" *) +(* generator = "nMigen" *) +module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, cu_wr__rel_o, cu_wr__go_i, o, ea, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) + wire \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) + wire \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) + wire \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) + wire \$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) + wire \$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) + wire \$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" *) + wire \$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + wire \$114 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + wire \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + wire \$118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + wire \$120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + wire \$122 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) + wire \$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + wire \$126 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) + wire \$128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) + wire \$130 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) + wire \$132 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) + wire \$134 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) + wire \$136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) + wire \$138 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + wire \$140 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + wire \$142 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + wire \$144 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + wire \$145 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + wire \$147 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + wire \$150 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) + wire \$152 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) + wire \$154 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) + wire \$156 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) + wire \$158 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) + wire \$160 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + wire \$162 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *) + wire \$164 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *) + wire [2:0] \$166 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + wire \$167 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *) + wire [2:0] \$169 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" *) + wire \$171 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" *) + wire \$173 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *) + wire [95:0] \$175 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" *) + wire \$177 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" *) + wire [2:0] \$18 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) + wire [63:0] \$186 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) + wire [63:0] \$188 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) + wire [63:0] \$190 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) + wire \$192 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) + wire [63:0] \$194 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) + wire [63:0] \$196 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) + wire [63:0] \$198 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *) + wire [1:0] \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *) + wire [1:0] \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$65 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) + wire [63:0] \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" *) + wire [63:0] \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *) + wire [64:0] \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *) + wire [64:0] \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + wire [2:0] \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + wire [1:0] \$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + wire [2:0] \$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + wire [2:0] \$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + wire [2:0] \$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) + wire \$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) + wire \$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" *) + wire \$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) + wire \$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) + wire \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) + wire \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" *) + wire addr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *) + wire [63:0] addr_r; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire adr_l_q_adr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg adr_l_r_adr = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \adr_l_r_adr$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire adr_l_s_adr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + wire alu_l_r_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" *) + wire [63:0] alu_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" *) + reg alu_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" *) + wire \alu_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" *) + wire alu_valid; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input cu_ad__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output cu_ad__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input cu_st__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output cu_st__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [1:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [1:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [1:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + reg [63:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] ea; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] ea_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \ea_r$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \exc_$signal$179 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \exc_$signal$180 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \exc_$signal$181 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \exc_$signal$182 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \exc_$signal$183 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \exc_$signal$184 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \exc_$signal$185 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" *) + wire ld_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" *) + wire ld_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" *) + reg [63:0] ldd_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" *) + wire [63:0] ldd_r; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" *) + reg [63:0] lddata_r; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] ldo_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \ldo_r$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [95:0] ldst_port0_addr_i; + reg [95:0] ldst_port0_addr_i = 96'h000000000000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [95:0] \ldst_port0_addr_i$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output ldst_port0_addr_i_ok; + reg ldst_port0_addr_i_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \ldst_port0_addr_i_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + input ldst_port0_addr_ok_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + input ldst_port0_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + output [3:0] ldst_port0_data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + output ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + output ldst_port0_is_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] ldst_port0_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input ldst_port0_ld_data_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] ldst_port0_st_data_i; + reg [63:0] ldst_port0_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output ldst_port0_st_data_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" *) + wire load_mem_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire lod_l_qn_lod; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + wire lod_l_r_lod; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire lod_l_s_lod; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire lsd_l_q_lsd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg lsd_l_r_lsd = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \lsd_l_r_lsd$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire lsd_l_s_lsd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" *) + wire op_is_ld; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" *) + wire op_is_st; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__byte_reverse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] oper_i_ldst_ldst0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_ldst_ldst0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_ldst_ldst0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_ldst_ldst0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_ldst_ldst0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__is_signed; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_ldst_ldst0__ldst_mode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__sign_extend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_ldst_ldst0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__byte_reverse = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__byte_reverse$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] oper_r__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \oper_r__data_len$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] oper_r__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \oper_r__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] oper_r__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \oper_r__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__imm_data__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] oper_r__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \oper_r__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] oper_r__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \oper_r__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__is_signed$next ; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] oper_r__ldst_mode = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \oper_r__ldst_mode$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__sign_extend = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__sign_extend$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg oper_r__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \oper_r__zero_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *) + reg p_st_go = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *) + wire \p_st_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" *) + wire rd_done; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" *) + wire rda_any; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" *) + wire reset_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" *) + wire reset_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" *) + wire reset_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" *) + wire [2:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" *) + wire reset_s; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" *) + wire reset_u; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" *) + wire reset_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" *) + reg [63:0] revnorev; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rst_l_q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + wire rst_l_r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire rst_l_s_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" *) + wire [63:0] src1_or_z; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" *) + wire [63:0] src2_or_imm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src3_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [2:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] src_l_r_src = 3'h7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] src_l_s_src = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + reg [63:0] src_r2 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + reg [63:0] \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" *) + wire st_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" *) + reg [63:0] stdata_r; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire sto_l_q_sto; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg sto_l_r_sto = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \sto_l_r_sto$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire sto_l_s_sto; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:115" *) + wire stwd_mem_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire upd_l_q_upd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg upd_l_r_upd = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \upd_l_r_upd$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg upd_l_s_upd = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \upd_l_s_upd$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" *) + wire wr_any; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" *) + wire wr_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire wri_l_q_wri; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg wri_l_r_wri = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \wri_l_r_wri$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire wri_l_s_wri; + assign \$100 = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$98 ; + assign \$102 = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) adr_l_q_adr; + assign \$104 = \$102 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) cu_busy_o; + assign \$106 = sto_l_q_sto & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) cu_busy_o; + assign \$108 = \$106 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) rd_done; + assign \$10 = cu_done_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" *) cu_go_die_i; + assign \$110 = \$108 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) op_is_st; + assign \$112 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" *) cu_shadown_i; + assign \$114 = rd_done & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) wri_l_q_wri; + assign \$116 = \$114 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) cu_busy_o; + assign \$118 = \$116 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) lod_l_qn_lod; + assign \$120 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) op_is_ld; + assign \$122 = \$120 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) cu_shadown_i; + assign \$124 = upd_l_q_upd & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) cu_busy_o; + assign \$126 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; + assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) \$126 ; + assign \$12 = cu_wr__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" *) cu_go_die_i; + assign \$130 = \$128 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) alu_valid; + assign \$132 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) cu_shadown_i; + assign \$134 = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) p_st_go; + assign \$136 = \$134 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) cu_wr__go_i[0]; + assign \$138 = \$136 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) cu_wr__go_i[1]; + assign \$140 = rst_l_q_rst & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_busy_o; + assign \$142 = \$140 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_shadown_i; + assign \$145 = cu_st__rel_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_wr__rel_o[0]; + assign \$147 = \$145 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_wr__rel_o[1]; + assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) \$147 ; + assign \$14 = cu_wr__go_i[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" *) cu_go_die_i; + assign \$150 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) \$144 ; + assign \$152 = lod_l_qn_lod | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) op_is_st; + assign \$154 = \$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) \$152 ; + assign \$156 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) ldst_port0_busy_o; + assign \$158 = \$156 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) op_is_ld; + assign \$160 = wr_reset & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) \$158 ; + assign \$162 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; + assign \$164 = \$162 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *) cu_wr__go_i[1]; + assign \$167 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; + assign \$16 = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" *) cu_go_die_i; + assign \$169 = { cu_busy_o, cu_busy_o, cu_busy_o } & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *) { \$167 , op_is_ld }; + assign \$171 = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" *) cu_busy_o; + assign \$173 = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" *) cu_busy_o; + assign \$175 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *) addr_r; + assign \$177 = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" *) lsd_l_q_lsd; + assign \$186 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) ldst_port0_ld_data_o[7:0]; + assign \$188 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8] }; + assign \$18 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$190 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24] }; + assign \$192 = oper_r__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) 2'h2; + assign \$194 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) src_r2[7:0]; + assign \$196 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8] }; + assign \$198 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24] }; + assign \$20 = cu_ad__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) cu_go_die_i; + assign \$22 = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" *) 7'h26; + assign \$24 = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" *) 7'h25; + assign \$26 = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" *) cu_ad__go_i; + assign \$28 = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" *) cu_st__go_i; + assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) alu_valid; + assign \$32 = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) \$30 ; + assign \$34 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) rda_any; + assign \$36 = \$32 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) \$34 ; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) ldst_port0_busy_o; + assign \$41 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; + assign \$43 = \$39 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$41 ; + assign \$45 = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$43 ; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) ldst_port0_busy_o; + assign \$49 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; + assign \$51 = \$47 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$49 ; + assign \$53 = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$51 ; + assign \$55 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *) { \$45 , \$53 }; + assign \$57 = addr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" *) op_is_st; + assign \$59 = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" *) p_st_go; + assign \$61 = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) p_st_go; + assign \$63 = \$61 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) ld_ok; + assign \$65 = ld_ok ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) ldd_o : ldo_r; + assign \$67 = alu_l_q_alu ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) alu_o : ea_r; + assign \$69 = oper_r__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) 64'h0000000000000000 : src_r0; + assign \$71 = oper_r__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" *) oper_r__imm_data__data : src_r1; + assign \$74 = src1_or_z + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *) src2_or_imm; + assign \$76 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) { oper_r__imm_data__ok, oper_r__zero_a }; + assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) \$78 ; + assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) cu_rdmaskn_i; + assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) \$82 ; + assign \$86 = src_l_q_src[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) cu_busy_o; + assign \$88 = \$86 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) op_is_st; + assign \$8 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" *) cu_go_die_i; + assign \$90 = cu_rd__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" *) cu_rd__go_i[1]; + assign \$93 = cu_rd__rel_o[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) cu_rd__rel_o[1]; + assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$93 ; + assign \$96 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$92 ; + assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) cu_rd__rel_o[2]; + always @(posedge coresync_clk) + ldst_port0_addr_i_ok <= \ldst_port0_addr_i_ok$next ; + always @(posedge coresync_clk) + ldst_port0_addr_i <= \$175 ; + always @(posedge coresync_clk) + alu_ok <= \$96 ; + always @(posedge coresync_clk) + ea_r <= \ea_r$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + ldo_r <= \ldo_r$next ; + always @(posedge coresync_clk) + oper_r__insn_type <= \oper_r__insn_type$next ; + always @(posedge coresync_clk) + oper_r__fn_unit <= \oper_r__fn_unit$next ; + always @(posedge coresync_clk) + oper_r__imm_data__data <= \oper_r__imm_data__data$next ; + always @(posedge coresync_clk) + oper_r__imm_data__ok <= \oper_r__imm_data__ok$next ; + always @(posedge coresync_clk) + oper_r__zero_a <= \oper_r__zero_a$next ; + always @(posedge coresync_clk) + oper_r__rc__rc <= \oper_r__rc__rc$next ; + always @(posedge coresync_clk) + oper_r__rc__ok <= \oper_r__rc__ok$next ; + always @(posedge coresync_clk) + oper_r__oe__oe <= \oper_r__oe__oe$next ; + always @(posedge coresync_clk) + oper_r__oe__ok <= \oper_r__oe__ok$next ; + always @(posedge coresync_clk) + oper_r__is_32bit <= \oper_r__is_32bit$next ; + always @(posedge coresync_clk) + oper_r__is_signed <= \oper_r__is_signed$next ; + always @(posedge coresync_clk) + oper_r__data_len <= \oper_r__data_len$next ; + always @(posedge coresync_clk) + oper_r__byte_reverse <= \oper_r__byte_reverse$next ; + always @(posedge coresync_clk) + oper_r__sign_extend <= \oper_r__sign_extend$next ; + always @(posedge coresync_clk) + oper_r__ldst_mode <= \oper_r__ldst_mode$next ; + always @(posedge coresync_clk) + oper_r__insn <= \oper_r__insn$next ; + always @(posedge coresync_clk) + lsd_l_r_lsd <= \lsd_l_r_lsd$next ; + always @(posedge coresync_clk) + sto_l_r_sto <= \sto_l_r_sto$next ; + always @(posedge coresync_clk) + upd_l_r_upd <= \upd_l_r_upd$next ; + always @(posedge coresync_clk) + upd_l_s_upd <= \upd_l_s_upd$next ; + always @(posedge coresync_clk) + wri_l_r_wri <= \wri_l_r_wri$next ; + always @(posedge coresync_clk) + adr_l_r_adr <= \adr_l_r_adr$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + p_st_go <= cu_st__go_i; + adr_l adr_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_adr(adr_l_q_adr), + .r_adr(adr_l_r_adr), + .s_adr(adr_l_s_adr) + ); + \alu_l$128 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + lod_l lod_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .qn_lod(lod_l_qn_lod), + .r_lod(lod_l_r_lod), + .s_lod(lod_l_s_lod) + ); + lsd_l lsd_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_lsd(lsd_l_q_lsd), + .r_lsd(lsd_l_r_lsd), + .s_lsd(lsd_l_s_lsd) + ); + \opc_l$126 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \rst_l$129 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rst(rst_l_q_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$127 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + sto_l sto_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_sto(sto_l_q_sto), + .r_sto(sto_l_r_sto), + .s_sto(sto_l_s_sto) + ); + upd_l upd_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_upd(upd_l_q_upd), + .r_upd(upd_l_r_upd), + .s_upd(upd_l_s_upd) + ); + wri_l wri_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_wri(wri_l_q_wri), + .r_wri(wri_l_r_wri), + .s_wri(wri_l_s_wri) + ); + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = reset_o; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \adr_l_r_adr$next = reset_a; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \adr_l_r_adr$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \wri_l_r_wri$next = \$38 [0]; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \wri_l_r_wri$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \upd_l_s_upd$next = reset_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \upd_l_s_upd$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \upd_l_r_upd$next = reset_u; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \upd_l_r_upd$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \sto_l_r_sto$next = \$59 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \sto_l_r_sto$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \lsd_l_r_lsd$next = \$63 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \lsd_l_r_lsd$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \oper_r__insn_type$next = oper_r__insn_type; + \oper_r__fn_unit$next = oper_r__fn_unit; + \oper_r__imm_data__data$next = oper_r__imm_data__data; + \oper_r__imm_data__ok$next = oper_r__imm_data__ok; + \oper_r__zero_a$next = oper_r__zero_a; + \oper_r__rc__rc$next = oper_r__rc__rc; + \oper_r__rc__ok$next = oper_r__rc__ok; + \oper_r__oe__oe$next = oper_r__oe__oe; + \oper_r__oe__ok$next = oper_r__oe__ok; + \oper_r__is_32bit$next = oper_r__is_32bit; + \oper_r__is_signed$next = oper_r__is_signed; + \oper_r__data_len$next = oper_r__data_len; + \oper_r__byte_reverse$next = oper_r__byte_reverse; + \oper_r__sign_extend$next = oper_r__sign_extend; + \oper_r__ldst_mode$next = oper_r__ldst_mode; + \oper_r__insn$next = oper_r__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" */ + 1'h1: + { \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = { oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__insn_type }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" *) + casez (cu_done_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" */ + 1'h1: + { \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = 133'h0000000000000000000000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \oper_r__imm_data__data$next = 64'h0000000000000000; + \oper_r__imm_data__ok$next = 1'h0; + \oper_r__rc__rc$next = 1'h0; + \oper_r__rc__ok$next = 1'h0; + \oper_r__oe__oe$next = 1'h0; + \oper_r__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \ldo_r$next = ldo_r; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (ld_ok) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \ldo_r$next = ldd_o; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *) + casez (cu_rd__go_i[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" */ + 1'h1: + \src_r0$next = src1_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" */ + 1'h1: + \src_r0$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *) + casez (cu_rd__go_i[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" */ + 1'h1: + \src_r1$next = src2_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" */ + 1'h1: + \src_r1$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *) + casez (cu_rd__go_i[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" */ + 1'h1: + \src_r2$next = src3_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" */ + 1'h1: + \src_r2$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \ea_r$next = ea_r; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (alu_l_q_alu) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \ea_r$next = alu_o; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) + casez (cu_wr__go_i[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" */ + 1'h1: + dest1_o = ldd_r; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *) + casez (\$164 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" */ + 1'h1: + dest2_o = addr_r; + endcase + end + always @* begin + if (\initial ) begin end + \ldst_port0_addr_i_ok$next = \$177 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ldst_port0_addr_i_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + lddata_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) + casez (oper_r__byte_reverse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" *) + casez (oper_r__data_len) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h1: + lddata_r = \$186 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h2: + lddata_r = \$188 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h4: + lddata_r = \$190 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h8: + lddata_r = { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24], ldst_port0_ld_data_o[39:32], ldst_port0_ld_data_o[47:40], ldst_port0_ld_data_o[55:48], ldst_port0_ld_data_o[63:56] }; + endcase + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) + casez (oper_r__byte_reverse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" */ + 1'h1: + revnorev = lddata_r; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:505" */ + default: + revnorev = ldst_port0_ld_data_o; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" *) + casez (oper_r__sign_extend) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) + casez (\$192 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" */ + 1'h1: + ldd_o = { revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15:0] }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:513" */ + default: + ldd_o = { revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31:0] }; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:515" */ + default: + ldd_o = revnorev; + endcase + end + always @* begin + if (\initial ) begin end + stdata_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) + casez (oper_r__byte_reverse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" *) + casez (oper_r__data_len) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h1: + stdata_r = \$194 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h2: + stdata_r = \$196 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h4: + stdata_r = \$198 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h8: + stdata_r = { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24], src_r2[39:32], src_r2[47:40], src_r2[55:48], src_r2[63:56] }; + endcase + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) + casez (oper_r__byte_reverse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" */ + 1'h1: + ldst_port0_st_data_i = stdata_r; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:528" */ + default: + ldst_port0_st_data_i = src_r2; + endcase + end + assign \$38 = \$55 ; + assign \$73 = \$74 ; + assign \$166 = \$169 ; + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign ldst_port0_st_data_i_ok = cu_st__go_i; + assign ld_ok = ldst_port0_ld_data_o_ok; + assign addr_ok = ldst_port0_addr_ok_o; + assign { \exc_$signal$185 , \exc_$signal$184 , \exc_$signal$183 , \exc_$signal$182 , \exc_$signal$181 , \exc_$signal$180 , \exc_$signal$179 , \exc_$signal } = { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal }; + assign \ldst_port0_addr_i$next = \$175 ; + assign ldst_port0_data_len = oper_r__data_len; + assign ldst_port0_is_st_i = \$173 ; + assign ldst_port0_is_ld_i = \$171 ; + assign cu_wrmask_o = \$169 [1:0]; + assign ea = dest2_o; + assign o = dest1_o; + assign cu_done_o = \$160 ; + assign wr_reset = \$154 ; + assign wr_any = \$138 ; + assign cu_wr__rel_o[1] = \$132 ; + assign cu_wr__rel_o[0] = \$122 ; + assign cu_st__rel_o = \$112 ; + assign cu_ad__rel_o = \$104 ; + assign rd_done = \$100 ; + assign alu_valid = \$96 ; + assign rda_any = \$90 ; + assign cu_rd__rel_o[2] = \$88 ; + assign cu_rd__rel_o[1:0] = \$84 [1:0]; + assign cu_busy_o = opc_l_q_opc; + assign \alu_ok$next = alu_valid; + assign alu_o = \$74 [63:0]; + assign src2_or_imm = \$71 ; + assign src1_or_z = \$69 ; + assign addr_r = \$67 ; + assign ldd_r = \$65 ; + assign rst_l_r_rst = cu_issue_i; + assign rst_l_s_rst = addr_ok; + assign lsd_l_s_lsd = cu_issue_i; + assign sto_l_s_sto = \$57 ; + assign wri_l_s_wri = cu_issue_i; + assign lod_l_r_lod = ld_ok; + assign lod_l_s_lod = reset_i; + assign adr_l_s_adr = reset_i; + assign alu_l_r_alu = \$36 ; + assign alu_l_s_alu = reset_i; + assign st_o = op_is_st; + assign ld_o = op_is_ld; + assign stwd_mem_o = \$28 ; + assign load_mem_o = \$26 ; + assign op_is_ld = \$24 ; + assign op_is_st = \$22 ; + assign \p_st_go$next = cu_st__go_i; + assign reset_a = \$20 ; + assign reset_r = \$18 ; + assign reset_s = \$16 ; + assign reset_u = \$14 ; + assign reset_w = \$12 ; + assign reset_o = \$10 ; + assign reset_i = \$8 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" *) +(* generator = "nMigen" *) +module left_mask(mask, shift); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$117 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$119 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$125 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$127 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" *) + output [63:0] mask; + reg [63:0] mask; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" *) + input [6:0] shift; + assign \$9 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h4; + assign \$99 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h31; + assign \$101 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h32; + assign \$103 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h33; + assign \$105 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h34; + assign \$107 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h35; + assign \$109 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h36; + assign \$111 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h37; + assign \$113 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h38; + assign \$115 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h39; + assign \$117 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3a; + assign \$11 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h5; + assign \$119 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3b; + assign \$121 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3c; + assign \$123 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3d; + assign \$125 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3e; + assign \$127 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3f; + assign \$13 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h6; + assign \$15 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h7; + assign \$17 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'h8; + assign \$1 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 1'h0; + assign \$19 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'h9; + assign \$21 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'ha; + assign \$23 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hb; + assign \$25 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hc; + assign \$27 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hd; + assign \$29 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'he; + assign \$31 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hf; + assign \$33 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h10; + assign \$35 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h11; + assign \$37 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h12; + assign \$3 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 1'h1; + assign \$39 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h13; + assign \$41 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h14; + assign \$43 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h15; + assign \$45 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h16; + assign \$47 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h17; + assign \$49 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h18; + assign \$51 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h19; + assign \$53 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1a; + assign \$55 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1b; + assign \$57 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1c; + assign \$5 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 2'h2; + assign \$59 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1d; + assign \$61 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1e; + assign \$63 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1f; + assign \$65 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h20; + assign \$67 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h21; + assign \$69 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h22; + assign \$71 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h23; + assign \$73 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h24; + assign \$75 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h25; + assign \$77 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h26; + assign \$7 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 2'h3; + assign \$79 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h27; + assign \$81 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h28; + assign \$83 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h29; + assign \$85 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2a; + assign \$87 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2b; + assign \$89 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2c; + assign \$91 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2d; + assign \$93 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2e; + assign \$95 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2f; + assign \$97 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h30; + always @* begin + if (\initial ) begin end + mask = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[0] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[1] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$5 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[2] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$7 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[3] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[4] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$11 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[5] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[6] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[7] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$17 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[8] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[9] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$21 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[10] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$23 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[11] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[12] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[13] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[14] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[15] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$33 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[16] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$35 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[17] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$37 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[18] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$39 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[19] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$41 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[20] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$43 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[21] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$45 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[22] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$47 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[23] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$49 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[24] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$51 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[25] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$53 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[26] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$55 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[27] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$57 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[28] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$59 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[29] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$61 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[30] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$63 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[31] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$65 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[32] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$67 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[33] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$69 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[34] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$71 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[35] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$73 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[36] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$75 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[37] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$77 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[38] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$79 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[39] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$81 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[40] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$83 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[41] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$85 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[42] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$87 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[43] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$89 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[44] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$91 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[45] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$93 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[46] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$95 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[47] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$97 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[48] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$99 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[49] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$101 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[50] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$103 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[51] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$105 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[52] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$107 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[53] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$109 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[54] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$111 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[55] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$113 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[56] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$115 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[57] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$117 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[58] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$119 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[59] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$121 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[60] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$123 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[61] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$125 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[62] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$127 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[63] = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.lenexp" *) +(* generator = "nMigen" *) +module lenexp(addr_i, lexp_o, rexp_o, len_i); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) + wire [20:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) + wire [19:0] \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) + wire [20:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *) + wire [63:0] \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *) + wire [31:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" *) + input [3:0] addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" *) + wire [16:0] binlen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" *) + input [3:0] len_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" *) + output [63:0] lexp_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" *) + output [175:0] rexp_o; + assign \$2 = 5'h01 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) len_i; + assign \$4 = \$2 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) 1'h1; + assign \$7 = binlen <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *) addr_i; + assign \$6 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *) \$7 ; + assign \$1 = \$4 ; + assign rexp_o = { lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21:20], lexp_o[20], lexp_o[20], lexp_o[20], lexp_o[20], lexp_o[20], lexp_o[20], lexp_o[20:19], lexp_o[19], lexp_o[19], lexp_o[19], lexp_o[19], lexp_o[19], lexp_o[19], lexp_o[19:18], lexp_o[18], lexp_o[18], lexp_o[18], lexp_o[18], lexp_o[18], lexp_o[18], lexp_o[18:17], lexp_o[17], lexp_o[17], lexp_o[17], lexp_o[17], lexp_o[17], lexp_o[17], lexp_o[17:16], lexp_o[16], lexp_o[16], lexp_o[16], lexp_o[16], lexp_o[16], lexp_o[16], lexp_o[16:15], lexp_o[15], lexp_o[15], lexp_o[15], lexp_o[15], lexp_o[15], lexp_o[15], lexp_o[15:14], lexp_o[14], lexp_o[14], lexp_o[14], lexp_o[14], lexp_o[14], lexp_o[14], lexp_o[14:13], lexp_o[13], lexp_o[13], lexp_o[13], lexp_o[13], lexp_o[13], lexp_o[13], lexp_o[13:12], lexp_o[12], lexp_o[12], lexp_o[12], lexp_o[12], lexp_o[12], lexp_o[12], lexp_o[12:11], lexp_o[11], lexp_o[11], lexp_o[11], lexp_o[11], lexp_o[11], lexp_o[11], lexp_o[11:10], lexp_o[10], lexp_o[10], lexp_o[10], lexp_o[10], lexp_o[10], lexp_o[10], lexp_o[10:9], lexp_o[9], lexp_o[9], lexp_o[9], lexp_o[9], lexp_o[9], lexp_o[9], lexp_o[9:8], lexp_o[8], lexp_o[8], lexp_o[8], lexp_o[8], lexp_o[8], lexp_o[8], lexp_o[8:7], lexp_o[7], lexp_o[7], lexp_o[7], lexp_o[7], lexp_o[7], lexp_o[7], lexp_o[7:6], lexp_o[6], lexp_o[6], lexp_o[6], lexp_o[6], lexp_o[6], lexp_o[6], lexp_o[6:5], lexp_o[5], lexp_o[5], lexp_o[5], lexp_o[5], lexp_o[5], lexp_o[5], lexp_o[5:4], lexp_o[4], lexp_o[4], lexp_o[4], lexp_o[4], lexp_o[4], lexp_o[4], lexp_o[4:3], lexp_o[3], lexp_o[3], lexp_o[3], lexp_o[3], lexp_o[3], lexp_o[3], lexp_o[3:2], lexp_o[2], lexp_o[2], lexp_o[2], lexp_o[2], lexp_o[2], lexp_o[2], lexp_o[2:1], lexp_o[1], lexp_o[1], lexp_o[1], lexp_o[1], lexp_o[1], lexp_o[1], lexp_o[1:0], lexp_o[0], lexp_o[0], lexp_o[0], lexp_o[0], lexp_o[0], lexp_o[0], lexp_o[0] }; + assign lexp_o = \$6 ; + assign binlen = \$4 [16:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.lod_l" *) +(* generator = "nMigen" *) +module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_lod; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_lod; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + output qn_lod; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_lod; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_lod; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_lod; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_lod; + assign \$15 = q_lod | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_lod; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_lod; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_lod; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_lod = \$15 ; + assign qn_lod = \$13 ; + assign q_lod = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0" *) +(* generator = "nMigen" *) +module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [1:0] \$109 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [1:0] \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [1:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [1:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [1:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [2:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [1:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [1:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [2:0] \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [2:0] \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [1:0] \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [1:0] \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$83 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$85 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] alu_logical0_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] alu_logical0_logical_op__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \alu_logical0_logical_op__data_len$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_logical0_logical_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_logical0_logical_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_logical0_logical_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_logical0_logical_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__imm_data__ok$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] alu_logical0_logical_op__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \alu_logical0_logical_op__input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_logical0_logical_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_logical0_logical_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_logical0_logical_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_logical0_logical_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__invert_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__invert_out$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__output_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_logical0_logical_op__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_logical0_logical_op__zero_a$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_logical0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_logical0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_logical0_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_logical0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_logical0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_logical0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_logical0_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire alu_logical0_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [1:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [1:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [1:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [1:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] data_r1__cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] \data_r1__cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] dest2_o; + reg [3:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] oper_i_alu_logical0__data_len; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_logical0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_logical0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_alu_logical0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_logical0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_logical0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_logical0__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [1:0] prev_wr_go = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [1:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [1:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [1:0] req_l_r_req = 2'h3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [1:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [1:0] req_l_s_req = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [1:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [2:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [1:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input src3_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [2:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] src_l_r_src = 3'h7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] src_l_s_src = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] src_or_imm; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] \src_or_imm$80 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg src_r2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire src_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire \src_sel$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + assign \$9 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$3 ; + assign \$99 = \$93 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 1'h1, \$97 , \$95 }; + assign \$101 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + assign \$103 = \$99 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$101 ; + assign \$105 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$107 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$109 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$105 , \$107 }; + assign \$111 = \$109 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$113 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$115 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$13 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$11 ; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$17 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$15 ; + assign \$1 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$19 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o }; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$25 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; + assign \$22 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ; + assign \$21 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$22 ; + assign \$29 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$21 ; + assign \$31 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$33 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$35 = \$31 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$33 ; + assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_logical0_n_ready_i; + assign \$39 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$37 ; + assign \$41 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$43 = \$41 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$45 = \$39 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$43 ; + assign \$47 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$4 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$49 = \$47 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_logical0_n_ready_i; + assign \$51 = \$49 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_logical0_n_valid_o; + assign \$53 = \$51 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$55 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$57 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$59 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i }; + assign \$61 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$63 = alu_logical0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$65 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$67 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$6 = \$4 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$69 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$71 = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$73 = alu_logical0_logical_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[0]; + assign \$75 = alu_logical0_logical_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) 64'h0000000000000000 : src1_i; + assign \$78 = alu_logical0_logical_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1]; + assign \$3 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$6 ; + assign \$81 = alu_logical0_logical_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_logical0_logical_op__imm_data__data : src2_i; + assign \$83 = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r0; + assign \$85 = \src_sel$77 ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) \src_or_imm$80 : src_r1; + assign \$87 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$89 = alu_logical0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$91 = alu_logical0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$93 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$95 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_logical0_logical_op__zero_a; + assign \$97 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_logical0_logical_op__imm_data__ok; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r1__cr_a <= \data_r1__cr_a$next ; + always @(posedge coresync_clk) + data_r1__cr_a_ok <= \data_r1__cr_a_ok$next ; + always @(posedge coresync_clk) + data_r0__o <= \data_r0__o$next ; + always @(posedge coresync_clk) + data_r0__o_ok <= \data_r0__o_ok$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__insn_type <= \alu_logical0_logical_op__insn_type$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__fn_unit <= \alu_logical0_logical_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__imm_data__data <= \alu_logical0_logical_op__imm_data__data$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__imm_data__ok <= \alu_logical0_logical_op__imm_data__ok$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__rc__rc <= \alu_logical0_logical_op__rc__rc$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__rc__ok <= \alu_logical0_logical_op__rc__ok$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__oe__oe <= \alu_logical0_logical_op__oe__oe$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__oe__ok <= \alu_logical0_logical_op__oe__ok$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__invert_in <= \alu_logical0_logical_op__invert_in$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__zero_a <= \alu_logical0_logical_op__zero_a$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__input_carry <= \alu_logical0_logical_op__input_carry$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__invert_out <= \alu_logical0_logical_op__invert_out$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__write_cr0 <= \alu_logical0_logical_op__write_cr0$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__output_carry <= \alu_logical0_logical_op__output_carry$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__is_32bit <= \alu_logical0_logical_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__is_signed <= \alu_logical0_logical_op__is_signed$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__data_len <= \alu_logical0_logical_op__data_len$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__insn <= \alu_logical0_logical_op__insn$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_logical0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$9 ; + \alu_l$61 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + alu_logical0 alu_logical0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(alu_logical0_cr_a), + .cr_a_ok(cr_a_ok), + .logical_op__data_len(alu_logical0_logical_op__data_len), + .logical_op__fn_unit(alu_logical0_logical_op__fn_unit), + .logical_op__imm_data__data(alu_logical0_logical_op__imm_data__data), + .logical_op__imm_data__ok(alu_logical0_logical_op__imm_data__ok), + .logical_op__input_carry(alu_logical0_logical_op__input_carry), + .logical_op__insn(alu_logical0_logical_op__insn), + .logical_op__insn_type(alu_logical0_logical_op__insn_type), + .logical_op__invert_in(alu_logical0_logical_op__invert_in), + .logical_op__invert_out(alu_logical0_logical_op__invert_out), + .logical_op__is_32bit(alu_logical0_logical_op__is_32bit), + .logical_op__is_signed(alu_logical0_logical_op__is_signed), + .logical_op__oe__oe(alu_logical0_logical_op__oe__oe), + .logical_op__oe__ok(alu_logical0_logical_op__oe__ok), + .logical_op__output_carry(alu_logical0_logical_op__output_carry), + .logical_op__rc__ok(alu_logical0_logical_op__rc__ok), + .logical_op__rc__rc(alu_logical0_logical_op__rc__rc), + .logical_op__write_cr0(alu_logical0_logical_op__write_cr0), + .logical_op__zero_a(alu_logical0_logical_op__zero_a), + .n_ready_i(alu_logical0_n_ready_i), + .n_valid_o(alu_logical0_n_valid_o), + .o(alu_logical0_o), + .o_ok(o_ok), + .p_ready_o(alu_logical0_p_ready_o), + .p_valid_i(alu_logical0_p_valid_i), + .ra(alu_logical0_ra), + .rb(alu_logical0_rb), + .xer_so(alu_logical0_xer_so) + ); + \alui_l$60 alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + \opc_l$56 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \req_l$57 req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + \rok_l$59 rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + \rst_l$58 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$55 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$53 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$63 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$65 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$67 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 2'h3; + endcase + end + always @* begin + if (\initial ) begin end + \alu_logical0_logical_op__insn_type$next = alu_logical0_logical_op__insn_type; + \alu_logical0_logical_op__fn_unit$next = alu_logical0_logical_op__fn_unit; + \alu_logical0_logical_op__imm_data__data$next = alu_logical0_logical_op__imm_data__data; + \alu_logical0_logical_op__imm_data__ok$next = alu_logical0_logical_op__imm_data__ok; + \alu_logical0_logical_op__rc__rc$next = alu_logical0_logical_op__rc__rc; + \alu_logical0_logical_op__rc__ok$next = alu_logical0_logical_op__rc__ok; + \alu_logical0_logical_op__oe__oe$next = alu_logical0_logical_op__oe__oe; + \alu_logical0_logical_op__oe__ok$next = alu_logical0_logical_op__oe__ok; + \alu_logical0_logical_op__invert_in$next = alu_logical0_logical_op__invert_in; + \alu_logical0_logical_op__zero_a$next = alu_logical0_logical_op__zero_a; + \alu_logical0_logical_op__input_carry$next = alu_logical0_logical_op__input_carry; + \alu_logical0_logical_op__invert_out$next = alu_logical0_logical_op__invert_out; + \alu_logical0_logical_op__write_cr0$next = alu_logical0_logical_op__write_cr0; + \alu_logical0_logical_op__output_carry$next = alu_logical0_logical_op__output_carry; + \alu_logical0_logical_op__is_32bit$next = alu_logical0_logical_op__is_32bit; + \alu_logical0_logical_op__is_signed$next = alu_logical0_logical_op__is_signed; + \alu_logical0_logical_op__data_len$next = alu_logical0_logical_op__data_len; + \alu_logical0_logical_op__insn$next = alu_logical0_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_logical0_logical_op__insn$next , \alu_logical0_logical_op__data_len$next , \alu_logical0_logical_op__is_signed$next , \alu_logical0_logical_op__is_32bit$next , \alu_logical0_logical_op__output_carry$next , \alu_logical0_logical_op__write_cr0$next , \alu_logical0_logical_op__invert_out$next , \alu_logical0_logical_op__input_carry$next , \alu_logical0_logical_op__zero_a$next , \alu_logical0_logical_op__invert_in$next , \alu_logical0_logical_op__oe__ok$next , \alu_logical0_logical_op__oe__oe$next , \alu_logical0_logical_op__rc__ok$next , \alu_logical0_logical_op__rc__rc$next , \alu_logical0_logical_op__imm_data__ok$next , \alu_logical0_logical_op__imm_data__data$next , \alu_logical0_logical_op__fn_unit$next , \alu_logical0_logical_op__insn_type$next } = { oper_i_alu_logical0__insn, oper_i_alu_logical0__data_len, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__insn_type }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \alu_logical0_logical_op__imm_data__data$next = 64'h0000000000000000; + \alu_logical0_logical_op__imm_data__ok$next = 1'h0; + \alu_logical0_logical_op__rc__rc$next = 1'h0; + \alu_logical0_logical_op__rc__ok$next = 1'h0; + \alu_logical0_logical_op__oe__oe$next = 1'h0; + \alu_logical0_logical_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__o$next = data_r0__o; + \data_r0__o_ok$next = data_r0__o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = { o_ok, alu_logical0_o }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__cr_a$next = data_r1__cr_a; + \data_r1__cr_a_ok$next = data_r1__cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = { cr_a_ok, alu_logical0_cr_a }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_sel) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src_or_imm; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (\src_sel$77 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = \src_or_imm$80 ; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$89 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$91 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$113 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__o; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$115 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__cr_a; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$19 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 2'h0; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$111 ; + assign cu_rd__rel_o = \$103 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_logical0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_logical0_p_valid_i = alui_l_q_alui; + assign alu_logical0_xer_so = \$87 ; + assign alu_logical0_rb = \$85 ; + assign alu_logical0_ra = \$83 ; + assign \src_or_imm$80 = \$81 ; + assign \src_sel$77 = \$78 ; + assign src_or_imm = \$75 ; + assign src_sel = \$73 ; + assign cu_wrmask_o = { \$71 , \$69 }; + assign reset_r = \$61 ; + assign reset_w = \$59 ; + assign rst_r = \$57 ; + assign reset = \$55 ; + assign wr_any = \$35 ; + assign cu_done_o = \$29 ; + assign alu_pulsem = { alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$17 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_logical0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$13 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$9 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" *) +(* generator = "nMigen" *) +module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , ra, rb, \xer_so$20 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + reg [3:0] cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + reg cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] input_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \input_logical_op__data_len$38 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] input_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \input_logical_op__fn_unit$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] input_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \input_logical_op__imm_data__data$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__imm_data__ok$25 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] input_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \input_logical_op__input_carry$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] input_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \input_logical_op__insn$39 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] input_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \input_logical_op__insn_type$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__invert_in$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__invert_out$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__is_32bit$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__is_signed$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__oe__oe$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__oe__ok$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__output_carry$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__rc__ok$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__rc__rc$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__write_cr0$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__zero_a$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] input_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \input_muxid$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_ra$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_rb$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire input_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \input_xer_so$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] logical_op__data_len; + reg [3:0] logical_op__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] \logical_op__data_len$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \logical_op__data_len$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \logical_op__data_len$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] logical_op__fn_unit; + reg [13:0] logical_op__fn_unit = 14'h0000; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] \logical_op__fn_unit$3 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \logical_op__fn_unit$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \logical_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] logical_op__imm_data__data; + reg [63:0] logical_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \logical_op__imm_data__data$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \logical_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__imm_data__ok; + reg logical_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__imm_data__ok$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__imm_data__ok$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] logical_op__input_carry; + reg [1:0] logical_op__input_carry = 2'h0; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] \logical_op__input_carry$12 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \logical_op__input_carry$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \logical_op__input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] logical_op__insn; + reg [31:0] logical_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] \logical_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \logical_op__insn$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \logical_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] logical_op__insn_type; + reg [6:0] logical_op__insn_type = 7'h00; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] \logical_op__insn_type$2 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \logical_op__insn_type$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \logical_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__invert_in; + reg logical_op__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_in$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__invert_out; + reg logical_op__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_out$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_out$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__is_32bit; + reg logical_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_32bit$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__is_signed; + reg logical_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_signed$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__oe__oe; + reg logical_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__oe$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__oe__ok; + reg logical_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__ok$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__output_carry; + reg logical_op__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__output_carry$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__output_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__rc__ok; + reg logical_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__ok$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__rc__rc; + reg logical_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__rc$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__write_cr0; + reg logical_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__write_cr0$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__zero_a; + reg logical_op__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__zero_a$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__zero_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] main_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \main_logical_op__data_len$60 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] main_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \main_logical_op__fn_unit$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] main_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \main_logical_op__imm_data__data$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__imm_data__ok$47 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] main_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \main_logical_op__input_carry$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] main_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \main_logical_op__insn$61 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] main_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \main_logical_op__insn_type$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__invert_in$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__invert_out$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__is_32bit$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__is_signed$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__oe__oe$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__oe__ok$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__output_carry$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__rc__ok$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__rc__rc$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__write_cr0$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_logical_op__zero_a$53 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] main_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \main_muxid$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] main_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire main_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \main_xer_so$62 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] muxid; + reg [1:0] muxid = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$66 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$63 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so; + reg xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so_ok$next ; + assign \$64 = \p_valid_i$63 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + xer_so <= \xer_so$next ; + always @(posedge coresync_clk) + xer_so_ok <= \xer_so_ok$next ; + always @(posedge coresync_clk) + cr_a <= \cr_a$next ; + always @(posedge coresync_clk) + cr_a_ok <= \cr_a_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; + always @(posedge coresync_clk) + o_ok <= \o_ok$next ; + always @(posedge coresync_clk) + logical_op__insn_type <= \logical_op__insn_type$next ; + always @(posedge coresync_clk) + logical_op__fn_unit <= \logical_op__fn_unit$next ; + always @(posedge coresync_clk) + logical_op__imm_data__data <= \logical_op__imm_data__data$next ; + always @(posedge coresync_clk) + logical_op__imm_data__ok <= \logical_op__imm_data__ok$next ; + always @(posedge coresync_clk) + logical_op__rc__rc <= \logical_op__rc__rc$next ; + always @(posedge coresync_clk) + logical_op__rc__ok <= \logical_op__rc__ok$next ; + always @(posedge coresync_clk) + logical_op__oe__oe <= \logical_op__oe__oe$next ; + always @(posedge coresync_clk) + logical_op__oe__ok <= \logical_op__oe__ok$next ; + always @(posedge coresync_clk) + logical_op__invert_in <= \logical_op__invert_in$next ; + always @(posedge coresync_clk) + logical_op__zero_a <= \logical_op__zero_a$next ; + always @(posedge coresync_clk) + logical_op__input_carry <= \logical_op__input_carry$next ; + always @(posedge coresync_clk) + logical_op__invert_out <= \logical_op__invert_out$next ; + always @(posedge coresync_clk) + logical_op__write_cr0 <= \logical_op__write_cr0$next ; + always @(posedge coresync_clk) + logical_op__output_carry <= \logical_op__output_carry$next ; + always @(posedge coresync_clk) + logical_op__is_32bit <= \logical_op__is_32bit$next ; + always @(posedge coresync_clk) + logical_op__is_signed <= \logical_op__is_signed$next ; + always @(posedge coresync_clk) + logical_op__data_len <= \logical_op__data_len$next ; + always @(posedge coresync_clk) + logical_op__insn <= \logical_op__insn$next ; + always @(posedge coresync_clk) + muxid <= \muxid$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \input$50 \input ( + .logical_op__data_len(input_logical_op__data_len), + .\logical_op__data_len$18 (\input_logical_op__data_len$38 ), + .logical_op__fn_unit(input_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$23 ), + .logical_op__imm_data__data(input_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$24 ), + .logical_op__imm_data__ok(input_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$25 ), + .logical_op__input_carry(input_logical_op__input_carry), + .\logical_op__input_carry$12 (\input_logical_op__input_carry$32 ), + .logical_op__insn(input_logical_op__insn), + .\logical_op__insn$19 (\input_logical_op__insn$39 ), + .logical_op__insn_type(input_logical_op__insn_type), + .\logical_op__insn_type$2 (\input_logical_op__insn_type$22 ), + .logical_op__invert_in(input_logical_op__invert_in), + .\logical_op__invert_in$10 (\input_logical_op__invert_in$30 ), + .logical_op__invert_out(input_logical_op__invert_out), + .\logical_op__invert_out$13 (\input_logical_op__invert_out$33 ), + .logical_op__is_32bit(input_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$36 ), + .logical_op__is_signed(input_logical_op__is_signed), + .\logical_op__is_signed$17 (\input_logical_op__is_signed$37 ), + .logical_op__oe__oe(input_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$28 ), + .logical_op__oe__ok(input_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$29 ), + .logical_op__output_carry(input_logical_op__output_carry), + .\logical_op__output_carry$15 (\input_logical_op__output_carry$35 ), + .logical_op__rc__ok(input_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$27 ), + .logical_op__rc__rc(input_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$26 ), + .logical_op__write_cr0(input_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$34 ), + .logical_op__zero_a(input_logical_op__zero_a), + .\logical_op__zero_a$11 (\input_logical_op__zero_a$31 ), + .muxid(input_muxid), + .\muxid$1 (\input_muxid$21 ), + .ra(input_ra), + .\ra$20 (\input_ra$40 ), + .rb(input_rb), + .\rb$21 (\input_rb$41 ), + .xer_so(input_xer_so), + .\xer_so$22 (\input_xer_so$42 ) + ); + \main$51 main ( + .logical_op__data_len(main_logical_op__data_len), + .\logical_op__data_len$18 (\main_logical_op__data_len$60 ), + .logical_op__fn_unit(main_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\main_logical_op__fn_unit$45 ), + .logical_op__imm_data__data(main_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\main_logical_op__imm_data__data$46 ), + .logical_op__imm_data__ok(main_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\main_logical_op__imm_data__ok$47 ), + .logical_op__input_carry(main_logical_op__input_carry), + .\logical_op__input_carry$12 (\main_logical_op__input_carry$54 ), + .logical_op__insn(main_logical_op__insn), + .\logical_op__insn$19 (\main_logical_op__insn$61 ), + .logical_op__insn_type(main_logical_op__insn_type), + .\logical_op__insn_type$2 (\main_logical_op__insn_type$44 ), + .logical_op__invert_in(main_logical_op__invert_in), + .\logical_op__invert_in$10 (\main_logical_op__invert_in$52 ), + .logical_op__invert_out(main_logical_op__invert_out), + .\logical_op__invert_out$13 (\main_logical_op__invert_out$55 ), + .logical_op__is_32bit(main_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\main_logical_op__is_32bit$58 ), + .logical_op__is_signed(main_logical_op__is_signed), + .\logical_op__is_signed$17 (\main_logical_op__is_signed$59 ), + .logical_op__oe__oe(main_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\main_logical_op__oe__oe$50 ), + .logical_op__oe__ok(main_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\main_logical_op__oe__ok$51 ), + .logical_op__output_carry(main_logical_op__output_carry), + .\logical_op__output_carry$15 (\main_logical_op__output_carry$57 ), + .logical_op__rc__ok(main_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\main_logical_op__rc__ok$49 ), + .logical_op__rc__rc(main_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\main_logical_op__rc__rc$48 ), + .logical_op__write_cr0(main_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\main_logical_op__write_cr0$56 ), + .logical_op__zero_a(main_logical_op__zero_a), + .\logical_op__zero_a$11 (\main_logical_op__zero_a$53 ), + .muxid(main_muxid), + .\muxid$1 (\main_muxid$43 ), + .o(main_o), + .o_ok(main_o_ok), + .ra(main_ra), + .rb(main_rb), + .xer_so(main_xer_so), + .\xer_so$20 (\main_xer_so$62 ) + ); + \n$49 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$48 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$next = muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$next = \muxid$66 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$next = \muxid$66 ; + endcase + end + always @* begin + if (\initial ) begin end + \logical_op__insn_type$next = logical_op__insn_type; + \logical_op__fn_unit$next = logical_op__fn_unit; + \logical_op__imm_data__data$next = logical_op__imm_data__data; + \logical_op__imm_data__ok$next = logical_op__imm_data__ok; + \logical_op__rc__rc$next = logical_op__rc__rc; + \logical_op__rc__ok$next = logical_op__rc__ok; + \logical_op__oe__oe$next = logical_op__oe__oe; + \logical_op__oe__ok$next = logical_op__oe__ok; + \logical_op__invert_in$next = logical_op__invert_in; + \logical_op__zero_a$next = logical_op__zero_a; + \logical_op__input_carry$next = logical_op__input_carry; + \logical_op__invert_out$next = logical_op__invert_out; + \logical_op__write_cr0$next = logical_op__write_cr0; + \logical_op__output_carry$next = logical_op__output_carry; + \logical_op__is_32bit$next = logical_op__is_32bit; + \logical_op__is_signed$next = logical_op__is_signed; + \logical_op__data_len$next = logical_op__data_len; + \logical_op__insn$next = logical_op__insn; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \logical_op__imm_data__data$next = 64'h0000000000000000; + \logical_op__imm_data__ok$next = 1'h0; + \logical_op__rc__rc$next = 1'h0; + \logical_op__rc__ok$next = 1'h0; + \logical_op__oe__oe$next = 1'h0; + \logical_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \o$next = o; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cr_a$next = cr_a; + \cr_a_ok$next = cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$next = xer_so; + \xer_so_ok$next = xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_so_ok$next = 1'h0; + endcase + end + assign \cr_a$89 = 4'h0; + assign \cr_a_ok$90 = 1'h0; + assign \xer_so_ok$93 = 1'h0; + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \xer_so_ok$92 , \xer_so$91 } = { 1'h0, \main_xer_so$62 }; + assign { \cr_a_ok$88 , \cr_a$87 } = 5'h00; + assign { \o_ok$86 , \o$85 } = { main_o_ok, main_o }; + assign { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67 } = { \main_logical_op__insn$61 , \main_logical_op__data_len$60 , \main_logical_op__is_signed$59 , \main_logical_op__is_32bit$58 , \main_logical_op__output_carry$57 , \main_logical_op__write_cr0$56 , \main_logical_op__invert_out$55 , \main_logical_op__input_carry$54 , \main_logical_op__zero_a$53 , \main_logical_op__invert_in$52 , \main_logical_op__oe__ok$51 , \main_logical_op__oe__oe$50 , \main_logical_op__rc__ok$49 , \main_logical_op__rc__rc$48 , \main_logical_op__imm_data__ok$47 , \main_logical_op__imm_data__data$46 , \main_logical_op__fn_unit$45 , \main_logical_op__insn_type$44 }; + assign \muxid$66 = \main_muxid$43 ; + assign p_valid_i_p_ready_o = \$64 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$63 = p_valid_i; + assign main_xer_so = \input_xer_so$42 ; + assign main_rb = \input_rb$41 ; + assign main_ra = \input_ra$40 ; + assign { main_logical_op__insn, main_logical_op__data_len, main_logical_op__is_signed, main_logical_op__is_32bit, main_logical_op__output_carry, main_logical_op__write_cr0, main_logical_op__invert_out, main_logical_op__input_carry, main_logical_op__zero_a, main_logical_op__invert_in, main_logical_op__oe__ok, main_logical_op__oe__oe, main_logical_op__rc__ok, main_logical_op__rc__rc, main_logical_op__imm_data__ok, main_logical_op__imm_data__data, main_logical_op__fn_unit, main_logical_op__insn_type } = { \input_logical_op__insn$39 , \input_logical_op__data_len$38 , \input_logical_op__is_signed$37 , \input_logical_op__is_32bit$36 , \input_logical_op__output_carry$35 , \input_logical_op__write_cr0$34 , \input_logical_op__invert_out$33 , \input_logical_op__input_carry$32 , \input_logical_op__zero_a$31 , \input_logical_op__invert_in$30 , \input_logical_op__oe__ok$29 , \input_logical_op__oe__oe$28 , \input_logical_op__rc__ok$27 , \input_logical_op__rc__rc$26 , \input_logical_op__imm_data__ok$25 , \input_logical_op__imm_data__data$24 , \input_logical_op__fn_unit$23 , \input_logical_op__insn_type$22 }; + assign main_muxid = \input_muxid$21 ; + assign input_xer_so = \xer_so$20 ; + assign input_rb = rb; + assign input_ra = ra; + assign { input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 }; + assign input_muxid = \muxid$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" *) +(* generator = "nMigen" *) +module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , \cr_a_ok$23 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$22 ; + reg [3:0] \cr_a$22 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$22$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_a_ok$23 ; + reg \cr_a_ok$23 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$23$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + reg [3:0] \logical_op__data_len$18 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \logical_op__data_len$18$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \logical_op__data_len$68 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + reg [13:0] \logical_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \logical_op__fn_unit$3$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \logical_op__fn_unit$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + reg [63:0] \logical_op__imm_data__data$4 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \logical_op__imm_data__data$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \logical_op__imm_data__data$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + reg \logical_op__imm_data__ok$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__imm_data__ok$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__imm_data__ok$55 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + reg [1:0] \logical_op__input_carry$12 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \logical_op__input_carry$12$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \logical_op__input_carry$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + reg [31:0] \logical_op__insn$19 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \logical_op__insn$19$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \logical_op__insn$69 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + reg [6:0] \logical_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \logical_op__insn_type$2$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \logical_op__insn_type$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + reg \logical_op__invert_in$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_in$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_in$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + reg \logical_op__invert_out$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_out$13$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_out$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + reg \logical_op__is_32bit$16 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_32bit$16$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_32bit$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + reg \logical_op__is_signed$17 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_signed$17$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_signed$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__oe$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + reg \logical_op__oe__oe$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__oe$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__ok$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + reg \logical_op__oe__ok$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__ok$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + reg \logical_op__output_carry$15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__output_carry$15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__output_carry$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__ok$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + reg \logical_op__rc__ok$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__ok$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__rc$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + reg \logical_op__rc__rc$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__rc$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + reg \logical_op__write_cr0$14 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__write_cr0$14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__write_cr0$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + reg \logical_op__zero_a$11 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__zero_a$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__zero_a$61 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$51 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$20 ; + reg [63:0] \o$20 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$20$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$21 ; + reg \o_ok$21 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$21$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] output_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \output_cr_a$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] output_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \output_logical_op__data_len$41 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] output_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \output_logical_op__fn_unit$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] output_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \output_logical_op__imm_data__data$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__imm_data__ok$28 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] output_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \output_logical_op__input_carry$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] output_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \output_logical_op__insn$42 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] output_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \output_logical_op__insn_type$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__invert_in$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__invert_out$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__is_32bit$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__is_signed$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__oe__oe$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__oe__ok$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__output_carry$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__rc__ok$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__rc__rc$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__write_cr0$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__zero_a$34 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] output_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \output_muxid$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] output_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \output_o$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_o_ok$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_so; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$48 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$47 ; + assign \$49 = \p_valid_i$48 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \cr_a$22 <= \cr_a$22$next ; + always @(posedge coresync_clk) + \cr_a_ok$23 <= \cr_a_ok$23$next ; + always @(posedge coresync_clk) + \o$20 <= \o$20$next ; + always @(posedge coresync_clk) + \o_ok$21 <= \o_ok$21$next ; + always @(posedge coresync_clk) + \logical_op__insn_type$2 <= \logical_op__insn_type$2$next ; + always @(posedge coresync_clk) + \logical_op__fn_unit$3 <= \logical_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \logical_op__imm_data__data$4 <= \logical_op__imm_data__data$4$next ; + always @(posedge coresync_clk) + \logical_op__imm_data__ok$5 <= \logical_op__imm_data__ok$5$next ; + always @(posedge coresync_clk) + \logical_op__rc__rc$6 <= \logical_op__rc__rc$6$next ; + always @(posedge coresync_clk) + \logical_op__rc__ok$7 <= \logical_op__rc__ok$7$next ; + always @(posedge coresync_clk) + \logical_op__oe__oe$8 <= \logical_op__oe__oe$8$next ; + always @(posedge coresync_clk) + \logical_op__oe__ok$9 <= \logical_op__oe__ok$9$next ; + always @(posedge coresync_clk) + \logical_op__invert_in$10 <= \logical_op__invert_in$10$next ; + always @(posedge coresync_clk) + \logical_op__zero_a$11 <= \logical_op__zero_a$11$next ; + always @(posedge coresync_clk) + \logical_op__input_carry$12 <= \logical_op__input_carry$12$next ; + always @(posedge coresync_clk) + \logical_op__invert_out$13 <= \logical_op__invert_out$13$next ; + always @(posedge coresync_clk) + \logical_op__write_cr0$14 <= \logical_op__write_cr0$14$next ; + always @(posedge coresync_clk) + \logical_op__output_carry$15 <= \logical_op__output_carry$15$next ; + always @(posedge coresync_clk) + \logical_op__is_32bit$16 <= \logical_op__is_32bit$16$next ; + always @(posedge coresync_clk) + \logical_op__is_signed$17 <= \logical_op__is_signed$17$next ; + always @(posedge coresync_clk) + \logical_op__data_len$18 <= \logical_op__data_len$18$next ; + always @(posedge coresync_clk) + \logical_op__insn$19 <= \logical_op__insn$19$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \n$53 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \output$54 \output ( + .cr_a(output_cr_a), + .\cr_a$22 (\output_cr_a$45 ), + .cr_a_ok(output_cr_a_ok), + .logical_op__data_len(output_logical_op__data_len), + .\logical_op__data_len$18 (\output_logical_op__data_len$41 ), + .logical_op__fn_unit(output_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$26 ), + .logical_op__imm_data__data(output_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$27 ), + .logical_op__imm_data__ok(output_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$28 ), + .logical_op__input_carry(output_logical_op__input_carry), + .\logical_op__input_carry$12 (\output_logical_op__input_carry$35 ), + .logical_op__insn(output_logical_op__insn), + .\logical_op__insn$19 (\output_logical_op__insn$42 ), + .logical_op__insn_type(output_logical_op__insn_type), + .\logical_op__insn_type$2 (\output_logical_op__insn_type$25 ), + .logical_op__invert_in(output_logical_op__invert_in), + .\logical_op__invert_in$10 (\output_logical_op__invert_in$33 ), + .logical_op__invert_out(output_logical_op__invert_out), + .\logical_op__invert_out$13 (\output_logical_op__invert_out$36 ), + .logical_op__is_32bit(output_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$39 ), + .logical_op__is_signed(output_logical_op__is_signed), + .\logical_op__is_signed$17 (\output_logical_op__is_signed$40 ), + .logical_op__oe__oe(output_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$31 ), + .logical_op__oe__ok(output_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$32 ), + .logical_op__output_carry(output_logical_op__output_carry), + .\logical_op__output_carry$15 (\output_logical_op__output_carry$38 ), + .logical_op__rc__ok(output_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$30 ), + .logical_op__rc__rc(output_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$29 ), + .logical_op__write_cr0(output_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$37 ), + .logical_op__zero_a(output_logical_op__zero_a), + .\logical_op__zero_a$11 (\output_logical_op__zero_a$34 ), + .muxid(output_muxid), + .\muxid$1 (\output_muxid$24 ), + .o(output_o), + .\o$20 (\output_o$43 ), + .o_ok(output_o_ok), + .\o_ok$21 (\output_o_ok$44 ), + .xer_so(output_xer_so) + ); + \p$52 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$51 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$51 ; + endcase + end + always @* begin + if (\initial ) begin end + \logical_op__insn_type$2$next = \logical_op__insn_type$2 ; + \logical_op__fn_unit$3$next = \logical_op__fn_unit$3 ; + \logical_op__imm_data__data$4$next = \logical_op__imm_data__data$4 ; + \logical_op__imm_data__ok$5$next = \logical_op__imm_data__ok$5 ; + \logical_op__rc__rc$6$next = \logical_op__rc__rc$6 ; + \logical_op__rc__ok$7$next = \logical_op__rc__ok$7 ; + \logical_op__oe__oe$8$next = \logical_op__oe__oe$8 ; + \logical_op__oe__ok$9$next = \logical_op__oe__ok$9 ; + \logical_op__invert_in$10$next = \logical_op__invert_in$10 ; + \logical_op__zero_a$11$next = \logical_op__zero_a$11 ; + \logical_op__input_carry$12$next = \logical_op__input_carry$12 ; + \logical_op__invert_out$13$next = \logical_op__invert_out$13 ; + \logical_op__write_cr0$14$next = \logical_op__write_cr0$14 ; + \logical_op__output_carry$15$next = \logical_op__output_carry$15 ; + \logical_op__is_32bit$16$next = \logical_op__is_32bit$16 ; + \logical_op__is_signed$17$next = \logical_op__is_signed$17 ; + \logical_op__data_len$18$next = \logical_op__data_len$18 ; + \logical_op__insn$19$next = \logical_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \logical_op__imm_data__data$4$next = 64'h0000000000000000; + \logical_op__imm_data__ok$5$next = 1'h0; + \logical_op__rc__rc$6$next = 1'h0; + \logical_op__rc__ok$7$next = 1'h0; + \logical_op__oe__oe$8$next = 1'h0; + \logical_op__oe__ok$9$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \o$20$next = \o$20 ; + \o_ok$21$next = \o_ok$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$21$next , \o$20$next } = { \o_ok$71 , \o$70 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$21$next , \o$20$next } = { \o_ok$71 , \o$70 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$21$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cr_a$22$next = \cr_a$22 ; + \cr_a_ok$23$next = \cr_a_ok$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$73 , \cr_a$72 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$73 , \cr_a$72 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$23$next = 1'h0; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \cr_a_ok$73 , \cr_a$72 } = { output_cr_a_ok, \output_cr_a$45 }; + assign { \o_ok$71 , \o$70 } = { \output_o_ok$44 , \output_o$43 }; + assign { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52 } = { \output_logical_op__insn$42 , \output_logical_op__data_len$41 , \output_logical_op__is_signed$40 , \output_logical_op__is_32bit$39 , \output_logical_op__output_carry$38 , \output_logical_op__write_cr0$37 , \output_logical_op__invert_out$36 , \output_logical_op__input_carry$35 , \output_logical_op__zero_a$34 , \output_logical_op__invert_in$33 , \output_logical_op__oe__ok$32 , \output_logical_op__oe__oe$31 , \output_logical_op__rc__ok$30 , \output_logical_op__rc__rc$29 , \output_logical_op__imm_data__ok$28 , \output_logical_op__imm_data__data$27 , \output_logical_op__fn_unit$26 , \output_logical_op__insn_type$25 }; + assign \muxid$51 = \output_muxid$24 ; + assign p_valid_i_p_ready_o = \$49 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$48 = p_valid_i; + assign { \xer_so_ok$47 , output_xer_so } = { xer_so_ok, xer_so }; + assign { \cr_a_ok$46 , output_cr_a } = { cr_a_ok, cr_a }; + assign { output_o_ok, output_o } = { o_ok, o }; + assign { output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign output_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.lsd_l" *) +(* generator = "nMigen" *) +module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_lsd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_lsd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_lsd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_lsd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_lsd; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_lsd; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_lsd; + assign \$15 = q_lsd | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_lsd; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_lsd; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_lsd; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_lsd = \$15 ; + assign qn_lsd = \$13 ; + assign q_lsd = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.lsmem" *) +(* generator = "nMigen" *) +module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_o, x_ld_i, x_st_i, m_valid_i, x_valid_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [44:0] dbus__adr; + reg [44:0] dbus__adr = 45'h000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + reg [44:0] \dbus__adr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__cyc; + reg dbus__cyc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + reg \dbus__cyc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input [63:0] dbus__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [63:0] dbus__dat_w; + reg [63:0] dbus__dat_w = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + reg [63:0] \dbus__dat_w$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [7:0] dbus__sel; + reg [7:0] dbus__sel = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + reg [7:0] \dbus__sel$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__stb; + reg dbus__stb = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + reg \dbus__stb$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__we; + reg dbus__we = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + reg \dbus__we$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" *) + reg [44:0] m_badaddr_o = 45'h000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" *) + reg [44:0] \m_badaddr_o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" *) + reg m_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *) + output [63:0] m_ld_data_o; + reg [63:0] m_ld_data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *) + reg [63:0] \m_ld_data_o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" *) + reg m_load_err_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" *) + reg \m_load_err_o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" *) + wire m_stall_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" *) + reg m_store_err_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" *) + reg \m_store_err_o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *) + input m_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + input wb_dcache_en; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" *) + input [47:0] x_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" *) + output x_busy_o; + reg x_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" *) + input x_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" *) + input [7:0] x_mask_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" *) + input [63:0] x_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" *) + input x_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:56" *) + wire x_stall_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *) + input x_valid_i; + assign \$9 = dbus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) dbus__err; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) m_valid_i; + assign \$13 = \$9 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) \$11 ; + assign \$15 = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i; + assign \$17 = \$15 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i; + assign \$1 = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i; + assign \$21 = \$17 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$19 ; + assign \$23 = dbus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) dbus__err; + assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) m_valid_i; + assign \$27 = \$23 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) \$25 ; + assign \$29 = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i; + assign \$31 = \$29 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i; + assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i; + assign \$35 = \$31 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$33 ; + assign \$37 = dbus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) dbus__err; + assign \$3 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) m_valid_i; + assign \$41 = \$37 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) \$39 ; + assign \$43 = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i; + assign \$45 = \$43 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i; + assign \$49 = \$45 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$47 ; + assign \$51 = dbus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) dbus__err; + assign \$53 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) m_valid_i; + assign \$55 = \$51 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) \$53 ; + assign \$57 = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i; + assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i; + assign \$59 = \$57 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i; + assign \$61 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i; + assign \$63 = \$59 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$61 ; + assign \$65 = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i; + assign \$67 = \$65 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i; + assign \$69 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i; + assign \$71 = \$67 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$69 ; + assign \$73 = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i; + assign \$75 = \$73 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i; + assign \$77 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i; + assign \$7 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$5 ; + assign \$79 = \$75 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$77 ; + assign \$81 = dbus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) dbus__err; + assign \$83 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) m_stall_i; + assign \$85 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" *) dbus__we; + assign \$87 = dbus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) dbus__err; + assign \$89 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) m_stall_i; + assign \$91 = dbus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) dbus__err; + assign \$93 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) m_stall_i; + assign \$95 = m_load_err_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) m_store_err_o; + always @(posedge coresync_clk) + m_badaddr_o <= \m_badaddr_o$next ; + always @(posedge coresync_clk) + m_store_err_o <= \m_store_err_o$next ; + always @(posedge coresync_clk) + m_load_err_o <= \m_load_err_o$next ; + always @(posedge coresync_clk) + dbus__dat_w <= \dbus__dat_w$next ; + always @(posedge coresync_clk) + dbus__we <= \dbus__we$next ; + always @(posedge coresync_clk) + dbus__adr <= \dbus__adr$next ; + always @(posedge coresync_clk) + m_ld_data_o <= \m_ld_data_o$next ; + always @(posedge coresync_clk) + dbus__sel <= \dbus__sel$next ; + always @(posedge coresync_clk) + dbus__stb <= \dbus__stb$next ; + always @(posedge coresync_clk) + dbus__cyc <= \dbus__cyc$next ; + always @* begin + if (\initial ) begin end + \dbus__cyc$next = dbus__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) + casez ({ \$7 , dbus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" */ + 1'h1: + \dbus__cyc$next = 1'h0; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" */ + 2'b1?: + \dbus__cyc$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dbus__cyc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dbus__stb$next = dbus__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) + casez ({ \$21 , dbus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" */ + 1'h1: + \dbus__stb$next = 1'h0; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" */ + 2'b1?: + \dbus__stb$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dbus__stb$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + x_busy_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + x_busy_o = dbus__cyc; + endcase + end + always @* begin + if (\initial ) begin end + m_busy_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) + casez (\$95 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" */ + 1'h1: + m_busy_o = 1'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:156" */ + default: + m_busy_o = dbus__cyc; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dbus__sel$next = dbus__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) + casez ({ \$35 , dbus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + casez (\$41 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" */ + 1'h1: + \dbus__sel$next = 8'h00; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" */ + 2'b1?: + \dbus__sel$next = x_mask_i; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" */ + default: + \dbus__sel$next = 8'h00; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dbus__sel$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \m_ld_data_o$next = m_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) + casez ({ \$49 , dbus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ + 2'b?1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) + casez (\$55 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" */ + 1'h1: + \m_ld_data_o$next = dbus__dat_r; + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \m_ld_data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \dbus__adr$next = dbus__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) + casez ({ \$63 , dbus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ + 2'b?1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" */ + 2'b1?: + \dbus__adr$next = x_addr_i[47:3]; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" */ + default: + \dbus__adr$next = 45'h000000000000; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dbus__adr$next = 45'h000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \dbus__we$next = dbus__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) + casez ({ \$71 , dbus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ + 2'b?1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" */ + 2'b1?: + \dbus__we$next = x_st_i; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" */ + default: + \dbus__we$next = 1'h0; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dbus__we$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dbus__dat_w$next = dbus__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) + casez ({ \$79 , dbus__cyc }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ + 2'b?1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" */ + 2'b1?: + \dbus__dat_w$next = x_st_data_i; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" */ + default: + \dbus__dat_w$next = 64'h0000000000000000; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \dbus__dat_w$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \m_load_err_o$next = m_load_err_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) + casez ({ \$83 , \$81 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" */ + 2'b?1: + \m_load_err_o$next = \$85 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" */ + 2'b1?: + \m_load_err_o$next = 1'h0; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \m_load_err_o$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \m_store_err_o$next = m_store_err_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) + casez ({ \$89 , \$87 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" */ + 2'b?1: + \m_store_err_o$next = dbus__we; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" */ + 2'b1?: + \m_store_err_o$next = 1'h0; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \m_store_err_o$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \m_badaddr_o$next = m_badaddr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *) + casez (wb_dcache_en) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) + casez ({ \$93 , \$91 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" */ + 2'b?1: + \m_badaddr_o$next = dbus__adr; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \m_badaddr_o$next = 45'h000000000000; + endcase + end + assign x_stall_i = 1'h0; + assign m_stall_i = 1'h0; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" *) +(* generator = "nMigen" *) +module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , o, o_ok, cr_a, cr_a_ok, \xer_ca$20 , xer_ca_ok, xer_ov, xer_ov_ok, \xer_so$21 , muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$119 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$127 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$129 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$131 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$133 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$135 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$137 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$141 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$143 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) + wire [66:0] \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) + wire [66:0] \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *) + wire [63:0] \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) + wire \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) + wire [31:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) + wire \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) + wire [31:0] \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:65" *) + reg [63:0] a_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" *) + reg a_lt; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" *) + reg [63:0] a_n; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" *) + reg [65:0] add_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" *) + reg [65:0] add_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" *) + reg [65:0] add_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \alu_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \alu_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \alu_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \alu_op__input_carry$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \alu_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \alu_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__invert_out$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__write_cr0$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" *) + reg [63:0] b_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" *) + reg [1:0] ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" *) + reg carry_32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" *) + reg carry_64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + reg [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + reg cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" *) + reg [7:0] eqs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" *) + reg is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" *) + reg msb_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" *) + reg msb_b; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" *) + reg [1:0] ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" *) + reg [7:0] src1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" *) + reg [4:0] tval; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ca$20 ; + reg [1:0] \xer_ca$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + reg xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + reg [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" *) + reg zerohi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" *) + reg zerolo; + assign \$99 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) eqs; + assign \$101 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) 1'h1; + assign \$103 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) 2'h2; + assign \$105 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) 3'h4; + assign \$107 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) eqs; + assign \$109 = a_i[32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) b_i[32]; + assign \$111 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) \$109 ; + assign \$113 = ca[0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[64]; + assign \$116 = a_i[63] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[63]; + assign \$115 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$116 ; + assign \$119 = \$113 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$115 ; + assign \$121 = ca[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[32]; + assign \$124 = a_i[31] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[31]; + assign \$123 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$124 ; + assign \$127 = \$121 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$123 ; + assign \$129 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[7:0]; + assign \$131 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[15:8]; + assign \$133 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[23:16]; + assign \$135 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[31:24]; + assign \$137 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[39:32]; + assign \$139 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[47:40]; + assign \$141 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[55:48]; + assign \$143 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[63:56]; + assign \$22 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) 7'h0a; + assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) alu_op__insn[21]; + assign \$26 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a; + assign \$28 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a; + assign \$30 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; + assign \$32 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$32 ; + assign \$36 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; + assign \$38 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; + assign \$40 = \$36 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$38 ; + assign \$42 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; + assign \$44 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; + assign \$46 = \$42 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$44 ; + assign \$49 = add_a + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) add_b; + assign \$51 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *) ra; + assign \$53 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) ra[32]; + assign \$55 = \$53 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) rb[32]; + assign \$59 = a_n[31:0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) rb[31:0]; + assign \$58 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$59 ; + assign \$57 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$58 ; + assign \$65 = a_n[63:32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) rb[63:32]; + assign \$64 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$65 ; + assign \$63 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$64 ; + assign \$69 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; + assign \$71 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$69 ; + assign \$73 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b; + assign \$75 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt; + assign \$77 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt; + assign \$79 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; + assign \$81 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$79 ; + assign \$83 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) a_n[31] : a_n[63]; + assign \$85 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; + assign \$87 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$85 ; + assign \$89 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) rb[31] : rb[63]; + assign \$91 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; + assign \$93 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$91 ; + assign \$95 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b; + assign \$97 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) carry_32 : carry_64; + always @* begin + if (\initial ) begin end + is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) + casez (\$22 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" */ + 1'h1: + is_32bit = \$24 ; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) + casez ({ is_32bit, \$26 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" */ + 2'b?1: + a_i = ra; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" */ + 2'b1?: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" *) + casez (alu_op__is_signed) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" */ + 1'h1: + a_i = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:74" */ + default: + a_i = { 32'h00000000, ra[31:0] }; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" */ + default: + a_i = ra; + endcase + end + always @* begin + if (\initial ) begin end + zerohi = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + zerohi = \$63 ; + endcase + end + always @* begin + if (\initial ) begin end + tval = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + casez (\$71 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ + 1'h1: + tval[2] = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */ + default: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) + casez (\$73 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" */ + 1'h1: + tval = { msb_a, msb_b, 1'h0, msb_b, msb_a }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" */ + default: + tval = { a_lt, \$77 , 1'h0, a_lt, \$75 }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + msb_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + casez (\$81 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */ + default: + msb_a = \$83 ; + endcase + endcase + end + always @* begin + if (\initial ) begin end + msb_b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + casez (\$87 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */ + default: + msb_b = \$89 ; + endcase + endcase + end + always @* begin + if (\initial ) begin end + a_lt = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + casez (\$93 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */ + default: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) + casez (\$95 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" */ + default: + a_lt = \$97 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + begin + cr_a[1:0] = { tval[2], xer_so }; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" *) + casez (alu_op__is_signed) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" */ + 1'h1: + cr_a[3:2] = tval[4:3]; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:136" */ + default: + cr_a[3:2] = tval[1:0]; + endcase + end + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + /* empty */; + /* \nmigen.decoding = "OP_EXTS/31" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:165" */ + 7'h1f: + /* empty */; + /* \nmigen.decoding = "OP_CMPEQB/12" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ + 7'h0c: + cr_a = { 1'h0, \$99 , 2'h0 }; + endcase + end + always @* begin + if (\initial ) begin end + cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + cr_a_ok = 1'h1; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + /* empty */; + /* \nmigen.decoding = "OP_EXTS/31" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:165" */ + 7'h1f: + /* empty */; + /* \nmigen.decoding = "OP_CMPEQB/12" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ + 7'h0c: + cr_a_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + o = add_o[64:1]; + /* \nmigen.decoding = "OP_EXTS/31" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:165" */ + 7'h1f: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) + casez (\$101 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" */ + 1'h1: + o = { ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7:0] }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) + casez (\$103 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" */ + 1'h1: + o = { ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15:0] }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) + casez (\$105 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" */ + 1'h1: + o = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] }; + endcase + end + /* \nmigen.decoding = "OP_CMPEQB/12" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ + 7'h0c: + o[0] = \$107 ; + endcase + end + always @* begin + if (\initial ) begin end + o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + o_ok = 1'h1; + /* \nmigen.decoding = "OP_EXTS/31" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:165" */ + 7'h1f: + o_ok = 1'h1; + /* \nmigen.decoding = "OP_CMPEQB/12" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ + 7'h0c: + o_ok = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + ca = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + begin + ca[0] = add_o[65]; + ca[1] = \$111 ; + end + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) + casez ({ is_32bit, \$28 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" */ + 2'b?1: + b_i = rb; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" */ + 2'b1?: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" *) + casez (alu_op__is_signed) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" */ + 1'h1: + b_i = { rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31:0] }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:74" */ + default: + b_i = { 32'h00000000, rb[31:0] }; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" */ + default: + b_i = rb; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$20 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + \xer_ca$20 = ca; + endcase + end + always @* begin + if (\initial ) begin end + xer_ca_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + xer_ca_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + begin + ov[0] = \$119 ; + ov[1] = \$127 ; + end + endcase + end + always @* begin + if (\initial ) begin end + xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + xer_ov = ov; + endcase + end + always @* begin + if (\initial ) begin end + xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + xer_ov_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + src1 = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + /* empty */; + /* \nmigen.decoding = "OP_EXTS/31" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:165" */ + 7'h1f: + /* empty */; + /* \nmigen.decoding = "OP_CMPEQB/12" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ + 7'h0c: + src1 = ra[7:0]; + endcase + end + always @* begin + if (\initial ) begin end + eqs = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + /* empty */; + /* \nmigen.decoding = "OP_ADD/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ + 7'h02: + /* empty */; + /* \nmigen.decoding = "OP_EXTS/31" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:165" */ + 7'h1f: + /* empty */; + /* \nmigen.decoding = "OP_CMPEQB/12" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ + 7'h0c: + begin + eqs[0] = \$129 ; + eqs[1] = \$131 ; + eqs[2] = \$133 ; + eqs[3] = \$135 ; + eqs[4] = \$137 ; + eqs[5] = \$139 ; + eqs[6] = \$141 ; + eqs[7] = \$143 ; + end + endcase + end + always @* begin + if (\initial ) begin end + add_a = 66'h00000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + casez (\$34 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */ + 1'h1: + add_a = { 1'h0, a_i, xer_ca[0] }; + endcase + end + always @* begin + if (\initial ) begin end + add_b = 66'h00000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + casez (\$40 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */ + 1'h1: + add_b = { 1'h0, b_i, 1'h1 }; + endcase + end + always @* begin + if (\initial ) begin end + add_o = 66'h00000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + casez (\$46 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */ + 1'h1: + add_o = \$48 [65:0]; + endcase + end + always @* begin + if (\initial ) begin end + a_n = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + a_n = \$51 ; + endcase + end + always @* begin + if (\initial ) begin end + carry_32 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + carry_32 = \$55 ; + endcase + end + always @* begin + if (\initial ) begin end + carry_64 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + carry_64 = add_o[65]; + endcase + end + always @* begin + if (\initial ) begin end + zerolo = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) + casez (alu_op__insn_type) + /* \nmigen.decoding = "OP_CMP/10" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ + 7'h0a: + zerolo = \$57 ; + endcase + end + assign \$48 = \$49 ; + assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$21 = xer_so; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" *) +(* generator = "nMigen" *) +module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, ra, rb, rc, xer_so, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , o, o_ok, \xer_so$19 , xer_ca, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" *) + wire [4:0] mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" *) + wire mb_extra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" *) + wire [4:0] me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" *) + reg [3:0] mode; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" *) + wire rotator_arith; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" *) + wire rotator_carry_out_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" *) + wire rotator_clear_left; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" *) + wire rotator_clear_right; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" *) + wire rotator_is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *) + wire [4:0] rotator_mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" *) + wire rotator_mb_extra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" *) + wire [4:0] rotator_me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" *) + wire [63:0] rotator_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" *) + wire [63:0] rotator_result_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" *) + wire rotator_right_shift; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" *) + wire [63:0] rotator_rs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" *) + wire [6:0] rotator_shift; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" *) + wire rotator_sign_ext_rs; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \sr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \sr_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \sr_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__input_cr$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \sr_op__insn$18 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \sr_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__invert_in$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__output_carry$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__output_cr$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$19 ; + rotator rotator ( + .arith(rotator_arith), + .carry_out_o(rotator_carry_out_o), + .clear_left(rotator_clear_left), + .clear_right(rotator_clear_right), + .is_32bit(rotator_is_32bit), + .mb(rotator_mb), + .mb_extra(rotator_mb_extra), + .me(rotator_me), + .ra(rotator_ra), + .result_o(rotator_result_o), + .right_shift(rotator_right_shift), + .rs(rotator_rs), + .shift(rotator_shift), + .sign_ext_rs(rotator_sign_ext_rs) + ); + always @* begin + if (\initial ) begin end + o_ok = 1'h1; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" *) + casez (sr_op__insn_type) + /* \nmigen.decoding = "OP_SHL/60" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71" */ + 7'h3c: + /* empty */; + /* \nmigen.decoding = "OP_SHR/61" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72" */ + 7'h3d: + /* empty */; + /* \nmigen.decoding = "OP_RLC/56" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73" */ + 7'h38: + /* empty */; + /* \nmigen.decoding = "OP_RLCL/57" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:74" */ + 7'h39: + /* empty */; + /* \nmigen.decoding = "OP_RLCR/58" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:75" */ + 7'h3a: + /* empty */; + /* \nmigen.decoding = "OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:76" */ + 7'h20: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:77" */ + default: + o_ok = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + mode = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" *) + casez (sr_op__insn_type) + /* \nmigen.decoding = "OP_SHL/60" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71" */ + 7'h3c: + mode = 4'h0; + /* \nmigen.decoding = "OP_SHR/61" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72" */ + 7'h3d: + mode = 4'h1; + /* \nmigen.decoding = "OP_RLC/56" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73" */ + 7'h38: + mode = 4'h6; + /* \nmigen.decoding = "OP_RLCL/57" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:74" */ + 7'h39: + mode = 4'h2; + /* \nmigen.decoding = "OP_RLCR/58" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:75" */ + 7'h3a: + mode = 4'h4; + /* \nmigen.decoding = "OP_EXTSWSLI/32" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:76" */ + 7'h20: + mode = 4'h8; + endcase + end + assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$19 = xer_so; + assign xer_ca = { rotator_carry_out_o, rotator_carry_out_o }; + assign o = rotator_result_o; + assign { rotator_sign_ext_rs, rotator_clear_right, rotator_clear_left, rotator_right_shift } = mode; + assign rotator_arith = sr_op__is_signed; + assign rotator_is_32bit = sr_op__is_32bit; + assign rotator_shift = rb[6:0]; + assign rotator_ra = ra; + assign rotator_rs = rc; + assign rotator_mb_extra = mb_extra; + assign rotator_mb = mb; + assign rotator_me = me; + assign mb_extra = sr_op__insn[5]; + assign me = sr_op__insn[5:1]; + assign mb = sr_op__insn[10:6]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" *) +(* generator = "nMigen" *) +module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, cr_a, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \fast1$10 , fast1_ok, \fast2$11 , fast2_ok, nia, nia_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) + wire [64:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) + wire [64:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) + wire [64:0] \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) + wire [64:0] \$36 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) + wire [63:0] \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) + wire [64:0] \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) + wire [64:0] \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" *) + reg bc_taken; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" *) + wire [1:0] bi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" *) + wire [4:0] bo; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" *) + reg [63:0] br_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" *) + reg [63:0] br_imm_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] br_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \br_op__cia$2 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] br_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \br_op__fn_unit$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] br_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \br_op__imm_data__data$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \br_op__imm_data__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] br_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \br_op__insn$5 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] br_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \br_op__insn_type$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \br_op__is_32bit$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \br_op__lk$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" *) + reg br_taken; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" *) + reg cr_bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" *) + reg [63:0] ctr_m; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" *) + reg [63:0] ctr_n; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" *) + reg ctr_write; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" *) + reg ctr_zero_bo1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast1$10 ; + reg [63:0] \fast1$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + reg fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast2$11 ; + reg [63:0] \fast2$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + reg fast2_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + assign \$12 = br_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) 7'h08; + assign \$14 = br_op__insn[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) \$12 ; + assign \$17 = br_imm_addr + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) br_op__cia; + assign \$19 = cr_bit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[3]; + assign \$21 = \$19 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[4]; + assign \$23 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) 1'h0; + assign \$25 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *) 1'h1; + assign \$27 = bo[4] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *) 1'h1; + assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) cr_bit; + assign \$31 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) \$29 ; + assign \$33 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) cr_bit; + assign \$36 = fast1 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) 1'h1; + assign \$38 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) fast1[31:0]; + assign \$40 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) ctr_n; + assign \$42 = bo[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) \$40 ; + assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) br_op__insn[6]; + assign \$46 = br_op__insn[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) \$44 ; + assign \$49 = br_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) 3'h4; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) + casez (\$14 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" */ + 1'h1: + br_addr = br_imm_addr; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:94" */ + default: + br_addr = \$16 [63:0]; + endcase + end + always @* begin + if (\initial ) begin end + br_imm_addr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" *) + casez (br_op__insn_type) + /* \nmigen.decoding = "OP_B/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" */ + 7'h06: + br_imm_addr = { br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25:2], 2'h0 }; + /* \nmigen.decoding = "OP_BC/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" */ + 7'h07: + br_imm_addr = { br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15:2], 2'h0 }; + /* \nmigen.decoding = "OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" */ + 7'h08: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) + casez (\$46 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" */ + 1'h1: + br_imm_addr = { fast1[63:2], 2'h0 }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:162" */ + default: + br_imm_addr = { fast2[63:2], 2'h0 }; + endcase + endcase + end + always @* begin + if (\initial ) begin end + br_taken = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" *) + casez (br_op__insn_type) + /* \nmigen.decoding = "OP_B/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" */ + 7'h06: + br_taken = 1'h1; + /* \nmigen.decoding = "OP_BC/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" */ + 7'h07: + br_taken = bc_taken; + /* \nmigen.decoding = "OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" */ + 7'h08: + br_taken = bc_taken; + endcase + end + always @* begin + if (\initial ) begin end + fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" *) + casez (br_op__insn_type) + /* \nmigen.decoding = "OP_B/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" */ + 7'h06: + /* empty */; + /* \nmigen.decoding = "OP_BC/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" */ + 7'h07: + fast1_ok = ctr_write; + /* \nmigen.decoding = "OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" */ + 7'h08: + fast1_ok = ctr_write; + endcase + end + always @* begin + if (\initial ) begin end + \fast2$11 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" *) + casez (br_op__lk) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" */ + 1'h1: + \fast2$11 = \$48 [63:0]; + endcase + end + always @* begin + if (\initial ) begin end + fast2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" *) + casez (br_op__lk) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" */ + 1'h1: + fast2_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" *) + casez (bi) + 2'h0: + cr_bit = cr_a[3]; + 2'h1: + cr_bit = cr_a[2]; + 2'h2: + cr_bit = cr_a[1]; + 2'h?: + cr_bit = cr_a[0]; + endcase + end + always @* begin + if (\initial ) begin end + ctr_write = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) + casez (bo[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ + default: + ctr_write = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + bc_taken = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) + casez (bo[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ + 1'h1: + bc_taken = \$21 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) + casez ({ \$27 , \$25 , \$23 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" */ + 3'b??1: + bc_taken = \$31 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" */ + 3'b?1?: + bc_taken = \$33 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" */ + 3'b1??: + bc_taken = ctr_zero_bo1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + ctr_n = 64'h0000000000000000; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) + casez (bo[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ + default: + ctr_n = \$35 [63:0]; + endcase + end + always @* begin + if (\initial ) begin end + \fast1$10 = 64'h0000000000000000; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) + casez (bo[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ + default: + \fast1$10 = ctr_n; + endcase + end + always @* begin + if (\initial ) begin end + ctr_m = 64'h0000000000000000; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) + casez (bo[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ + default: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" *) + casez (br_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" */ + 1'h1: + ctr_m = \$38 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" */ + default: + ctr_m = fast1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + ctr_zero_bo1 = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) + casez (bo[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ + default: + ctr_zero_bo1 = \$42 ; + endcase + end + assign \$16 = \$17 ; + assign \$35 = \$36 ; + assign \$48 = \$49 ; + assign { \br_op__is_32bit$9 , \br_op__lk$8 , \br_op__imm_data__ok$7 , \br_op__imm_data__data$6 , \br_op__insn$5 , \br_op__fn_unit$4 , \br_op__insn_type$3 , \br_op__cia$2 } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; + assign \muxid$1 = muxid; + assign nia_ok = br_taken; + assign nia = br_addr; + assign bi = br_op__insn[17:16]; + assign bo = br_op__insn[25:21]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" *) +(* generator = "nMigen" *) +module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , o, o_ok, \fast1$11 , fast1_ok, \fast2$12 , fast2_ok, nia, nia_ok, msr, msr_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) + wire [63:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) + wire [63:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) + wire [4:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) + wire [63:0] \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) + wire [19:0] \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *) + wire [64:0] \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *) + wire [64:0] \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *) + wire [7:0] \$45 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) + wire [7:0] \$49 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) + wire [7:0] \$53 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) + wire [7:0] \$57 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *) + wire [7:0] \$64 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) + wire [7:0] \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [64:0] \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" *) + reg [63:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" *) + reg [63:0] a_s; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:142" *) + reg [63:0] b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:139" *) + reg [63:0] b_s; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" *) + wire equal; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast1$11 ; + reg [63:0] \fast1$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + reg fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast2$12 ; + reg [63:0] \fast2$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + reg fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" *) + wire gt_s; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" *) + wire gt_u; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" *) + wire lt_s; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" *) + wire lt_u; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] msr; + reg [63:0] msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output msr_ok; + reg msr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] nia; + reg [63:0] nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + reg nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" *) + wire should_trap; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" *) + wire [4:0] to; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *) + wire [4:0] trap_bits; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] trap_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \trap_op__cia$6 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] trap_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \trap_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] trap_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \trap_op__insn$4 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] trap_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \trap_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input trap_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \trap_op__is_32bit$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [7:0] \trap_op__ldst_exc$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] trap_op__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \trap_op__msr$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [12:0] trap_op__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [12:0] \trap_op__trapaddr$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] trap_op__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [7:0] \trap_op__traptype$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \trapexc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \trapexc_$signal$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \trapexc_$signal$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \trapexc_$signal$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \trapexc_$signal$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \trapexc_$signal$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \trapexc_$signal$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \trapexc_$signal$70 ; + assign \$13 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ra[31:0]; + assign \$15 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) rb[31:0]; + assign \$17 = $signed(a_s) < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" *) $signed(b_s); + assign \$19 = $signed(a_s) > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" *) $signed(b_s); + assign \$21 = a < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" *) b; + assign \$23 = a > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" *) b; + assign \$25 = a == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" *) b; + assign \$28 = trap_bits & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) to; + assign \$27 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) \$28 ; + assign \$31 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) trap_op__traptype; + assign \$33 = \$27 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) \$31 ; + assign \$36 = trap_op__trapaddr <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) 3'h4; + assign \$35 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) \$36 ; + assign \$40 = trap_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *) 3'h4; + assign \$42 = trap_op__traptype == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *) 1'h0; + assign \$45 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *) 2'h2; + assign \$44 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$45 ; + assign \$49 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) 1'h1; + assign \$48 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$49 ; + assign \$53 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) 4'h8; + assign \$52 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$53 ; + assign \$57 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) 7'h40; + assign \$56 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$57 ; + assign \$64 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *) 8'h80; + assign \$63 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$64 ; + assign \$72 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) 7'h40; + assign \$71 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$72 ; + assign \$75 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) trap_op__msr; + assign \$77 = trap_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *) 7'h48; + assign \$79 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" *) 3'h2; + assign \$81 = ra[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) 3'h0; + assign \$83 = \$79 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) \$81 ; + assign \$85 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *) trap_op__msr[60]; + assign \$87 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *) trap_op__insn[9]; + assign \$89 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" *) 3'h2; + assign \$91 = fast2[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) 3'h0; + assign \$93 = \$89 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) \$91 ; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) + casez (trap_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ + 1'h1: + a_s = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" */ + default: + a_s = ra; + endcase + end + always @* begin + if (\initial ) begin end + nia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + 1'h1: + nia = \$35 ; + endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + 7'h46: + nia = { fast1[63:2], 2'h0 }; + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + 7'h49: + nia = 64'h0000000000000c00; + endcase + end + always @* begin + if (\initial ) begin end + nia_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + 1'h1: + nia_ok = 1'h1; + endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + 7'h46: + nia_ok = 1'h1; + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + 7'h49: + nia_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \fast1$11 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + 1'h1: + \fast1$11 = trap_op__cia; + endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + 7'h46: + /* empty */; + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + 7'h49: + \fast1$11 = \$39 [63:0]; + endcase + end + always @* begin + if (\initial ) begin end + fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + 1'h1: + fast1_ok = 1'h1; + endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + 7'h46: + /* empty */; + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + 7'h49: + fast1_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \fast2$12 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + 1'h1: + begin + \fast2$12 = 64'h0000000000000000; + \fast2$12 [15:0] = trap_op__msr[15:0]; + \fast2$12 [26:22] = trap_op__msr[26:22]; + \fast2$12 [63:31] = trap_op__msr[63:31]; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *) + casez (\$42 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" */ + 1'h1: + \fast2$12 [17] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *) + casez (\$44 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ + 1'h1: + \fast2$12 [18] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) + casez (\$48 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ + 1'h1: + \fast2$12 [20] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) + casez (\$52 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" */ + 1'h1: + \fast2$12 [16] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) + casez (\$56 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" */ + 1'h1: + begin + \fast2$12 [30] = \trapexc_$signal ; + \fast2$12 [28] = \trapexc_$signal$60 ; + \fast2$12 [19] = \trapexc_$signal$61 ; + \fast2$12 [18] = \trapexc_$signal$62 ; + end + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *) + casez (\$63 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" */ + 1'h1: + \fast2$12 [19] = 1'h1; + endcase + end + endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + 7'h46: + /* empty */; + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + 7'h49: + begin + \fast2$12 = 64'h0000000000000000; + \fast2$12 [15:0] = trap_op__msr[15:0]; + \fast2$12 [26:22] = trap_op__msr[26:22]; + \fast2$12 [63:31] = trap_op__msr[63:31]; + end + endcase + end + always @* begin + if (\initial ) begin end + fast2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + 1'h1: + fast2_ok = 1'h1; + endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + 7'h46: + /* empty */; + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + 7'h49: + fast2_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \trapexc_$signal$67 = 1'h0; + \trapexc_$signal$68 = 1'h0; + \trapexc_$signal$69 = 1'h0; + \trapexc_$signal = 1'h0; + \trapexc_$signal$61 = 1'h0; + \trapexc_$signal$60 = 1'h0; + \trapexc_$signal$62 = 1'h0; + \trapexc_$signal$70 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) + casez (\$71 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" */ + 1'h1: + { \trapexc_$signal$70 , \trapexc_$signal$62 , \trapexc_$signal$60 , \trapexc_$signal$61 , \trapexc_$signal , \trapexc_$signal$69 , \trapexc_$signal$68 , \trapexc_$signal$67 } = trap_op__ldst_exc; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) + casez (trap_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ + 1'h1: + b_s = { rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31:0] }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" */ + default: + b_s = rb; + endcase + end + always @* begin + if (\initial ) begin end + msr = 64'h0000000000000000; + msr_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + 1'h1: + begin + msr = trap_op__msr; + msr[63] = 1'h1; + msr[15] = 1'h0; + msr[14] = 1'h0; + msr[5] = 1'h0; + msr[4] = 1'h0; + msr[1] = 1'h0; + msr[0] = 1'h1; + msr[11] = 1'h0; + msr[8] = 1'h0; + msr[23] = 1'h0; + msr[32] = 1'h0; + msr[25] = 1'h0; + msr[13] = 1'h0; + msr[3] = 1'h0; + msr[10] = 1'h0; + msr[9] = 1'h0; + msr[58] = 1'h0; + msr_ok = 1'h1; + end + endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + begin + { msr_ok, msr } = \$75 ; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" *) + casez (trap_op__insn[21]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" */ + 1'h1: + begin + msr[1] = ra[1]; + msr[15] = ra[15]; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" */ + default: + begin + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *) + casez (\$77 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" */ + 1'h1: + begin + msr[11:1] = ra[11:1]; + msr[59:13] = ra[59:13]; + msr[63:61] = ra[63:61]; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) + casez (\$83 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" */ + 1'h1: + msr[34:32] = trap_op__msr[34:32]; + endcase + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:244" */ + default: + begin + msr[11:1] = ra[11:1]; + msr[31:13] = ra[31:13]; + end + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" *) + casez (msr[14]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" */ + 1'h1: + begin + msr[15] = 1'h1; + msr[5] = 1'h1; + msr[4] = 1'h1; + end + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *) + casez (\$85 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" */ + 1'h1: + begin + msr[60] = trap_op__msr[60]; + msr[12] = trap_op__msr[12]; + end + endcase + begin + msr_ok = 1'h1; + end + end + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + 7'h46: + begin + msr[15:0] = fast2[15:0]; + msr[26:22] = fast2[26:22]; + msr[63:31] = fast2[63:31]; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *) + casez (\$87 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" *) + casez (trap_op__msr[60]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" */ + 1'h1: + msr[12] = fast2[12]; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ + default: + msr[12] = trap_op__msr[12]; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" *) + casez (msr[14]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" */ + 1'h1: + begin + msr[15] = 1'h1; + msr[5] = 1'h1; + msr[4] = 1'h1; + end + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) + casez (\$93 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" */ + 1'h1: + msr[34:32] = trap_op__msr[34:32]; + endcase + begin + msr_ok = 1'h1; + end + end + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + 7'h49: + begin + msr = trap_op__msr; + msr[63] = 1'h1; + msr[15] = 1'h0; + msr[14] = 1'h0; + msr[5] = 1'h0; + msr[4] = 1'h0; + msr[1] = 1'h0; + msr[0] = 1'h1; + msr[11] = 1'h0; + msr[8] = 1'h0; + msr[23] = 1'h0; + msr[32] = 1'h0; + msr[25] = 1'h0; + msr[13] = 1'h0; + msr[3] = 1'h0; + msr[10] = 1'h0; + msr[9] = 1'h0; + msr[58] = 1'h0; + msr_ok = 1'h1; + end + endcase + end + always @* begin + if (\initial ) begin end + o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + /* empty */; + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + o = trap_op__msr; + endcase + end + always @* begin + if (\initial ) begin end + o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + 7'h3f: + /* empty */; + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + 7'h47: + o_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) + casez (trap_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ + 1'h1: + a = \$13 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" */ + default: + a = ra; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) + casez (trap_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ + 1'h1: + b = \$15 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" */ + default: + b = rb; + endcase + end + assign \$39 = \$40 ; + assign { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; + assign \muxid$1 = muxid; + assign should_trap = \$33 ; + assign trap_bits = { lt_s, gt_s, equal, lt_u, gt_u }; + assign equal = \$25 ; + assign gt_u = \$23 ; + assign lt_u = \$21 ; + assign gt_s = \$19 ; + assign lt_s = \$17 ; + assign to = trap_op__insn[25:21]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" *) +(* generator = "nMigen" *) +module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, \xer_so$20 , muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$117 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$119 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$125 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$127 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$129 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$131 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$133 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$135 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$137 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$141 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$143 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$145 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$147 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$149 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$151 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$153 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) + wire \$155 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) + wire [63:0] \$157 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) + wire \$158 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) + wire [63:0] \$161 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) + wire [7:0] \$162 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) + wire [7:0] \$164 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) + wire [7:0] \$166 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \$169 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *) + wire \$171 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *) + wire \$173 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) + wire [63:0] \$175 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) + wire [31:0] \$176 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *) + wire [63:0] \$179 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *) + wire [63:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *) + wire [63:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *) + wire [63:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:103" *) + reg [31:0] a32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" *) + reg [63:0] b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" *) + wire [63:0] bpermd_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" *) + reg [63:0] bpermd_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" *) + reg [63:0] bpermd_rs; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) + wire [6:0] clz_lz; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" *) + reg [63:0] clz_sig_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" *) + reg [63:0] cntz_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" *) + reg count_right; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" *) + reg par0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" *) + reg par1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" *) + reg [63:0] popcount_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" *) + reg [63:0] popcount_data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" *) + wire [63:0] popcount_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$20 ; + assign \$99 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$101 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$103 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$105 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$107 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$109 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$111 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$113 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$115 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$117 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$119 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$121 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$123 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$125 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$127 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$129 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$131 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$133 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$135 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$137 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$139 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$141 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$143 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$145 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$147 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$149 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$151 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$153 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$155 = logical_op__data_len[3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) 1'h1; + assign \$158 = par0 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) par1; + assign \$157 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) \$158 ; + assign \$162 = clz_lz - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) 6'h20; + assign \$164 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) clz_lz; + assign \$166 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$162 : \$164 ; + assign \$161 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$166 ; + assign \$169 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) logical_op__data_len; + assign \$171 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *) { ra[24], ra[16], ra[8], ra[0] }; + assign \$173 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *) { ra[56], ra[48], ra[40], ra[32] }; + assign \$176 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) { a32[0], a32[1], a32[2], a32[3], a32[4], a32[5], a32[6], a32[7], a32[8], a32[9], a32[10], a32[11], a32[12], a32[13], a32[14], a32[15], a32[16], a32[17], a32[18], a32[19], a32[20], a32[21], a32[22], a32[23], a32[24], a32[25], a32[26], a32[27], a32[28], a32[29], a32[30], a32[31] } : a32; + assign \$175 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) \$176 ; + assign \$179 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *) { ra[0], ra[1], ra[2], ra[3], ra[4], ra[5], ra[6], ra[7], ra[8], ra[9], ra[10], ra[11], ra[12], ra[13], ra[14], ra[15], ra[16], ra[17], ra[18], ra[19], ra[20], ra[21], ra[22], ra[23], ra[24], ra[25], ra[26], ra[27], ra[28], ra[29], ra[30], ra[31], ra[32], ra[33], ra[34], ra[35], ra[36], ra[37], ra[38], ra[39], ra[40], ra[41], ra[42], ra[43], ra[44], ra[45], ra[46], ra[47], ra[48], ra[49], ra[50], ra[51], ra[52], ra[53], ra[54], ra[55], ra[56], ra[57], ra[58], ra[59], ra[60], ra[61], ra[62], ra[63] } : ra; + assign \$21 = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *) rb; + assign \$23 = ra | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *) rb; + assign \$25 = ra ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *) rb; + assign \$27 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$29 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$31 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$33 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$35 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$37 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$39 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$41 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$43 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$45 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$47 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$49 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$51 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$53 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$55 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$57 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$59 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$61 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$63 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$65 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$67 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$69 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$71 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$73 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$75 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$77 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$79 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$81 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$83 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$85 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$87 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$89 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$91 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$93 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$95 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$97 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + bpermd bpermd ( + .ra(bpermd_ra), + .rb(bpermd_rb), + .rs(bpermd_rs) + ); + clz clz ( + .lz(clz_lz), + .sig_in(clz_sig_in) + ); + popcount popcount ( + .a(popcount_a), + .data_len(popcount_data_len), + .o(popcount_o) + ); + always @* begin + if (\initial ) begin end + o = 64'h0000000000000000; + o_ok = 1'h1; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + o = \$21 ; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + o = \$23 ; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + o = \$25 ; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + o = { \$139 , \$141 , \$143 , \$145 , \$147 , \$149 , \$151 , \$153 , \$123 , \$125 , \$127 , \$129 , \$131 , \$133 , \$135 , \$137 , \$107 , \$109 , \$111 , \$113 , \$115 , \$117 , \$119 , \$121 , \$91 , \$93 , \$95 , \$97 , \$99 , \$101 , \$103 , \$105 , \$75 , \$77 , \$79 , \$81 , \$83 , \$85 , \$87 , \$89 , \$59 , \$61 , \$63 , \$65 , \$67 , \$69 , \$71 , \$73 , \$43 , \$45 , \$47 , \$49 , \$51 , \$53 , \$55 , \$57 , \$27 , \$29 , \$31 , \$33 , \$35 , \$37 , \$39 , \$41 }; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + o = popcount_o; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) + casez (\$155 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" */ + 1'h1: + o = \$157 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:90" */ + default: + begin + o[0] = par0; + o[32] = par1; + end + endcase + /* \nmigen.decoding = "OP_CNTZ/14" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ + 7'h0e: + o = \$161 ; + /* \nmigen.decoding = "OP_BPERM/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" */ + 7'h09: + o = bpermd_ra; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" */ + default: + o_ok = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + clz_sig_in = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + /* empty */; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + /* empty */; + /* \nmigen.decoding = "OP_CNTZ/14" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ + 7'h0e: + clz_sig_in = cntz_i; + endcase + end + always @* begin + if (\initial ) begin end + bpermd_rs = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + /* empty */; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + /* empty */; + /* \nmigen.decoding = "OP_CNTZ/14" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ + 7'h0e: + /* empty */; + /* \nmigen.decoding = "OP_BPERM/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" */ + 7'h09: + bpermd_rs = ra; + endcase + end + always @* begin + if (\initial ) begin end + bpermd_rb = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + /* empty */; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + /* empty */; + /* \nmigen.decoding = "OP_CNTZ/14" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ + 7'h0e: + /* empty */; + /* \nmigen.decoding = "OP_BPERM/9" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" */ + 7'h09: + bpermd_rb = rb; + endcase + end + always @* begin + if (\initial ) begin end + popcount_a = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + popcount_a = ra; + endcase + end + always @* begin + if (\initial ) begin end + b = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + b = rb; + endcase + end + always @* begin + if (\initial ) begin end + popcount_data_len = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + popcount_data_len = \$169 ; + endcase + end + always @* begin + if (\initial ) begin end + par0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + /* empty */; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + par0 = \$171 ; + endcase + end + always @* begin + if (\initial ) begin end + par1 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + /* empty */; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + par1 = \$173 ; + endcase + end + always @* begin + if (\initial ) begin end + count_right = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + /* empty */; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + /* empty */; + /* \nmigen.decoding = "OP_CNTZ/14" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ + 7'h0e: + count_right = logical_op__insn[10]; + endcase + end + always @* begin + if (\initial ) begin end + a32 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + /* empty */; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + /* empty */; + /* \nmigen.decoding = "OP_CNTZ/14" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ + 7'h0e: + a32 = ra[31:0]; + endcase + end + always @* begin + if (\initial ) begin end + cntz_i = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_AND/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ + 7'h04: + /* empty */; + /* \nmigen.decoding = "OP_OR/53" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ + 7'h35: + /* empty */; + /* \nmigen.decoding = "OP_XOR/67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ + 7'h43: + /* empty */; + /* \nmigen.decoding = "OP_CMPB/11" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ + 7'h0b: + /* empty */; + /* \nmigen.decoding = "OP_POPCNT/54" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ + 7'h36: + /* empty */; + /* \nmigen.decoding = "OP_PRTY/55" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ + 7'h37: + /* empty */; + /* \nmigen.decoding = "OP_CNTZ/14" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ + 7'h0e: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" *) + casez (logical_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" */ + 1'h1: + cntz_i = \$175 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108" */ + default: + cntz_i = \$179 ; + endcase + endcase + end + assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$20 = xer_so; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" *) +(* generator = "nMigen" *) +module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, cr_a, cr_b, cr_c, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , o, o_ok, \full_cr$5 , full_cr_ok, \cr_a$6 , cr_a_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) + wire [2:0] \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) + wire [2:0] \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) + wire [2:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) + wire [64:0] \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) + wire [63:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [4:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" *) + reg [1:0] BC; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" *) + reg [1:0] ba; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" *) + reg [1:0] bb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" *) + reg bit_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" *) + reg bit_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" *) + reg bit_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" *) + reg [1:0] bt; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$6 ; + reg [3:0] \cr_a$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + reg cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" *) + reg cr_bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_c; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] cr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \cr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] cr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \cr_op__insn$4 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] cr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \cr_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [31:0] full_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [31:0] \full_cr$5 ; + reg [31:0] \full_cr$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output full_cr_ok; + reg full_cr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" *) + reg [3:0] lut; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + assign \$10 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) cr_op__insn[22:21]; + assign \$13 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) cr_op__insn[17:16]; + assign \$16 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) cr_op__insn[12:11]; + assign \$18 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *) lut[3] : lut[1]; + assign \$20 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) lut[2] : lut[0]; + assign \$22 = bit_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) \$18 : \$20 ; + assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) full_cr; + assign \$27 = cr_bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) ra : rb; + assign \$26 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) \$27 ; + assign \$7 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) cr_a; + always @* begin + if (\initial ) begin end + \cr_a$6 = 4'h0; + cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + begin + { cr_a_ok, \cr_a$6 } = \$7 ; + cr_a_ok = 1'h1; + end + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + begin + \cr_a$6 = cr_c; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" *) + casez (bt) + 2'h0: + \cr_a$6 [0] = bit_o; + 2'h1: + \cr_a$6 [1] = bit_o; + 2'h2: + \cr_a$6 [2] = bit_o; + 2'h?: + \cr_a$6 [3] = bit_o; + endcase + begin + cr_a_ok = 1'h1; + end + end + endcase + end + always @* begin + if (\initial ) begin end + full_cr_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + /* empty */; + /* \nmigen.decoding = "OP_MTCRF/48" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" */ + 7'h30: + full_cr_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + o = 64'h0000000000000000; + o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + /* empty */; + /* \nmigen.decoding = "OP_MTCRF/48" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" */ + 7'h30: + /* empty */; + /* \nmigen.decoding = "OP_MFCR/45" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" */ + 7'h2d: + begin + o = \$24 ; + o_ok = 1'h1; + end + /* \nmigen.decoding = "OP_ISEL/35" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" */ + 7'h23: + begin + { o_ok, o } = \$26 ; + o_ok = 1'h1; + end + /* \nmigen.decoding = "OP_SETB/59" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" */ + 7'h3b: + begin + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" *) + casez ({ cr_a[2], cr_a[3] }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" */ + 2'b?1: + o = 64'hffffffffffffffff; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:146" */ + 2'b1?: + o = 64'h0000000000000001; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:148" */ + default: + o = 64'h0000000000000000; + endcase + begin + o_ok = 1'h1; + end + end + endcase + end + always @* begin + if (\initial ) begin end + BC = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + /* empty */; + /* \nmigen.decoding = "OP_MTCRF/48" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" */ + 7'h30: + /* empty */; + /* \nmigen.decoding = "OP_MFCR/45" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" */ + 7'h2d: + /* empty */; + /* \nmigen.decoding = "OP_ISEL/35" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" */ + 7'h23: + BC = cr_op__insn[7:6]; + endcase + end + always @* begin + if (\initial ) begin end + cr_bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + /* empty */; + /* \nmigen.decoding = "OP_MTCRF/48" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" */ + 7'h30: + /* empty */; + /* \nmigen.decoding = "OP_MFCR/45" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" */ + 7'h2d: + /* empty */; + /* \nmigen.decoding = "OP_ISEL/35" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" */ + 7'h23: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" *) + casez (BC) + 2'h0: + cr_bit = cr_a[3]; + 2'h1: + cr_bit = cr_a[2]; + 2'h2: + cr_bit = cr_a[1]; + 2'h?: + cr_bit = cr_a[0]; + endcase + endcase + end + always @* begin + if (\initial ) begin end + lut = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + lut = cr_op__insn[9:6]; + endcase + end + always @* begin + if (\initial ) begin end + bt = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + bt = \$9 [1:0]; + endcase + end + always @* begin + if (\initial ) begin end + ba = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + ba = \$12 [1:0]; + endcase + end + always @* begin + if (\initial ) begin end + bb = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + bb = \$15 [1:0]; + endcase + end + always @* begin + if (\initial ) begin end + bit_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" *) + casez (ba) + 2'h0: + bit_a = cr_a[0]; + 2'h1: + bit_a = cr_a[1]; + 2'h2: + bit_a = cr_a[2]; + 2'h?: + bit_a = cr_a[3]; + endcase + endcase + end + always @* begin + if (\initial ) begin end + bit_b = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" *) + casez (bb) + 2'h0: + bit_b = cr_b[0]; + 2'h1: + bit_b = cr_b[1]; + 2'h2: + bit_b = cr_b[2]; + 2'h?: + bit_b = cr_b[3]; + endcase + endcase + end + always @* begin + if (\initial ) begin end + bit_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + bit_o = \$22 ; + endcase + end + always @* begin + if (\initial ) begin end + \full_cr$5 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) + casez (cr_op__insn_type) + /* \nmigen.decoding = "OP_MCRF/42" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ + 7'h2a: + /* empty */; + /* \nmigen.decoding = "OP_CROP/69" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ + 7'h45: + /* empty */; + /* \nmigen.decoding = "OP_MTCRF/48" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" */ + 7'h30: + \full_cr$5 = ra[31:0]; + endcase + end + assign \$9 = \$10 ; + assign \$12 = \$13 ; + assign \$15 = \$16 ; + assign { \cr_op__insn$4 , \cr_op__fn_unit$3 , \cr_op__insn_type$2 } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; + assign \muxid$1 = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0" *) +(* generator = "nMigen" *) +module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [3:0] \$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [3:0] \$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$114 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$118 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$120 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [3:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [3:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [3:0] \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [3:0] \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [3:0] \$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [2:0] \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [3:0] \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [3:0] \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$80 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$82 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$84 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire \$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [2:0] \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] alu_mul0_cr_a; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_mul0_mul_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_mul0_mul_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_mul0_mul_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_mul0_mul_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_mul0_mul_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_mul0_mul_op__imm_data__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_mul0_mul_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_mul0_mul_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_mul0_mul_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_mul0_mul_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_mul0_mul_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_mul0_mul_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_mul0_mul_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_mul0_mul_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_mul0_mul_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_mul0_mul_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_mul0_mul_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_mul0_mul_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_mul0_mul_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_mul0_mul_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_mul0_mul_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_mul0_mul_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_mul0_mul_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_mul0_mul_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_mul0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_mul0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_mul0_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_mul0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_mul0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_mul0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_mul0_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] alu_mul0_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire alu_mul0_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \alu_mul0_xer_so$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [3:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [2:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [3:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [3:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [3:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] data_r1__cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] \data_r1__cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] data_r2__xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] \data_r2__xer_ov$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r2__xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r2__xer_ov_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__xer_so$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__xer_so_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] dest2_o; + reg [3:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest3_o; + reg [1:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output dest4_o; + reg dest4_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_mul0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_mul0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_mul0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_mul0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_mul0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [3:0] prev_wr_go = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [3:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [3:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [3:0] req_l_r_req = 4'hf; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [3:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [3:0] req_l_s_req = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [3:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [2:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [3:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input src3_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [2:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] src_l_r_src = 3'h7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] src_l_s_src = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] src_or_imm; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg src_r2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire src_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + assign \$100 = \$96 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$98 ; + assign \$102 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$104 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$106 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$108 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$10 = \$2 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$4 ; + assign \$110 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$102 , \$104 , \$106 , \$108 }; + assign \$112 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$114 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$116 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$118 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$120 = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$14 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$12 ; + assign \$16 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$18 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$16 ; + assign \$20 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$26 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; + assign \$23 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ; + assign \$22 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; + assign \$2 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$30 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$22 ; + assign \$32 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$36 = \$32 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$34 ; + assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_mul0_n_ready_i; + assign \$40 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$38 ; + assign \$42 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$44 = \$42 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$46 = \$40 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$44 ; + assign \$48 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$50 = \$48 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_mul0_n_ready_i; + assign \$52 = \$50 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_mul0_n_valid_o; + assign \$54 = \$52 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$56 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$58 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$60 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$62 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$64 = alu_mul0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$66 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$68 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$70 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$72 = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$74 = xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$76 = xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$78 = alu_mul0_mul_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1]; + assign \$7 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$80 = alu_mul0_mul_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_mul0_mul_op__imm_data__data : src2_i; + assign \$82 = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0; + assign \$84 = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r1; + assign \$86 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$88 = alu_mul0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$4 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$7 ; + assign \$90 = alu_mul0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$92 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$94 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_mul0_mul_op__imm_data__ok; + assign \$96 = \$92 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 1'h1, \$94 , 1'h1 }; + assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r3__xer_so <= \data_r3__xer_so$next ; + always @(posedge coresync_clk) + data_r3__xer_so_ok <= \data_r3__xer_so_ok$next ; + always @(posedge coresync_clk) + data_r2__xer_ov <= \data_r2__xer_ov$next ; + always @(posedge coresync_clk) + data_r2__xer_ov_ok <= \data_r2__xer_ov_ok$next ; + always @(posedge coresync_clk) + data_r1__cr_a <= \data_r1__cr_a$next ; + always @(posedge coresync_clk) + data_r1__cr_a_ok <= \data_r1__cr_a_ok$next ; + always @(posedge coresync_clk) + data_r0__o <= \data_r0__o$next ; + always @(posedge coresync_clk) + data_r0__o_ok <= \data_r0__o_ok$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__insn_type <= \alu_mul0_mul_op__insn_type$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__fn_unit <= \alu_mul0_mul_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__imm_data__data <= \alu_mul0_mul_op__imm_data__data$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__imm_data__ok <= \alu_mul0_mul_op__imm_data__ok$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__rc__rc <= \alu_mul0_mul_op__rc__rc$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__rc__ok <= \alu_mul0_mul_op__rc__ok$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__oe__oe <= \alu_mul0_mul_op__oe__oe$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__oe__ok <= \alu_mul0_mul_op__oe__ok$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__write_cr0 <= \alu_mul0_mul_op__write_cr0$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__is_32bit <= \alu_mul0_mul_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__is_signed <= \alu_mul0_mul_op__is_signed$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__insn <= \alu_mul0_mul_op__insn$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_mul0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$10 ; + \alu_l$107 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + alu_mul0 alu_mul0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(alu_mul0_cr_a), + .cr_a_ok(cr_a_ok), + .mul_op__fn_unit(alu_mul0_mul_op__fn_unit), + .mul_op__imm_data__data(alu_mul0_mul_op__imm_data__data), + .mul_op__imm_data__ok(alu_mul0_mul_op__imm_data__ok), + .mul_op__insn(alu_mul0_mul_op__insn), + .mul_op__insn_type(alu_mul0_mul_op__insn_type), + .mul_op__is_32bit(alu_mul0_mul_op__is_32bit), + .mul_op__is_signed(alu_mul0_mul_op__is_signed), + .mul_op__oe__oe(alu_mul0_mul_op__oe__oe), + .mul_op__oe__ok(alu_mul0_mul_op__oe__ok), + .mul_op__rc__ok(alu_mul0_mul_op__rc__ok), + .mul_op__rc__rc(alu_mul0_mul_op__rc__rc), + .mul_op__write_cr0(alu_mul0_mul_op__write_cr0), + .n_ready_i(alu_mul0_n_ready_i), + .n_valid_o(alu_mul0_n_valid_o), + .o(alu_mul0_o), + .o_ok(o_ok), + .p_ready_o(alu_mul0_p_ready_o), + .p_valid_i(alu_mul0_p_valid_i), + .ra(alu_mul0_ra), + .rb(alu_mul0_rb), + .xer_ov(alu_mul0_xer_ov), + .xer_ov_ok(xer_ov_ok), + .xer_so(alu_mul0_xer_so), + .\xer_so$1 (\alu_mul0_xer_so$1 ), + .xer_so_ok(xer_so_ok) + ); + \alui_l$106 alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + \opc_l$102 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \req_l$103 req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + \rok_l$105 rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + \rst_l$104 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$101 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$54 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$64 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$66 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$68 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 4'hf; + endcase + end + always @* begin + if (\initial ) begin end + \alu_mul0_mul_op__insn_type$next = alu_mul0_mul_op__insn_type; + \alu_mul0_mul_op__fn_unit$next = alu_mul0_mul_op__fn_unit; + \alu_mul0_mul_op__imm_data__data$next = alu_mul0_mul_op__imm_data__data; + \alu_mul0_mul_op__imm_data__ok$next = alu_mul0_mul_op__imm_data__ok; + \alu_mul0_mul_op__rc__rc$next = alu_mul0_mul_op__rc__rc; + \alu_mul0_mul_op__rc__ok$next = alu_mul0_mul_op__rc__ok; + \alu_mul0_mul_op__oe__oe$next = alu_mul0_mul_op__oe__oe; + \alu_mul0_mul_op__oe__ok$next = alu_mul0_mul_op__oe__ok; + \alu_mul0_mul_op__write_cr0$next = alu_mul0_mul_op__write_cr0; + \alu_mul0_mul_op__is_32bit$next = alu_mul0_mul_op__is_32bit; + \alu_mul0_mul_op__is_signed$next = alu_mul0_mul_op__is_signed; + \alu_mul0_mul_op__insn$next = alu_mul0_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_mul0_mul_op__insn$next , \alu_mul0_mul_op__is_signed$next , \alu_mul0_mul_op__is_32bit$next , \alu_mul0_mul_op__write_cr0$next , \alu_mul0_mul_op__oe__ok$next , \alu_mul0_mul_op__oe__oe$next , \alu_mul0_mul_op__rc__ok$next , \alu_mul0_mul_op__rc__rc$next , \alu_mul0_mul_op__imm_data__ok$next , \alu_mul0_mul_op__imm_data__data$next , \alu_mul0_mul_op__fn_unit$next , \alu_mul0_mul_op__insn_type$next } = { oper_i_alu_mul0__insn, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__insn_type }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \alu_mul0_mul_op__imm_data__data$next = 64'h0000000000000000; + \alu_mul0_mul_op__imm_data__ok$next = 1'h0; + \alu_mul0_mul_op__rc__rc$next = 1'h0; + \alu_mul0_mul_op__rc__ok$next = 1'h0; + \alu_mul0_mul_op__oe__oe$next = 1'h0; + \alu_mul0_mul_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__o$next = data_r0__o; + \data_r0__o_ok$next = data_r0__o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = { o_ok, alu_mul0_o }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__cr_a$next = data_r1__cr_a; + \data_r1__cr_a_ok$next = data_r1__cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = { cr_a_ok, alu_mul0_cr_a }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r2__xer_ov$next = data_r2__xer_ov; + \data_r2__xer_ov_ok$next = data_r2__xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = { xer_ov_ok, alu_mul0_xer_ov }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r2__xer_ov_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r3__xer_so$next = data_r3__xer_so; + \data_r3__xer_so_ok$next = data_r3__xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = { xer_so_ok, alu_mul0_xer_so }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r3__xer_so_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[0]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src1_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_sel) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = src_or_imm; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$88 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$90 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$114 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__o; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$116 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__cr_a; + endcase + end + always @* begin + if (\initial ) begin end + dest3_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$118 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest3_o = data_r2__xer_ov; + endcase + end + always @* begin + if (\initial ) begin end + dest4_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$120 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest4_o = data_r3__xer_so; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$20 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 4'h0; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$112 ; + assign cu_rd__rel_o = \$100 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_mul0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_mul0_p_valid_i = alui_l_q_alui; + assign \alu_mul0_xer_so$1 = \$86 ; + assign alu_mul0_rb = \$84 ; + assign alu_mul0_ra = \$82 ; + assign src_or_imm = \$80 ; + assign src_sel = \$78 ; + assign cu_wrmask_o = { \$76 , \$74 , \$72 , \$70 }; + assign reset_r = \$62 ; + assign reset_w = \$60 ; + assign rst_r = \$58 ; + assign reset = \$56 ; + assign wr_any = \$36 ; + assign cu_done_o = \$30 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$18 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_mul0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$14 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$10 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" *) +(* generator = "nMigen" *) +module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , neg_res, neg_res32, muxid); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) + wire [64:0] \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) + wire [64:0] \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [64:0] \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) + wire [64:0] \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) + wire [64:0] \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) + wire [64:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [64:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) + wire [64:0] \$45 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) + wire [31:0] \$47 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) + wire [31:0] \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" *) + wire [63:0] abs_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51" *) + wire [63:0] abs_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" *) + wire is_32bit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \mul_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \mul_op__insn$13 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \mul_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_32bit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_signed$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + output neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + output neg_res32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \ra$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rb$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" *) + wire sign32_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" *) + wire sign32_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" *) + wire sign_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" *) + wire sign_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$16 ; + assign \$17 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) ra[31] : ra[63]; + assign \$19 = \$17 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) mul_op__is_signed; + assign \$21 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) rb[31] : rb[63]; + assign \$23 = \$21 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) mul_op__is_signed; + assign \$25 = ra[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *) mul_op__is_signed; + assign \$27 = rb[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *) mul_op__is_signed; + assign \$29 = sign_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *) sign_b; + assign \$31 = sign32_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *) sign32_b; + assign \$34 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) ra; + assign \$36 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) ra; + assign \$38 = sign_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) \$34 : \$36 ; + assign \$41 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) rb; + assign \$43 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) rb; + assign \$45 = sign_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) \$41 : \$43 ; + assign \$47 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_a[63:32]; + assign \$49 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_b[63:32]; + assign \$33 = \$38 ; + assign \$40 = \$45 ; + assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$16 = xer_so; + assign \rb$15 [63:32] = \$49 ; + assign \rb$15 [31:0] = abs_b[31:0]; + assign \ra$14 [63:32] = \$47 ; + assign \ra$14 [31:0] = abs_a[31:0]; + assign abs_b = \$45 [63:0]; + assign abs_a = \$38 [63:0]; + assign neg_res32 = \$31 ; + assign neg_res = \$29 ; + assign sign32_b = \$27 ; + assign sign32_a = \$25 ; + assign sign_b = \$23 ; + assign sign_a = \$19 ; + assign is_32bit = mul_op__is_32bit; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" *) +(* generator = "nMigen" *) +module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , o, \xer_so$14 , \neg_res$15 , \neg_res32$16 , muxid); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) + wire [128:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) + wire [127:0] \$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \mul_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \mul_op__insn$13 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \mul_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_32bit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_signed$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + input neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + output \neg_res$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + input neg_res32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + output \neg_res32$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [128:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$14 ; + assign \$18 = ra * (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) rb; + assign \$17 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) \$18 ; + assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$14 = xer_so; + assign \neg_res32$16 = neg_res32; + assign \neg_res$15 = neg_res; + assign o = \$17 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" *) +(* generator = "nMigen" *) +module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, xer_so, neg_res, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , o_ok, xer_ov, xer_ov_ok, \xer_so$15 , xer_so_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) + wire [129:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) + wire [129:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [129:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) + wire [129:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" *) + wire is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" *) + wire [128:0] mul_o; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \mul_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \mul_op__insn$13 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \mul_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_32bit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_signed$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" *) + reg mul_ov; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + input neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [128:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$14 ; + reg [63:0] \o$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + reg [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + assign \$17 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) o; + assign \$19 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) o; + assign \$21 = neg_res ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) \$17 : \$19 ; + assign \$23 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31]; + assign \$26 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31]; + assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$26 ; + assign \$29 = \$23 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$25 ; + assign \$31 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63]; + assign \$34 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63]; + assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$34 ; + assign \$37 = \$31 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$33 ; + assign \$39 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) xer_so; + always @* begin + if (\initial ) begin end + \o$14 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *) + casez (mul_op__insn_type) + /* \nmigen.decoding = "OP_MUL_H32/52" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" */ + 7'h34: + \o$14 = { mul_o[63:32], mul_o[63:32] }; + /* \nmigen.decoding = "OP_MUL_H64/51" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" */ + 7'h33: + \o$14 = mul_o[127:64]; + /* \nmigen.decoding = "OP_MUL_L64/50" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" */ + 7'h32: + \o$14 = mul_o[63:0]; + endcase + end + always @* begin + if (\initial ) begin end + o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *) + casez (mul_op__insn_type) + /* \nmigen.decoding = "OP_MUL_H32/52" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" */ + 7'h34: + o_ok = 1'h1; + /* \nmigen.decoding = "OP_MUL_H64/51" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" */ + 7'h33: + o_ok = 1'h1; + /* \nmigen.decoding = "OP_MUL_L64/50" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" */ + 7'h32: + o_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + mul_ov = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *) + casez (mul_op__insn_type) + /* \nmigen.decoding = "OP_MUL_H32/52" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" */ + 7'h34: + /* empty */; + /* \nmigen.decoding = "OP_MUL_H64/51" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" */ + 7'h33: + /* empty */; + /* \nmigen.decoding = "OP_MUL_L64/50" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" */ + 7'h32: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" *) + casez (is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" */ + 1'h1: + mul_ov = \$29 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:66" */ + default: + mul_ov = \$37 ; + endcase + endcase + end + always @* begin + if (\initial ) begin end + xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *) + casez (mul_op__insn_type) + /* \nmigen.decoding = "OP_MUL_H32/52" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" */ + 7'h34: + /* empty */; + /* \nmigen.decoding = "OP_MUL_H64/51" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" */ + 7'h33: + /* empty */; + /* \nmigen.decoding = "OP_MUL_L64/50" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" */ + 7'h32: + xer_ov = { mul_ov, mul_ov }; + endcase + end + always @* begin + if (\initial ) begin end + xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *) + casez (mul_op__insn_type) + /* \nmigen.decoding = "OP_MUL_H32/52" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" */ + 7'h34: + /* empty */; + /* \nmigen.decoding = "OP_MUL_H64/51" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" */ + 7'h33: + /* empty */; + /* \nmigen.decoding = "OP_MUL_L64/50" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" */ + 7'h32: + xer_ov_ok = 1'h1; + endcase + end + assign \$16 = \$21 ; + assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \muxid$1 = muxid; + assign { xer_so_ok, \xer_so$15 } = \$39 ; + assign mul_o = \$21 [128:0]; + assign is_32bit = mul_op__is_32bit; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" *) +(* generator = "nMigen" *) +module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, p_valid_i, p_ready_o, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] input_mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \input_mul_op__fn_unit$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] input_mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \input_mul_op__imm_data__data$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_mul_op__imm_data__ok$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] input_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \input_mul_op__insn$29 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] input_mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \input_mul_op__insn_type$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_mul_op__is_32bit$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_mul_op__is_signed$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_mul_op__oe__oe$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_mul_op__oe__ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_mul_op__rc__ok$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_mul_op__rc__rc$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_mul_op__write_cr0$26 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] input_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \input_muxid$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_ra$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_rb$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire input_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \input_xer_so$32 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] mul1_mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul1_mul_op__fn_unit$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] mul1_mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul1_mul_op__imm_data__data$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul1_mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul1_mul_op__imm_data__ok$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] mul1_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul1_mul_op__insn$45 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] mul1_mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul1_mul_op__insn_type$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul1_mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul1_mul_op__is_32bit$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul1_mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul1_mul_op__is_signed$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul1_mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul1_mul_op__oe__oe$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul1_mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul1_mul_op__oe__ok$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul1_mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul1_mul_op__rc__ok$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul1_mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul1_mul_op__rc__rc$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul1_mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul1_mul_op__write_cr0$42 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] mul1_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \mul1_muxid$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + wire mul1_neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + wire mul1_neg_res32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] mul1_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \mul1_ra$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] mul1_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \mul1_rb$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire mul1_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \mul1_xer_so$48 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] mul_op__fn_unit; + reg [13:0] mul_op__fn_unit = 14'h0000; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] \mul_op__fn_unit$3 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul_op__fn_unit$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \mul_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] mul_op__imm_data__data; + reg [63:0] mul_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] \mul_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul_op__imm_data__data$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \mul_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output mul_op__imm_data__ok; + reg mul_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \mul_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__imm_data__ok$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__imm_data__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] mul_op__insn; + reg [31:0] mul_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] \mul_op__insn$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul_op__insn$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \mul_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] mul_op__insn_type; + reg [6:0] mul_op__insn_type = 7'h00; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] \mul_op__insn_type$2 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul_op__insn_type$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \mul_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output mul_op__is_32bit; + reg mul_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \mul_op__is_32bit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__is_32bit$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output mul_op__is_signed; + reg mul_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \mul_op__is_signed$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__is_signed$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output mul_op__oe__oe; + reg mul_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__oe__oe$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \mul_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output mul_op__oe__ok; + reg mul_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__oe__ok$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \mul_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output mul_op__rc__ok; + reg mul_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__rc__ok$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \mul_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output mul_op__rc__rc; + reg mul_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__rc__rc$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \mul_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output mul_op__write_cr0; + reg mul_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \mul_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__write_cr0$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] muxid; + reg [1:0] muxid = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$52 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + output neg_res; + reg neg_res = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + wire \neg_res$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + reg \neg_res$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + output neg_res32; + reg neg_res32 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + wire \neg_res32$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + reg \neg_res32$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$49 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] ra; + reg [63:0] ra = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \ra$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \ra$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \ra$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] rb; + reg [63:0] rb = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \rb$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \rb$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \rb$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output xer_so; + reg xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \xer_so$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg \xer_so$next ; + assign \$50 = \p_valid_i$49 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + neg_res32 <= \neg_res32$next ; + always @(posedge coresync_clk) + neg_res <= \neg_res$next ; + always @(posedge coresync_clk) + xer_so <= \xer_so$next ; + always @(posedge coresync_clk) + rb <= \rb$next ; + always @(posedge coresync_clk) + ra <= \ra$next ; + always @(posedge coresync_clk) + mul_op__insn_type <= \mul_op__insn_type$next ; + always @(posedge coresync_clk) + mul_op__fn_unit <= \mul_op__fn_unit$next ; + always @(posedge coresync_clk) + mul_op__imm_data__data <= \mul_op__imm_data__data$next ; + always @(posedge coresync_clk) + mul_op__imm_data__ok <= \mul_op__imm_data__ok$next ; + always @(posedge coresync_clk) + mul_op__rc__rc <= \mul_op__rc__rc$next ; + always @(posedge coresync_clk) + mul_op__rc__ok <= \mul_op__rc__ok$next ; + always @(posedge coresync_clk) + mul_op__oe__oe <= \mul_op__oe__oe$next ; + always @(posedge coresync_clk) + mul_op__oe__ok <= \mul_op__oe__ok$next ; + always @(posedge coresync_clk) + mul_op__write_cr0 <= \mul_op__write_cr0$next ; + always @(posedge coresync_clk) + mul_op__is_32bit <= \mul_op__is_32bit$next ; + always @(posedge coresync_clk) + mul_op__is_signed <= \mul_op__is_signed$next ; + always @(posedge coresync_clk) + mul_op__insn <= \mul_op__insn$next ; + always @(posedge coresync_clk) + muxid <= \muxid$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \input$95 \input ( + .mul_op__fn_unit(input_mul_op__fn_unit), + .\mul_op__fn_unit$3 (\input_mul_op__fn_unit$19 ), + .mul_op__imm_data__data(input_mul_op__imm_data__data), + .\mul_op__imm_data__data$4 (\input_mul_op__imm_data__data$20 ), + .mul_op__imm_data__ok(input_mul_op__imm_data__ok), + .\mul_op__imm_data__ok$5 (\input_mul_op__imm_data__ok$21 ), + .mul_op__insn(input_mul_op__insn), + .\mul_op__insn$13 (\input_mul_op__insn$29 ), + .mul_op__insn_type(input_mul_op__insn_type), + .\mul_op__insn_type$2 (\input_mul_op__insn_type$18 ), + .mul_op__is_32bit(input_mul_op__is_32bit), + .\mul_op__is_32bit$11 (\input_mul_op__is_32bit$27 ), + .mul_op__is_signed(input_mul_op__is_signed), + .\mul_op__is_signed$12 (\input_mul_op__is_signed$28 ), + .mul_op__oe__oe(input_mul_op__oe__oe), + .\mul_op__oe__oe$8 (\input_mul_op__oe__oe$24 ), + .mul_op__oe__ok(input_mul_op__oe__ok), + .\mul_op__oe__ok$9 (\input_mul_op__oe__ok$25 ), + .mul_op__rc__ok(input_mul_op__rc__ok), + .\mul_op__rc__ok$7 (\input_mul_op__rc__ok$23 ), + .mul_op__rc__rc(input_mul_op__rc__rc), + .\mul_op__rc__rc$6 (\input_mul_op__rc__rc$22 ), + .mul_op__write_cr0(input_mul_op__write_cr0), + .\mul_op__write_cr0$10 (\input_mul_op__write_cr0$26 ), + .muxid(input_muxid), + .\muxid$1 (\input_muxid$17 ), + .ra(input_ra), + .\ra$14 (\input_ra$30 ), + .rb(input_rb), + .\rb$15 (\input_rb$31 ), + .xer_so(input_xer_so), + .\xer_so$16 (\input_xer_so$32 ) + ); + mul1 mul1 ( + .mul_op__fn_unit(mul1_mul_op__fn_unit), + .\mul_op__fn_unit$3 (\mul1_mul_op__fn_unit$35 ), + .mul_op__imm_data__data(mul1_mul_op__imm_data__data), + .\mul_op__imm_data__data$4 (\mul1_mul_op__imm_data__data$36 ), + .mul_op__imm_data__ok(mul1_mul_op__imm_data__ok), + .\mul_op__imm_data__ok$5 (\mul1_mul_op__imm_data__ok$37 ), + .mul_op__insn(mul1_mul_op__insn), + .\mul_op__insn$13 (\mul1_mul_op__insn$45 ), + .mul_op__insn_type(mul1_mul_op__insn_type), + .\mul_op__insn_type$2 (\mul1_mul_op__insn_type$34 ), + .mul_op__is_32bit(mul1_mul_op__is_32bit), + .\mul_op__is_32bit$11 (\mul1_mul_op__is_32bit$43 ), + .mul_op__is_signed(mul1_mul_op__is_signed), + .\mul_op__is_signed$12 (\mul1_mul_op__is_signed$44 ), + .mul_op__oe__oe(mul1_mul_op__oe__oe), + .\mul_op__oe__oe$8 (\mul1_mul_op__oe__oe$40 ), + .mul_op__oe__ok(mul1_mul_op__oe__ok), + .\mul_op__oe__ok$9 (\mul1_mul_op__oe__ok$41 ), + .mul_op__rc__ok(mul1_mul_op__rc__ok), + .\mul_op__rc__ok$7 (\mul1_mul_op__rc__ok$39 ), + .mul_op__rc__rc(mul1_mul_op__rc__rc), + .\mul_op__rc__rc$6 (\mul1_mul_op__rc__rc$38 ), + .mul_op__write_cr0(mul1_mul_op__write_cr0), + .\mul_op__write_cr0$10 (\mul1_mul_op__write_cr0$42 ), + .muxid(mul1_muxid), + .\muxid$1 (\mul1_muxid$33 ), + .neg_res(mul1_neg_res), + .neg_res32(mul1_neg_res32), + .ra(mul1_ra), + .\ra$14 (\mul1_ra$46 ), + .rb(mul1_rb), + .\rb$15 (\mul1_rb$47 ), + .xer_so(mul1_xer_so), + .\xer_so$16 (\mul1_xer_so$48 ) + ); + \n$94 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$93 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$next = muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$next = \muxid$52 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$next = \muxid$52 ; + endcase + end + always @* begin + if (\initial ) begin end + \mul_op__insn_type$next = mul_op__insn_type; + \mul_op__fn_unit$next = mul_op__fn_unit; + \mul_op__imm_data__data$next = mul_op__imm_data__data; + \mul_op__imm_data__ok$next = mul_op__imm_data__ok; + \mul_op__rc__rc$next = mul_op__rc__rc; + \mul_op__rc__ok$next = mul_op__rc__ok; + \mul_op__oe__oe$next = mul_op__oe__oe; + \mul_op__oe__ok$next = mul_op__oe__ok; + \mul_op__write_cr0$next = mul_op__write_cr0; + \mul_op__is_32bit$next = mul_op__is_32bit; + \mul_op__is_signed$next = mul_op__is_signed; + \mul_op__insn$next = mul_op__insn; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \mul_op__imm_data__data$next = 64'h0000000000000000; + \mul_op__imm_data__ok$next = 1'h0; + \mul_op__rc__rc$next = 1'h0; + \mul_op__rc__ok$next = 1'h0; + \mul_op__oe__oe$next = 1'h0; + \mul_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \ra$next = ra; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \ra$next = \ra$65 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \ra$next = \ra$65 ; + endcase + end + always @* begin + if (\initial ) begin end + \rb$next = rb; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \rb$next = \rb$66 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \rb$next = \rb$66 ; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$next = xer_so; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \xer_so$next = \xer_so$67 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \xer_so$next = \xer_so$67 ; + endcase + end + always @* begin + if (\initial ) begin end + \neg_res$next = neg_res; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \neg_res$next = \neg_res$68 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \neg_res$next = \neg_res$68 ; + endcase + end + always @* begin + if (\initial ) begin end + \neg_res32$next = neg_res32; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \neg_res32$next = \neg_res32$69 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \neg_res32$next = \neg_res32$69 ; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign \neg_res32$69 = mul1_neg_res32; + assign \neg_res$68 = mul1_neg_res; + assign \xer_so$67 = \mul1_xer_so$48 ; + assign \rb$66 = \mul1_rb$47 ; + assign \ra$65 = \mul1_ra$46 ; + assign { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53 } = { \mul1_mul_op__insn$45 , \mul1_mul_op__is_signed$44 , \mul1_mul_op__is_32bit$43 , \mul1_mul_op__write_cr0$42 , \mul1_mul_op__oe__ok$41 , \mul1_mul_op__oe__oe$40 , \mul1_mul_op__rc__ok$39 , \mul1_mul_op__rc__rc$38 , \mul1_mul_op__imm_data__ok$37 , \mul1_mul_op__imm_data__data$36 , \mul1_mul_op__fn_unit$35 , \mul1_mul_op__insn_type$34 }; + assign \muxid$52 = \mul1_muxid$33 ; + assign p_valid_i_p_ready_o = \$50 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$49 = p_valid_i; + assign mul1_xer_so = \input_xer_so$32 ; + assign mul1_rb = \input_rb$31 ; + assign mul1_ra = \input_ra$30 ; + assign { mul1_mul_op__insn, mul1_mul_op__is_signed, mul1_mul_op__is_32bit, mul1_mul_op__write_cr0, mul1_mul_op__oe__ok, mul1_mul_op__oe__oe, mul1_mul_op__rc__ok, mul1_mul_op__rc__rc, mul1_mul_op__imm_data__ok, mul1_mul_op__imm_data__data, mul1_mul_op__fn_unit, mul1_mul_op__insn_type } = { \input_mul_op__insn$29 , \input_mul_op__is_signed$28 , \input_mul_op__is_32bit$27 , \input_mul_op__write_cr0$26 , \input_mul_op__oe__ok$25 , \input_mul_op__oe__oe$24 , \input_mul_op__rc__ok$23 , \input_mul_op__rc__rc$22 , \input_mul_op__imm_data__ok$21 , \input_mul_op__imm_data__data$20 , \input_mul_op__fn_unit$19 , \input_mul_op__insn_type$18 }; + assign mul1_muxid = \input_muxid$17 ; + assign input_xer_so = \xer_so$16 ; + assign input_rb = \rb$15 ; + assign input_ra = \ra$14 ; + assign { input_mul_op__insn, input_mul_op__is_signed, input_mul_op__is_32bit, input_mul_op__write_cr0, input_mul_op__oe__ok, input_mul_op__oe__oe, input_mul_op__rc__ok, input_mul_op__rc__rc, input_mul_op__imm_data__ok, input_mul_op__imm_data__data, input_mul_op__fn_unit, input_mul_op__insn_type } = { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 }; + assign input_muxid = \muxid$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" *) +(* generator = "nMigen" *) +module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , o, \xer_so$14 , \neg_res$15 , \neg_res32$16 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] mul2_mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul2_mul_op__fn_unit$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] mul2_mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul2_mul_op__imm_data__data$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul2_mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul2_mul_op__imm_data__ok$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] mul2_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul2_mul_op__insn$29 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] mul2_mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul2_mul_op__insn_type$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul2_mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul2_mul_op__is_32bit$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul2_mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul2_mul_op__is_signed$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul2_mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul2_mul_op__oe__oe$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul2_mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul2_mul_op__oe__ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul2_mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul2_mul_op__rc__ok$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul2_mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul2_mul_op__rc__rc$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul2_mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul2_mul_op__write_cr0$26 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] mul2_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \mul2_muxid$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + wire mul2_neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + wire \mul2_neg_res$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + wire mul2_neg_res32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + wire \mul2_neg_res32$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [128:0] mul2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] mul2_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] mul2_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire mul2_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \mul2_xer_so$30 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \mul_op__fn_unit$3 ; + reg [13:0] \mul_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \mul_op__fn_unit$3$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul_op__fn_unit$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul_op__imm_data__data$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \mul_op__imm_data__data$4 ; + reg [63:0] \mul_op__imm_data__data$4 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \mul_op__imm_data__data$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__imm_data__ok$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__imm_data__ok$5 ; + reg \mul_op__imm_data__ok$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__imm_data__ok$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \mul_op__insn$13 ; + reg [31:0] \mul_op__insn$13 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \mul_op__insn$13$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul_op__insn$48 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \mul_op__insn_type$2 ; + reg [6:0] \mul_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \mul_op__insn_type$2$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul_op__insn_type$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_32bit$11 ; + reg \mul_op__is_32bit$11 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__is_32bit$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__is_32bit$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_signed$12 ; + reg \mul_op__is_signed$12 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__is_signed$12$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__is_signed$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__oe__oe$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__oe$8 ; + reg \mul_op__oe__oe$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__oe__oe$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__oe__ok$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__ok$9 ; + reg \mul_op__oe__ok$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__oe__ok$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__rc__ok$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__ok$7 ; + reg \mul_op__rc__ok$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__rc__ok$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__rc__rc$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__rc$6 ; + reg \mul_op__rc__rc$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__rc__rc$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__write_cr0$10 ; + reg \mul_op__write_cr0$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__write_cr0$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__write_cr0$45 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$36 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) + input neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + output \neg_res$15 ; + reg \neg_res$15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + reg \neg_res$15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + wire \neg_res$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) + input neg_res32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + output \neg_res32$16 ; + reg \neg_res32$16 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + reg \neg_res32$16$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + wire \neg_res32$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [128:0] o; + reg [128:0] o = 129'h000000000000000000000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [128:0] \o$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [128:0] \o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$33 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$14 ; + reg \xer_so$14 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg \xer_so$14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \xer_so$50 ; + assign \$34 = \p_valid_i$33 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \neg_res32$16 <= \neg_res32$16$next ; + always @(posedge coresync_clk) + \neg_res$15 <= \neg_res$15$next ; + always @(posedge coresync_clk) + \xer_so$14 <= \xer_so$14$next ; + always @(posedge coresync_clk) + o <= \o$next ; + always @(posedge coresync_clk) + \mul_op__insn_type$2 <= \mul_op__insn_type$2$next ; + always @(posedge coresync_clk) + \mul_op__fn_unit$3 <= \mul_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \mul_op__imm_data__data$4 <= \mul_op__imm_data__data$4$next ; + always @(posedge coresync_clk) + \mul_op__imm_data__ok$5 <= \mul_op__imm_data__ok$5$next ; + always @(posedge coresync_clk) + \mul_op__rc__rc$6 <= \mul_op__rc__rc$6$next ; + always @(posedge coresync_clk) + \mul_op__rc__ok$7 <= \mul_op__rc__ok$7$next ; + always @(posedge coresync_clk) + \mul_op__oe__oe$8 <= \mul_op__oe__oe$8$next ; + always @(posedge coresync_clk) + \mul_op__oe__ok$9 <= \mul_op__oe__ok$9$next ; + always @(posedge coresync_clk) + \mul_op__write_cr0$10 <= \mul_op__write_cr0$10$next ; + always @(posedge coresync_clk) + \mul_op__is_32bit$11 <= \mul_op__is_32bit$11$next ; + always @(posedge coresync_clk) + \mul_op__is_signed$12 <= \mul_op__is_signed$12$next ; + always @(posedge coresync_clk) + \mul_op__insn$13 <= \mul_op__insn$13$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + mul2 mul2 ( + .mul_op__fn_unit(mul2_mul_op__fn_unit), + .\mul_op__fn_unit$3 (\mul2_mul_op__fn_unit$19 ), + .mul_op__imm_data__data(mul2_mul_op__imm_data__data), + .\mul_op__imm_data__data$4 (\mul2_mul_op__imm_data__data$20 ), + .mul_op__imm_data__ok(mul2_mul_op__imm_data__ok), + .\mul_op__imm_data__ok$5 (\mul2_mul_op__imm_data__ok$21 ), + .mul_op__insn(mul2_mul_op__insn), + .\mul_op__insn$13 (\mul2_mul_op__insn$29 ), + .mul_op__insn_type(mul2_mul_op__insn_type), + .\mul_op__insn_type$2 (\mul2_mul_op__insn_type$18 ), + .mul_op__is_32bit(mul2_mul_op__is_32bit), + .\mul_op__is_32bit$11 (\mul2_mul_op__is_32bit$27 ), + .mul_op__is_signed(mul2_mul_op__is_signed), + .\mul_op__is_signed$12 (\mul2_mul_op__is_signed$28 ), + .mul_op__oe__oe(mul2_mul_op__oe__oe), + .\mul_op__oe__oe$8 (\mul2_mul_op__oe__oe$24 ), + .mul_op__oe__ok(mul2_mul_op__oe__ok), + .\mul_op__oe__ok$9 (\mul2_mul_op__oe__ok$25 ), + .mul_op__rc__ok(mul2_mul_op__rc__ok), + .\mul_op__rc__ok$7 (\mul2_mul_op__rc__ok$23 ), + .mul_op__rc__rc(mul2_mul_op__rc__rc), + .\mul_op__rc__rc$6 (\mul2_mul_op__rc__rc$22 ), + .mul_op__write_cr0(mul2_mul_op__write_cr0), + .\mul_op__write_cr0$10 (\mul2_mul_op__write_cr0$26 ), + .muxid(mul2_muxid), + .\muxid$1 (\mul2_muxid$17 ), + .neg_res(mul2_neg_res), + .\neg_res$15 (\mul2_neg_res$31 ), + .neg_res32(mul2_neg_res32), + .\neg_res32$16 (\mul2_neg_res32$32 ), + .o(mul2_o), + .ra(mul2_ra), + .rb(mul2_rb), + .xer_so(mul2_xer_so), + .\xer_so$14 (\mul2_xer_so$30 ) + ); + \n$97 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$96 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$36 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$36 ; + endcase + end + always @* begin + if (\initial ) begin end + \mul_op__insn_type$2$next = \mul_op__insn_type$2 ; + \mul_op__fn_unit$3$next = \mul_op__fn_unit$3 ; + \mul_op__imm_data__data$4$next = \mul_op__imm_data__data$4 ; + \mul_op__imm_data__ok$5$next = \mul_op__imm_data__ok$5 ; + \mul_op__rc__rc$6$next = \mul_op__rc__rc$6 ; + \mul_op__rc__ok$7$next = \mul_op__rc__ok$7 ; + \mul_op__oe__oe$8$next = \mul_op__oe__oe$8 ; + \mul_op__oe__ok$9$next = \mul_op__oe__ok$9 ; + \mul_op__write_cr0$10$next = \mul_op__write_cr0$10 ; + \mul_op__is_32bit$11$next = \mul_op__is_32bit$11 ; + \mul_op__is_signed$12$next = \mul_op__is_signed$12 ; + \mul_op__insn$13$next = \mul_op__insn$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \mul_op__imm_data__data$4$next = 64'h0000000000000000; + \mul_op__imm_data__ok$5$next = 1'h0; + \mul_op__rc__rc$6$next = 1'h0; + \mul_op__rc__ok$7$next = 1'h0; + \mul_op__oe__oe$8$next = 1'h0; + \mul_op__oe__ok$9$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \o$next = o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \o$next = \o$49 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \o$next = \o$49 ; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$14$next = \xer_so$14 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \xer_so$14$next = \xer_so$50 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \xer_so$14$next = \xer_so$50 ; + endcase + end + always @* begin + if (\initial ) begin end + \neg_res$15$next = \neg_res$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \neg_res$15$next = \neg_res$51 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \neg_res$15$next = \neg_res$51 ; + endcase + end + always @* begin + if (\initial ) begin end + \neg_res32$16$next = \neg_res32$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \neg_res32$16$next = \neg_res32$52 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \neg_res32$16$next = \neg_res32$52 ; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign \neg_res32$52 = \mul2_neg_res32$32 ; + assign \neg_res$51 = \mul2_neg_res$31 ; + assign \xer_so$50 = \mul2_xer_so$30 ; + assign \o$49 = mul2_o; + assign { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37 } = { \mul2_mul_op__insn$29 , \mul2_mul_op__is_signed$28 , \mul2_mul_op__is_32bit$27 , \mul2_mul_op__write_cr0$26 , \mul2_mul_op__oe__ok$25 , \mul2_mul_op__oe__oe$24 , \mul2_mul_op__rc__ok$23 , \mul2_mul_op__rc__rc$22 , \mul2_mul_op__imm_data__ok$21 , \mul2_mul_op__imm_data__data$20 , \mul2_mul_op__fn_unit$19 , \mul2_mul_op__insn_type$18 }; + assign \muxid$36 = \mul2_muxid$17 ; + assign p_valid_i_p_ready_o = \$34 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$33 = p_valid_i; + assign mul2_neg_res32 = neg_res32; + assign mul2_neg_res = neg_res; + assign mul2_xer_so = xer_so; + assign mul2_rb = rb; + assign mul2_ra = ra; + assign { mul2_mul_op__insn, mul2_mul_op__is_signed, mul2_mul_op__is_32bit, mul2_mul_op__write_cr0, mul2_mul_op__oe__ok, mul2_mul_op__oe__oe, mul2_mul_op__rc__ok, mul2_mul_op__rc__rc, mul2_mul_op__imm_data__ok, mul2_mul_op__imm_data__data, mul2_mul_op__fn_unit, mul2_mul_op__insn_type } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign mul2_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" *) +(* generator = "nMigen" *) +module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$15 , xer_so_ok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + reg [3:0] cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + reg cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] mul3_mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul3_mul_op__fn_unit$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] mul3_mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul3_mul_op__imm_data__data$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul3_mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul3_mul_op__imm_data__ok$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] mul3_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul3_mul_op__insn$28 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] mul3_mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul3_mul_op__insn_type$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul3_mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul3_mul_op__is_32bit$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul3_mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul3_mul_op__is_signed$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul3_mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul3_mul_op__oe__oe$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul3_mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul3_mul_op__oe__ok$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul3_mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul3_mul_op__rc__ok$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul3_mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul3_mul_op__rc__rc$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire mul3_mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul3_mul_op__write_cr0$25 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] mul3_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \mul3_muxid$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + wire mul3_neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [128:0] mul3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \mul3_o$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire mul3_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] mul3_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire mul3_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire mul3_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \mul3_xer_so$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire mul3_xer_so_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \mul_op__fn_unit$3 ; + reg [13:0] \mul_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \mul_op__fn_unit$3$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \mul_op__fn_unit$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \mul_op__imm_data__data$4 ; + reg [63:0] \mul_op__imm_data__data$4 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \mul_op__imm_data__data$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \mul_op__imm_data__data$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__imm_data__ok$5 ; + reg \mul_op__imm_data__ok$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__imm_data__ok$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__imm_data__ok$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \mul_op__insn$13 ; + reg [31:0] \mul_op__insn$13 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \mul_op__insn$13$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \mul_op__insn$70 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \mul_op__insn_type$2 ; + reg [6:0] \mul_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \mul_op__insn_type$2$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \mul_op__insn_type$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_32bit$11 ; + reg \mul_op__is_32bit$11 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__is_32bit$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__is_32bit$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_signed$12 ; + reg \mul_op__is_signed$12 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__is_signed$12$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__is_signed$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__oe__oe$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__oe$8 ; + reg \mul_op__oe__oe$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__oe__oe$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__oe__ok$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__ok$9 ; + reg \mul_op__oe__ok$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__oe__ok$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__rc__ok$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__ok$7 ; + reg \mul_op__rc__ok$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__rc__ok$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__rc$6 ; + reg \mul_op__rc__rc$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__rc__rc$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__rc__rc$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__write_cr0$10 ; + reg \mul_op__write_cr0$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \mul_op__write_cr0$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \mul_op__write_cr0$67 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$58 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) + input neg_res; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + input neg_res32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) + wire \neg_res32$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [128:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$14 ; + reg [63:0] \o$14 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] output_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \output_cr_a$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_cr_a_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] output_mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \output_mul_op__fn_unit$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] output_mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \output_mul_op__imm_data__data$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_mul_op__imm_data__ok$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] output_mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \output_mul_op__insn$43 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] output_mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \output_mul_op__insn_type$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_mul_op__is_32bit$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_mul_op__is_signed$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_mul_op__oe__oe$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_mul_op__oe__ok$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_mul_op__rc__ok$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_mul_op__rc__rc$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_mul_op__write_cr0$40 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] output_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \output_muxid$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] output_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \output_o$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_o_ok$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] output_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_xer_ov$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_xer_so$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$55 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + reg [1:0] xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ov$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ov$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ov_ok$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ov_ok$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ov_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$15 ; + reg \xer_so$15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so$15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so_ok$next ; + assign \$56 = \p_valid_i$55 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \xer_so$15 <= \xer_so$15$next ; + always @(posedge coresync_clk) + xer_so_ok <= \xer_so_ok$next ; + always @(posedge coresync_clk) + xer_ov <= \xer_ov$next ; + always @(posedge coresync_clk) + xer_ov_ok <= \xer_ov_ok$next ; + always @(posedge coresync_clk) + cr_a <= \cr_a$next ; + always @(posedge coresync_clk) + cr_a_ok <= \cr_a_ok$next ; + always @(posedge coresync_clk) + \o$14 <= \o$14$next ; + always @(posedge coresync_clk) + o_ok <= \o_ok$next ; + always @(posedge coresync_clk) + \mul_op__insn_type$2 <= \mul_op__insn_type$2$next ; + always @(posedge coresync_clk) + \mul_op__fn_unit$3 <= \mul_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \mul_op__imm_data__data$4 <= \mul_op__imm_data__data$4$next ; + always @(posedge coresync_clk) + \mul_op__imm_data__ok$5 <= \mul_op__imm_data__ok$5$next ; + always @(posedge coresync_clk) + \mul_op__rc__rc$6 <= \mul_op__rc__rc$6$next ; + always @(posedge coresync_clk) + \mul_op__rc__ok$7 <= \mul_op__rc__ok$7$next ; + always @(posedge coresync_clk) + \mul_op__oe__oe$8 <= \mul_op__oe__oe$8$next ; + always @(posedge coresync_clk) + \mul_op__oe__ok$9 <= \mul_op__oe__ok$9$next ; + always @(posedge coresync_clk) + \mul_op__write_cr0$10 <= \mul_op__write_cr0$10$next ; + always @(posedge coresync_clk) + \mul_op__is_32bit$11 <= \mul_op__is_32bit$11$next ; + always @(posedge coresync_clk) + \mul_op__is_signed$12 <= \mul_op__is_signed$12$next ; + always @(posedge coresync_clk) + \mul_op__insn$13 <= \mul_op__insn$13$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + mul3 mul3 ( + .mul_op__fn_unit(mul3_mul_op__fn_unit), + .\mul_op__fn_unit$3 (\mul3_mul_op__fn_unit$18 ), + .mul_op__imm_data__data(mul3_mul_op__imm_data__data), + .\mul_op__imm_data__data$4 (\mul3_mul_op__imm_data__data$19 ), + .mul_op__imm_data__ok(mul3_mul_op__imm_data__ok), + .\mul_op__imm_data__ok$5 (\mul3_mul_op__imm_data__ok$20 ), + .mul_op__insn(mul3_mul_op__insn), + .\mul_op__insn$13 (\mul3_mul_op__insn$28 ), + .mul_op__insn_type(mul3_mul_op__insn_type), + .\mul_op__insn_type$2 (\mul3_mul_op__insn_type$17 ), + .mul_op__is_32bit(mul3_mul_op__is_32bit), + .\mul_op__is_32bit$11 (\mul3_mul_op__is_32bit$26 ), + .mul_op__is_signed(mul3_mul_op__is_signed), + .\mul_op__is_signed$12 (\mul3_mul_op__is_signed$27 ), + .mul_op__oe__oe(mul3_mul_op__oe__oe), + .\mul_op__oe__oe$8 (\mul3_mul_op__oe__oe$23 ), + .mul_op__oe__ok(mul3_mul_op__oe__ok), + .\mul_op__oe__ok$9 (\mul3_mul_op__oe__ok$24 ), + .mul_op__rc__ok(mul3_mul_op__rc__ok), + .\mul_op__rc__ok$7 (\mul3_mul_op__rc__ok$22 ), + .mul_op__rc__rc(mul3_mul_op__rc__rc), + .\mul_op__rc__rc$6 (\mul3_mul_op__rc__rc$21 ), + .mul_op__write_cr0(mul3_mul_op__write_cr0), + .\mul_op__write_cr0$10 (\mul3_mul_op__write_cr0$25 ), + .muxid(mul3_muxid), + .\muxid$1 (\mul3_muxid$16 ), + .neg_res(mul3_neg_res), + .o(mul3_o), + .\o$14 (\mul3_o$29 ), + .o_ok(mul3_o_ok), + .xer_ov(mul3_xer_ov), + .xer_ov_ok(mul3_xer_ov_ok), + .xer_so(mul3_xer_so), + .\xer_so$15 (\mul3_xer_so$30 ), + .xer_so_ok(mul3_xer_so_ok) + ); + \n$99 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \output$100 \output ( + .cr_a(output_cr_a), + .\cr_a$16 (\output_cr_a$46 ), + .cr_a_ok(output_cr_a_ok), + .mul_op__fn_unit(output_mul_op__fn_unit), + .\mul_op__fn_unit$3 (\output_mul_op__fn_unit$33 ), + .mul_op__imm_data__data(output_mul_op__imm_data__data), + .\mul_op__imm_data__data$4 (\output_mul_op__imm_data__data$34 ), + .mul_op__imm_data__ok(output_mul_op__imm_data__ok), + .\mul_op__imm_data__ok$5 (\output_mul_op__imm_data__ok$35 ), + .mul_op__insn(output_mul_op__insn), + .\mul_op__insn$13 (\output_mul_op__insn$43 ), + .mul_op__insn_type(output_mul_op__insn_type), + .\mul_op__insn_type$2 (\output_mul_op__insn_type$32 ), + .mul_op__is_32bit(output_mul_op__is_32bit), + .\mul_op__is_32bit$11 (\output_mul_op__is_32bit$41 ), + .mul_op__is_signed(output_mul_op__is_signed), + .\mul_op__is_signed$12 (\output_mul_op__is_signed$42 ), + .mul_op__oe__oe(output_mul_op__oe__oe), + .\mul_op__oe__oe$8 (\output_mul_op__oe__oe$38 ), + .mul_op__oe__ok(output_mul_op__oe__ok), + .\mul_op__oe__ok$9 (\output_mul_op__oe__ok$39 ), + .mul_op__rc__ok(output_mul_op__rc__ok), + .\mul_op__rc__ok$7 (\output_mul_op__rc__ok$37 ), + .mul_op__rc__rc(output_mul_op__rc__rc), + .\mul_op__rc__rc$6 (\output_mul_op__rc__rc$36 ), + .mul_op__write_cr0(output_mul_op__write_cr0), + .\mul_op__write_cr0$10 (\output_mul_op__write_cr0$40 ), + .muxid(output_muxid), + .\muxid$1 (\output_muxid$31 ), + .o(output_o), + .\o$14 (\output_o$44 ), + .o_ok(output_o_ok), + .\o_ok$15 (\output_o_ok$45 ), + .xer_ov(output_xer_ov), + .\xer_ov$17 (\output_xer_ov$47 ), + .xer_ov_ok(output_xer_ov_ok), + .xer_so(output_xer_so), + .\xer_so$18 (\output_xer_so$48 ), + .xer_so_ok(output_xer_so_ok) + ); + \p$98 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$58 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$58 ; + endcase + end + always @* begin + if (\initial ) begin end + \mul_op__insn_type$2$next = \mul_op__insn_type$2 ; + \mul_op__fn_unit$3$next = \mul_op__fn_unit$3 ; + \mul_op__imm_data__data$4$next = \mul_op__imm_data__data$4 ; + \mul_op__imm_data__ok$5$next = \mul_op__imm_data__ok$5 ; + \mul_op__rc__rc$6$next = \mul_op__rc__rc$6 ; + \mul_op__rc__ok$7$next = \mul_op__rc__ok$7 ; + \mul_op__oe__oe$8$next = \mul_op__oe__oe$8 ; + \mul_op__oe__ok$9$next = \mul_op__oe__ok$9 ; + \mul_op__write_cr0$10$next = \mul_op__write_cr0$10 ; + \mul_op__is_32bit$11$next = \mul_op__is_32bit$11 ; + \mul_op__is_signed$12$next = \mul_op__is_signed$12 ; + \mul_op__insn$13$next = \mul_op__insn$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \mul_op__imm_data__data$4$next = 64'h0000000000000000; + \mul_op__imm_data__ok$5$next = 1'h0; + \mul_op__rc__rc$6$next = 1'h0; + \mul_op__rc__ok$7$next = 1'h0; + \mul_op__oe__oe$8$next = 1'h0; + \mul_op__oe__ok$9$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \o$14$next = \o$14 ; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$14$next } = { \o_ok$72 , \o$71 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$14$next } = { \o_ok$72 , \o$71 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cr_a$next = cr_a; + \cr_a_ok$next = cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$74 , \cr_a$73 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$74 , \cr_a$73 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$next = xer_ov; + \xer_ov_ok$next = xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$76 , \xer_ov$75 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$76 , \xer_ov$75 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ov_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$15$next = \xer_so$15 ; + \xer_so_ok$next = xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_so_ok$next , \xer_so$15$next } = { \xer_so_ok$78 , \xer_so$77 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_so_ok$next , \xer_so$15$next } = { \xer_so_ok$78 , \xer_so$77 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_so_ok$next = 1'h0; + endcase + end + assign \cr_a$51 = 4'h0; + assign \cr_a_ok$52 = 1'h0; + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \xer_so_ok$78 , \xer_so$77 } = { output_xer_so_ok, \output_xer_so$48 }; + assign { \xer_ov_ok$76 , \xer_ov$75 } = { output_xer_ov_ok, \output_xer_ov$47 }; + assign { \cr_a_ok$74 , \cr_a$73 } = { output_cr_a_ok, \output_cr_a$46 }; + assign { \o_ok$72 , \o$71 } = { \output_o_ok$45 , \output_o$44 }; + assign { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59 } = { \output_mul_op__insn$43 , \output_mul_op__is_signed$42 , \output_mul_op__is_32bit$41 , \output_mul_op__write_cr0$40 , \output_mul_op__oe__ok$39 , \output_mul_op__oe__oe$38 , \output_mul_op__rc__ok$37 , \output_mul_op__rc__rc$36 , \output_mul_op__imm_data__ok$35 , \output_mul_op__imm_data__data$34 , \output_mul_op__fn_unit$33 , \output_mul_op__insn_type$32 }; + assign \muxid$58 = \output_muxid$31 ; + assign p_valid_i_p_ready_o = \$56 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$55 = p_valid_i; + assign { \xer_so_ok$54 , output_xer_so } = { mul3_xer_so_ok, \mul3_xer_so$30 }; + assign { \xer_ov_ok$53 , output_xer_ov } = { mul3_xer_ov_ok, mul3_xer_ov }; + assign { \cr_a_ok$50 , output_cr_a } = 5'h00; + assign { output_o_ok, output_o } = { mul3_o_ok, \mul3_o$29 }; + assign { output_mul_op__insn, output_mul_op__is_signed, output_mul_op__is_32bit, output_mul_op__write_cr0, output_mul_op__oe__ok, output_mul_op__oe__oe, output_mul_op__rc__ok, output_mul_op__rc__rc, output_mul_op__imm_data__ok, output_mul_op__imm_data__data, output_mul_op__fn_unit, output_mul_op__insn_type } = { \mul3_mul_op__insn$28 , \mul3_mul_op__is_signed$27 , \mul3_mul_op__is_32bit$26 , \mul3_mul_op__write_cr0$25 , \mul3_mul_op__oe__ok$24 , \mul3_mul_op__oe__oe$23 , \mul3_mul_op__rc__ok$22 , \mul3_mul_op__rc__rc$21 , \mul3_mul_op__imm_data__ok$20 , \mul3_mul_op__imm_data__data$19 , \mul3_mul_op__fn_unit$18 , \mul3_mul_op__insn_type$17 }; + assign output_muxid = \mul3_muxid$16 ; + assign \neg_res32$49 = neg_res32; + assign mul3_neg_res = neg_res; + assign mul3_xer_so = xer_so; + assign mul3_o = o; + assign { mul3_mul_op__insn, mul3_mul_op__is_signed, mul3_mul_op__is_32bit, mul3_mul_op__write_cr0, mul3_mul_op__oe__ok, mul3_mul_op__oe__oe, mul3_mul_op__rc__ok, mul3_mul_op__rc__rc, mul3_mul_op__imm_data__ok, mul3_mul_op__imm_data__data, mul3_mul_op__fn_unit, mul3_mul_op__insn_type } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign mul3_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.n" *) +(* generator = "nMigen" *) +module n(n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" *) +(* generator = "nMigen" *) +module \n$109 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" *) +(* generator = "nMigen" *) +module \n$112 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" *) +(* generator = "nMigen" *) +module \n$117 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.n" *) +(* generator = "nMigen" *) +module \n$18 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" *) +(* generator = "nMigen" *) +module \n$2 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" *) +(* generator = "nMigen" *) +module \n$21 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.n" *) +(* generator = "nMigen" *) +module \n$31 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" *) +(* generator = "nMigen" *) +module \n$34 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" *) +(* generator = "nMigen" *) +module \n$37 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" *) +(* generator = "nMigen" *) +module \n$4 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.n" *) +(* generator = "nMigen" *) +module \n$47 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" *) +(* generator = "nMigen" *) +module \n$49 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" *) +(* generator = "nMigen" *) +module \n$53 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.n" *) +(* generator = "nMigen" *) +module \n$6 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.n" *) +(* generator = "nMigen" *) +module \n$63 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" *) +(* generator = "nMigen" *) +module \n$66 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.n" *) +(* generator = "nMigen" *) +module \n$75 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" *) +(* generator = "nMigen" *) +module \n$77 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" *) +(* generator = "nMigen" *) +module \n$8 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" *) +(* generator = "nMigen" *) +module \n$80 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" *) +(* generator = "nMigen" *) +module \n$82 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.n" *) +(* generator = "nMigen" *) +module \n$92 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" *) +(* generator = "nMigen" *) +module \n$94 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" *) +(* generator = "nMigen" *) +module \n$97 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" *) +(* generator = "nMigen" *) +module \n$99 (n_ready_i, n_valid_o); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + input n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *) + wire trigger; + assign \$1 = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.opc_l" *) +(* generator = "nMigen" *) +module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.opc_l" *) +(* generator = "nMigen" *) +module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_opc; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc; + assign \$15 = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_opc = \$15 ; + assign qn_opc = \$13 ; + assign q_opc = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" *) +(* generator = "nMigen" *) +module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, xer_ca, xer_ov, xer_so, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, \xer_ca$23 , xer_ca_ok, \xer_ov$24 , xer_ov_ok, \xer_so$25 , xer_so_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + wire [64:0] \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + wire [63:0] \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [64:0] \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \alu_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \alu_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \alu_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \alu_op__input_carry$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \alu_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \alu_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__invert_out$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__write_cr0$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + reg [3:0] cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + wire is_cmp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + wire is_cmpeqb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + wire is_negative; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + wire is_nzero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) + wire is_positive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + wire msb_test; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) + reg [64:0] \o$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) + wire oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *) + wire \oe$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *) + reg so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + wire [63:0] target; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ca$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ov$24 ; + reg [1:0] \xer_ov$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$25 ; + reg \xer_so$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok; + assign \$26 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) alu_op__oe__ok; + assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; + assign \$29 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$30 ; + assign \$33 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$35 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; + assign \$37 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; + assign \$39 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; + assign \$41 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; + assign \$43 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$41 ; + assign \$45 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; + assign \$50 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) alu_op__oe__ok; + assign \$52 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *) + casez (oe) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ + 1'h1: + so = \xer_so$25 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */ + default: + so = xer_so; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + casez (\$45 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + 1'h1: + cr0 = cr_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + default: + cr0 = { is_negative, is_positive, \$47 , so }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) + casez (alu_op__invert_out) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ + 1'h1: + \o$28 = \$29 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" */ + default: + \o$28 = \$33 ; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$25 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$49 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + \xer_so$25 = \$52 ; + endcase + end + always @* begin + if (\initial ) begin end + xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$49 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + xer_so_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$24 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$49 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + \xer_ov$24 = xer_ov; + endcase + end + always @* begin + if (\initial ) begin end + xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$49 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + xer_ov_ok = 1'h1; + endcase + end + assign \oe$49 = \$50 ; + assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign \muxid$1 = muxid; + assign cr_a_ok = alu_op__write_cr0; + assign \cr_a$22 = cr0; + assign \o_ok$21 = o_ok; + assign \o$20 = \o$28 [63:0]; + assign is_positive = \$43 ; + assign is_negative = msb_test; + assign is_nzero = \$39 ; + assign msb_test = target[63]; + assign is_cmpeqb = \$37 ; + assign is_cmp = \$35 ; + assign xer_ca_ok = alu_op__output_carry; + assign \xer_ca$23 = xer_ca; + assign target = \o$28 [63:0]; + assign oe = \$26 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" *) +(* generator = "nMigen" *) +module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , \o_ok$15 , \cr_a$16 , cr_a_ok, \xer_ov$17 , xer_ov_ok, \xer_so$18 , xer_so_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [64:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + reg [3:0] cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + wire is_cmp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + wire is_cmpeqb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + wire is_negative; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + wire is_nzero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) + wire is_positive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + wire msb_test; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] mul_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] mul_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \mul_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] mul_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \mul_op__insn$13 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] mul_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \mul_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_32bit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__is_signed$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input mul_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \mul_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) + wire [64:0] \o$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) + wire oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *) + wire \oe$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *) + reg so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + wire [63:0] target; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ov$17 ; + reg [1:0] \xer_ov$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$18 ; + reg \xer_so$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok; + assign \$19 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) mul_op__oe__ok; + assign \$22 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$24 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; + assign \$26 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; + assign \$28 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; + assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; + assign \$32 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$30 ; + assign \$34 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; + assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; + assign \$39 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) mul_op__oe__ok; + assign \$41 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *) + casez (oe) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ + 1'h1: + so = \xer_so$18 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */ + default: + so = xer_so; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + casez (\$34 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + 1'h1: + cr0 = cr_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + default: + cr0 = { is_negative, is_positive, \$36 , so }; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$18 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$38 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + \xer_so$18 = \$41 ; + endcase + end + always @* begin + if (\initial ) begin end + xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$38 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + xer_so_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$17 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$38 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + \xer_ov$17 = xer_ov; + endcase + end + always @* begin + if (\initial ) begin end + xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$38 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + xer_ov_ok = 1'h1; + endcase + end + assign \oe$38 = \$39 ; + assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \muxid$1 = muxid; + assign cr_a_ok = mul_op__write_cr0; + assign \cr_a$16 = cr0; + assign \o_ok$15 = o_ok; + assign \o$14 = \o$21 [63:0]; + assign is_positive = \$32 ; + assign is_negative = msb_test; + assign is_nzero = \$28 ; + assign msb_test = target[63]; + assign is_cmpeqb = \$26 ; + assign is_cmp = \$24 ; + assign target = \o$21 [63:0]; + assign \o$21 = \$22 ; + assign oe = \$19 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" *) +(* generator = "nMigen" *) +module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \o$19 , \o_ok$20 , \cr_a$21 , cr_a_ok, \xer_ca$22 , xer_ca_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [64:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + reg [3:0] cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + wire is_cmp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + wire is_cmpeqb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + wire is_negative; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + wire is_nzero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) + wire is_positive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + wire msb_test; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) + wire [64:0] \o$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$20 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \sr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \sr_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \sr_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__input_cr$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \sr_op__insn$18 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \sr_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__invert_in$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__output_carry$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__output_cr$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + wire [63:0] target; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ca$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so; + assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$26 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; + assign \$28 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; + assign \$30 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; + assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; + assign \$34 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$32 ; + assign \$36 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; + assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + casez (\$36 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + 1'h1: + cr0 = cr_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + default: + cr0 = { is_negative, is_positive, \$38 , xer_so }; + endcase + end + assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign \muxid$1 = muxid; + assign cr_a_ok = sr_op__write_cr0; + assign \cr_a$21 = cr0; + assign \o_ok$20 = o_ok; + assign \o$19 = \o$23 [63:0]; + assign is_positive = \$34 ; + assign is_negative = msb_test; + assign is_nzero = \$30 ; + assign msb_test = target[63]; + assign is_cmpeqb = \$28 ; + assign is_cmp = \$26 ; + assign xer_ca_ok = sr_op__output_carry; + assign \xer_ca$22 = xer_ca; + assign target = \o$23 [63:0]; + assign \o$23 = \$24 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" *) +(* generator = "nMigen" *) +module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + wire [64:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + wire [63:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [64:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + reg [3:0] cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + wire is_cmp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + wire is_cmpeqb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + wire is_negative; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + wire is_nzero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) + wire is_positive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + wire msb_test; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) + reg [64:0] \o$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + wire [63:0] target; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so; + assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; + assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$25 ; + assign \$28 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$30 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; + assign \$32 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; + assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; + assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; + assign \$38 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$36 ; + assign \$40 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; + assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) + casez (logical_op__invert_out) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ + 1'h1: + \o$23 = \$24 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" */ + default: + \o$23 = \$28 ; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + casez (\$40 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + 1'h1: + cr0 = cr_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + default: + cr0 = { is_negative, is_positive, \$42 , xer_so }; + endcase + end + assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \muxid$1 = muxid; + assign cr_a_ok = logical_op__write_cr0; + assign \cr_a$22 = cr0; + assign \o_ok$21 = o_ok; + assign \o$20 = \o$23 [63:0]; + assign is_positive = \$38 ; + assign is_negative = msb_test; + assign is_nzero = \$34 ; + assign msb_test = target[63]; + assign is_cmpeqb = \$32 ; + assign is_cmp = \$30 ; + assign target = \o$23 [63:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" *) +(* generator = "nMigen" *) +module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, \xer_ov$23 , xer_ov_ok, \xer_so$24 , xer_so_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + wire [64:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + wire [63:0] \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [64:0] \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + reg [3:0] cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + wire is_cmp; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + wire is_cmpeqb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + wire is_negative; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + wire is_nzero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) + wire is_positive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + wire msb_test; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) + reg [64:0] \o$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) + wire oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *) + wire \oe$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *) + reg so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + wire [63:0] target; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ov$23 ; + reg [1:0] \xer_ov$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$24 ; + reg \xer_so$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok; + assign \$25 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) logical_op__oe__ok; + assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; + assign \$28 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$29 ; + assign \$32 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; + assign \$34 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; + assign \$36 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; + assign \$38 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; + assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; + assign \$42 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$40 ; + assign \$44 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; + assign \$49 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) logical_op__oe__ok; + assign \$51 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *) + casez (oe) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ + 1'h1: + so = \xer_so$24 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */ + default: + so = xer_so; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + casez (\$44 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + 1'h1: + cr0 = cr_a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + default: + cr0 = { is_negative, is_positive, \$46 , so }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) + casez (logical_op__invert_out) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ + 1'h1: + \o$27 = \$28 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" */ + default: + \o$27 = \$32 ; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$24 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$48 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + \xer_so$24 = \$51 ; + endcase + end + always @* begin + if (\initial ) begin end + xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$48 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + xer_so_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$23 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$48 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + \xer_ov$23 = xer_ov; + endcase + end + always @* begin + if (\initial ) begin end + xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) + casez (\oe$48 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ + 1'h1: + xer_ov_ok = 1'h1; + endcase + end + assign \oe$48 = \$49 ; + assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \muxid$1 = muxid; + assign cr_a_ok = logical_op__write_cr0; + assign \cr_a$22 = cr0; + assign \o_ok$21 = o_ok; + assign \o$20 = \o$27 [63:0]; + assign is_positive = \$42 ; + assign is_negative = msb_test; + assign is_nzero = \$38 ; + assign msb_test = target[63]; + assign is_cmpeqb = \$36 ; + assign is_cmp = \$34 ; + assign target = \o$27 [63:0]; + assign oe = \$25 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" *) +(* generator = "nMigen" *) +module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, xer_ov, xer_ov_ok, \xer_so$20 , muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) + wire [64:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) + wire [64:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) + wire [64:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) + wire [64:0] \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) + wire [64:0] \$30 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) + wire [64:0] \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) + wire [64:0] \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) + wire [63:0] \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) + wire [63:0] \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) + wire [63:0] \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) + wire [63:0] \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) + wire [63:0] \$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) + wire [63:0] \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + input div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + input dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + input dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + input dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + input divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" *) + reg ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" *) + wire [64:0] quotient_65; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" *) + wire quotient_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) + input [63:0] quotient_root; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) + input [191:0] remainder; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" *) + wire [63:0] remainder_64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" *) + wire remainder_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) + wire [31:0] remainder_s32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" *) + wire [63:0] remainder_s32_as_s64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$20 ; + assign \$21 = dividend_neg ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) divisor_neg; + assign \$23 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) quotient_root; + assign \$25 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) quotient_root; + assign \$27 = quotient_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) \$23 : \$25 ; + assign \$30 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) remainder[127:64]; + assign \$32 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) remainder[127:64]; + assign \$34 = remainder_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) \$30 : \$32 ; + assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) logical_op__is_32bit; + assign \$38 = quotient_65[64] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) quotient_65[63]; + assign \$40 = logical_op__is_signed & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) \$38 ; + assign \$42 = quotient_65[32] != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) quotient_65[31]; + assign \$44 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) $signed(remainder_s32); + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) ov; + assign \$48 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) quotient_65[31:0]; + assign \$50 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) quotient_65[31:0]; + assign \$52 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) quotient_65[31:0]; + assign \$54 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) quotient_65[31:0]; + assign \$56 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) remainder_64[31:0]; + always @* begin + if (\initial ) begin end + o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) + casez (\$46 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_DIVE/30" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" */ + 7'h1e: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" *) + casez (logical_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" *) + casez (logical_op__is_signed) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" */ + 1'h1: + o = \$48 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" */ + default: + o = \$50 ; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" */ + default: + o = quotient_65[63:0]; + endcase + /* \nmigen.decoding = "OP_DIV/29" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" */ + 7'h1d: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" *) + casez (logical_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" *) + casez (logical_op__is_signed) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" */ + 1'h1: + o = \$52 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" */ + default: + o = \$54 ; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" */ + default: + o = quotient_65[63:0]; + endcase + /* \nmigen.decoding = "OP_MOD/47" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" */ + 7'h2f: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" *) + casez (logical_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" *) + casez (logical_op__is_signed) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" */ + 1'h1: + o = remainder_s32_as_s64; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:127" */ + default: + o = \$56 ; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:129" */ + default: + o = remainder_64; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" *) + casez ({ logical_op__is_signed, \$36 , div_by_zero }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" */ + 3'b??1: + ov = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" */ + 3'b?1?: + begin + ov = dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) + casez (\$40 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" */ + 1'h1: + ov = 1'h1; + endcase + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:82" */ + 3'b1??: + begin + ov = dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) + casez (\$42 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" */ + 1'h1: + ov = 1'h1; + endcase + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:86" */ + default: + ov = dive_abs_ov32; + endcase + end + assign \$29 = \$34 ; + assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$20 = xer_so; + assign remainder_s32_as_s64 = \$44 ; + assign remainder_s32 = remainder_64[31:0]; + assign o_ok = 1'h1; + assign xer_ov = { ov, ov }; + assign xer_ov_ok = 1'h1; + assign remainder_64 = \$34 [63:0]; + assign quotient_65 = \$27 ; + assign remainder_neg = dividend_neg; + assign quotient_neg = \$21 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.p" *) +(* generator = "nMigen" *) +module p(p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" *) +(* generator = "nMigen" *) +module \p$1 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" *) +(* generator = "nMigen" *) +module \p$108 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" *) +(* generator = "nMigen" *) +module \p$111 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" *) +(* generator = "nMigen" *) +module \p$116 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.p" *) +(* generator = "nMigen" *) +module \p$17 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" *) +(* generator = "nMigen" *) +module \p$20 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" *) +(* generator = "nMigen" *) +module \p$3 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.p" *) +(* generator = "nMigen" *) +module \p$30 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" *) +(* generator = "nMigen" *) +module \p$33 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" *) +(* generator = "nMigen" *) +module \p$36 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.p" *) +(* generator = "nMigen" *) +module \p$46 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" *) +(* generator = "nMigen" *) +module \p$48 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.p" *) +(* generator = "nMigen" *) +module \p$5 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" *) +(* generator = "nMigen" *) +module \p$52 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.p" *) +(* generator = "nMigen" *) +module \p$62 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" *) +(* generator = "nMigen" *) +module \p$65 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" *) +(* generator = "nMigen" *) +module \p$7 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.p" *) +(* generator = "nMigen" *) +module \p$74 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" *) +(* generator = "nMigen" *) +module \p$76 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" *) +(* generator = "nMigen" *) +module \p$79 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" *) +(* generator = "nMigen" *) +module \p$81 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.p" *) +(* generator = "nMigen" *) +module \p$91 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" *) +(* generator = "nMigen" *) +module \p$93 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" *) +(* generator = "nMigen" *) +module \p$96 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" *) +(* generator = "nMigen" *) +module \p$98 (p_ready_o, p_valid_i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + input p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *) + wire trigger; + assign \$1 = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o; + assign trigger = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.l0.pick" *) +(* generator = "nMigen" *) +module pick(o, n, i); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" *) + output n; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" *) + output o; + reg o; + assign \$1 = i == (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" *) 1'h0; + always @* begin + if (\initial ) begin end + o = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" *) + casez (i) + /* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" */ + 1'h1: + o = 1'h0; + endcase + end + assign n = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem" *) +(* generator = "nMigen" *) +module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_busy_o, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, x_mask_i, x_addr_i, ldst_port0_addr_ok_o, m_ld_data_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i_ok, ldst_port0_st_data_i, x_st_data_i, x_busy_o, \ldst_port0_exc_$signal , x_ld_i, x_st_i, m_valid_i, x_valid_i, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) + wire [3:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) + wire [3:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) + wire [175:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" *) + wire [175:0] \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) + wire [7:0] \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) + wire [175:0] \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + wire \$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) + wire [318:0] \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) + wire [7:0] \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) + wire [318:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire adrok_l_q_addr_acked; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire adrok_l_qn_addr_acked; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg adrok_l_r_addr_acked; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg adrok_l_s_addr_acked = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \adrok_l_s_addr_acked$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" *) + reg busy_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" *) + reg \busy_delay$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" *) + wire busy_edge; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire busy_l_q_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg busy_l_r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg busy_l_s_busy; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire cyc_l_q_cyc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg cyc_l_r_cyc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg cyc_l_s_cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" *) + reg [1:0] fsm_state = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" *) + reg [1:0] \fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire ld_active_q_ld_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg ld_active_r_ld_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire ld_active_s_ld_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" *) + wire [63:0] lddata; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" *) + wire lds; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg lds_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \lds_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire lds_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [47:0] ldst_port0_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input ldst_port0_addr_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + output ldst_port0_addr_ok_o; + reg ldst_port0_addr_ok_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + output ldst_port0_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + input [3:0] ldst_port0_data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + input \ldst_port0_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + input ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + input ldst_port0_is_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] ldst_port0_ld_data_o; + reg [63:0] ldst_port0_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output ldst_port0_ld_data_o_ok; + reg ldst_port0_ld_data_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] ldst_port0_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input ldst_port0_st_data_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" *) + reg [3:0] lenexp_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" *) + reg [3:0] lenexp_len_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" *) + wire [63:0] lenexp_lexp_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" *) + wire [175:0] lenexp_rexp_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" *) + wire lsui_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg lsui_active_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \lsui_active_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire lsui_active_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" *) + reg lsui_busy; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *) + input [63:0] m_ld_data_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *) + output m_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" *) + reg reset_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" *) + wire \reset_delay$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire reset_l_q_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg reset_l_r_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg reset_l_s_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire st_active_q_st_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg st_active_r_st_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire st_active_s_st_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire st_done_q_st_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg st_done_r_st_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg st_done_s_st_done = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \st_done_s_st_done$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) + reg [63:0] stdata; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" *) + wire sts; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg sts_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \sts_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire sts_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire valid_l_q_valid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + wire valid_l_r_valid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg valid_l_s_valid; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" *) + output [47:0] x_addr_i; + reg [47:0] x_addr_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" *) + input x_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" *) + output x_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" *) + output [7:0] x_mask_i; + reg [7:0] x_mask_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" *) + output [63:0] x_st_data_i; + reg [63:0] x_st_data_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" *) + output x_st_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *) + output x_valid_i; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) busy_delay; + assign \$11 = ldst_port0_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) \$9 ; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) lds_dly; + assign \$15 = lds & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ; + assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) sts_dly; + assign \$1 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok; + assign \$19 = sts & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ; + assign \$21 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ldst_port0_addr_i[2:0]; + assign \$23 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ldst_port0_addr_i[2:0]; + assign \$25 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; + assign \$27 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; + assign \$29 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; + assign \$31 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; + assign \$33 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked; + assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) lsui_busy; + assign \$38 = x_busy_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) lsui_busy; + assign \$3 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *) ldst_port0_is_st_i; + assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) \$38 ; + assign \$42 = m_ld_data_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" *) lenexp_rexp_o; + assign \$44 = lenexp_addr_i * (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) 4'h8; + assign \$46 = \$42 >>> (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) \$44 ; + assign \$48 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked; + assign \$50 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked; + assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) lsui_busy; + assign \$54 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok; + assign \$57 = lenexp_addr_i * (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) 4'h8; + assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" *) busy_delay; + assign \$59 = ldst_port0_st_data_i <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) \$57 ; + assign \$61 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok; + assign \$63 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) ldst_port0_is_st_i; + assign \$65 = \$63 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) valid_l_q_valid; + assign \$67 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) ldst_port0_is_st_i; + assign \$69 = \$67 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) valid_l_q_valid; + assign \$71 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) x_busy_o; + assign \$73 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) ldst_port0_is_st_i; + assign \$75 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) ldst_port0_busy_o; + assign \$77 = \$73 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) \$75 ; + assign \$7 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; + assign \$79 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" *) x_busy_o; + assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) lsui_active_dly; + assign \$83 = lsui_active & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$81 ; + always @(posedge coresync_clk) + lsui_active_dly <= \lsui_active_dly$next ; + always @(posedge coresync_clk) + fsm_state <= \fsm_state$next ; + always @(posedge coresync_clk) + reset_delay <= reset_l_q_reset; + always @(posedge coresync_clk) + sts_dly <= ldst_port0_is_st_i; + always @(posedge coresync_clk) + lds_dly <= ldst_port0_is_ld_i; + always @(posedge coresync_clk) + busy_delay <= \busy_delay$next ; + always @(posedge coresync_clk) + adrok_l_s_addr_acked <= \adrok_l_s_addr_acked$next ; + always @(posedge coresync_clk) + st_done_s_st_done <= \st_done_s_st_done$next ; + adrok_l adrok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_addr_acked(adrok_l_q_addr_acked), + .qn_addr_acked(adrok_l_qn_addr_acked), + .r_addr_acked(adrok_l_r_addr_acked), + .s_addr_acked(adrok_l_s_addr_acked) + ); + busy_l busy_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_busy(busy_l_q_busy), + .r_busy(busy_l_r_busy), + .s_busy(busy_l_s_busy) + ); + cyc_l cyc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_cyc(cyc_l_q_cyc), + .r_cyc(cyc_l_r_cyc), + .s_cyc(cyc_l_s_cyc) + ); + ld_active ld_active ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_ld_active(ld_active_q_ld_active), + .r_ld_active(ld_active_r_ld_active), + .s_ld_active(ld_active_s_ld_active) + ); + lenexp lenexp ( + .addr_i(lenexp_addr_i), + .len_i(lenexp_len_i), + .lexp_o(lenexp_lexp_o), + .rexp_o(lenexp_rexp_o) + ); + reset_l reset_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_reset(reset_l_q_reset), + .r_reset(reset_l_r_reset), + .s_reset(reset_l_s_reset) + ); + st_active st_active ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_st_active(st_active_q_st_active), + .r_st_active(st_active_r_st_active), + .s_st_active(st_active_s_st_active) + ); + st_done st_done ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_st_done(st_done_q_st_done), + .r_st_done(st_done_r_st_done), + .s_st_done(st_done_s_st_done) + ); + valid_l valid_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_valid(valid_l_q_valid), + .r_valid(valid_l_r_valid), + .s_valid(valid_l_s_valid) + ); + always @* begin + if (\initial ) begin end + \st_done_s_st_done$next = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" */ + 1'h1: + \st_done_s_st_done$next = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \st_done_s_st_done$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + st_done_r_st_done = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + casez (reset_l_q_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + 1'h1: + st_done_r_st_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \busy_delay$next = ldst_port0_busy_o; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \busy_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + st_active_r_st_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + casez (reset_l_q_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + 1'h1: + st_active_r_st_active = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + lenexp_len_i = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + casez (ld_active_q_ld_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + 1'h1: + lenexp_len_i = ldst_port0_data_len; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + casez (st_active_q_st_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + 1'h1: + lenexp_len_i = ldst_port0_data_len; + endcase + end + always @* begin + if (\initial ) begin end + lenexp_addr_i = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + casez (ld_active_q_ld_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + 1'h1: + lenexp_addr_i = \$21 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + casez (st_active_q_st_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + 1'h1: + lenexp_addr_i = \$23 ; + endcase + end + always @* begin + if (\initial ) begin end + valid_l_s_valid = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + casez (ld_active_q_ld_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + 1'h1: + valid_l_s_valid = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + casez (st_active_q_st_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + casez (ldst_port0_addr_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + 1'h1: + valid_l_s_valid = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + x_mask_i = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + casez (ld_active_q_ld_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + 1'h1: + x_mask_i = lenexp_lexp_o[7:0]; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + casez (st_active_q_st_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + casez (ldst_port0_addr_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + 1'h1: + x_mask_i = lenexp_lexp_o[7:0]; + endcase + endcase + end + always @* begin + if (\initial ) begin end + x_addr_i = 48'h000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + casez (ld_active_q_ld_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + 1'h1: + x_addr_i = ldst_port0_addr_i; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + casez (st_active_q_st_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + casez (ldst_port0_addr_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + 1'h1: + x_addr_i = ldst_port0_addr_i; + endcase + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_addr_ok_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + casez (ld_active_q_ld_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + 1'h1: + ldst_port0_addr_ok_o = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + casez (st_active_q_st_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + casez (ldst_port0_addr_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" *) + casez (adrok_l_qn_addr_acked) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" */ + 1'h1: + ldst_port0_addr_ok_o = 1'h1; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + reset_l_s_reset = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) + casez (\$33 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" */ + 1'h1: + reset_l_s_reset = \$35 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" *) + casez (st_done_q_st_done) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" */ + 1'h1: + reset_l_s_reset = \$37 ; + endcase + end + always @* begin + if (\initial ) begin end + reset_l_r_reset = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + casez (reset_l_q_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + 1'h1: + reset_l_r_reset = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_ld_data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) + casez (\$48 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" */ + 1'h1: + ldst_port0_ld_data_o = lddata; + endcase + end + always @* begin + if (\initial ) begin end + ld_active_r_ld_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + casez (reset_l_q_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + 1'h1: + ld_active_r_ld_active = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_ld_data_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) + casez (\$50 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" */ + 1'h1: + ldst_port0_ld_data_o_ok = \$52 ; + endcase + end + always @* begin + if (\initial ) begin end + stdata = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + casez (\$54 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" */ + 1'h1: + stdata = \$56 [63:0]; + endcase + end + always @* begin + if (\initial ) begin end + x_st_data_i = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + casez (\$61 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" */ + 1'h1: + x_st_data_i = stdata; + endcase + end + always @* begin + if (\initial ) begin end + lsui_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) + casez (\$65 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" */ + 1'h1: + lsui_busy = 1'h1; + endcase + /* \nmigen.decoding = "BUSY/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:91" */ + 2'h1: + lsui_busy = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \fsm_state$next = fsm_state; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) + casez (\$69 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" */ + 1'h1: + \fsm_state$next = 2'h1; + endcase + /* \nmigen.decoding = "BUSY/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:91" */ + 2'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) + casez (\$71 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" */ + 1'h1: + \fsm_state$next = 2'h2; + endcase + /* \nmigen.decoding = "WAITDEASSERT/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" */ + 2'h2: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) + casez (\$77 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" */ + 1'h1: + \fsm_state$next = 2'h0; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \fsm_state$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + cyc_l_s_cyc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" *) + casez (reset_l_s_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" */ + 1'h1: + cyc_l_s_cyc = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \lsui_active_dly$next = lsui_active; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \lsui_active_dly$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + cyc_l_r_cyc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" *) + casez (cyc_l_q_cyc) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" */ + 1'h1: + cyc_l_r_cyc = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + busy_l_s_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" */ + 1'h1: + busy_l_s_busy = \$5 ; + endcase + end + always @* begin + if (\initial ) begin end + busy_l_r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" *) + casez (\ldst_port0_exc_$signal ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" */ + 1'h1: + busy_l_r_busy = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" *) + casez (cyc_l_q_cyc) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" */ + 1'h1: + busy_l_r_busy = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \adrok_l_s_addr_acked$next = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + casez (ld_active_q_ld_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + casez (\$7 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + 1'h1: + \adrok_l_s_addr_acked$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + casez (st_active_q_st_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + casez (ldst_port0_addr_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" *) + casez (adrok_l_qn_addr_acked) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" */ + 1'h1: + \adrok_l_s_addr_acked$next = 1'h1; + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \adrok_l_s_addr_acked$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + adrok_l_r_addr_acked = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" *) + casez (reset_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" */ + 1'h1: + adrok_l_r_addr_acked = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + casez (reset_l_q_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + 1'h1: + adrok_l_r_addr_acked = 1'h1; + endcase + end + assign \$41 = \$46 ; + assign \$56 = \$59 ; + assign valid_l_r_valid = lsui_active_rise; + assign lsui_active_rise = \$83 ; + assign lsui_active = \$79 ; + assign x_valid_i = valid_l_q_valid; + assign m_valid_i = valid_l_q_valid; + assign x_st_i = ldst_port0_is_st_i; + assign x_ld_i = ldst_port0_is_ld_i; + assign ldst_port0_busy_o = busy_l_q_busy; + assign \reset_delay$next = reset_l_q_reset; + assign lddata = \$46 [63:0]; + assign st_active_s_st_active = sts_rise; + assign sts_rise = \$19 ; + assign \sts_dly$next = sts; + assign ld_active_s_ld_active = lds_rise; + assign lds_rise = \$15 ; + assign \lds_dly$next = lds; + assign busy_edge = \$11 ; + assign sts = ldst_port0_is_st_i; + assign lds = ldst_port0_is_ld_i; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" *) +(* generator = "nMigen" *) +module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, cr_a, cr_b, cr_c, n_valid_o, n_ready_i, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , o, o_ok, \full_cr$5 , full_cr_ok, \cr_a$6 , cr_a_ok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$6 ; + reg [3:0] \cr_a$6 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + reg cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_c; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] cr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \cr_op__fn_unit$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \cr_op__fn_unit$3 ; + reg [13:0] \cr_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \cr_op__fn_unit$3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] cr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \cr_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \cr_op__insn$4 ; + reg [31:0] \cr_op__insn$4 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \cr_op__insn$4$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] cr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \cr_op__insn_type$17 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \cr_op__insn_type$2 ; + reg [6:0] \cr_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \cr_op__insn_type$2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [31:0] full_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [31:0] \full_cr$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [31:0] \full_cr$5 ; + reg [31:0] \full_cr$5 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [31:0] \full_cr$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output full_cr_ok; + reg full_cr_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \full_cr_ok$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \full_cr_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] main_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \main_cr_a$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] main_cr_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] main_cr_c; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] main_cr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \main_cr_op__fn_unit$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] main_cr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \main_cr_op__insn$10 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] main_cr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \main_cr_op__insn_type$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [31:0] main_full_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [31:0] \main_full_cr$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_full_cr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] main_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \main_muxid$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] main_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_rb; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + assign \$14 = \p_valid_i$13 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \cr_a$6 <= \cr_a$6$next ; + always @(posedge coresync_clk) + cr_a_ok <= \cr_a_ok$next ; + always @(posedge coresync_clk) + \full_cr$5 <= \full_cr$5$next ; + always @(posedge coresync_clk) + full_cr_ok <= \full_cr_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; + always @(posedge coresync_clk) + o_ok <= \o_ok$next ; + always @(posedge coresync_clk) + \cr_op__insn_type$2 <= \cr_op__insn_type$2$next ; + always @(posedge coresync_clk) + \cr_op__fn_unit$3 <= \cr_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \cr_op__insn$4 <= \cr_op__insn$4$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \main$9 main ( + .cr_a(main_cr_a), + .\cr_a$6 (\main_cr_a$12 ), + .cr_a_ok(main_cr_a_ok), + .cr_b(main_cr_b), + .cr_c(main_cr_c), + .cr_op__fn_unit(main_cr_op__fn_unit), + .\cr_op__fn_unit$3 (\main_cr_op__fn_unit$9 ), + .cr_op__insn(main_cr_op__insn), + .\cr_op__insn$4 (\main_cr_op__insn$10 ), + .cr_op__insn_type(main_cr_op__insn_type), + .\cr_op__insn_type$2 (\main_cr_op__insn_type$8 ), + .full_cr(main_full_cr), + .\full_cr$5 (\main_full_cr$11 ), + .full_cr_ok(main_full_cr_ok), + .muxid(main_muxid), + .\muxid$1 (\main_muxid$7 ), + .o(main_o), + .o_ok(main_o_ok), + .ra(main_ra), + .rb(main_rb) + ); + \n$8 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$7 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$16 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$16 ; + endcase + end + always @* begin + if (\initial ) begin end + \cr_op__insn_type$2$next = \cr_op__insn_type$2 ; + \cr_op__fn_unit$3$next = \cr_op__fn_unit$3 ; + \cr_op__insn$4$next = \cr_op__insn$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17 }; + endcase + end + always @* begin + if (\initial ) begin end + \o$next = o; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$next } = { \o_ok$21 , \o$20 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$next } = { \o_ok$21 , \o$20 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \full_cr$5$next = \full_cr$5 ; + \full_cr_ok$next = full_cr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \full_cr_ok$next , \full_cr$5$next } = { \full_cr_ok$23 , \full_cr$22 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \full_cr_ok$next , \full_cr$5$next } = { \full_cr_ok$23 , \full_cr$22 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \full_cr_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cr_a$6$next = \cr_a$6 ; + \cr_a_ok$next = cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$next , \cr_a$6$next } = { \cr_a_ok$25 , \cr_a$24 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$next , \cr_a$6$next } = { \cr_a_ok$25 , \cr_a$24 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$next = 1'h0; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \cr_a_ok$25 , \cr_a$24 } = { main_cr_a_ok, \main_cr_a$12 }; + assign { \full_cr_ok$23 , \full_cr$22 } = { main_full_cr_ok, \main_full_cr$11 }; + assign { \o_ok$21 , \o$20 } = { main_o_ok, main_o }; + assign { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17 } = { \main_cr_op__insn$10 , \main_cr_op__fn_unit$9 , \main_cr_op__insn_type$8 }; + assign \muxid$16 = \main_muxid$7 ; + assign p_valid_i_p_ready_o = \$14 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$13 = p_valid_i; + assign main_cr_c = cr_c; + assign main_cr_b = cr_b; + assign main_cr_a = cr_a; + assign main_full_cr = full_cr; + assign main_rb = rb; + assign main_ra = ra; + assign { main_cr_op__insn, main_cr_op__fn_unit, main_cr_op__insn_type } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; + assign main_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" *) +(* generator = "nMigen" *) +module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, cr_a, n_valid_o, n_ready_i, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \fast1$10 , fast1_ok, \fast2$11 , fast2_ok, nia, nia_ok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] br_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \br_op__cia$2 ; + reg [63:0] \br_op__cia$2 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \br_op__cia$2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \br_op__cia$27 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] br_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \br_op__fn_unit$29 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \br_op__fn_unit$4 ; + reg [13:0] \br_op__fn_unit$4 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \br_op__fn_unit$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] br_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \br_op__imm_data__data$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \br_op__imm_data__data$6 ; + reg [63:0] \br_op__imm_data__data$6 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \br_op__imm_data__data$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \br_op__imm_data__ok$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \br_op__imm_data__ok$7 ; + reg \br_op__imm_data__ok$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \br_op__imm_data__ok$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] br_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \br_op__insn$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \br_op__insn$5 ; + reg [31:0] \br_op__insn$5 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \br_op__insn$5$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] br_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \br_op__insn_type$28 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \br_op__insn_type$3 ; + reg [6:0] \br_op__insn_type$3 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \br_op__insn_type$3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \br_op__is_32bit$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \br_op__is_32bit$9 ; + reg \br_op__is_32bit$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \br_op__is_32bit$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input br_op__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \br_op__lk$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \br_op__lk$8 ; + reg \br_op__lk$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \br_op__lk$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast1$10 ; + reg [63:0] \fast1$10 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \fast1$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \fast1$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + reg fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fast1_ok$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \fast1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast2$11 ; + reg [63:0] \fast2$11 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \fast2$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \fast2$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + reg fast2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fast2_ok$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \fast2_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] main_br_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \main_br_op__cia$13 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] main_br_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \main_br_op__fn_unit$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] main_br_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \main_br_op__imm_data__data$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_br_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_br_op__imm_data__ok$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] main_br_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \main_br_op__insn$16 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] main_br_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \main_br_op__insn_type$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_br_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_br_op__is_32bit$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_br_op__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_br_op__lk$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [3:0] main_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \main_fast1$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \main_fast2$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_fast2_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] main_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \main_muxid$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] main_nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_nia_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$26 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] nia; + reg [63:0] nia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \nia$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \nia$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + reg nia_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \nia_ok$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \nia_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + assign \$24 = \p_valid_i$23 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + nia <= \nia$next ; + always @(posedge coresync_clk) + nia_ok <= \nia_ok$next ; + always @(posedge coresync_clk) + \fast2$11 <= \fast2$11$next ; + always @(posedge coresync_clk) + fast2_ok <= \fast2_ok$next ; + always @(posedge coresync_clk) + \fast1$10 <= \fast1$10$next ; + always @(posedge coresync_clk) + fast1_ok <= \fast1_ok$next ; + always @(posedge coresync_clk) + \br_op__cia$2 <= \br_op__cia$2$next ; + always @(posedge coresync_clk) + \br_op__insn_type$3 <= \br_op__insn_type$3$next ; + always @(posedge coresync_clk) + \br_op__fn_unit$4 <= \br_op__fn_unit$4$next ; + always @(posedge coresync_clk) + \br_op__insn$5 <= \br_op__insn$5$next ; + always @(posedge coresync_clk) + \br_op__imm_data__data$6 <= \br_op__imm_data__data$6$next ; + always @(posedge coresync_clk) + \br_op__imm_data__ok$7 <= \br_op__imm_data__ok$7$next ; + always @(posedge coresync_clk) + \br_op__lk$8 <= \br_op__lk$8$next ; + always @(posedge coresync_clk) + \br_op__is_32bit$9 <= \br_op__is_32bit$9$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \main$22 main ( + .br_op__cia(main_br_op__cia), + .\br_op__cia$2 (\main_br_op__cia$13 ), + .br_op__fn_unit(main_br_op__fn_unit), + .\br_op__fn_unit$4 (\main_br_op__fn_unit$15 ), + .br_op__imm_data__data(main_br_op__imm_data__data), + .\br_op__imm_data__data$6 (\main_br_op__imm_data__data$17 ), + .br_op__imm_data__ok(main_br_op__imm_data__ok), + .\br_op__imm_data__ok$7 (\main_br_op__imm_data__ok$18 ), + .br_op__insn(main_br_op__insn), + .\br_op__insn$5 (\main_br_op__insn$16 ), + .br_op__insn_type(main_br_op__insn_type), + .\br_op__insn_type$3 (\main_br_op__insn_type$14 ), + .br_op__is_32bit(main_br_op__is_32bit), + .\br_op__is_32bit$9 (\main_br_op__is_32bit$20 ), + .br_op__lk(main_br_op__lk), + .\br_op__lk$8 (\main_br_op__lk$19 ), + .cr_a(main_cr_a), + .fast1(main_fast1), + .\fast1$10 (\main_fast1$21 ), + .fast1_ok(main_fast1_ok), + .fast2(main_fast2), + .\fast2$11 (\main_fast2$22 ), + .fast2_ok(main_fast2_ok), + .muxid(main_muxid), + .\muxid$1 (\main_muxid$12 ), + .nia(main_nia), + .nia_ok(main_nia_ok) + ); + \n$21 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$20 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$26 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$26 ; + endcase + end + always @* begin + if (\initial ) begin end + \br_op__cia$2$next = \br_op__cia$2 ; + \br_op__insn_type$3$next = \br_op__insn_type$3 ; + \br_op__fn_unit$4$next = \br_op__fn_unit$4 ; + \br_op__insn$5$next = \br_op__insn$5 ; + \br_op__imm_data__data$6$next = \br_op__imm_data__data$6 ; + \br_op__imm_data__ok$7$next = \br_op__imm_data__ok$7 ; + \br_op__lk$8$next = \br_op__lk$8 ; + \br_op__is_32bit$9$next = \br_op__is_32bit$9 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \br_op__imm_data__data$6$next = 64'h0000000000000000; + \br_op__imm_data__ok$7$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \fast1$10$next = \fast1$10 ; + \fast1_ok$next = fast1_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \fast1_ok$next , \fast1$10$next } = { \fast1_ok$36 , \fast1$35 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \fast1_ok$next , \fast1$10$next } = { \fast1_ok$36 , \fast1$35 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \fast1_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fast2$11$next = \fast2$11 ; + \fast2_ok$next = fast2_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \fast2_ok$next , \fast2$11$next } = { \fast2_ok$38 , \fast2$37 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \fast2_ok$next , \fast2$11$next } = { \fast2_ok$38 , \fast2$37 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \fast2_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \nia$next = nia; + \nia_ok$next = nia_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \nia_ok$next , \nia$next } = { \nia_ok$40 , \nia$39 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \nia_ok$next , \nia$next } = { \nia_ok$40 , \nia$39 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \nia_ok$next = 1'h0; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \nia_ok$40 , \nia$39 } = { main_nia_ok, main_nia }; + assign { \fast2_ok$38 , \fast2$37 } = { main_fast2_ok, \main_fast2$22 }; + assign { \fast1_ok$36 , \fast1$35 } = { main_fast1_ok, \main_fast1$21 }; + assign { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27 } = { \main_br_op__is_32bit$20 , \main_br_op__lk$19 , \main_br_op__imm_data__ok$18 , \main_br_op__imm_data__data$17 , \main_br_op__insn$16 , \main_br_op__fn_unit$15 , \main_br_op__insn_type$14 , \main_br_op__cia$13 }; + assign \muxid$26 = \main_muxid$12 ; + assign p_valid_i_p_ready_o = \$24 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$23 = p_valid_i; + assign main_cr_a = cr_a; + assign main_fast2 = fast2; + assign main_fast1 = fast1; + assign { main_br_op__is_32bit, main_br_op__lk, main_br_op__imm_data__ok, main_br_op__imm_data__data, main_br_op__insn, main_br_op__fn_unit, main_br_op__insn_type, main_br_op__cia } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; + assign main_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" *) +(* generator = "nMigen" *) +module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, ra, spr1, fast1, xer_so, xer_ov, xer_ca, n_valid_o, n_ready_i, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , o, o_ok, \spr1$6 , spr1_ok, \fast1$7 , fast1_ok, \xer_so$8 , xer_so_ok, \xer_ov$9 , xer_ov_ok, \xer_ca$10 , xer_ca_ok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \fast1$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast1$7 ; + reg [63:0] \fast1$7 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \fast1$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + reg fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fast1_ok$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \fast1_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \spr1$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \spr1$6 ; + reg [63:0] \spr1$6 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \spr1$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr1_ok; + reg spr1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \spr1_ok$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \spr1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] spr_main_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \spr_main_fast1$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire spr_main_fast1_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] spr_main_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \spr_main_muxid$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] spr_main_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire spr_main_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] spr_main_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] spr_main_spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \spr_main_spr1$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire spr_main_spr1_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] spr_main_spr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \spr_main_spr_op__fn_unit$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] spr_main_spr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \spr_main_spr_op__insn$14 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] spr_main_spr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \spr_main_spr_op__insn_type$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire spr_main_spr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \spr_main_spr_op__is_32bit$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] spr_main_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \spr_main_xer_ca$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire spr_main_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] spr_main_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \spr_main_xer_ov$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire spr_main_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire spr_main_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \spr_main_xer_so$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire spr_main_xer_so_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] spr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \spr_op__fn_unit$26 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \spr_op__fn_unit$3 ; + reg [13:0] \spr_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \spr_op__fn_unit$3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] spr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \spr_op__insn$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \spr_op__insn$4 ; + reg [31:0] \spr_op__insn$4 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \spr_op__insn$4$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] spr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \spr_op__insn_type$2 ; + reg [6:0] \spr_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \spr_op__insn_type$2$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \spr_op__insn_type$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input spr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \spr_op__is_32bit$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \spr_op__is_32bit$5 ; + reg \spr_op__is_32bit$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \spr_op__is_32bit$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ca$10 ; + reg [1:0] \xer_ca$10 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ca$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ca$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + reg xer_ca_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ca_ok$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ca_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ov$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ov$9 ; + reg [1:0] \xer_ov$9 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ov$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ov_ok$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ov_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$8 ; + reg \xer_so$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so_ok$next ; + assign \$22 = \p_valid_i$21 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \xer_ca$10 <= \xer_ca$10$next ; + always @(posedge coresync_clk) + xer_ca_ok <= \xer_ca_ok$next ; + always @(posedge coresync_clk) + \xer_ov$9 <= \xer_ov$9$next ; + always @(posedge coresync_clk) + xer_ov_ok <= \xer_ov_ok$next ; + always @(posedge coresync_clk) + \xer_so$8 <= \xer_so$8$next ; + always @(posedge coresync_clk) + xer_so_ok <= \xer_so_ok$next ; + always @(posedge coresync_clk) + \fast1$7 <= \fast1$7$next ; + always @(posedge coresync_clk) + fast1_ok <= \fast1_ok$next ; + always @(posedge coresync_clk) + \spr1$6 <= \spr1$6$next ; + always @(posedge coresync_clk) + spr1_ok <= \spr1_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; + always @(posedge coresync_clk) + o_ok <= \o_ok$next ; + always @(posedge coresync_clk) + \spr_op__insn_type$2 <= \spr_op__insn_type$2$next ; + always @(posedge coresync_clk) + \spr_op__fn_unit$3 <= \spr_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \spr_op__insn$4 <= \spr_op__insn$4$next ; + always @(posedge coresync_clk) + \spr_op__is_32bit$5 <= \spr_op__is_32bit$5$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \n$66 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$65 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + spr_main spr_main ( + .fast1(spr_main_fast1), + .\fast1$7 (\spr_main_fast1$17 ), + .fast1_ok(spr_main_fast1_ok), + .muxid(spr_main_muxid), + .\muxid$1 (\spr_main_muxid$11 ), + .o(spr_main_o), + .o_ok(spr_main_o_ok), + .ra(spr_main_ra), + .spr1(spr_main_spr1), + .\spr1$6 (\spr_main_spr1$16 ), + .spr1_ok(spr_main_spr1_ok), + .spr_op__fn_unit(spr_main_spr_op__fn_unit), + .\spr_op__fn_unit$3 (\spr_main_spr_op__fn_unit$13 ), + .spr_op__insn(spr_main_spr_op__insn), + .\spr_op__insn$4 (\spr_main_spr_op__insn$14 ), + .spr_op__insn_type(spr_main_spr_op__insn_type), + .\spr_op__insn_type$2 (\spr_main_spr_op__insn_type$12 ), + .spr_op__is_32bit(spr_main_spr_op__is_32bit), + .\spr_op__is_32bit$5 (\spr_main_spr_op__is_32bit$15 ), + .xer_ca(spr_main_xer_ca), + .\xer_ca$10 (\spr_main_xer_ca$20 ), + .xer_ca_ok(spr_main_xer_ca_ok), + .xer_ov(spr_main_xer_ov), + .\xer_ov$9 (\spr_main_xer_ov$19 ), + .xer_ov_ok(spr_main_xer_ov_ok), + .xer_so(spr_main_xer_so), + .\xer_so$8 (\spr_main_xer_so$18 ), + .xer_so_ok(spr_main_xer_so_ok) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$24 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$24 ; + endcase + end + always @* begin + if (\initial ) begin end + \spr_op__insn_type$2$next = \spr_op__insn_type$2 ; + \spr_op__fn_unit$3$next = \spr_op__fn_unit$3 ; + \spr_op__insn$4$next = \spr_op__insn$4 ; + \spr_op__is_32bit$5$next = \spr_op__is_32bit$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25 }; + endcase + end + always @* begin + if (\initial ) begin end + \o$next = o; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$next } = { \o_ok$30 , \o$29 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$next } = { \o_ok$30 , \o$29 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \spr1$6$next = \spr1$6 ; + \spr1_ok$next = spr1_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \spr1_ok$next , \spr1$6$next } = { \spr1_ok$32 , \spr1$31 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \spr1_ok$next , \spr1$6$next } = { \spr1_ok$32 , \spr1$31 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \spr1_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fast1$7$next = \fast1$7 ; + \fast1_ok$next = fast1_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \fast1_ok$next , \fast1$7$next } = { \fast1_ok$34 , \fast1$33 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \fast1_ok$next , \fast1$7$next } = { \fast1_ok$34 , \fast1$33 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \fast1_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$8$next = \xer_so$8 ; + \xer_so_ok$next = xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_so_ok$next , \xer_so$8$next } = { \xer_so_ok$36 , \xer_so$35 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_so_ok$next , \xer_so$8$next } = { \xer_so_ok$36 , \xer_so$35 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_so_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$9$next = \xer_ov$9 ; + \xer_ov_ok$next = xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ov_ok$next , \xer_ov$9$next } = { \xer_ov_ok$38 , \xer_ov$37 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ov_ok$next , \xer_ov$9$next } = { \xer_ov_ok$38 , \xer_ov$37 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ov_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$10$next = \xer_ca$10 ; + \xer_ca_ok$next = xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ca_ok$next , \xer_ca$10$next } = { \xer_ca_ok$40 , \xer_ca$39 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ca_ok$next , \xer_ca$10$next } = { \xer_ca_ok$40 , \xer_ca$39 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ca_ok$next = 1'h0; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \xer_ca_ok$40 , \xer_ca$39 } = { spr_main_xer_ca_ok, \spr_main_xer_ca$20 }; + assign { \xer_ov_ok$38 , \xer_ov$37 } = { spr_main_xer_ov_ok, \spr_main_xer_ov$19 }; + assign { \xer_so_ok$36 , \xer_so$35 } = { spr_main_xer_so_ok, \spr_main_xer_so$18 }; + assign { \fast1_ok$34 , \fast1$33 } = { spr_main_fast1_ok, \spr_main_fast1$17 }; + assign { \spr1_ok$32 , \spr1$31 } = { spr_main_spr1_ok, \spr_main_spr1$16 }; + assign { \o_ok$30 , \o$29 } = { spr_main_o_ok, spr_main_o }; + assign { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25 } = { \spr_main_spr_op__is_32bit$15 , \spr_main_spr_op__insn$14 , \spr_main_spr_op__fn_unit$13 , \spr_main_spr_op__insn_type$12 }; + assign \muxid$24 = \spr_main_muxid$11 ; + assign p_valid_i_p_ready_o = \$22 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$21 = p_valid_i; + assign spr_main_xer_ca = xer_ca; + assign spr_main_xer_ov = xer_ov; + assign spr_main_xer_so = xer_so; + assign spr_main_fast1 = fast1; + assign spr_main_spr1 = spr1; + assign spr_main_ra = ra; + assign { spr_main_spr_op__is_32bit, spr_main_spr_op__insn, spr_main_spr_op__fn_unit, spr_main_spr_op__insn_type } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; + assign spr_main_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" *) +(* generator = "nMigen" *) +module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , ra, rb, \xer_so$20 , \xer_ca$21 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] alu_op__data_len; + reg [3:0] alu_op__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] \alu_op__data_len$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \alu_op__data_len$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \alu_op__data_len$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] alu_op__fn_unit; + reg [13:0] alu_op__fn_unit = 14'h0000; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] \alu_op__fn_unit$3 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \alu_op__fn_unit$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] alu_op__imm_data__data; + reg [63:0] alu_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] \alu_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \alu_op__imm_data__data$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__imm_data__ok; + reg alu_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__imm_data__ok$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__imm_data__ok$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] alu_op__input_carry; + reg [1:0] alu_op__input_carry = 2'h0; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] \alu_op__input_carry$14 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \alu_op__input_carry$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \alu_op__input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] alu_op__insn; + reg [31:0] alu_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] \alu_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \alu_op__insn$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] alu_op__insn_type; + reg [6:0] alu_op__insn_type = 7'h00; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] \alu_op__insn_type$2 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \alu_op__insn_type$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__invert_in; + reg alu_op__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__invert_in$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__invert_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__invert_out; + reg alu_op__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__invert_out$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__invert_out$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__invert_out$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__is_32bit; + reg alu_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__is_32bit$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__is_signed; + reg alu_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__is_signed$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__oe__oe; + reg alu_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__oe__oe$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__oe__ok; + reg alu_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__oe__ok$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__output_carry; + reg alu_op__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__output_carry$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__output_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__rc__ok; + reg alu_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__rc__ok$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__rc__rc; + reg alu_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__rc__rc$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__write_cr0; + reg alu_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__write_cr0$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__write_cr0$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output alu_op__zero_a; + reg alu_op__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \alu_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__zero_a$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__zero_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + reg [3:0] cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + reg cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] input_alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \input_alu_op__data_len$39 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] input_alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \input_alu_op__fn_unit$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] input_alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \input_alu_op__imm_data__data$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__imm_data__ok$26 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] input_alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \input_alu_op__input_carry$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] input_alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \input_alu_op__insn$40 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] input_alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \input_alu_op__insn_type$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__invert_in$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__invert_out$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__is_32bit$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__is_signed$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__oe__oe$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__oe__ok$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__output_carry$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__rc__ok$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__rc__rc$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__write_cr0$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_alu_op__zero_a$32 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] input_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \input_muxid$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_ra$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_rb$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] input_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \input_xer_ca$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire input_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \input_xer_so$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] main_alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \main_alu_op__data_len$62 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] main_alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \main_alu_op__fn_unit$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] main_alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \main_alu_op__imm_data__data$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__imm_data__ok$49 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] main_alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \main_alu_op__input_carry$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] main_alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \main_alu_op__insn$63 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] main_alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \main_alu_op__insn_type$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__invert_in$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__invert_out$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__is_32bit$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__is_signed$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__oe__oe$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__oe__ok$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__output_carry$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__rc__ok$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__rc__rc$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__write_cr0$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_alu_op__zero_a$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] main_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] main_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \main_muxid$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] main_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] main_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \main_xer_ca$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] main_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire main_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \main_xer_so$65 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] muxid; + reg [1:0] muxid = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$69 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$66 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ca; + reg [1:0] xer_ca = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] \xer_ca$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ca$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ca$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + reg xer_ca_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ca_ok$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ca_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + reg [1:0] xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ov$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ov$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ov_ok$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ov_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so; + reg xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so_ok$next ; + assign \$67 = \p_valid_i$66 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + xer_so <= \xer_so$next ; + always @(posedge coresync_clk) + xer_so_ok <= \xer_so_ok$next ; + always @(posedge coresync_clk) + xer_ov <= \xer_ov$next ; + always @(posedge coresync_clk) + xer_ov_ok <= \xer_ov_ok$next ; + always @(posedge coresync_clk) + xer_ca <= \xer_ca$next ; + always @(posedge coresync_clk) + xer_ca_ok <= \xer_ca_ok$next ; + always @(posedge coresync_clk) + cr_a <= \cr_a$next ; + always @(posedge coresync_clk) + cr_a_ok <= \cr_a_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; + always @(posedge coresync_clk) + o_ok <= \o_ok$next ; + always @(posedge coresync_clk) + alu_op__insn_type <= \alu_op__insn_type$next ; + always @(posedge coresync_clk) + alu_op__fn_unit <= \alu_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_op__imm_data__data <= \alu_op__imm_data__data$next ; + always @(posedge coresync_clk) + alu_op__imm_data__ok <= \alu_op__imm_data__ok$next ; + always @(posedge coresync_clk) + alu_op__rc__rc <= \alu_op__rc__rc$next ; + always @(posedge coresync_clk) + alu_op__rc__ok <= \alu_op__rc__ok$next ; + always @(posedge coresync_clk) + alu_op__oe__oe <= \alu_op__oe__oe$next ; + always @(posedge coresync_clk) + alu_op__oe__ok <= \alu_op__oe__ok$next ; + always @(posedge coresync_clk) + alu_op__invert_in <= \alu_op__invert_in$next ; + always @(posedge coresync_clk) + alu_op__zero_a <= \alu_op__zero_a$next ; + always @(posedge coresync_clk) + alu_op__invert_out <= \alu_op__invert_out$next ; + always @(posedge coresync_clk) + alu_op__write_cr0 <= \alu_op__write_cr0$next ; + always @(posedge coresync_clk) + alu_op__input_carry <= \alu_op__input_carry$next ; + always @(posedge coresync_clk) + alu_op__output_carry <= \alu_op__output_carry$next ; + always @(posedge coresync_clk) + alu_op__is_32bit <= \alu_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_op__is_signed <= \alu_op__is_signed$next ; + always @(posedge coresync_clk) + alu_op__data_len <= \alu_op__data_len$next ; + always @(posedge coresync_clk) + alu_op__insn <= \alu_op__insn$next ; + always @(posedge coresync_clk) + muxid <= \muxid$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \input \input ( + .alu_op__data_len(input_alu_op__data_len), + .\alu_op__data_len$18 (\input_alu_op__data_len$39 ), + .alu_op__fn_unit(input_alu_op__fn_unit), + .\alu_op__fn_unit$3 (\input_alu_op__fn_unit$24 ), + .alu_op__imm_data__data(input_alu_op__imm_data__data), + .\alu_op__imm_data__data$4 (\input_alu_op__imm_data__data$25 ), + .alu_op__imm_data__ok(input_alu_op__imm_data__ok), + .\alu_op__imm_data__ok$5 (\input_alu_op__imm_data__ok$26 ), + .alu_op__input_carry(input_alu_op__input_carry), + .\alu_op__input_carry$14 (\input_alu_op__input_carry$35 ), + .alu_op__insn(input_alu_op__insn), + .\alu_op__insn$19 (\input_alu_op__insn$40 ), + .alu_op__insn_type(input_alu_op__insn_type), + .\alu_op__insn_type$2 (\input_alu_op__insn_type$23 ), + .alu_op__invert_in(input_alu_op__invert_in), + .\alu_op__invert_in$10 (\input_alu_op__invert_in$31 ), + .alu_op__invert_out(input_alu_op__invert_out), + .\alu_op__invert_out$12 (\input_alu_op__invert_out$33 ), + .alu_op__is_32bit(input_alu_op__is_32bit), + .\alu_op__is_32bit$16 (\input_alu_op__is_32bit$37 ), + .alu_op__is_signed(input_alu_op__is_signed), + .\alu_op__is_signed$17 (\input_alu_op__is_signed$38 ), + .alu_op__oe__oe(input_alu_op__oe__oe), + .\alu_op__oe__oe$8 (\input_alu_op__oe__oe$29 ), + .alu_op__oe__ok(input_alu_op__oe__ok), + .\alu_op__oe__ok$9 (\input_alu_op__oe__ok$30 ), + .alu_op__output_carry(input_alu_op__output_carry), + .\alu_op__output_carry$15 (\input_alu_op__output_carry$36 ), + .alu_op__rc__ok(input_alu_op__rc__ok), + .\alu_op__rc__ok$7 (\input_alu_op__rc__ok$28 ), + .alu_op__rc__rc(input_alu_op__rc__rc), + .\alu_op__rc__rc$6 (\input_alu_op__rc__rc$27 ), + .alu_op__write_cr0(input_alu_op__write_cr0), + .\alu_op__write_cr0$13 (\input_alu_op__write_cr0$34 ), + .alu_op__zero_a(input_alu_op__zero_a), + .\alu_op__zero_a$11 (\input_alu_op__zero_a$32 ), + .muxid(input_muxid), + .\muxid$1 (\input_muxid$22 ), + .ra(input_ra), + .\ra$20 (\input_ra$41 ), + .rb(input_rb), + .\rb$21 (\input_rb$42 ), + .xer_ca(input_xer_ca), + .\xer_ca$23 (\input_xer_ca$44 ), + .xer_so(input_xer_so), + .\xer_so$22 (\input_xer_so$43 ) + ); + main main ( + .alu_op__data_len(main_alu_op__data_len), + .\alu_op__data_len$18 (\main_alu_op__data_len$62 ), + .alu_op__fn_unit(main_alu_op__fn_unit), + .\alu_op__fn_unit$3 (\main_alu_op__fn_unit$47 ), + .alu_op__imm_data__data(main_alu_op__imm_data__data), + .\alu_op__imm_data__data$4 (\main_alu_op__imm_data__data$48 ), + .alu_op__imm_data__ok(main_alu_op__imm_data__ok), + .\alu_op__imm_data__ok$5 (\main_alu_op__imm_data__ok$49 ), + .alu_op__input_carry(main_alu_op__input_carry), + .\alu_op__input_carry$14 (\main_alu_op__input_carry$58 ), + .alu_op__insn(main_alu_op__insn), + .\alu_op__insn$19 (\main_alu_op__insn$63 ), + .alu_op__insn_type(main_alu_op__insn_type), + .\alu_op__insn_type$2 (\main_alu_op__insn_type$46 ), + .alu_op__invert_in(main_alu_op__invert_in), + .\alu_op__invert_in$10 (\main_alu_op__invert_in$54 ), + .alu_op__invert_out(main_alu_op__invert_out), + .\alu_op__invert_out$12 (\main_alu_op__invert_out$56 ), + .alu_op__is_32bit(main_alu_op__is_32bit), + .\alu_op__is_32bit$16 (\main_alu_op__is_32bit$60 ), + .alu_op__is_signed(main_alu_op__is_signed), + .\alu_op__is_signed$17 (\main_alu_op__is_signed$61 ), + .alu_op__oe__oe(main_alu_op__oe__oe), + .\alu_op__oe__oe$8 (\main_alu_op__oe__oe$52 ), + .alu_op__oe__ok(main_alu_op__oe__ok), + .\alu_op__oe__ok$9 (\main_alu_op__oe__ok$53 ), + .alu_op__output_carry(main_alu_op__output_carry), + .\alu_op__output_carry$15 (\main_alu_op__output_carry$59 ), + .alu_op__rc__ok(main_alu_op__rc__ok), + .\alu_op__rc__ok$7 (\main_alu_op__rc__ok$51 ), + .alu_op__rc__rc(main_alu_op__rc__rc), + .\alu_op__rc__rc$6 (\main_alu_op__rc__rc$50 ), + .alu_op__write_cr0(main_alu_op__write_cr0), + .\alu_op__write_cr0$13 (\main_alu_op__write_cr0$57 ), + .alu_op__zero_a(main_alu_op__zero_a), + .\alu_op__zero_a$11 (\main_alu_op__zero_a$55 ), + .cr_a(main_cr_a), + .cr_a_ok(main_cr_a_ok), + .muxid(main_muxid), + .\muxid$1 (\main_muxid$45 ), + .o(main_o), + .o_ok(main_o_ok), + .ra(main_ra), + .rb(main_rb), + .xer_ca(main_xer_ca), + .\xer_ca$20 (\main_xer_ca$64 ), + .xer_ca_ok(main_xer_ca_ok), + .xer_ov(main_xer_ov), + .xer_ov_ok(main_xer_ov_ok), + .xer_so(main_xer_so), + .\xer_so$21 (\main_xer_so$65 ) + ); + \n$2 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$1 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \cr_a$next = cr_a; + \cr_a_ok$next = cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$91 , \cr_a$90 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$91 , \cr_a$90 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$next = xer_ca; + \xer_ca_ok$next = xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$93 , \xer_ca$92 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$93 , \xer_ca$92 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ca_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$next = xer_ov; + \xer_ov_ok$next = xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$95 , \xer_ov$94 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$95 , \xer_ov$94 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ov_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$next = xer_so; + \xer_so_ok$next = xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$97 , \xer_so$96 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$97 , \xer_so$96 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_so_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$next = muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$next = \muxid$69 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$next = \muxid$69 ; + endcase + end + always @* begin + if (\initial ) begin end + \alu_op__insn_type$next = alu_op__insn_type; + \alu_op__fn_unit$next = alu_op__fn_unit; + \alu_op__imm_data__data$next = alu_op__imm_data__data; + \alu_op__imm_data__ok$next = alu_op__imm_data__ok; + \alu_op__rc__rc$next = alu_op__rc__rc; + \alu_op__rc__ok$next = alu_op__rc__ok; + \alu_op__oe__oe$next = alu_op__oe__oe; + \alu_op__oe__ok$next = alu_op__oe__ok; + \alu_op__invert_in$next = alu_op__invert_in; + \alu_op__zero_a$next = alu_op__zero_a; + \alu_op__invert_out$next = alu_op__invert_out; + \alu_op__write_cr0$next = alu_op__write_cr0; + \alu_op__input_carry$next = alu_op__input_carry; + \alu_op__output_carry$next = alu_op__output_carry; + \alu_op__is_32bit$next = alu_op__is_32bit; + \alu_op__is_signed$next = alu_op__is_signed; + \alu_op__data_len$next = alu_op__data_len; + \alu_op__insn$next = alu_op__insn; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \alu_op__imm_data__data$next = 64'h0000000000000000; + \alu_op__imm_data__ok$next = 1'h0; + \alu_op__rc__rc$next = 1'h0; + \alu_op__rc__ok$next = 1'h0; + \alu_op__oe__oe$next = 1'h0; + \alu_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \o$next = o; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$next } = { \o_ok$89 , \o$88 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$next } = { \o_ok$89 , \o$88 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end + assign \xer_so_ok$98 = 1'h0; + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \xer_so_ok$97 , \xer_so$96 } = { 1'h0, \main_xer_so$65 }; + assign { \xer_ov_ok$95 , \xer_ov$94 } = { main_xer_ov_ok, main_xer_ov }; + assign { \xer_ca_ok$93 , \xer_ca$92 } = { main_xer_ca_ok, \main_xer_ca$64 }; + assign { \cr_a_ok$91 , \cr_a$90 } = { main_cr_a_ok, main_cr_a }; + assign { \o_ok$89 , \o$88 } = { main_o_ok, main_o }; + assign { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70 } = { \main_alu_op__insn$63 , \main_alu_op__data_len$62 , \main_alu_op__is_signed$61 , \main_alu_op__is_32bit$60 , \main_alu_op__output_carry$59 , \main_alu_op__input_carry$58 , \main_alu_op__write_cr0$57 , \main_alu_op__invert_out$56 , \main_alu_op__zero_a$55 , \main_alu_op__invert_in$54 , \main_alu_op__oe__ok$53 , \main_alu_op__oe__oe$52 , \main_alu_op__rc__ok$51 , \main_alu_op__rc__rc$50 , \main_alu_op__imm_data__ok$49 , \main_alu_op__imm_data__data$48 , \main_alu_op__fn_unit$47 , \main_alu_op__insn_type$46 }; + assign \muxid$69 = \main_muxid$45 ; + assign p_valid_i_p_ready_o = \$67 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$66 = p_valid_i; + assign main_xer_ca = \input_xer_ca$44 ; + assign main_xer_so = \input_xer_so$43 ; + assign main_rb = \input_rb$42 ; + assign main_ra = \input_ra$41 ; + assign { main_alu_op__insn, main_alu_op__data_len, main_alu_op__is_signed, main_alu_op__is_32bit, main_alu_op__output_carry, main_alu_op__input_carry, main_alu_op__write_cr0, main_alu_op__invert_out, main_alu_op__zero_a, main_alu_op__invert_in, main_alu_op__oe__ok, main_alu_op__oe__oe, main_alu_op__rc__ok, main_alu_op__rc__rc, main_alu_op__imm_data__ok, main_alu_op__imm_data__data, main_alu_op__fn_unit, main_alu_op__insn_type } = { \input_alu_op__insn$40 , \input_alu_op__data_len$39 , \input_alu_op__is_signed$38 , \input_alu_op__is_32bit$37 , \input_alu_op__output_carry$36 , \input_alu_op__input_carry$35 , \input_alu_op__write_cr0$34 , \input_alu_op__invert_out$33 , \input_alu_op__zero_a$32 , \input_alu_op__invert_in$31 , \input_alu_op__oe__ok$30 , \input_alu_op__oe__oe$29 , \input_alu_op__rc__ok$28 , \input_alu_op__rc__rc$27 , \input_alu_op__imm_data__ok$26 , \input_alu_op__imm_data__data$25 , \input_alu_op__fn_unit$24 , \input_alu_op__insn_type$23 }; + assign main_muxid = \input_muxid$22 ; + assign input_xer_ca = \xer_ca$21 ; + assign input_xer_so = \xer_so$20 ; + assign input_rb = rb; + assign input_ra = ra; + assign { input_alu_op__insn, input_alu_op__data_len, input_alu_op__is_signed, input_alu_op__is_32bit, input_alu_op__output_carry, input_alu_op__input_carry, input_alu_op__write_cr0, input_alu_op__invert_out, input_alu_op__zero_a, input_alu_op__invert_in, input_alu_op__oe__ok, input_alu_op__oe__oe, input_alu_op__rc__ok, input_alu_op__rc__rc, input_alu_op__imm_data__ok, input_alu_op__imm_data__data, input_alu_op__fn_unit, input_alu_op__insn_type } = { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 }; + assign input_muxid = \muxid$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" *) +(* generator = "nMigen" *) +module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, p_valid_i, p_ready_o, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , ra, rb, rc, \xer_so$19 , \xer_ca$20 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + reg [3:0] cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + reg cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] input_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \input_muxid$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_ra$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_rb$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_rc$41 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] input_sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \input_sr_op__fn_unit$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] input_sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \input_sr_op__imm_data__data$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__imm_data__ok$25 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] input_sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \input_sr_op__input_carry$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__input_cr$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] input_sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \input_sr_op__insn$38 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] input_sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \input_sr_op__insn_type$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__invert_in$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__is_32bit$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__is_signed$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__oe__oe$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__oe__ok$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__output_carry$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__output_cr$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__rc__ok$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__rc__rc$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_sr_op__write_cr0$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] input_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \input_xer_ca$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire input_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \input_xer_so$42 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] main_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \main_muxid$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] main_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_rc; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] main_sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \main_sr_op__fn_unit$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] main_sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \main_sr_op__imm_data__data$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__imm_data__ok$48 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] main_sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \main_sr_op__input_carry$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__input_cr$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] main_sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \main_sr_op__insn$61 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] main_sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \main_sr_op__insn_type$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__invert_in$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__is_32bit$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__is_signed$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__oe__oe$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__oe__ok$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__output_carry$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__output_cr$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__rc__ok$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__rc__rc$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_sr_op__write_cr0$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] main_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire main_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \main_xer_so$62 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] muxid; + reg [1:0] muxid = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$67 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$64 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rc; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] sr_op__fn_unit; + reg [13:0] sr_op__fn_unit = 14'h0000; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] \sr_op__fn_unit$3 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \sr_op__fn_unit$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \sr_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] sr_op__imm_data__data; + reg [63:0] sr_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] \sr_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \sr_op__imm_data__data$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \sr_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__imm_data__ok; + reg sr_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__imm_data__ok$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__imm_data__ok$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] sr_op__input_carry; + reg [1:0] sr_op__input_carry = 2'h0; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] \sr_op__input_carry$12 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \sr_op__input_carry$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \sr_op__input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__input_cr; + reg sr_op__input_cr = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__input_cr$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__input_cr$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__input_cr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] sr_op__insn; + reg [31:0] sr_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] \sr_op__insn$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \sr_op__insn$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \sr_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] sr_op__insn_type; + reg [6:0] sr_op__insn_type = 7'h00; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] \sr_op__insn_type$2 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \sr_op__insn_type$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \sr_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__invert_in; + reg sr_op__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__invert_in$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__invert_in$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__invert_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__is_32bit; + reg sr_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__is_32bit$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__is_signed; + reg sr_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__is_signed$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__oe__oe; + reg sr_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__oe__oe$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__oe__ok; + reg sr_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__oe__ok$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__output_carry; + reg sr_op__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__output_carry$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__output_carry$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__output_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__output_cr; + reg sr_op__output_cr = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__output_cr$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__output_cr$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__output_cr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__rc__ok; + reg sr_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__rc__ok$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__rc__rc; + reg sr_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__rc__rc$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output sr_op__write_cr0; + reg sr_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \sr_op__write_cr0$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__write_cr0$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ca; + reg [1:0] xer_ca = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] \xer_ca$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \xer_ca$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ca$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ca$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + reg xer_ca_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ca_ok$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ca_ok$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ca_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so; + reg xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so_ok$next ; + assign \$65 = \p_valid_i$64 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + xer_ca <= \xer_ca$next ; + always @(posedge coresync_clk) + xer_ca_ok <= \xer_ca_ok$next ; + always @(posedge coresync_clk) + xer_so <= \xer_so$next ; + always @(posedge coresync_clk) + xer_so_ok <= \xer_so_ok$next ; + always @(posedge coresync_clk) + cr_a <= \cr_a$next ; + always @(posedge coresync_clk) + cr_a_ok <= \cr_a_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; + always @(posedge coresync_clk) + o_ok <= \o_ok$next ; + always @(posedge coresync_clk) + sr_op__insn_type <= \sr_op__insn_type$next ; + always @(posedge coresync_clk) + sr_op__fn_unit <= \sr_op__fn_unit$next ; + always @(posedge coresync_clk) + sr_op__imm_data__data <= \sr_op__imm_data__data$next ; + always @(posedge coresync_clk) + sr_op__imm_data__ok <= \sr_op__imm_data__ok$next ; + always @(posedge coresync_clk) + sr_op__rc__rc <= \sr_op__rc__rc$next ; + always @(posedge coresync_clk) + sr_op__rc__ok <= \sr_op__rc__ok$next ; + always @(posedge coresync_clk) + sr_op__oe__oe <= \sr_op__oe__oe$next ; + always @(posedge coresync_clk) + sr_op__oe__ok <= \sr_op__oe__ok$next ; + always @(posedge coresync_clk) + sr_op__write_cr0 <= \sr_op__write_cr0$next ; + always @(posedge coresync_clk) + sr_op__invert_in <= \sr_op__invert_in$next ; + always @(posedge coresync_clk) + sr_op__input_carry <= \sr_op__input_carry$next ; + always @(posedge coresync_clk) + sr_op__output_carry <= \sr_op__output_carry$next ; + always @(posedge coresync_clk) + sr_op__input_cr <= \sr_op__input_cr$next ; + always @(posedge coresync_clk) + sr_op__output_cr <= \sr_op__output_cr$next ; + always @(posedge coresync_clk) + sr_op__is_32bit <= \sr_op__is_32bit$next ; + always @(posedge coresync_clk) + sr_op__is_signed <= \sr_op__is_signed$next ; + always @(posedge coresync_clk) + sr_op__insn <= \sr_op__insn$next ; + always @(posedge coresync_clk) + muxid <= \muxid$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \input$113 \input ( + .muxid(input_muxid), + .\muxid$1 (\input_muxid$21 ), + .ra(input_ra), + .\ra$19 (\input_ra$39 ), + .rb(input_rb), + .\rb$20 (\input_rb$40 ), + .rc(input_rc), + .\rc$21 (\input_rc$41 ), + .sr_op__fn_unit(input_sr_op__fn_unit), + .\sr_op__fn_unit$3 (\input_sr_op__fn_unit$23 ), + .sr_op__imm_data__data(input_sr_op__imm_data__data), + .\sr_op__imm_data__data$4 (\input_sr_op__imm_data__data$24 ), + .sr_op__imm_data__ok(input_sr_op__imm_data__ok), + .\sr_op__imm_data__ok$5 (\input_sr_op__imm_data__ok$25 ), + .sr_op__input_carry(input_sr_op__input_carry), + .\sr_op__input_carry$12 (\input_sr_op__input_carry$32 ), + .sr_op__input_cr(input_sr_op__input_cr), + .\sr_op__input_cr$14 (\input_sr_op__input_cr$34 ), + .sr_op__insn(input_sr_op__insn), + .\sr_op__insn$18 (\input_sr_op__insn$38 ), + .sr_op__insn_type(input_sr_op__insn_type), + .\sr_op__insn_type$2 (\input_sr_op__insn_type$22 ), + .sr_op__invert_in(input_sr_op__invert_in), + .\sr_op__invert_in$11 (\input_sr_op__invert_in$31 ), + .sr_op__is_32bit(input_sr_op__is_32bit), + .\sr_op__is_32bit$16 (\input_sr_op__is_32bit$36 ), + .sr_op__is_signed(input_sr_op__is_signed), + .\sr_op__is_signed$17 (\input_sr_op__is_signed$37 ), + .sr_op__oe__oe(input_sr_op__oe__oe), + .\sr_op__oe__oe$8 (\input_sr_op__oe__oe$28 ), + .sr_op__oe__ok(input_sr_op__oe__ok), + .\sr_op__oe__ok$9 (\input_sr_op__oe__ok$29 ), + .sr_op__output_carry(input_sr_op__output_carry), + .\sr_op__output_carry$13 (\input_sr_op__output_carry$33 ), + .sr_op__output_cr(input_sr_op__output_cr), + .\sr_op__output_cr$15 (\input_sr_op__output_cr$35 ), + .sr_op__rc__ok(input_sr_op__rc__ok), + .\sr_op__rc__ok$7 (\input_sr_op__rc__ok$27 ), + .sr_op__rc__rc(input_sr_op__rc__rc), + .\sr_op__rc__rc$6 (\input_sr_op__rc__rc$26 ), + .sr_op__write_cr0(input_sr_op__write_cr0), + .\sr_op__write_cr0$10 (\input_sr_op__write_cr0$30 ), + .xer_ca(input_xer_ca), + .\xer_ca$23 (\input_xer_ca$43 ), + .xer_so(input_xer_so), + .\xer_so$22 (\input_xer_so$42 ) + ); + \main$114 main ( + .muxid(main_muxid), + .\muxid$1 (\main_muxid$44 ), + .o(main_o), + .o_ok(main_o_ok), + .ra(main_ra), + .rb(main_rb), + .rc(main_rc), + .sr_op__fn_unit(main_sr_op__fn_unit), + .\sr_op__fn_unit$3 (\main_sr_op__fn_unit$46 ), + .sr_op__imm_data__data(main_sr_op__imm_data__data), + .\sr_op__imm_data__data$4 (\main_sr_op__imm_data__data$47 ), + .sr_op__imm_data__ok(main_sr_op__imm_data__ok), + .\sr_op__imm_data__ok$5 (\main_sr_op__imm_data__ok$48 ), + .sr_op__input_carry(main_sr_op__input_carry), + .\sr_op__input_carry$12 (\main_sr_op__input_carry$55 ), + .sr_op__input_cr(main_sr_op__input_cr), + .\sr_op__input_cr$14 (\main_sr_op__input_cr$57 ), + .sr_op__insn(main_sr_op__insn), + .\sr_op__insn$18 (\main_sr_op__insn$61 ), + .sr_op__insn_type(main_sr_op__insn_type), + .\sr_op__insn_type$2 (\main_sr_op__insn_type$45 ), + .sr_op__invert_in(main_sr_op__invert_in), + .\sr_op__invert_in$11 (\main_sr_op__invert_in$54 ), + .sr_op__is_32bit(main_sr_op__is_32bit), + .\sr_op__is_32bit$16 (\main_sr_op__is_32bit$59 ), + .sr_op__is_signed(main_sr_op__is_signed), + .\sr_op__is_signed$17 (\main_sr_op__is_signed$60 ), + .sr_op__oe__oe(main_sr_op__oe__oe), + .\sr_op__oe__oe$8 (\main_sr_op__oe__oe$51 ), + .sr_op__oe__ok(main_sr_op__oe__ok), + .\sr_op__oe__ok$9 (\main_sr_op__oe__ok$52 ), + .sr_op__output_carry(main_sr_op__output_carry), + .\sr_op__output_carry$13 (\main_sr_op__output_carry$56 ), + .sr_op__output_cr(main_sr_op__output_cr), + .\sr_op__output_cr$15 (\main_sr_op__output_cr$58 ), + .sr_op__rc__ok(main_sr_op__rc__ok), + .\sr_op__rc__ok$7 (\main_sr_op__rc__ok$50 ), + .sr_op__rc__rc(main_sr_op__rc__rc), + .\sr_op__rc__rc$6 (\main_sr_op__rc__rc$49 ), + .sr_op__write_cr0(main_sr_op__write_cr0), + .\sr_op__write_cr0$10 (\main_sr_op__write_cr0$53 ), + .xer_ca(main_xer_ca), + .xer_so(main_xer_so), + .\xer_so$19 (\main_xer_so$62 ) + ); + \n$112 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$111 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \xer_ca$next = xer_ca; + \xer_ca_ok$next = xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$95 , \xer_ca$94 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$95 , \xer_ca$94 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ca_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$next = muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$next = \muxid$67 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$next = \muxid$67 ; + endcase + end + always @* begin + if (\initial ) begin end + \sr_op__insn_type$next = sr_op__insn_type; + \sr_op__fn_unit$next = sr_op__fn_unit; + \sr_op__imm_data__data$next = sr_op__imm_data__data; + \sr_op__imm_data__ok$next = sr_op__imm_data__ok; + \sr_op__rc__rc$next = sr_op__rc__rc; + \sr_op__rc__ok$next = sr_op__rc__ok; + \sr_op__oe__oe$next = sr_op__oe__oe; + \sr_op__oe__ok$next = sr_op__oe__ok; + \sr_op__write_cr0$next = sr_op__write_cr0; + \sr_op__invert_in$next = sr_op__invert_in; + \sr_op__input_carry$next = sr_op__input_carry; + \sr_op__output_carry$next = sr_op__output_carry; + \sr_op__input_cr$next = sr_op__input_cr; + \sr_op__output_cr$next = sr_op__output_cr; + \sr_op__is_32bit$next = sr_op__is_32bit; + \sr_op__is_signed$next = sr_op__is_signed; + \sr_op__insn$next = sr_op__insn; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \sr_op__imm_data__data$next = 64'h0000000000000000; + \sr_op__imm_data__ok$next = 1'h0; + \sr_op__rc__rc$next = 1'h0; + \sr_op__rc__ok$next = 1'h0; + \sr_op__oe__oe$next = 1'h0; + \sr_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \o$next = o; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cr_a$next = cr_a; + \cr_a_ok$next = cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$next = xer_so; + \xer_so_ok$next = xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_so_ok$next = 1'h0; + endcase + end + assign \cr_a$89 = 4'h0; + assign \cr_a_ok$90 = 1'h0; + assign \xer_so_ok$93 = 1'h0; + assign \xer_ca_ok$96 = 1'h0; + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \xer_ca_ok$95 , \xer_ca$94 } = { 1'h0, main_xer_ca }; + assign { \xer_so_ok$92 , \xer_so$91 } = { 1'h0, \main_xer_so$62 }; + assign { \cr_a_ok$88 , \cr_a$87 } = 5'h00; + assign { \o_ok$86 , \o$85 } = { main_o_ok, main_o }; + assign { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68 } = { \main_sr_op__insn$61 , \main_sr_op__is_signed$60 , \main_sr_op__is_32bit$59 , \main_sr_op__output_cr$58 , \main_sr_op__input_cr$57 , \main_sr_op__output_carry$56 , \main_sr_op__input_carry$55 , \main_sr_op__invert_in$54 , \main_sr_op__write_cr0$53 , \main_sr_op__oe__ok$52 , \main_sr_op__oe__oe$51 , \main_sr_op__rc__ok$50 , \main_sr_op__rc__rc$49 , \main_sr_op__imm_data__ok$48 , \main_sr_op__imm_data__data$47 , \main_sr_op__fn_unit$46 , \main_sr_op__insn_type$45 }; + assign \muxid$67 = \main_muxid$44 ; + assign p_valid_i_p_ready_o = \$65 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$64 = p_valid_i; + assign \xer_ca$63 = \input_xer_ca$43 ; + assign main_xer_so = \input_xer_so$42 ; + assign main_rc = \input_rc$41 ; + assign main_rb = \input_rb$40 ; + assign main_ra = \input_ra$39 ; + assign { main_sr_op__insn, main_sr_op__is_signed, main_sr_op__is_32bit, main_sr_op__output_cr, main_sr_op__input_cr, main_sr_op__output_carry, main_sr_op__input_carry, main_sr_op__invert_in, main_sr_op__write_cr0, main_sr_op__oe__ok, main_sr_op__oe__oe, main_sr_op__rc__ok, main_sr_op__rc__rc, main_sr_op__imm_data__ok, main_sr_op__imm_data__data, main_sr_op__fn_unit, main_sr_op__insn_type } = { \input_sr_op__insn$38 , \input_sr_op__is_signed$37 , \input_sr_op__is_32bit$36 , \input_sr_op__output_cr$35 , \input_sr_op__input_cr$34 , \input_sr_op__output_carry$33 , \input_sr_op__input_carry$32 , \input_sr_op__invert_in$31 , \input_sr_op__write_cr0$30 , \input_sr_op__oe__ok$29 , \input_sr_op__oe__oe$28 , \input_sr_op__rc__ok$27 , \input_sr_op__rc__rc$26 , \input_sr_op__imm_data__ok$25 , \input_sr_op__imm_data__data$24 , \input_sr_op__fn_unit$23 , \input_sr_op__insn_type$22 }; + assign main_muxid = \input_muxid$21 ; + assign input_xer_ca = \xer_ca$20 ; + assign input_xer_so = \xer_so$19 ; + assign input_rc = rc; + assign input_rb = rb; + assign input_ra = ra; + assign { input_sr_op__insn, input_sr_op__is_signed, input_sr_op__is_32bit, input_sr_op__output_cr, input_sr_op__input_cr, input_sr_op__output_carry, input_sr_op__input_carry, input_sr_op__invert_in, input_sr_op__write_cr0, input_sr_op__oe__ok, input_sr_op__oe__oe, input_sr_op__rc__ok, input_sr_op__rc__rc, input_sr_op__imm_data__ok, input_sr_op__imm_data__data, input_sr_op__fn_unit, input_sr_op__insn_type } = { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 }; + assign input_muxid = \muxid$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" *) +(* generator = "nMigen" *) +module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, p_valid_i, p_ready_o, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , \ra$11 , \rb$12 , \fast1$13 , \fast2$14 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] dummy_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \dummy_fast1$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] dummy_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \dummy_fast2$28 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] dummy_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \dummy_muxid$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] dummy_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \dummy_ra$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] dummy_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \dummy_rb$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dummy_trap_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \dummy_trap_op__cia$20 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] dummy_trap_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \dummy_trap_op__fn_unit$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] dummy_trap_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \dummy_trap_op__insn$18 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] dummy_trap_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \dummy_trap_op__insn_type$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire dummy_trap_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \dummy_trap_op__is_32bit$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] dummy_trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \dummy_trap_op__ldst_exc$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] dummy_trap_op__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \dummy_trap_op__msr$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] dummy_trap_op__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] \dummy_trap_op__trapaddr$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] dummy_trap_op__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \dummy_trap_op__traptype$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] fast1; + reg [63:0] fast1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \fast1$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \fast1$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \fast1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] fast2; + reg [63:0] fast2 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \fast2$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \fast2$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \fast2$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] muxid; + reg [1:0] muxid = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$32 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$29 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] ra; + reg [63:0] ra = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \ra$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \ra$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \ra$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] rb; + reg [63:0] rb = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \rb$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \rb$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \rb$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] trap_op__cia; + reg [63:0] trap_op__cia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \trap_op__cia$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] \trap_op__cia$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \trap_op__cia$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] trap_op__fn_unit; + reg [13:0] trap_op__fn_unit = 14'h0000; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] \trap_op__fn_unit$3 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \trap_op__fn_unit$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \trap_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] trap_op__insn; + reg [31:0] trap_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \trap_op__insn$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] \trap_op__insn$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \trap_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] trap_op__insn_type; + reg [6:0] trap_op__insn_type = 7'h00; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] \trap_op__insn_type$2 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \trap_op__insn_type$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \trap_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output trap_op__is_32bit; + reg trap_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \trap_op__is_32bit$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \trap_op__is_32bit$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \trap_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [7:0] trap_op__ldst_exc; + reg [7:0] trap_op__ldst_exc = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] \trap_op__ldst_exc$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \trap_op__ldst_exc$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] \trap_op__ldst_exc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] trap_op__msr; + reg [63:0] trap_op__msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \trap_op__msr$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] \trap_op__msr$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \trap_op__msr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [12:0] trap_op__trapaddr; + reg [12:0] trap_op__trapaddr = 13'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] \trap_op__trapaddr$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [12:0] \trap_op__trapaddr$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [12:0] \trap_op__trapaddr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [7:0] trap_op__traptype; + reg [7:0] trap_op__traptype = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \trap_op__traptype$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] \trap_op__traptype$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] \trap_op__traptype$next ; + assign \$30 = \p_valid_i$29 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + fast2 <= \fast2$next ; + always @(posedge coresync_clk) + fast1 <= \fast1$next ; + always @(posedge coresync_clk) + rb <= \rb$next ; + always @(posedge coresync_clk) + ra <= \ra$next ; + always @(posedge coresync_clk) + trap_op__insn_type <= \trap_op__insn_type$next ; + always @(posedge coresync_clk) + trap_op__fn_unit <= \trap_op__fn_unit$next ; + always @(posedge coresync_clk) + trap_op__insn <= \trap_op__insn$next ; + always @(posedge coresync_clk) + trap_op__msr <= \trap_op__msr$next ; + always @(posedge coresync_clk) + trap_op__cia <= \trap_op__cia$next ; + always @(posedge coresync_clk) + trap_op__is_32bit <= \trap_op__is_32bit$next ; + always @(posedge coresync_clk) + trap_op__traptype <= \trap_op__traptype$next ; + always @(posedge coresync_clk) + trap_op__trapaddr <= \trap_op__trapaddr$next ; + always @(posedge coresync_clk) + trap_op__ldst_exc <= \trap_op__ldst_exc$next ; + always @(posedge coresync_clk) + muxid <= \muxid$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + dummy dummy ( + .fast1(dummy_fast1), + .\fast1$13 (\dummy_fast1$27 ), + .fast2(dummy_fast2), + .\fast2$14 (\dummy_fast2$28 ), + .muxid(dummy_muxid), + .\muxid$1 (\dummy_muxid$15 ), + .ra(dummy_ra), + .\ra$11 (\dummy_ra$25 ), + .rb(dummy_rb), + .\rb$12 (\dummy_rb$26 ), + .trap_op__cia(dummy_trap_op__cia), + .\trap_op__cia$6 (\dummy_trap_op__cia$20 ), + .trap_op__fn_unit(dummy_trap_op__fn_unit), + .\trap_op__fn_unit$3 (\dummy_trap_op__fn_unit$17 ), + .trap_op__insn(dummy_trap_op__insn), + .\trap_op__insn$4 (\dummy_trap_op__insn$18 ), + .trap_op__insn_type(dummy_trap_op__insn_type), + .\trap_op__insn_type$2 (\dummy_trap_op__insn_type$16 ), + .trap_op__is_32bit(dummy_trap_op__is_32bit), + .\trap_op__is_32bit$7 (\dummy_trap_op__is_32bit$21 ), + .trap_op__ldst_exc(dummy_trap_op__ldst_exc), + .\trap_op__ldst_exc$10 (\dummy_trap_op__ldst_exc$24 ), + .trap_op__msr(dummy_trap_op__msr), + .\trap_op__msr$5 (\dummy_trap_op__msr$19 ), + .trap_op__trapaddr(dummy_trap_op__trapaddr), + .\trap_op__trapaddr$9 (\dummy_trap_op__trapaddr$23 ), + .trap_op__traptype(dummy_trap_op__traptype), + .\trap_op__traptype$8 (\dummy_trap_op__traptype$22 ) + ); + \n$34 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$33 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$next = muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$next = \muxid$32 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$next = \muxid$32 ; + endcase + end + always @* begin + if (\initial ) begin end + \trap_op__insn_type$next = trap_op__insn_type; + \trap_op__fn_unit$next = trap_op__fn_unit; + \trap_op__insn$next = trap_op__insn; + \trap_op__msr$next = trap_op__msr; + \trap_op__cia$next = trap_op__cia; + \trap_op__is_32bit$next = trap_op__is_32bit; + \trap_op__traptype$next = trap_op__traptype; + \trap_op__trapaddr$next = trap_op__trapaddr; + \trap_op__ldst_exc$next = trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33 }; + endcase + end + always @* begin + if (\initial ) begin end + \ra$next = ra; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \ra$next = \ra$42 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \ra$next = \ra$42 ; + endcase + end + always @* begin + if (\initial ) begin end + \rb$next = rb; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \rb$next = \rb$43 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \rb$next = \rb$43 ; + endcase + end + always @* begin + if (\initial ) begin end + \fast1$next = fast1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \fast1$next = \fast1$44 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \fast1$next = \fast1$44 ; + endcase + end + always @* begin + if (\initial ) begin end + \fast2$next = fast2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \fast2$next = \fast2$45 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \fast2$next = \fast2$45 ; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign \fast2$45 = \dummy_fast2$28 ; + assign \fast1$44 = \dummy_fast1$27 ; + assign \rb$43 = \dummy_rb$26 ; + assign \ra$42 = \dummy_ra$25 ; + assign { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33 } = { \dummy_trap_op__ldst_exc$24 , \dummy_trap_op__trapaddr$23 , \dummy_trap_op__traptype$22 , \dummy_trap_op__is_32bit$21 , \dummy_trap_op__cia$20 , \dummy_trap_op__msr$19 , \dummy_trap_op__insn$18 , \dummy_trap_op__fn_unit$17 , \dummy_trap_op__insn_type$16 }; + assign \muxid$32 = \dummy_muxid$15 ; + assign p_valid_i_p_ready_o = \$30 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$29 = p_valid_i; + assign dummy_fast2 = \fast2$14 ; + assign dummy_fast1 = \fast1$13 ; + assign dummy_rb = \rb$12 ; + assign dummy_ra = \ra$11 ; + assign { dummy_trap_op__ldst_exc, dummy_trap_op__trapaddr, dummy_trap_op__traptype, dummy_trap_op__is_32bit, dummy_trap_op__cia, dummy_trap_op__msr, dummy_trap_op__insn, dummy_trap_op__fn_unit, dummy_trap_op__insn_type } = { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 }; + assign dummy_muxid = \muxid$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" *) +(* generator = "nMigen" *) +module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , \cr_a_ok$23 , \xer_ca$24 , \xer_ca_ok$25 , \xer_ov$26 , \xer_ov_ok$27 , \xer_so$28 , \xer_so_ok$29 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \alu_op__data_len$18 ; + reg [3:0] \alu_op__data_len$18 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \alu_op__data_len$18$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \alu_op__data_len$79 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \alu_op__fn_unit$3 ; + reg [13:0] \alu_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_op__fn_unit$3$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \alu_op__fn_unit$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \alu_op__imm_data__data$4 ; + reg [63:0] \alu_op__imm_data__data$4 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_op__imm_data__data$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \alu_op__imm_data__data$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__imm_data__ok$5 ; + reg \alu_op__imm_data__ok$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__imm_data__ok$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__imm_data__ok$66 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \alu_op__input_carry$14 ; + reg [1:0] \alu_op__input_carry$14 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \alu_op__input_carry$14$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \alu_op__input_carry$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \alu_op__insn$19 ; + reg [31:0] \alu_op__insn$19 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_op__insn$19$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \alu_op__insn$80 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \alu_op__insn_type$2 ; + reg [6:0] \alu_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_op__insn_type$2$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \alu_op__insn_type$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__invert_in$10 ; + reg \alu_op__invert_in$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__invert_in$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__invert_in$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__invert_out$12 ; + reg \alu_op__invert_out$12 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__invert_out$12$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__invert_out$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__is_32bit$16 ; + reg \alu_op__is_32bit$16 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__is_32bit$16$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__is_32bit$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__is_signed$17 ; + reg \alu_op__is_signed$17 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__is_signed$17$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__is_signed$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__oe__oe$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__oe__oe$8 ; + reg \alu_op__oe__oe$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__oe__oe$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__oe__ok$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__oe__ok$9 ; + reg \alu_op__oe__ok$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__oe__ok$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__output_carry$15 ; + reg \alu_op__output_carry$15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__output_carry$15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__output_carry$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__rc__ok$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__rc__ok$7 ; + reg \alu_op__rc__ok$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__rc__ok$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__rc__rc$6 ; + reg \alu_op__rc__rc$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__rc__rc$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__rc__rc$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__write_cr0$13 ; + reg \alu_op__write_cr0$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__write_cr0$13$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__write_cr0$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \alu_op__zero_a$11 ; + reg \alu_op__zero_a$11 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_op__zero_a$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \alu_op__zero_a$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$22 ; + reg [3:0] \cr_a$22 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$22$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_a_ok$23 ; + reg \cr_a_ok$23 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$23$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$84 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$62 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$20 ; + reg [63:0] \o$20 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$20$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$21 ; + reg \o_ok$21 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$21$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] output_alu_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \output_alu_op__data_len$47 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] output_alu_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \output_alu_op__fn_unit$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] output_alu_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \output_alu_op__imm_data__data$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__imm_data__ok$34 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] output_alu_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \output_alu_op__input_carry$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] output_alu_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \output_alu_op__insn$48 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] output_alu_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \output_alu_op__insn_type$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__invert_in$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__invert_out$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__is_32bit$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__is_signed$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__oe__oe$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__oe__ok$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__output_carry$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__rc__ok$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__rc__rc$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__write_cr0$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_alu_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_alu_op__zero_a$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] output_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \output_cr_a$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] output_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \output_muxid$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] output_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \output_o$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_o_ok$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] output_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_xer_ca$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] output_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_xer_ov$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_xer_so$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$59 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ca$24 ; + reg [1:0] \xer_ca$24 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ca$24$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ca$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_ca_ok$25 ; + reg \xer_ca_ok$25 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ca_ok$25$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ca_ok$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ca_ok$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ov$26 ; + reg [1:0] \xer_ov$26 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ov$26$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ov$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_ov_ok$27 ; + reg \xer_ov_ok$27 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ov_ok$27$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ov_ok$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ov_ok$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$28 ; + reg \xer_so$28 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so$28$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so_ok$29 ; + reg \xer_so_ok$29 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so_ok$29$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$90 ; + assign \$60 = \p_valid_i$59 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \xer_so$28 <= \xer_so$28$next ; + always @(posedge coresync_clk) + \xer_so_ok$29 <= \xer_so_ok$29$next ; + always @(posedge coresync_clk) + \xer_ov$26 <= \xer_ov$26$next ; + always @(posedge coresync_clk) + \xer_ov_ok$27 <= \xer_ov_ok$27$next ; + always @(posedge coresync_clk) + \xer_ca$24 <= \xer_ca$24$next ; + always @(posedge coresync_clk) + \xer_ca_ok$25 <= \xer_ca_ok$25$next ; + always @(posedge coresync_clk) + \cr_a$22 <= \cr_a$22$next ; + always @(posedge coresync_clk) + \cr_a_ok$23 <= \cr_a_ok$23$next ; + always @(posedge coresync_clk) + \o$20 <= \o$20$next ; + always @(posedge coresync_clk) + \o_ok$21 <= \o_ok$21$next ; + always @(posedge coresync_clk) + \alu_op__insn_type$2 <= \alu_op__insn_type$2$next ; + always @(posedge coresync_clk) + \alu_op__fn_unit$3 <= \alu_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \alu_op__imm_data__data$4 <= \alu_op__imm_data__data$4$next ; + always @(posedge coresync_clk) + \alu_op__imm_data__ok$5 <= \alu_op__imm_data__ok$5$next ; + always @(posedge coresync_clk) + \alu_op__rc__rc$6 <= \alu_op__rc__rc$6$next ; + always @(posedge coresync_clk) + \alu_op__rc__ok$7 <= \alu_op__rc__ok$7$next ; + always @(posedge coresync_clk) + \alu_op__oe__oe$8 <= \alu_op__oe__oe$8$next ; + always @(posedge coresync_clk) + \alu_op__oe__ok$9 <= \alu_op__oe__ok$9$next ; + always @(posedge coresync_clk) + \alu_op__invert_in$10 <= \alu_op__invert_in$10$next ; + always @(posedge coresync_clk) + \alu_op__zero_a$11 <= \alu_op__zero_a$11$next ; + always @(posedge coresync_clk) + \alu_op__invert_out$12 <= \alu_op__invert_out$12$next ; + always @(posedge coresync_clk) + \alu_op__write_cr0$13 <= \alu_op__write_cr0$13$next ; + always @(posedge coresync_clk) + \alu_op__input_carry$14 <= \alu_op__input_carry$14$next ; + always @(posedge coresync_clk) + \alu_op__output_carry$15 <= \alu_op__output_carry$15$next ; + always @(posedge coresync_clk) + \alu_op__is_32bit$16 <= \alu_op__is_32bit$16$next ; + always @(posedge coresync_clk) + \alu_op__is_signed$17 <= \alu_op__is_signed$17$next ; + always @(posedge coresync_clk) + \alu_op__data_len$18 <= \alu_op__data_len$18$next ; + always @(posedge coresync_clk) + \alu_op__insn$19 <= \alu_op__insn$19$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \n$4 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \output \output ( + .alu_op__data_len(output_alu_op__data_len), + .\alu_op__data_len$18 (\output_alu_op__data_len$47 ), + .alu_op__fn_unit(output_alu_op__fn_unit), + .\alu_op__fn_unit$3 (\output_alu_op__fn_unit$32 ), + .alu_op__imm_data__data(output_alu_op__imm_data__data), + .\alu_op__imm_data__data$4 (\output_alu_op__imm_data__data$33 ), + .alu_op__imm_data__ok(output_alu_op__imm_data__ok), + .\alu_op__imm_data__ok$5 (\output_alu_op__imm_data__ok$34 ), + .alu_op__input_carry(output_alu_op__input_carry), + .\alu_op__input_carry$14 (\output_alu_op__input_carry$43 ), + .alu_op__insn(output_alu_op__insn), + .\alu_op__insn$19 (\output_alu_op__insn$48 ), + .alu_op__insn_type(output_alu_op__insn_type), + .\alu_op__insn_type$2 (\output_alu_op__insn_type$31 ), + .alu_op__invert_in(output_alu_op__invert_in), + .\alu_op__invert_in$10 (\output_alu_op__invert_in$39 ), + .alu_op__invert_out(output_alu_op__invert_out), + .\alu_op__invert_out$12 (\output_alu_op__invert_out$41 ), + .alu_op__is_32bit(output_alu_op__is_32bit), + .\alu_op__is_32bit$16 (\output_alu_op__is_32bit$45 ), + .alu_op__is_signed(output_alu_op__is_signed), + .\alu_op__is_signed$17 (\output_alu_op__is_signed$46 ), + .alu_op__oe__oe(output_alu_op__oe__oe), + .\alu_op__oe__oe$8 (\output_alu_op__oe__oe$37 ), + .alu_op__oe__ok(output_alu_op__oe__ok), + .\alu_op__oe__ok$9 (\output_alu_op__oe__ok$38 ), + .alu_op__output_carry(output_alu_op__output_carry), + .\alu_op__output_carry$15 (\output_alu_op__output_carry$44 ), + .alu_op__rc__ok(output_alu_op__rc__ok), + .\alu_op__rc__ok$7 (\output_alu_op__rc__ok$36 ), + .alu_op__rc__rc(output_alu_op__rc__rc), + .\alu_op__rc__rc$6 (\output_alu_op__rc__rc$35 ), + .alu_op__write_cr0(output_alu_op__write_cr0), + .\alu_op__write_cr0$13 (\output_alu_op__write_cr0$42 ), + .alu_op__zero_a(output_alu_op__zero_a), + .\alu_op__zero_a$11 (\output_alu_op__zero_a$40 ), + .cr_a(output_cr_a), + .\cr_a$22 (\output_cr_a$51 ), + .cr_a_ok(output_cr_a_ok), + .muxid(output_muxid), + .\muxid$1 (\output_muxid$30 ), + .o(output_o), + .\o$20 (\output_o$49 ), + .o_ok(output_o_ok), + .\o_ok$21 (\output_o_ok$50 ), + .xer_ca(output_xer_ca), + .\xer_ca$23 (\output_xer_ca$52 ), + .xer_ca_ok(output_xer_ca_ok), + .xer_ov(output_xer_ov), + .\xer_ov$24 (\output_xer_ov$53 ), + .xer_ov_ok(output_xer_ov_ok), + .xer_so(output_xer_so), + .\xer_so$25 (\output_xer_so$54 ), + .xer_so_ok(output_xer_so_ok) + ); + \p$3 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$62 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$62 ; + endcase + end + always @* begin + if (\initial ) begin end + \alu_op__insn_type$2$next = \alu_op__insn_type$2 ; + \alu_op__fn_unit$3$next = \alu_op__fn_unit$3 ; + \alu_op__imm_data__data$4$next = \alu_op__imm_data__data$4 ; + \alu_op__imm_data__ok$5$next = \alu_op__imm_data__ok$5 ; + \alu_op__rc__rc$6$next = \alu_op__rc__rc$6 ; + \alu_op__rc__ok$7$next = \alu_op__rc__ok$7 ; + \alu_op__oe__oe$8$next = \alu_op__oe__oe$8 ; + \alu_op__oe__ok$9$next = \alu_op__oe__ok$9 ; + \alu_op__invert_in$10$next = \alu_op__invert_in$10 ; + \alu_op__zero_a$11$next = \alu_op__zero_a$11 ; + \alu_op__invert_out$12$next = \alu_op__invert_out$12 ; + \alu_op__write_cr0$13$next = \alu_op__write_cr0$13 ; + \alu_op__input_carry$14$next = \alu_op__input_carry$14 ; + \alu_op__output_carry$15$next = \alu_op__output_carry$15 ; + \alu_op__is_32bit$16$next = \alu_op__is_32bit$16 ; + \alu_op__is_signed$17$next = \alu_op__is_signed$17 ; + \alu_op__data_len$18$next = \alu_op__data_len$18 ; + \alu_op__insn$19$next = \alu_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \alu_op__imm_data__data$4$next = 64'h0000000000000000; + \alu_op__imm_data__ok$5$next = 1'h0; + \alu_op__rc__rc$6$next = 1'h0; + \alu_op__rc__ok$7$next = 1'h0; + \alu_op__oe__oe$8$next = 1'h0; + \alu_op__oe__ok$9$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \o$20$next = \o$20 ; + \o_ok$21$next = \o_ok$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$21$next , \o$20$next } = { \o_ok$82 , \o$81 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$21$next , \o$20$next } = { \o_ok$82 , \o$81 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$21$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cr_a$22$next = \cr_a$22 ; + \cr_a_ok$23$next = \cr_a_ok$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$84 , \cr_a$83 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$84 , \cr_a$83 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$23$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$24$next = \xer_ca$24 ; + \xer_ca_ok$25$next = \xer_ca_ok$25 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ca_ok$25$next , \xer_ca$24$next } = { \xer_ca_ok$86 , \xer_ca$85 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ca_ok$25$next , \xer_ca$24$next } = { \xer_ca_ok$86 , \xer_ca$85 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ca_ok$25$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$26$next = \xer_ov$26 ; + \xer_ov_ok$27$next = \xer_ov_ok$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ov_ok$27$next , \xer_ov$26$next } = { \xer_ov_ok$88 , \xer_ov$87 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ov_ok$27$next , \xer_ov$26$next } = { \xer_ov_ok$88 , \xer_ov$87 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ov_ok$27$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$28$next = \xer_so$28 ; + \xer_so_ok$29$next = \xer_so_ok$29 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_so_ok$29$next , \xer_so$28$next } = { \xer_so_ok$90 , \xer_so$89 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_so_ok$29$next , \xer_so$28$next } = { \xer_so_ok$90 , \xer_so$89 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_so_ok$29$next = 1'h0; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \xer_so_ok$90 , \xer_so$89 } = { output_xer_so_ok, \output_xer_so$54 }; + assign { \xer_ov_ok$88 , \xer_ov$87 } = { output_xer_ov_ok, \output_xer_ov$53 }; + assign { \xer_ca_ok$86 , \xer_ca$85 } = { output_xer_ca_ok, \output_xer_ca$52 }; + assign { \cr_a_ok$84 , \cr_a$83 } = { output_cr_a_ok, \output_cr_a$51 }; + assign { \o_ok$82 , \o$81 } = { \output_o_ok$50 , \output_o$49 }; + assign { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63 } = { \output_alu_op__insn$48 , \output_alu_op__data_len$47 , \output_alu_op__is_signed$46 , \output_alu_op__is_32bit$45 , \output_alu_op__output_carry$44 , \output_alu_op__input_carry$43 , \output_alu_op__write_cr0$42 , \output_alu_op__invert_out$41 , \output_alu_op__zero_a$40 , \output_alu_op__invert_in$39 , \output_alu_op__oe__ok$38 , \output_alu_op__oe__oe$37 , \output_alu_op__rc__ok$36 , \output_alu_op__rc__rc$35 , \output_alu_op__imm_data__ok$34 , \output_alu_op__imm_data__data$33 , \output_alu_op__fn_unit$32 , \output_alu_op__insn_type$31 }; + assign \muxid$62 = \output_muxid$30 ; + assign p_valid_i_p_ready_o = \$60 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$59 = p_valid_i; + assign { \xer_so_ok$58 , output_xer_so } = { xer_so_ok, xer_so }; + assign { \xer_ov_ok$57 , output_xer_ov } = { xer_ov_ok, xer_ov }; + assign { \xer_ca_ok$56 , output_xer_ca } = { xer_ca_ok, xer_ca }; + assign { \cr_a_ok$55 , output_cr_a } = { cr_a_ok, cr_a }; + assign { output_o_ok, output_o } = { o_ok, o }; + assign { output_alu_op__insn, output_alu_op__data_len, output_alu_op__is_signed, output_alu_op__is_32bit, output_alu_op__output_carry, output_alu_op__input_carry, output_alu_op__write_cr0, output_alu_op__invert_out, output_alu_op__zero_a, output_alu_op__invert_in, output_alu_op__oe__ok, output_alu_op__oe__oe, output_alu_op__rc__ok, output_alu_op__rc__rc, output_alu_op__imm_data__ok, output_alu_op__imm_data__data, output_alu_op__fn_unit, output_alu_op__insn_type } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign output_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" *) +(* generator = "nMigen" *) +module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, n_valid_o, n_ready_i, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \o$19 , \o_ok$20 , \cr_a$21 , \cr_a_ok$22 , \xer_ca$23 , \xer_ca_ok$24 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [3:0] cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] \cr_a$21 ; + reg [3:0] \cr_a$21 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$21$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \cr_a_ok$22 ; + reg \cr_a_ok$22 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$22$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$74 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$53 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \o$19 ; + reg [63:0] \o$19 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$19$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \o_ok$20 ; + reg \o_ok$20 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$20$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] output_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \output_cr_a$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] output_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \output_muxid$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] output_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \output_o$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_o_ok$44 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] output_sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \output_sr_op__fn_unit$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] output_sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \output_sr_op__imm_data__data$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__imm_data__ok$29 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] output_sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \output_sr_op__input_carry$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__input_cr$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] output_sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \output_sr_op__insn$42 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] output_sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \output_sr_op__insn_type$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__invert_in$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__is_32bit$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__is_signed$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__oe__oe$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__oe__ok$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__output_carry$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__output_cr$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__rc__ok$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__rc__rc$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_sr_op__write_cr0$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] output_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_xer_ca$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_so; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$50 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] sr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \sr_op__fn_unit$3 ; + reg [13:0] \sr_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \sr_op__fn_unit$3$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \sr_op__fn_unit$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] sr_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \sr_op__imm_data__data$4 ; + reg [63:0] \sr_op__imm_data__data$4 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \sr_op__imm_data__data$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \sr_op__imm_data__data$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__imm_data__ok$5 ; + reg \sr_op__imm_data__ok$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__imm_data__ok$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__imm_data__ok$57 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] sr_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \sr_op__input_carry$12 ; + reg [1:0] \sr_op__input_carry$12 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \sr_op__input_carry$12$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \sr_op__input_carry$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__input_cr$14 ; + reg \sr_op__input_cr$14 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__input_cr$14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__input_cr$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \sr_op__insn$18 ; + reg [31:0] \sr_op__insn$18 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \sr_op__insn$18$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \sr_op__insn$70 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] sr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \sr_op__insn_type$2 ; + reg [6:0] \sr_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \sr_op__insn_type$2$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \sr_op__insn_type$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__invert_in$11 ; + reg \sr_op__invert_in$11 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__invert_in$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__invert_in$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__is_32bit$16 ; + reg \sr_op__is_32bit$16 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__is_32bit$16$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__is_32bit$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__is_signed$17 ; + reg \sr_op__is_signed$17 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__is_signed$17$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__is_signed$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__oe__oe$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__oe__oe$8 ; + reg \sr_op__oe__oe$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__oe__oe$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__oe__ok$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__oe__ok$9 ; + reg \sr_op__oe__ok$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__oe__ok$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__output_carry$13 ; + reg \sr_op__output_carry$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__output_carry$13$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__output_carry$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__output_cr$15 ; + reg \sr_op__output_cr$15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__output_cr$15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__output_cr$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__rc__ok$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__rc__ok$7 ; + reg \sr_op__rc__ok$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__rc__ok$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__rc__rc$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__rc__rc$6 ; + reg \sr_op__rc__rc$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__rc__rc$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input sr_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \sr_op__write_cr0$10 ; + reg \sr_op__write_cr0$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \sr_op__write_cr0$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \sr_op__write_cr0$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ca$23 ; + reg [1:0] \xer_ca$23 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ca$23$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ca$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_ca_ok$24 ; + reg \xer_ca_ok$24 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ca_ok$24$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ca_ok$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ca_ok$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$48 ; + assign \$51 = \p_valid_i$50 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \xer_ca$23 <= \xer_ca$23$next ; + always @(posedge coresync_clk) + \xer_ca_ok$24 <= \xer_ca_ok$24$next ; + always @(posedge coresync_clk) + \cr_a$21 <= \cr_a$21$next ; + always @(posedge coresync_clk) + \cr_a_ok$22 <= \cr_a_ok$22$next ; + always @(posedge coresync_clk) + \o$19 <= \o$19$next ; + always @(posedge coresync_clk) + \o_ok$20 <= \o_ok$20$next ; + always @(posedge coresync_clk) + \sr_op__insn_type$2 <= \sr_op__insn_type$2$next ; + always @(posedge coresync_clk) + \sr_op__fn_unit$3 <= \sr_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \sr_op__imm_data__data$4 <= \sr_op__imm_data__data$4$next ; + always @(posedge coresync_clk) + \sr_op__imm_data__ok$5 <= \sr_op__imm_data__ok$5$next ; + always @(posedge coresync_clk) + \sr_op__rc__rc$6 <= \sr_op__rc__rc$6$next ; + always @(posedge coresync_clk) + \sr_op__rc__ok$7 <= \sr_op__rc__ok$7$next ; + always @(posedge coresync_clk) + \sr_op__oe__oe$8 <= \sr_op__oe__oe$8$next ; + always @(posedge coresync_clk) + \sr_op__oe__ok$9 <= \sr_op__oe__ok$9$next ; + always @(posedge coresync_clk) + \sr_op__write_cr0$10 <= \sr_op__write_cr0$10$next ; + always @(posedge coresync_clk) + \sr_op__invert_in$11 <= \sr_op__invert_in$11$next ; + always @(posedge coresync_clk) + \sr_op__input_carry$12 <= \sr_op__input_carry$12$next ; + always @(posedge coresync_clk) + \sr_op__output_carry$13 <= \sr_op__output_carry$13$next ; + always @(posedge coresync_clk) + \sr_op__input_cr$14 <= \sr_op__input_cr$14$next ; + always @(posedge coresync_clk) + \sr_op__output_cr$15 <= \sr_op__output_cr$15$next ; + always @(posedge coresync_clk) + \sr_op__is_32bit$16 <= \sr_op__is_32bit$16$next ; + always @(posedge coresync_clk) + \sr_op__is_signed$17 <= \sr_op__is_signed$17$next ; + always @(posedge coresync_clk) + \sr_op__insn$18 <= \sr_op__insn$18$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \n$117 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \output$118 \output ( + .cr_a(output_cr_a), + .\cr_a$21 (\output_cr_a$45 ), + .cr_a_ok(output_cr_a_ok), + .muxid(output_muxid), + .\muxid$1 (\output_muxid$25 ), + .o(output_o), + .\o$19 (\output_o$43 ), + .o_ok(output_o_ok), + .\o_ok$20 (\output_o_ok$44 ), + .sr_op__fn_unit(output_sr_op__fn_unit), + .\sr_op__fn_unit$3 (\output_sr_op__fn_unit$27 ), + .sr_op__imm_data__data(output_sr_op__imm_data__data), + .\sr_op__imm_data__data$4 (\output_sr_op__imm_data__data$28 ), + .sr_op__imm_data__ok(output_sr_op__imm_data__ok), + .\sr_op__imm_data__ok$5 (\output_sr_op__imm_data__ok$29 ), + .sr_op__input_carry(output_sr_op__input_carry), + .\sr_op__input_carry$12 (\output_sr_op__input_carry$36 ), + .sr_op__input_cr(output_sr_op__input_cr), + .\sr_op__input_cr$14 (\output_sr_op__input_cr$38 ), + .sr_op__insn(output_sr_op__insn), + .\sr_op__insn$18 (\output_sr_op__insn$42 ), + .sr_op__insn_type(output_sr_op__insn_type), + .\sr_op__insn_type$2 (\output_sr_op__insn_type$26 ), + .sr_op__invert_in(output_sr_op__invert_in), + .\sr_op__invert_in$11 (\output_sr_op__invert_in$35 ), + .sr_op__is_32bit(output_sr_op__is_32bit), + .\sr_op__is_32bit$16 (\output_sr_op__is_32bit$40 ), + .sr_op__is_signed(output_sr_op__is_signed), + .\sr_op__is_signed$17 (\output_sr_op__is_signed$41 ), + .sr_op__oe__oe(output_sr_op__oe__oe), + .\sr_op__oe__oe$8 (\output_sr_op__oe__oe$32 ), + .sr_op__oe__ok(output_sr_op__oe__ok), + .\sr_op__oe__ok$9 (\output_sr_op__oe__ok$33 ), + .sr_op__output_carry(output_sr_op__output_carry), + .\sr_op__output_carry$13 (\output_sr_op__output_carry$37 ), + .sr_op__output_cr(output_sr_op__output_cr), + .\sr_op__output_cr$15 (\output_sr_op__output_cr$39 ), + .sr_op__rc__ok(output_sr_op__rc__ok), + .\sr_op__rc__ok$7 (\output_sr_op__rc__ok$31 ), + .sr_op__rc__rc(output_sr_op__rc__rc), + .\sr_op__rc__rc$6 (\output_sr_op__rc__rc$30 ), + .sr_op__write_cr0(output_sr_op__write_cr0), + .\sr_op__write_cr0$10 (\output_sr_op__write_cr0$34 ), + .xer_ca(output_xer_ca), + .\xer_ca$22 (\output_xer_ca$46 ), + .xer_ca_ok(output_xer_ca_ok), + .xer_so(output_xer_so) + ); + \p$116 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$53 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$53 ; + endcase + end + always @* begin + if (\initial ) begin end + \sr_op__insn_type$2$next = \sr_op__insn_type$2 ; + \sr_op__fn_unit$3$next = \sr_op__fn_unit$3 ; + \sr_op__imm_data__data$4$next = \sr_op__imm_data__data$4 ; + \sr_op__imm_data__ok$5$next = \sr_op__imm_data__ok$5 ; + \sr_op__rc__rc$6$next = \sr_op__rc__rc$6 ; + \sr_op__rc__ok$7$next = \sr_op__rc__ok$7 ; + \sr_op__oe__oe$8$next = \sr_op__oe__oe$8 ; + \sr_op__oe__ok$9$next = \sr_op__oe__ok$9 ; + \sr_op__write_cr0$10$next = \sr_op__write_cr0$10 ; + \sr_op__invert_in$11$next = \sr_op__invert_in$11 ; + \sr_op__input_carry$12$next = \sr_op__input_carry$12 ; + \sr_op__output_carry$13$next = \sr_op__output_carry$13 ; + \sr_op__input_cr$14$next = \sr_op__input_cr$14 ; + \sr_op__output_cr$15$next = \sr_op__output_cr$15 ; + \sr_op__is_32bit$16$next = \sr_op__is_32bit$16 ; + \sr_op__is_signed$17$next = \sr_op__is_signed$17 ; + \sr_op__insn$18$next = \sr_op__insn$18 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \sr_op__imm_data__data$4$next = 64'h0000000000000000; + \sr_op__imm_data__ok$5$next = 1'h0; + \sr_op__rc__rc$6$next = 1'h0; + \sr_op__rc__ok$7$next = 1'h0; + \sr_op__oe__oe$8$next = 1'h0; + \sr_op__oe__ok$9$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \o$19$next = \o$19 ; + \o_ok$20$next = \o_ok$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$20$next , \o$19$next } = { \o_ok$72 , \o$71 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$20$next , \o$19$next } = { \o_ok$72 , \o$71 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$20$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cr_a$21$next = \cr_a$21 ; + \cr_a_ok$22$next = \cr_a_ok$22 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$22$next , \cr_a$21$next } = { \cr_a_ok$74 , \cr_a$73 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$22$next , \cr_a$21$next } = { \cr_a_ok$74 , \cr_a$73 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$22$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$23$next = \xer_ca$23 ; + \xer_ca_ok$24$next = \xer_ca_ok$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ca_ok$24$next , \xer_ca$23$next } = { \xer_ca_ok$76 , \xer_ca$75 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ca_ok$24$next , \xer_ca$23$next } = { \xer_ca_ok$76 , \xer_ca$75 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ca_ok$24$next = 1'h0; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \xer_ca_ok$76 , \xer_ca$75 } = { output_xer_ca_ok, \output_xer_ca$46 }; + assign { \cr_a_ok$74 , \cr_a$73 } = { output_cr_a_ok, \output_cr_a$45 }; + assign { \o_ok$72 , \o$71 } = { \output_o_ok$44 , \output_o$43 }; + assign { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54 } = { \output_sr_op__insn$42 , \output_sr_op__is_signed$41 , \output_sr_op__is_32bit$40 , \output_sr_op__output_cr$39 , \output_sr_op__input_cr$38 , \output_sr_op__output_carry$37 , \output_sr_op__input_carry$36 , \output_sr_op__invert_in$35 , \output_sr_op__write_cr0$34 , \output_sr_op__oe__ok$33 , \output_sr_op__oe__oe$32 , \output_sr_op__rc__ok$31 , \output_sr_op__rc__rc$30 , \output_sr_op__imm_data__ok$29 , \output_sr_op__imm_data__data$28 , \output_sr_op__fn_unit$27 , \output_sr_op__insn_type$26 }; + assign \muxid$53 = \output_muxid$25 ; + assign p_valid_i_p_ready_o = \$51 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$50 = p_valid_i; + assign { \xer_ca_ok$49 , output_xer_ca } = { xer_ca_ok, xer_ca }; + assign { \xer_so_ok$48 , output_xer_so } = { xer_so_ok, xer_so }; + assign { \cr_a_ok$47 , output_cr_a } = { cr_a_ok, cr_a }; + assign { output_o_ok, output_o } = { o_ok, o }; + assign { output_sr_op__insn, output_sr_op__is_signed, output_sr_op__is_32bit, output_sr_op__output_cr, output_sr_op__input_cr, output_sr_op__output_carry, output_sr_op__input_carry, output_sr_op__invert_in, output_sr_op__write_cr0, output_sr_op__oe__ok, output_sr_op__oe__oe, output_sr_op__rc__ok, output_sr_op__rc__rc, output_sr_op__imm_data__ok, output_sr_op__imm_data__data, output_sr_op__fn_unit, output_sr_op__insn_type } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign output_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" *) +(* generator = "nMigen" *) +module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, n_valid_o, n_ready_i, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , o, o_ok, \fast1$11 , fast1_ok, \fast2$12 , fast2_ok, nia, nia_ok, msr, msr_ok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast1$11 ; + reg [63:0] \fast1$11 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \fast1$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \fast1$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + reg fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fast1_ok$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \fast1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast2$12 ; + reg [63:0] \fast2$12 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \fast2$12$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \fast2$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + reg fast2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \fast2_ok$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \fast2_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \main_fast1$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \main_fast2$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] main_msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_msr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] main_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \main_muxid$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] main_nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] main_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire main_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] main_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] main_trap_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \main_trap_op__cia$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] main_trap_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \main_trap_op__fn_unit$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] main_trap_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \main_trap_op__insn$16 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] main_trap_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \main_trap_op__insn_type$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire main_trap_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \main_trap_op__is_32bit$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] main_trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \main_trap_op__ldst_exc$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] main_trap_op__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \main_trap_op__msr$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] main_trap_op__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] \main_trap_op__trapaddr$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] main_trap_op__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \main_trap_op__traptype$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] msr; + reg [63:0] msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \msr$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \msr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output msr_ok; + reg msr_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \msr_ok$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \msr_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$28 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] nia; + reg [63:0] nia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \nia$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \nia$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + reg nia_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \nia_ok$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \nia_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$25 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] trap_op__cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \trap_op__cia$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \trap_op__cia$6 ; + reg [63:0] \trap_op__cia$6 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \trap_op__cia$6$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] trap_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \trap_op__fn_unit$3 ; + reg [13:0] \trap_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \trap_op__fn_unit$3$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \trap_op__fn_unit$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] trap_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \trap_op__insn$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \trap_op__insn$4 ; + reg [31:0] \trap_op__insn$4 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \trap_op__insn$4$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] trap_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \trap_op__insn_type$2 ; + reg [6:0] \trap_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \trap_op__insn_type$2$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \trap_op__insn_type$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input trap_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \trap_op__is_32bit$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \trap_op__is_32bit$7 ; + reg \trap_op__is_32bit$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \trap_op__is_32bit$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [7:0] \trap_op__ldst_exc$10 ; + reg [7:0] \trap_op__ldst_exc$10 = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] \trap_op__ldst_exc$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \trap_op__ldst_exc$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] trap_op__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \trap_op__msr$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \trap_op__msr$5 ; + reg [63:0] \trap_op__msr$5 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \trap_op__msr$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [12:0] trap_op__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [12:0] \trap_op__trapaddr$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [12:0] \trap_op__trapaddr$9 ; + reg [12:0] \trap_op__trapaddr$9 = 13'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [12:0] \trap_op__trapaddr$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] trap_op__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [7:0] \trap_op__traptype$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [7:0] \trap_op__traptype$8 ; + reg [7:0] \trap_op__traptype$8 = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] \trap_op__traptype$8$next ; + assign \$26 = \p_valid_i$25 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \fast1$11 <= \fast1$11$next ; + always @(posedge coresync_clk) + fast1_ok <= \fast1_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; + always @(posedge coresync_clk) + o_ok <= \o_ok$next ; + always @(posedge coresync_clk) + \trap_op__insn_type$2 <= \trap_op__insn_type$2$next ; + always @(posedge coresync_clk) + \trap_op__fn_unit$3 <= \trap_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \trap_op__insn$4 <= \trap_op__insn$4$next ; + always @(posedge coresync_clk) + \trap_op__msr$5 <= \trap_op__msr$5$next ; + always @(posedge coresync_clk) + \trap_op__cia$6 <= \trap_op__cia$6$next ; + always @(posedge coresync_clk) + \trap_op__is_32bit$7 <= \trap_op__is_32bit$7$next ; + always @(posedge coresync_clk) + \trap_op__traptype$8 <= \trap_op__traptype$8$next ; + always @(posedge coresync_clk) + \trap_op__trapaddr$9 <= \trap_op__trapaddr$9$next ; + always @(posedge coresync_clk) + \trap_op__ldst_exc$10 <= \trap_op__ldst_exc$10$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + always @(posedge coresync_clk) + msr <= \msr$next ; + always @(posedge coresync_clk) + msr_ok <= \msr_ok$next ; + always @(posedge coresync_clk) + nia <= \nia$next ; + always @(posedge coresync_clk) + nia_ok <= \nia_ok$next ; + always @(posedge coresync_clk) + \fast2$12 <= \fast2$12$next ; + always @(posedge coresync_clk) + fast2_ok <= \fast2_ok$next ; + \main$38 main ( + .fast1(main_fast1), + .\fast1$11 (\main_fast1$23 ), + .fast1_ok(main_fast1_ok), + .fast2(main_fast2), + .\fast2$12 (\main_fast2$24 ), + .fast2_ok(main_fast2_ok), + .msr(main_msr), + .msr_ok(main_msr_ok), + .muxid(main_muxid), + .\muxid$1 (\main_muxid$13 ), + .nia(main_nia), + .nia_ok(main_nia_ok), + .o(main_o), + .o_ok(main_o_ok), + .ra(main_ra), + .rb(main_rb), + .trap_op__cia(main_trap_op__cia), + .\trap_op__cia$6 (\main_trap_op__cia$18 ), + .trap_op__fn_unit(main_trap_op__fn_unit), + .\trap_op__fn_unit$3 (\main_trap_op__fn_unit$15 ), + .trap_op__insn(main_trap_op__insn), + .\trap_op__insn$4 (\main_trap_op__insn$16 ), + .trap_op__insn_type(main_trap_op__insn_type), + .\trap_op__insn_type$2 (\main_trap_op__insn_type$14 ), + .trap_op__is_32bit(main_trap_op__is_32bit), + .\trap_op__is_32bit$7 (\main_trap_op__is_32bit$19 ), + .trap_op__ldst_exc(main_trap_op__ldst_exc), + .\trap_op__ldst_exc$10 (\main_trap_op__ldst_exc$22 ), + .trap_op__msr(main_trap_op__msr), + .\trap_op__msr$5 (\main_trap_op__msr$17 ), + .trap_op__trapaddr(main_trap_op__trapaddr), + .\trap_op__trapaddr$9 (\main_trap_op__trapaddr$21 ), + .trap_op__traptype(main_trap_op__traptype), + .\trap_op__traptype$8 (\main_trap_op__traptype$20 ) + ); + \n$37 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$36 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$28 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$28 ; + endcase + end + always @* begin + if (\initial ) begin end + \trap_op__insn_type$2$next = \trap_op__insn_type$2 ; + \trap_op__fn_unit$3$next = \trap_op__fn_unit$3 ; + \trap_op__insn$4$next = \trap_op__insn$4 ; + \trap_op__msr$5$next = \trap_op__msr$5 ; + \trap_op__cia$6$next = \trap_op__cia$6 ; + \trap_op__is_32bit$7$next = \trap_op__is_32bit$7 ; + \trap_op__traptype$8$next = \trap_op__traptype$8 ; + \trap_op__trapaddr$9$next = \trap_op__trapaddr$9 ; + \trap_op__ldst_exc$10$next = \trap_op__ldst_exc$10 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \trap_op__ldst_exc$10$next , \trap_op__trapaddr$9$next , \trap_op__traptype$8$next , \trap_op__is_32bit$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \trap_op__ldst_exc$10$next , \trap_op__trapaddr$9$next , \trap_op__traptype$8$next , \trap_op__is_32bit$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29 }; + endcase + end + always @* begin + if (\initial ) begin end + \o$next = o; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$next } = { \o_ok$39 , \o$38 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$next } = { \o_ok$39 , \o$38 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fast1$11$next = \fast1$11 ; + \fast1_ok$next = fast1_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$41 , \fast1$40 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$41 , \fast1$40 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \fast1_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fast2$12$next = \fast2$12 ; + \fast2_ok$next = fast2_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \fast2_ok$next , \fast2$12$next } = { \fast2_ok$43 , \fast2$42 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \fast2_ok$next , \fast2$12$next } = { \fast2_ok$43 , \fast2$42 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \fast2_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \nia$next = nia; + \nia_ok$next = nia_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \nia_ok$next , \nia$next } = { \nia_ok$45 , \nia$44 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \nia_ok$next , \nia$next } = { \nia_ok$45 , \nia$44 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \nia_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \msr$next = msr; + \msr_ok$next = msr_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \msr_ok$next , \msr$next } = { \msr_ok$47 , \msr$46 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \msr_ok$next , \msr$next } = { \msr_ok$47 , \msr$46 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \msr_ok$next = 1'h0; + endcase + end + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \msr_ok$47 , \msr$46 } = { main_msr_ok, main_msr }; + assign { \nia_ok$45 , \nia$44 } = { main_nia_ok, main_nia }; + assign { \fast2_ok$43 , \fast2$42 } = { main_fast2_ok, \main_fast2$24 }; + assign { \fast1_ok$41 , \fast1$40 } = { main_fast1_ok, \main_fast1$23 }; + assign { \o_ok$39 , \o$38 } = { main_o_ok, main_o }; + assign { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29 } = { \main_trap_op__ldst_exc$22 , \main_trap_op__trapaddr$21 , \main_trap_op__traptype$20 , \main_trap_op__is_32bit$19 , \main_trap_op__cia$18 , \main_trap_op__msr$17 , \main_trap_op__insn$16 , \main_trap_op__fn_unit$15 , \main_trap_op__insn_type$14 }; + assign \muxid$28 = \main_muxid$13 ; + assign p_valid_i_p_ready_o = \$26 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$25 = p_valid_i; + assign main_fast2 = fast2; + assign main_fast1 = fast1; + assign main_rb = rb; + assign main_ra = ra; + assign { main_trap_op__ldst_exc, main_trap_op__trapaddr, main_trap_op__traptype, main_trap_op__is_32bit, main_trap_op__cia, main_trap_op__msr, main_trap_op__insn, main_trap_op__fn_unit, main_trap_op__insn_type } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; + assign main_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" *) +(* generator = "nMigen" *) +module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$20 , xer_so_ok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [3:0] cr_a; + reg [3:0] cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \cr_a$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [3:0] \cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + reg cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \cr_a_ok$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + input div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + input dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + input dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + input dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + input divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + reg [3:0] \logical_op__data_len$18 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \logical_op__data_len$18$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \logical_op__data_len$93 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + reg [13:0] \logical_op__fn_unit$3 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \logical_op__fn_unit$3$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \logical_op__fn_unit$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + reg [63:0] \logical_op__imm_data__data$4 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \logical_op__imm_data__data$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \logical_op__imm_data__data$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + reg \logical_op__imm_data__ok$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__imm_data__ok$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__imm_data__ok$80 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + reg [1:0] \logical_op__input_carry$12 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \logical_op__input_carry$12$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \logical_op__input_carry$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + reg [31:0] \logical_op__insn$19 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \logical_op__insn$19$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \logical_op__insn$94 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + reg [6:0] \logical_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \logical_op__insn_type$2$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \logical_op__insn_type$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + reg \logical_op__invert_in$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_in$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_in$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + reg \logical_op__invert_out$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_out$13$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_out$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + reg \logical_op__is_32bit$16 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_32bit$16$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_32bit$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + reg \logical_op__is_signed$17 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_signed$17$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_signed$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + reg \logical_op__oe__oe$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__oe$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__oe$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__ok$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + reg \logical_op__oe__ok$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__ok$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + reg \logical_op__output_carry$15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__output_carry$15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__output_carry$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + reg \logical_op__rc__ok$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__ok$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__ok$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + reg \logical_op__rc__rc$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__rc$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__rc$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + reg \logical_op__write_cr0$14 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__write_cr0$14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__write_cr0$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + reg \logical_op__zero_a$11 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__zero_a$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__zero_a$86 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + reg [1:0] \muxid$1 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$76 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \o$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [63:0] \o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \o_ok$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] output_cr_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] \output_cr_a$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] output_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \output_logical_op__data_len$58 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] output_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \output_logical_op__fn_unit$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] output_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \output_logical_op__imm_data__data$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__imm_data__ok$45 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] output_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \output_logical_op__input_carry$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] output_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \output_logical_op__insn$59 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] output_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \output_logical_op__insn_type$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__invert_in$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__invert_out$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__is_32bit$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__is_signed$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__oe__oe$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__oe__ok$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__output_carry$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__rc__ok$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__rc__rc$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__write_cr0$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_logical_op__zero_a$51 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] output_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \output_muxid$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] output_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \output_o$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_o_ok$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + wire output_stage_div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + wire output_stage_dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + wire output_stage_dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + wire output_stage_dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + wire output_stage_divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] output_stage_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \output_stage_logical_op__data_len$38 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] output_stage_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \output_stage_logical_op__fn_unit$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] output_stage_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \output_stage_logical_op__imm_data__data$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__imm_data__ok$25 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] output_stage_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \output_stage_logical_op__input_carry$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] output_stage_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \output_stage_logical_op__insn$39 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] output_stage_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \output_stage_logical_op__insn_type$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__invert_in$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__invert_out$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__is_32bit$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__is_signed$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__oe__oe$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__oe__ok$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__output_carry$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__rc__ok$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__rc__rc$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__write_cr0$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire output_stage_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \output_stage_logical_op__zero_a$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] output_stage_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \output_stage_muxid$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] output_stage_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_stage_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) + wire [63:0] output_stage_quotient_root; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) + wire [191:0] output_stage_remainder; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] output_stage_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_stage_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire output_stage_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_stage_xer_so$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] output_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_xer_ov$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \output_xer_so$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire output_xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$73 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) + input [63:0] quotient_root; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \ra$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \rb$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) + input [191:0] remainder; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] xer_ov; + reg [1:0] xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \xer_ov$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [1:0] \xer_ov$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ov_ok$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_ov_ok$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_ov_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$20 ; + reg \xer_so$20 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so$20$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \xer_so_ok$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \xer_so_ok$next ; + assign \$74 = \p_valid_i$73 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + \xer_so$20 <= \xer_so$20$next ; + always @(posedge coresync_clk) + xer_so_ok <= \xer_so_ok$next ; + always @(posedge coresync_clk) + xer_ov <= \xer_ov$next ; + always @(posedge coresync_clk) + xer_ov_ok <= \xer_ov_ok$next ; + always @(posedge coresync_clk) + cr_a <= \cr_a$next ; + always @(posedge coresync_clk) + cr_a_ok <= \cr_a_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; + always @(posedge coresync_clk) + o_ok <= \o_ok$next ; + always @(posedge coresync_clk) + \logical_op__insn_type$2 <= \logical_op__insn_type$2$next ; + always @(posedge coresync_clk) + \logical_op__fn_unit$3 <= \logical_op__fn_unit$3$next ; + always @(posedge coresync_clk) + \logical_op__imm_data__data$4 <= \logical_op__imm_data__data$4$next ; + always @(posedge coresync_clk) + \logical_op__imm_data__ok$5 <= \logical_op__imm_data__ok$5$next ; + always @(posedge coresync_clk) + \logical_op__rc__rc$6 <= \logical_op__rc__rc$6$next ; + always @(posedge coresync_clk) + \logical_op__rc__ok$7 <= \logical_op__rc__ok$7$next ; + always @(posedge coresync_clk) + \logical_op__oe__oe$8 <= \logical_op__oe__oe$8$next ; + always @(posedge coresync_clk) + \logical_op__oe__ok$9 <= \logical_op__oe__ok$9$next ; + always @(posedge coresync_clk) + \logical_op__invert_in$10 <= \logical_op__invert_in$10$next ; + always @(posedge coresync_clk) + \logical_op__zero_a$11 <= \logical_op__zero_a$11$next ; + always @(posedge coresync_clk) + \logical_op__input_carry$12 <= \logical_op__input_carry$12$next ; + always @(posedge coresync_clk) + \logical_op__invert_out$13 <= \logical_op__invert_out$13$next ; + always @(posedge coresync_clk) + \logical_op__write_cr0$14 <= \logical_op__write_cr0$14$next ; + always @(posedge coresync_clk) + \logical_op__output_carry$15 <= \logical_op__output_carry$15$next ; + always @(posedge coresync_clk) + \logical_op__is_32bit$16 <= \logical_op__is_32bit$16$next ; + always @(posedge coresync_clk) + \logical_op__is_signed$17 <= \logical_op__is_signed$17$next ; + always @(posedge coresync_clk) + \logical_op__data_len$18 <= \logical_op__data_len$18$next ; + always @(posedge coresync_clk) + \logical_op__insn$19 <= \logical_op__insn$19$next ; + always @(posedge coresync_clk) + \muxid$1 <= \muxid$1$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \n$82 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \output$83 \output ( + .cr_a(output_cr_a), + .\cr_a$22 (\output_cr_a$62 ), + .cr_a_ok(output_cr_a_ok), + .logical_op__data_len(output_logical_op__data_len), + .\logical_op__data_len$18 (\output_logical_op__data_len$58 ), + .logical_op__fn_unit(output_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$43 ), + .logical_op__imm_data__data(output_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$44 ), + .logical_op__imm_data__ok(output_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$45 ), + .logical_op__input_carry(output_logical_op__input_carry), + .\logical_op__input_carry$12 (\output_logical_op__input_carry$52 ), + .logical_op__insn(output_logical_op__insn), + .\logical_op__insn$19 (\output_logical_op__insn$59 ), + .logical_op__insn_type(output_logical_op__insn_type), + .\logical_op__insn_type$2 (\output_logical_op__insn_type$42 ), + .logical_op__invert_in(output_logical_op__invert_in), + .\logical_op__invert_in$10 (\output_logical_op__invert_in$50 ), + .logical_op__invert_out(output_logical_op__invert_out), + .\logical_op__invert_out$13 (\output_logical_op__invert_out$53 ), + .logical_op__is_32bit(output_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$56 ), + .logical_op__is_signed(output_logical_op__is_signed), + .\logical_op__is_signed$17 (\output_logical_op__is_signed$57 ), + .logical_op__oe__oe(output_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$48 ), + .logical_op__oe__ok(output_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$49 ), + .logical_op__output_carry(output_logical_op__output_carry), + .\logical_op__output_carry$15 (\output_logical_op__output_carry$55 ), + .logical_op__rc__ok(output_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$47 ), + .logical_op__rc__rc(output_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$46 ), + .logical_op__write_cr0(output_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$54 ), + .logical_op__zero_a(output_logical_op__zero_a), + .\logical_op__zero_a$11 (\output_logical_op__zero_a$51 ), + .muxid(output_muxid), + .\muxid$1 (\output_muxid$41 ), + .o(output_o), + .\o$20 (\output_o$60 ), + .o_ok(output_o_ok), + .\o_ok$21 (\output_o_ok$61 ), + .xer_ov(output_xer_ov), + .\xer_ov$23 (\output_xer_ov$63 ), + .xer_ov_ok(output_xer_ov_ok), + .xer_so(output_xer_so), + .\xer_so$24 (\output_xer_so$64 ), + .xer_so_ok(output_xer_so_ok) + ); + output_stage output_stage ( + .div_by_zero(output_stage_div_by_zero), + .dive_abs_ov32(output_stage_dive_abs_ov32), + .dive_abs_ov64(output_stage_dive_abs_ov64), + .dividend_neg(output_stage_dividend_neg), + .divisor_neg(output_stage_divisor_neg), + .logical_op__data_len(output_stage_logical_op__data_len), + .\logical_op__data_len$18 (\output_stage_logical_op__data_len$38 ), + .logical_op__fn_unit(output_stage_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\output_stage_logical_op__fn_unit$23 ), + .logical_op__imm_data__data(output_stage_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\output_stage_logical_op__imm_data__data$24 ), + .logical_op__imm_data__ok(output_stage_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\output_stage_logical_op__imm_data__ok$25 ), + .logical_op__input_carry(output_stage_logical_op__input_carry), + .\logical_op__input_carry$12 (\output_stage_logical_op__input_carry$32 ), + .logical_op__insn(output_stage_logical_op__insn), + .\logical_op__insn$19 (\output_stage_logical_op__insn$39 ), + .logical_op__insn_type(output_stage_logical_op__insn_type), + .\logical_op__insn_type$2 (\output_stage_logical_op__insn_type$22 ), + .logical_op__invert_in(output_stage_logical_op__invert_in), + .\logical_op__invert_in$10 (\output_stage_logical_op__invert_in$30 ), + .logical_op__invert_out(output_stage_logical_op__invert_out), + .\logical_op__invert_out$13 (\output_stage_logical_op__invert_out$33 ), + .logical_op__is_32bit(output_stage_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\output_stage_logical_op__is_32bit$36 ), + .logical_op__is_signed(output_stage_logical_op__is_signed), + .\logical_op__is_signed$17 (\output_stage_logical_op__is_signed$37 ), + .logical_op__oe__oe(output_stage_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\output_stage_logical_op__oe__oe$28 ), + .logical_op__oe__ok(output_stage_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\output_stage_logical_op__oe__ok$29 ), + .logical_op__output_carry(output_stage_logical_op__output_carry), + .\logical_op__output_carry$15 (\output_stage_logical_op__output_carry$35 ), + .logical_op__rc__ok(output_stage_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\output_stage_logical_op__rc__ok$27 ), + .logical_op__rc__rc(output_stage_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\output_stage_logical_op__rc__rc$26 ), + .logical_op__write_cr0(output_stage_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\output_stage_logical_op__write_cr0$34 ), + .logical_op__zero_a(output_stage_logical_op__zero_a), + .\logical_op__zero_a$11 (\output_stage_logical_op__zero_a$31 ), + .muxid(output_stage_muxid), + .\muxid$1 (\output_stage_muxid$21 ), + .o(output_stage_o), + .o_ok(output_stage_o_ok), + .quotient_root(output_stage_quotient_root), + .remainder(output_stage_remainder), + .xer_ov(output_stage_xer_ov), + .xer_ov_ok(output_stage_xer_ov_ok), + .xer_so(output_stage_xer_so), + .\xer_so$20 (\output_stage_xer_so$40 ) + ); + \p$81 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \o$next = o; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$next } = { \o_ok$96 , \o$95 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$next } = { \o_ok$96 , \o$95 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cr_a$next = cr_a; + \cr_a_ok$next = cr_a_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$98 , \cr_a$97 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$98 , \cr_a$97 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$next = xer_ov; + \xer_ov_ok$next = xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$100 , \xer_ov$99 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$100 , \xer_ov$99 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_ov_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$20$next = \xer_so$20 ; + \xer_so_ok$next = xer_so_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_so_ok$next , \xer_so$20$next } = { \xer_so_ok$102 , \xer_so$101 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_so_ok$next , \xer_so$20$next } = { \xer_so_ok$102 , \xer_so$101 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \xer_so_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$1$next = \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$1$next = \muxid$76 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$1$next = \muxid$76 ; + endcase + end + always @* begin + if (\initial ) begin end + \logical_op__insn_type$2$next = \logical_op__insn_type$2 ; + \logical_op__fn_unit$3$next = \logical_op__fn_unit$3 ; + \logical_op__imm_data__data$4$next = \logical_op__imm_data__data$4 ; + \logical_op__imm_data__ok$5$next = \logical_op__imm_data__ok$5 ; + \logical_op__rc__rc$6$next = \logical_op__rc__rc$6 ; + \logical_op__rc__ok$7$next = \logical_op__rc__ok$7 ; + \logical_op__oe__oe$8$next = \logical_op__oe__oe$8 ; + \logical_op__oe__ok$9$next = \logical_op__oe__ok$9 ; + \logical_op__invert_in$10$next = \logical_op__invert_in$10 ; + \logical_op__zero_a$11$next = \logical_op__zero_a$11 ; + \logical_op__input_carry$12$next = \logical_op__input_carry$12 ; + \logical_op__invert_out$13$next = \logical_op__invert_out$13 ; + \logical_op__write_cr0$14$next = \logical_op__write_cr0$14 ; + \logical_op__output_carry$15$next = \logical_op__output_carry$15 ; + \logical_op__is_32bit$16$next = \logical_op__is_32bit$16 ; + \logical_op__is_signed$17$next = \logical_op__is_signed$17 ; + \logical_op__data_len$18$next = \logical_op__data_len$18 ; + \logical_op__insn$19$next = \logical_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \logical_op__imm_data__data$4$next = 64'h0000000000000000; + \logical_op__imm_data__ok$5$next = 1'h0; + \logical_op__rc__rc$6$next = 1'h0; + \logical_op__rc__ok$7$next = 1'h0; + \logical_op__oe__oe$8$next = 1'h0; + \logical_op__oe__ok$9$next = 1'h0; + end + endcase + end + assign \cr_a$68 = 4'h0; + assign \cr_a_ok$69 = 1'h0; + assign \xer_so_ok$72 = 1'h0; + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign { \xer_so_ok$102 , \xer_so$101 } = { output_xer_so_ok, \output_xer_so$64 }; + assign { \xer_ov_ok$100 , \xer_ov$99 } = { output_xer_ov_ok, \output_xer_ov$63 }; + assign { \cr_a_ok$98 , \cr_a$97 } = { output_cr_a_ok, \output_cr_a$62 }; + assign { \o_ok$96 , \o$95 } = { \output_o_ok$61 , \output_o$60 }; + assign { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77 } = { \output_logical_op__insn$59 , \output_logical_op__data_len$58 , \output_logical_op__is_signed$57 , \output_logical_op__is_32bit$56 , \output_logical_op__output_carry$55 , \output_logical_op__write_cr0$54 , \output_logical_op__invert_out$53 , \output_logical_op__input_carry$52 , \output_logical_op__zero_a$51 , \output_logical_op__invert_in$50 , \output_logical_op__oe__ok$49 , \output_logical_op__oe__oe$48 , \output_logical_op__rc__ok$47 , \output_logical_op__rc__rc$46 , \output_logical_op__imm_data__ok$45 , \output_logical_op__imm_data__data$44 , \output_logical_op__fn_unit$43 , \output_logical_op__insn_type$42 }; + assign \muxid$76 = \output_muxid$41 ; + assign p_valid_i_p_ready_o = \$74 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$73 = p_valid_i; + assign { \xer_so_ok$71 , output_xer_so } = { 1'h0, \output_stage_xer_so$40 }; + assign { \xer_ov_ok$70 , output_xer_ov } = { output_stage_xer_ov_ok, output_stage_xer_ov }; + assign { \cr_a_ok$67 , output_cr_a } = 5'h00; + assign { output_o_ok, output_o } = { output_stage_o_ok, output_stage_o }; + assign { output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { \output_stage_logical_op__insn$39 , \output_stage_logical_op__data_len$38 , \output_stage_logical_op__is_signed$37 , \output_stage_logical_op__is_32bit$36 , \output_stage_logical_op__output_carry$35 , \output_stage_logical_op__write_cr0$34 , \output_stage_logical_op__invert_out$33 , \output_stage_logical_op__input_carry$32 , \output_stage_logical_op__zero_a$31 , \output_stage_logical_op__invert_in$30 , \output_stage_logical_op__oe__ok$29 , \output_stage_logical_op__oe__oe$28 , \output_stage_logical_op__rc__ok$27 , \output_stage_logical_op__rc__rc$26 , \output_stage_logical_op__imm_data__ok$25 , \output_stage_logical_op__imm_data__data$24 , \output_stage_logical_op__fn_unit$23 , \output_stage_logical_op__insn_type$22 }; + assign output_muxid = \output_stage_muxid$21 ; + assign output_stage_remainder = remainder; + assign output_stage_quotient_root = quotient_root; + assign output_stage_div_by_zero = div_by_zero; + assign output_stage_dive_abs_ov64 = dive_abs_ov64; + assign output_stage_dive_abs_ov32 = dive_abs_ov32; + assign output_stage_dividend_neg = dividend_neg; + assign output_stage_divisor_neg = divisor_neg; + assign output_stage_xer_so = xer_so; + assign \rb$66 = rb; + assign \ra$65 = ra; + assign { output_stage_logical_op__insn, output_stage_logical_op__data_len, output_stage_logical_op__is_signed, output_stage_logical_op__is_32bit, output_stage_logical_op__output_carry, output_stage_logical_op__write_cr0, output_stage_logical_op__invert_out, output_stage_logical_op__input_carry, output_stage_logical_op__zero_a, output_stage_logical_op__invert_in, output_stage_logical_op__oe__ok, output_stage_logical_op__oe__oe, output_stage_logical_op__rc__ok, output_stage_logical_op__rc__rc, output_stage_logical_op__imm_data__ok, output_stage_logical_op__imm_data__data, output_stage_logical_op__fn_unit, output_stage_logical_op__insn_type } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign output_stage_muxid = muxid; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" *) +(* generator = "nMigen" *) +module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , \divisor_neg$23 , \dividend_neg$24 , \dive_abs_ov32$25 , \dive_abs_ov64$26 , \div_by_zero$27 , quotient_root, remainder, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) + wire [191:0] \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) + wire [190:0] \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) + wire \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + input div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + output \div_by_zero$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + reg \div_by_zero$54 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + reg \div_by_zero$54$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" *) + wire [127:0] div_state_init_dividend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) + wire [127:0] div_state_init_o_dividend_quotient; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) + wire [6:0] div_state_init_o_q_bits_known; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" *) + reg [63:0] div_state_next_divisor; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) + reg [127:0] div_state_next_i_dividend_quotient; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) + reg [6:0] div_state_next_i_q_bits_known; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) + wire [127:0] div_state_next_o_dividend_quotient; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) + wire [6:0] div_state_next_o_q_bits_known; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + input dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + output \dive_abs_ov32$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + reg \dive_abs_ov32$52 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + reg \dive_abs_ov32$52$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + input dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + output \dive_abs_ov64$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + reg \dive_abs_ov64$53 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + reg \dive_abs_ov64$53$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + input [127:0] dividend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + reg [127:0] \dividend$68 = 128'h00000000000000000000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + reg [127:0] \dividend$68$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + input dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + output \dividend_neg$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + reg \dividend_neg$51 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + reg \dividend_neg$51$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + input divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + output \divisor_neg$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + reg \divisor_neg$50 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + reg \divisor_neg$50$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + input [63:0] divisor_radicand; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + reg [63:0] \divisor_radicand$65 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + reg [63:0] \divisor_radicand$65$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" *) + reg empty = 1'h1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" *) + reg \empty$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \logical_op__data_len$45 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \logical_op__data_len$45$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \logical_op__fn_unit$30 = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \logical_op__fn_unit$30$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \logical_op__imm_data__data$31 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \logical_op__imm_data__data$31$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__imm_data__ok$32 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__imm_data__ok$32$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \logical_op__input_carry$39 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \logical_op__input_carry$39$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \logical_op__insn$46 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \logical_op__insn$46$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \logical_op__insn_type$29 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \logical_op__insn_type$29$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_in$37 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_in$37$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_out$40 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_out$40$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_32bit$43 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_32bit$43$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_signed$44 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_signed$44$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__oe$35 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__oe$35$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__ok$36 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__ok$36$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__output_carry$42 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__output_carry$42$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__ok$34 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__ok$34$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__rc$33 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__rc$33$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__write_cr0$41 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__write_cr0$41$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__zero_a$38 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__zero_a$38$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$28 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$28$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + input [1:0] operation; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + reg [1:0] \operation$69 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + reg [1:0] \operation$69$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) + output [63:0] quotient_root; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \ra$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \ra$47 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \ra$47$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] \rb$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \rb$48 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \rb$48$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) + output [191:0] remainder; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) + reg [127:0] saved_state_dividend_quotient = 128'h00000000000000000000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) + reg [127:0] \saved_state_dividend_quotient$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) + reg [6:0] saved_state_q_bits_known = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) + reg [6:0] \saved_state_q_bits_known$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg \xer_so$49 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg \xer_so$49$next ; + assign \$56 = div_state_next_o_dividend_quotient[127:64] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) 7'h40; + assign \$55 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) \$56 ; + assign \$59 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) empty; + assign \$61 = saved_state_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 6'h3f; + assign \$63 = \$59 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) \$61 ; + assign \$66 = n_ready_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) n_valid_o; + always @(posedge coresync_clk) + \operation$69 <= \operation$69$next ; + always @(posedge coresync_clk) + \divisor_radicand$65 <= \divisor_radicand$65$next ; + always @(posedge coresync_clk) + \dividend$68 <= \dividend$68$next ; + always @(posedge coresync_clk) + \div_by_zero$54 <= \div_by_zero$54$next ; + always @(posedge coresync_clk) + \dive_abs_ov64$53 <= \dive_abs_ov64$53$next ; + always @(posedge coresync_clk) + \dive_abs_ov32$52 <= \dive_abs_ov32$52$next ; + always @(posedge coresync_clk) + \dividend_neg$51 <= \dividend_neg$51$next ; + always @(posedge coresync_clk) + \divisor_neg$50 <= \divisor_neg$50$next ; + always @(posedge coresync_clk) + \xer_so$49 <= \xer_so$49$next ; + always @(posedge coresync_clk) + \rb$48 <= \rb$48$next ; + always @(posedge coresync_clk) + \ra$47 <= \ra$47$next ; + always @(posedge coresync_clk) + \logical_op__insn_type$29 <= \logical_op__insn_type$29$next ; + always @(posedge coresync_clk) + \logical_op__fn_unit$30 <= \logical_op__fn_unit$30$next ; + always @(posedge coresync_clk) + \logical_op__imm_data__data$31 <= \logical_op__imm_data__data$31$next ; + always @(posedge coresync_clk) + \logical_op__imm_data__ok$32 <= \logical_op__imm_data__ok$32$next ; + always @(posedge coresync_clk) + \logical_op__rc__rc$33 <= \logical_op__rc__rc$33$next ; + always @(posedge coresync_clk) + \logical_op__rc__ok$34 <= \logical_op__rc__ok$34$next ; + always @(posedge coresync_clk) + \logical_op__oe__oe$35 <= \logical_op__oe__oe$35$next ; + always @(posedge coresync_clk) + \logical_op__oe__ok$36 <= \logical_op__oe__ok$36$next ; + always @(posedge coresync_clk) + \logical_op__invert_in$37 <= \logical_op__invert_in$37$next ; + always @(posedge coresync_clk) + \logical_op__zero_a$38 <= \logical_op__zero_a$38$next ; + always @(posedge coresync_clk) + \logical_op__input_carry$39 <= \logical_op__input_carry$39$next ; + always @(posedge coresync_clk) + \logical_op__invert_out$40 <= \logical_op__invert_out$40$next ; + always @(posedge coresync_clk) + \logical_op__write_cr0$41 <= \logical_op__write_cr0$41$next ; + always @(posedge coresync_clk) + \logical_op__output_carry$42 <= \logical_op__output_carry$42$next ; + always @(posedge coresync_clk) + \logical_op__is_32bit$43 <= \logical_op__is_32bit$43$next ; + always @(posedge coresync_clk) + \logical_op__is_signed$44 <= \logical_op__is_signed$44$next ; + always @(posedge coresync_clk) + \logical_op__data_len$45 <= \logical_op__data_len$45$next ; + always @(posedge coresync_clk) + \logical_op__insn$46 <= \logical_op__insn$46$next ; + always @(posedge coresync_clk) + \muxid$28 <= \muxid$28$next ; + always @(posedge coresync_clk) + empty <= \empty$next ; + always @(posedge coresync_clk) + saved_state_dividend_quotient <= \saved_state_dividend_quotient$next ; + always @(posedge coresync_clk) + saved_state_q_bits_known <= \saved_state_q_bits_known$next ; + div_state_init div_state_init ( + .dividend(div_state_init_dividend), + .o_dividend_quotient(div_state_init_o_dividend_quotient), + .o_q_bits_known(div_state_init_o_q_bits_known) + ); + div_state_next div_state_next ( + .divisor(div_state_next_divisor), + .i_dividend_quotient(div_state_next_i_dividend_quotient), + .i_q_bits_known(div_state_next_i_q_bits_known), + .o_dividend_quotient(div_state_next_o_dividend_quotient), + .o_q_bits_known(div_state_next_o_q_bits_known) + ); + \n$80 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$79 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + always @* begin + if (\initial ) begin end + \saved_state_q_bits_known$next = div_state_next_o_q_bits_known; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \saved_state_q_bits_known$next = 7'h00; + endcase + end + always @* begin + if (\initial ) begin end + \saved_state_dividend_quotient$next = div_state_next_o_dividend_quotient; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \saved_state_dividend_quotient$next = 128'h00000000000000000000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + div_state_next_i_q_bits_known = div_state_init_o_q_bits_known; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" */ + default: + div_state_next_i_q_bits_known = saved_state_q_bits_known; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + div_state_next_i_dividend_quotient = div_state_init_o_dividend_quotient; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" */ + default: + div_state_next_i_dividend_quotient = saved_state_dividend_quotient; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + div_state_next_divisor = divisor_radicand; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" */ + default: + div_state_next_divisor = \divisor_radicand$65 ; + endcase + end + always @* begin + if (\initial ) begin end + \empty$next = empty; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \empty$next = 1'h0; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) + casez (\$66 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" */ + 1'h1: + \empty$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \empty$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$28$next = \muxid$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \muxid$28$next = muxid; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \logical_op__insn_type$29$next = \logical_op__insn_type$29 ; + \logical_op__fn_unit$30$next = \logical_op__fn_unit$30 ; + \logical_op__imm_data__data$31$next = \logical_op__imm_data__data$31 ; + \logical_op__imm_data__ok$32$next = \logical_op__imm_data__ok$32 ; + \logical_op__rc__rc$33$next = \logical_op__rc__rc$33 ; + \logical_op__rc__ok$34$next = \logical_op__rc__ok$34 ; + \logical_op__oe__oe$35$next = \logical_op__oe__oe$35 ; + \logical_op__oe__ok$36$next = \logical_op__oe__ok$36 ; + \logical_op__invert_in$37$next = \logical_op__invert_in$37 ; + \logical_op__zero_a$38$next = \logical_op__zero_a$38 ; + \logical_op__input_carry$39$next = \logical_op__input_carry$39 ; + \logical_op__invert_out$40$next = \logical_op__invert_out$40 ; + \logical_op__write_cr0$41$next = \logical_op__write_cr0$41 ; + \logical_op__output_carry$42$next = \logical_op__output_carry$42 ; + \logical_op__is_32bit$43$next = \logical_op__is_32bit$43 ; + \logical_op__is_signed$44$next = \logical_op__is_signed$44 ; + \logical_op__data_len$45$next = \logical_op__data_len$45 ; + \logical_op__insn$46$next = \logical_op__insn$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + { \logical_op__insn$46$next , \logical_op__data_len$45$next , \logical_op__is_signed$44$next , \logical_op__is_32bit$43$next , \logical_op__output_carry$42$next , \logical_op__write_cr0$41$next , \logical_op__invert_out$40$next , \logical_op__input_carry$39$next , \logical_op__zero_a$38$next , \logical_op__invert_in$37$next , \logical_op__oe__ok$36$next , \logical_op__oe__oe$35$next , \logical_op__rc__ok$34$next , \logical_op__rc__rc$33$next , \logical_op__imm_data__ok$32$next , \logical_op__imm_data__data$31$next , \logical_op__fn_unit$30$next , \logical_op__insn_type$29$next } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \logical_op__imm_data__data$31$next = 64'h0000000000000000; + \logical_op__imm_data__ok$32$next = 1'h0; + \logical_op__rc__rc$33$next = 1'h0; + \logical_op__rc__ok$34$next = 1'h0; + \logical_op__oe__oe$35$next = 1'h0; + \logical_op__oe__ok$36$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \ra$47$next = \ra$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \ra$47$next = ra; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \rb$48$next = \rb$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \rb$48$next = rb; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$49$next = \xer_so$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \xer_so$49$next = xer_so; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \divisor_neg$50$next = \divisor_neg$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \divisor_neg$50$next = divisor_neg; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dividend_neg$51$next = \dividend_neg$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \dividend_neg$51$next = dividend_neg; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dive_abs_ov32$52$next = \dive_abs_ov32$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \dive_abs_ov32$52$next = dive_abs_ov32; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dive_abs_ov64$53$next = \dive_abs_ov64$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \dive_abs_ov64$53$next = dive_abs_ov64; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \div_by_zero$54$next = \div_by_zero$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \div_by_zero$54$next = div_by_zero; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dividend$68$next = \dividend$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \dividend$68$next = dividend; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \divisor_radicand$65$next = \divisor_radicand$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \divisor_radicand$65$next = divisor_radicand; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \operation$69$next = \operation$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) + casez (empty) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *) + casez (p_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ + 1'h1: + \operation$69$next = operation; + endcase + endcase + end + assign p_ready_o = empty; + assign n_valid_o = \$63 ; + assign remainder = \$55 ; + assign quotient_root = div_state_next_o_dividend_quotient[63:0]; + assign \div_by_zero$27 = \div_by_zero$54 ; + assign \dive_abs_ov64$26 = \dive_abs_ov64$53 ; + assign \dive_abs_ov32$25 = \dive_abs_ov32$52 ; + assign \dividend_neg$24 = \dividend_neg$51 ; + assign \divisor_neg$23 = \divisor_neg$50 ; + assign \xer_so$22 = \xer_so$49 ; + assign \rb$21 = \rb$48 ; + assign \ra$20 = \ra$47 ; + assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { \logical_op__insn$46 , \logical_op__data_len$45 , \logical_op__is_signed$44 , \logical_op__is_32bit$43 , \logical_op__output_carry$42 , \logical_op__write_cr0$41 , \logical_op__invert_out$40 , \logical_op__input_carry$39 , \logical_op__zero_a$38 , \logical_op__invert_in$37 , \logical_op__oe__ok$36 , \logical_op__oe__oe$35 , \logical_op__rc__ok$34 , \logical_op__rc__rc$33 , \logical_op__imm_data__ok$32 , \logical_op__imm_data__data$31 , \logical_op__fn_unit$30 , \logical_op__insn_type$29 }; + assign \muxid$1 = \muxid$28 ; + assign div_state_init_dividend = dividend; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" *) +(* generator = "nMigen" *) +module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) + wire \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + output div_by_zero; + reg div_by_zero = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + wire \div_by_zero$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + reg \div_by_zero$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + output dive_abs_ov32; + reg dive_abs_ov32 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + wire \dive_abs_ov32$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + reg \dive_abs_ov32$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + output dive_abs_ov64; + reg dive_abs_ov64 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + wire \dive_abs_ov64$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + reg \dive_abs_ov64$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + output [127:0] dividend; + reg [127:0] dividend = 128'h00000000000000000000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + wire [127:0] \dividend$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + reg [127:0] \dividend$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + output dividend_neg; + reg dividend_neg = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + wire \dividend_neg$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + reg \dividend_neg$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + output divisor_neg; + reg divisor_neg = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + wire \divisor_neg$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + reg \divisor_neg$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + output [63:0] divisor_radicand; + reg [63:0] divisor_radicand = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + wire [63:0] \divisor_radicand$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + reg [63:0] \divisor_radicand$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] input_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \input_logical_op__data_len$40 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] input_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \input_logical_op__fn_unit$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] input_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \input_logical_op__imm_data__data$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__imm_data__ok$27 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] input_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \input_logical_op__input_carry$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] input_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \input_logical_op__insn$41 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] input_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \input_logical_op__insn_type$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__invert_in$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__invert_out$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__is_32bit$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__is_signed$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__oe__oe$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__oe__ok$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__output_carry$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__rc__ok$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__rc__rc$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__write_cr0$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire input_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \input_logical_op__zero_a$33 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] input_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \input_muxid$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_ra$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] input_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \input_rb$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire input_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \input_xer_so$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] logical_op__data_len; + reg [3:0] logical_op__data_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] \logical_op__data_len$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \logical_op__data_len$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [3:0] \logical_op__data_len$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] logical_op__fn_unit; + reg [13:0] logical_op__fn_unit = 14'h0000; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] \logical_op__fn_unit$3 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \logical_op__fn_unit$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \logical_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] logical_op__imm_data__data; + reg [63:0] logical_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \logical_op__imm_data__data$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \logical_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__imm_data__ok; + reg logical_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__imm_data__ok$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__imm_data__ok$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__imm_data__ok$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] logical_op__input_carry; + reg [1:0] logical_op__input_carry = 2'h0; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] \logical_op__input_carry$12 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \logical_op__input_carry$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \logical_op__input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] logical_op__insn; + reg [31:0] logical_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] \logical_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \logical_op__insn$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \logical_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] logical_op__insn_type; + reg [6:0] logical_op__insn_type = 7'h00; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] \logical_op__insn_type$2 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \logical_op__insn_type$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \logical_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__invert_in; + reg logical_op__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_in$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__invert_out; + reg logical_op__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__invert_out$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__invert_out$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__is_32bit; + reg logical_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_32bit$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__is_signed; + reg logical_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__is_signed$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__oe__oe; + reg logical_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__oe$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__oe__ok; + reg logical_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__oe__ok$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__output_carry; + reg logical_op__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__output_carry$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__output_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__rc__ok; + reg logical_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__ok$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__rc__rc; + reg logical_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__rc__rc$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__write_cr0; + reg logical_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__write_cr0$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output logical_op__zero_a; + reg logical_op__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \logical_op__zero_a$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \logical_op__zero_a$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] muxid; + reg [1:0] muxid = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \muxid$68 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + reg [1:0] \muxid$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) + wire n_i_rdy_data; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + input n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + output n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + output [1:0] operation; + reg [1:0] operation = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + wire [1:0] \operation$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + reg [1:0] \operation$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + output p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + input p_valid_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) + wire \p_valid_i$65 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) + wire p_valid_i_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg r_busy = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) + reg \r_busy$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] ra; + reg [63:0] ra = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \ra$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \ra$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \ra$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \ra$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output [63:0] rb; + reg [63:0] rb = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] \rb$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \rb$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \rb$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg [63:0] \rb$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + wire setup_stage_div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + wire setup_stage_dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + wire setup_stage_dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + wire [127:0] setup_stage_dividend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + wire setup_stage_dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + wire setup_stage_divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + wire [63:0] setup_stage_divisor_radicand; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] setup_stage_logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [3:0] \setup_stage_logical_op__data_len$62 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] setup_stage_logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [13:0] \setup_stage_logical_op__fn_unit$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] setup_stage_logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [63:0] \setup_stage_logical_op__imm_data__data$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__imm_data__ok$49 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] setup_stage_logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [1:0] \setup_stage_logical_op__input_carry$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] setup_stage_logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [31:0] \setup_stage_logical_op__insn$63 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] setup_stage_logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire [6:0] \setup_stage_logical_op__insn_type$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__invert_in$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__invert_out$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__is_32bit$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__is_signed$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__oe__oe$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__oe__ok$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__output_carry$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__rc__ok$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__rc__rc$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__write_cr0$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire setup_stage_logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \setup_stage_logical_op__zero_a$55 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] setup_stage_muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + wire [1:0] \setup_stage_muxid$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + wire [1:0] setup_stage_operation; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] setup_stage_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] setup_stage_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire setup_stage_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \setup_stage_xer_so$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output xer_so; + reg xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input \xer_so$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \xer_so$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + reg \xer_so$next ; + assign \$66 = \p_valid_i$65 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + operation <= \operation$next ; + always @(posedge coresync_clk) + divisor_radicand <= \divisor_radicand$next ; + always @(posedge coresync_clk) + dividend <= \dividend$next ; + always @(posedge coresync_clk) + div_by_zero <= \div_by_zero$next ; + always @(posedge coresync_clk) + dive_abs_ov64 <= \dive_abs_ov64$next ; + always @(posedge coresync_clk) + dive_abs_ov32 <= \dive_abs_ov32$next ; + always @(posedge coresync_clk) + dividend_neg <= \dividend_neg$next ; + always @(posedge coresync_clk) + divisor_neg <= \divisor_neg$next ; + always @(posedge coresync_clk) + xer_so <= \xer_so$next ; + always @(posedge coresync_clk) + rb <= \rb$next ; + always @(posedge coresync_clk) + ra <= \ra$next ; + always @(posedge coresync_clk) + logical_op__insn_type <= \logical_op__insn_type$next ; + always @(posedge coresync_clk) + logical_op__fn_unit <= \logical_op__fn_unit$next ; + always @(posedge coresync_clk) + logical_op__imm_data__data <= \logical_op__imm_data__data$next ; + always @(posedge coresync_clk) + logical_op__imm_data__ok <= \logical_op__imm_data__ok$next ; + always @(posedge coresync_clk) + logical_op__rc__rc <= \logical_op__rc__rc$next ; + always @(posedge coresync_clk) + logical_op__rc__ok <= \logical_op__rc__ok$next ; + always @(posedge coresync_clk) + logical_op__oe__oe <= \logical_op__oe__oe$next ; + always @(posedge coresync_clk) + logical_op__oe__ok <= \logical_op__oe__ok$next ; + always @(posedge coresync_clk) + logical_op__invert_in <= \logical_op__invert_in$next ; + always @(posedge coresync_clk) + logical_op__zero_a <= \logical_op__zero_a$next ; + always @(posedge coresync_clk) + logical_op__input_carry <= \logical_op__input_carry$next ; + always @(posedge coresync_clk) + logical_op__invert_out <= \logical_op__invert_out$next ; + always @(posedge coresync_clk) + logical_op__write_cr0 <= \logical_op__write_cr0$next ; + always @(posedge coresync_clk) + logical_op__output_carry <= \logical_op__output_carry$next ; + always @(posedge coresync_clk) + logical_op__is_32bit <= \logical_op__is_32bit$next ; + always @(posedge coresync_clk) + logical_op__is_signed <= \logical_op__is_signed$next ; + always @(posedge coresync_clk) + logical_op__data_len <= \logical_op__data_len$next ; + always @(posedge coresync_clk) + logical_op__insn <= \logical_op__insn$next ; + always @(posedge coresync_clk) + muxid <= \muxid$next ; + always @(posedge coresync_clk) + r_busy <= \r_busy$next ; + \input$78 \input ( + .logical_op__data_len(input_logical_op__data_len), + .\logical_op__data_len$18 (\input_logical_op__data_len$40 ), + .logical_op__fn_unit(input_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$25 ), + .logical_op__imm_data__data(input_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$26 ), + .logical_op__imm_data__ok(input_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$27 ), + .logical_op__input_carry(input_logical_op__input_carry), + .\logical_op__input_carry$12 (\input_logical_op__input_carry$34 ), + .logical_op__insn(input_logical_op__insn), + .\logical_op__insn$19 (\input_logical_op__insn$41 ), + .logical_op__insn_type(input_logical_op__insn_type), + .\logical_op__insn_type$2 (\input_logical_op__insn_type$24 ), + .logical_op__invert_in(input_logical_op__invert_in), + .\logical_op__invert_in$10 (\input_logical_op__invert_in$32 ), + .logical_op__invert_out(input_logical_op__invert_out), + .\logical_op__invert_out$13 (\input_logical_op__invert_out$35 ), + .logical_op__is_32bit(input_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$38 ), + .logical_op__is_signed(input_logical_op__is_signed), + .\logical_op__is_signed$17 (\input_logical_op__is_signed$39 ), + .logical_op__oe__oe(input_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$30 ), + .logical_op__oe__ok(input_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$31 ), + .logical_op__output_carry(input_logical_op__output_carry), + .\logical_op__output_carry$15 (\input_logical_op__output_carry$37 ), + .logical_op__rc__ok(input_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$29 ), + .logical_op__rc__rc(input_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$28 ), + .logical_op__write_cr0(input_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$36 ), + .logical_op__zero_a(input_logical_op__zero_a), + .\logical_op__zero_a$11 (\input_logical_op__zero_a$33 ), + .muxid(input_muxid), + .\muxid$1 (\input_muxid$23 ), + .ra(input_ra), + .\ra$20 (\input_ra$42 ), + .rb(input_rb), + .\rb$21 (\input_rb$43 ), + .xer_so(input_xer_so), + .\xer_so$22 (\input_xer_so$44 ) + ); + \n$77 n ( + .n_ready_i(n_ready_i), + .n_valid_o(n_valid_o) + ); + \p$76 p ( + .p_ready_o(p_ready_o), + .p_valid_i(p_valid_i) + ); + setup_stage setup_stage ( + .div_by_zero(setup_stage_div_by_zero), + .dive_abs_ov32(setup_stage_dive_abs_ov32), + .dive_abs_ov64(setup_stage_dive_abs_ov64), + .dividend(setup_stage_dividend), + .dividend_neg(setup_stage_dividend_neg), + .divisor_neg(setup_stage_divisor_neg), + .divisor_radicand(setup_stage_divisor_radicand), + .logical_op__data_len(setup_stage_logical_op__data_len), + .\logical_op__data_len$18 (\setup_stage_logical_op__data_len$62 ), + .logical_op__fn_unit(setup_stage_logical_op__fn_unit), + .\logical_op__fn_unit$3 (\setup_stage_logical_op__fn_unit$47 ), + .logical_op__imm_data__data(setup_stage_logical_op__imm_data__data), + .\logical_op__imm_data__data$4 (\setup_stage_logical_op__imm_data__data$48 ), + .logical_op__imm_data__ok(setup_stage_logical_op__imm_data__ok), + .\logical_op__imm_data__ok$5 (\setup_stage_logical_op__imm_data__ok$49 ), + .logical_op__input_carry(setup_stage_logical_op__input_carry), + .\logical_op__input_carry$12 (\setup_stage_logical_op__input_carry$56 ), + .logical_op__insn(setup_stage_logical_op__insn), + .\logical_op__insn$19 (\setup_stage_logical_op__insn$63 ), + .logical_op__insn_type(setup_stage_logical_op__insn_type), + .\logical_op__insn_type$2 (\setup_stage_logical_op__insn_type$46 ), + .logical_op__invert_in(setup_stage_logical_op__invert_in), + .\logical_op__invert_in$10 (\setup_stage_logical_op__invert_in$54 ), + .logical_op__invert_out(setup_stage_logical_op__invert_out), + .\logical_op__invert_out$13 (\setup_stage_logical_op__invert_out$57 ), + .logical_op__is_32bit(setup_stage_logical_op__is_32bit), + .\logical_op__is_32bit$16 (\setup_stage_logical_op__is_32bit$60 ), + .logical_op__is_signed(setup_stage_logical_op__is_signed), + .\logical_op__is_signed$17 (\setup_stage_logical_op__is_signed$61 ), + .logical_op__oe__oe(setup_stage_logical_op__oe__oe), + .\logical_op__oe__oe$8 (\setup_stage_logical_op__oe__oe$52 ), + .logical_op__oe__ok(setup_stage_logical_op__oe__ok), + .\logical_op__oe__ok$9 (\setup_stage_logical_op__oe__ok$53 ), + .logical_op__output_carry(setup_stage_logical_op__output_carry), + .\logical_op__output_carry$15 (\setup_stage_logical_op__output_carry$59 ), + .logical_op__rc__ok(setup_stage_logical_op__rc__ok), + .\logical_op__rc__ok$7 (\setup_stage_logical_op__rc__ok$51 ), + .logical_op__rc__rc(setup_stage_logical_op__rc__rc), + .\logical_op__rc__rc$6 (\setup_stage_logical_op__rc__rc$50 ), + .logical_op__write_cr0(setup_stage_logical_op__write_cr0), + .\logical_op__write_cr0$14 (\setup_stage_logical_op__write_cr0$58 ), + .logical_op__zero_a(setup_stage_logical_op__zero_a), + .\logical_op__zero_a$11 (\setup_stage_logical_op__zero_a$55 ), + .muxid(setup_stage_muxid), + .\muxid$1 (\setup_stage_muxid$45 ), + .operation(setup_stage_operation), + .ra(setup_stage_ra), + .rb(setup_stage_rb), + .xer_so(setup_stage_xer_so), + .\xer_so$20 (\setup_stage_xer_so$64 ) + ); + always @* begin + if (\initial ) begin end + \divisor_neg$next = divisor_neg; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \divisor_neg$next = \divisor_neg$92 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \divisor_neg$next = \divisor_neg$92 ; + endcase + end + always @* begin + if (\initial ) begin end + \dividend_neg$next = dividend_neg; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \dividend_neg$next = \dividend_neg$93 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \dividend_neg$next = \dividend_neg$93 ; + endcase + end + always @* begin + if (\initial ) begin end + \dive_abs_ov32$next = dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \dive_abs_ov32$next = \dive_abs_ov32$94 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \dive_abs_ov32$next = \dive_abs_ov32$94 ; + endcase + end + always @* begin + if (\initial ) begin end + \dive_abs_ov64$next = dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \dive_abs_ov64$next = \dive_abs_ov64$95 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \dive_abs_ov64$next = \dive_abs_ov64$95 ; + endcase + end + always @* begin + if (\initial ) begin end + \div_by_zero$next = div_by_zero; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \div_by_zero$next = \div_by_zero$96 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \div_by_zero$next = \div_by_zero$96 ; + endcase + end + always @* begin + if (\initial ) begin end + \dividend$next = dividend; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \dividend$next = \dividend$97 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \dividend$next = \dividend$97 ; + endcase + end + always @* begin + if (\initial ) begin end + \divisor_radicand$next = divisor_radicand; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \divisor_radicand$next = \divisor_radicand$98 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \divisor_radicand$next = \divisor_radicand$98 ; + endcase + end + always @* begin + if (\initial ) begin end + \operation$next = operation; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \operation$next = \operation$99 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \operation$next = \operation$99 ; + endcase + end + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$next = muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$next = \muxid$68 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$next = \muxid$68 ; + endcase + end + always @* begin + if (\initial ) begin end + \logical_op__insn_type$next = logical_op__insn_type; + \logical_op__fn_unit$next = logical_op__fn_unit; + \logical_op__imm_data__data$next = logical_op__imm_data__data; + \logical_op__imm_data__ok$next = logical_op__imm_data__ok; + \logical_op__rc__rc$next = logical_op__rc__rc; + \logical_op__rc__ok$next = logical_op__rc__ok; + \logical_op__oe__oe$next = logical_op__oe__oe; + \logical_op__oe__ok$next = logical_op__oe__ok; + \logical_op__invert_in$next = logical_op__invert_in; + \logical_op__zero_a$next = logical_op__zero_a; + \logical_op__input_carry$next = logical_op__input_carry; + \logical_op__invert_out$next = logical_op__invert_out; + \logical_op__write_cr0$next = logical_op__write_cr0; + \logical_op__output_carry$next = logical_op__output_carry; + \logical_op__is_32bit$next = logical_op__is_32bit; + \logical_op__is_signed$next = logical_op__is_signed; + \logical_op__data_len$next = logical_op__data_len; + \logical_op__insn$next = logical_op__insn; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \logical_op__imm_data__data$next = 64'h0000000000000000; + \logical_op__imm_data__ok$next = 1'h0; + \logical_op__rc__rc$next = 1'h0; + \logical_op__rc__ok$next = 1'h0; + \logical_op__oe__oe$next = 1'h0; + \logical_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \ra$next = ra; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \ra$next = \ra$87 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \ra$next = \ra$87 ; + endcase + end + always @* begin + if (\initial ) begin end + \rb$next = rb; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \rb$next = \rb$89 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \rb$next = \rb$89 ; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$next = xer_so; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \xer_so$next = \xer_so$91 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \xer_so$next = \xer_so$91 ; + endcase + end + assign \ra$88 = 64'h0000000000000000; + assign \rb$90 = 64'h0000000000000000; + assign p_ready_o = n_i_rdy_data; + assign n_valid_o = r_busy; + assign \operation$99 = setup_stage_operation; + assign \divisor_radicand$98 = setup_stage_divisor_radicand; + assign \dividend$97 = setup_stage_dividend; + assign \div_by_zero$96 = setup_stage_div_by_zero; + assign \dive_abs_ov64$95 = setup_stage_dive_abs_ov64; + assign \dive_abs_ov32$94 = setup_stage_dive_abs_ov32; + assign \dividend_neg$93 = setup_stage_dividend_neg; + assign \divisor_neg$92 = setup_stage_divisor_neg; + assign \xer_so$91 = \setup_stage_xer_so$64 ; + assign \rb$89 = 64'h0000000000000000; + assign \ra$87 = 64'h0000000000000000; + assign { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69 } = { \setup_stage_logical_op__insn$63 , \setup_stage_logical_op__data_len$62 , \setup_stage_logical_op__is_signed$61 , \setup_stage_logical_op__is_32bit$60 , \setup_stage_logical_op__output_carry$59 , \setup_stage_logical_op__write_cr0$58 , \setup_stage_logical_op__invert_out$57 , \setup_stage_logical_op__input_carry$56 , \setup_stage_logical_op__zero_a$55 , \setup_stage_logical_op__invert_in$54 , \setup_stage_logical_op__oe__ok$53 , \setup_stage_logical_op__oe__oe$52 , \setup_stage_logical_op__rc__ok$51 , \setup_stage_logical_op__rc__rc$50 , \setup_stage_logical_op__imm_data__ok$49 , \setup_stage_logical_op__imm_data__data$48 , \setup_stage_logical_op__fn_unit$47 , \setup_stage_logical_op__insn_type$46 }; + assign \muxid$68 = \setup_stage_muxid$45 ; + assign p_valid_i_p_ready_o = \$66 ; + assign n_i_rdy_data = n_ready_i; + assign \p_valid_i$65 = p_valid_i; + assign setup_stage_xer_so = \input_xer_so$44 ; + assign setup_stage_rb = \input_rb$43 ; + assign setup_stage_ra = \input_ra$42 ; + assign { setup_stage_logical_op__insn, setup_stage_logical_op__data_len, setup_stage_logical_op__is_signed, setup_stage_logical_op__is_32bit, setup_stage_logical_op__output_carry, setup_stage_logical_op__write_cr0, setup_stage_logical_op__invert_out, setup_stage_logical_op__input_carry, setup_stage_logical_op__zero_a, setup_stage_logical_op__invert_in, setup_stage_logical_op__oe__ok, setup_stage_logical_op__oe__oe, setup_stage_logical_op__rc__ok, setup_stage_logical_op__rc__rc, setup_stage_logical_op__imm_data__ok, setup_stage_logical_op__imm_data__data, setup_stage_logical_op__fn_unit, setup_stage_logical_op__insn_type } = { \input_logical_op__insn$41 , \input_logical_op__data_len$40 , \input_logical_op__is_signed$39 , \input_logical_op__is_32bit$38 , \input_logical_op__output_carry$37 , \input_logical_op__write_cr0$36 , \input_logical_op__invert_out$35 , \input_logical_op__input_carry$34 , \input_logical_op__zero_a$33 , \input_logical_op__invert_in$32 , \input_logical_op__oe__ok$31 , \input_logical_op__oe__oe$30 , \input_logical_op__rc__ok$29 , \input_logical_op__rc__rc$28 , \input_logical_op__imm_data__ok$27 , \input_logical_op__imm_data__data$26 , \input_logical_op__fn_unit$25 , \input_logical_op__insn_type$24 }; + assign setup_stage_muxid = \input_muxid$23 ; + assign input_xer_so = \xer_so$22 ; + assign input_rb = \rb$21 ; + assign input_ra = \ra$20 ; + assign { input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 }; + assign input_muxid = \muxid$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.pll" *) +(* generator = "nMigen" *) +module pll(clk_24_i, pll_18_o, clk_sel_i, pll_lck_o, clk_pll_o); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *) + input clk_24_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *) + output clk_pll_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) + input [1:0] clk_sel_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *) + output pll_18_o; + reg pll_18_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *) + output pll_lck_o; + reg pll_lck_o; + assign \$1 = clk_sel_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *) 2'h0; + assign \$3 = clk_sel_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *) 2'h0; + assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) clk_24_i; + always @* begin + if (\initial ) begin end + pll_lck_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" */ + 1'h1: + pll_lck_o = clk_24_i; + endcase + end + always @* begin + if (\initial ) begin end + pll_18_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" */ + 1'h1: + pll_18_o = \$5 ; + endcase + end + assign clk_pll_o = clk_24_i; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" *) +(* generator = "nMigen" *) +module popcount(data_len, o, a); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$119 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$122 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$125 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$127 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$130 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$131 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$133 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$134 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$137 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$140 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$142 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$143 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$145 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$146 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$148 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$149 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$151 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$152 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$154 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$155 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$157 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$158 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$160 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$161 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$163 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$164 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$166 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [4:0] \$167 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [5:0] \$169 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [5:0] \$170 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [5:0] \$172 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [5:0] \$173 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [5:0] \$175 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [5:0] \$176 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [5:0] \$178 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [5:0] \$179 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [6:0] \$181 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [6:0] \$182 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [6:0] \$184 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [6:0] \$185 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [7:0] \$187 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [7:0] \$188 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" *) + wire \$190 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" *) + wire \$192 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [7:0] \$194 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [7:0] \$196 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [7:0] \$198 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [7:0] \$200 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [7:0] \$202 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [7:0] \$204 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [7:0] \$206 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [7:0] \$208 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [31:0] \$210 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [31:0] \$212 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [63:0] \$214 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [2:0] \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) + wire [3:0] \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" *) + input [63:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" *) + input [63:0] data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" *) + output [63:0] o; + reg [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_15; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_16; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_17; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_18; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_19; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_20; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_21; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_22; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_23; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_24; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_25; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_26; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_27; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_28; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_29; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_30; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_31; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [1:0] pop_2_9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_15; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [2:0] pop_3_9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [3:0] pop_4_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [3:0] pop_4_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [3:0] pop_4_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [3:0] pop_4_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [3:0] pop_4_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [3:0] pop_4_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [3:0] pop_4_6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [3:0] pop_4_7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [4:0] pop_5_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [4:0] pop_5_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [4:0] pop_5_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [4:0] pop_5_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [5:0] pop_6_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [5:0] pop_6_1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) + wire [6:0] pop_7_0; + assign \$101 = { 1'h0, pop_2_2 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_3 }; + assign \$104 = { 1'h0, pop_2_4 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_5 }; + assign \$107 = { 1'h0, pop_2_6 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_7 }; + assign \$110 = { 1'h0, pop_2_8 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_9 }; + assign \$113 = { 1'h0, pop_2_10 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_11 }; + assign \$116 = { 1'h0, pop_2_12 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_13 }; + assign \$11 = { 1'h0, a[6] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[7] }; + assign \$119 = { 1'h0, pop_2_14 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_15 }; + assign \$122 = { 1'h0, pop_2_16 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_17 }; + assign \$125 = { 1'h0, pop_2_18 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_19 }; + assign \$128 = { 1'h0, pop_2_20 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_21 }; + assign \$131 = { 1'h0, pop_2_22 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_23 }; + assign \$134 = { 1'h0, pop_2_24 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_25 }; + assign \$137 = { 1'h0, pop_2_26 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_27 }; + assign \$140 = { 1'h0, pop_2_28 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_29 }; + assign \$143 = { 1'h0, pop_2_30 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_31 }; + assign \$146 = { 1'h0, pop_3_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_3_1 }; + assign \$14 = { 1'h0, a[8] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[9] }; + assign \$149 = { 1'h0, pop_3_2 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_3_3 }; + assign \$152 = { 1'h0, pop_3_4 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_3_5 }; + assign \$155 = { 1'h0, pop_3_6 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_3_7 }; + assign \$158 = { 1'h0, pop_3_8 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_3_9 }; + assign \$161 = { 1'h0, pop_3_10 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_3_11 }; + assign \$164 = { 1'h0, pop_3_12 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_3_13 }; + assign \$167 = { 1'h0, pop_3_14 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_3_15 }; + assign \$170 = { 1'h0, pop_4_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_4_1 }; + assign \$173 = { 1'h0, pop_4_2 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_4_3 }; + assign \$176 = { 1'h0, pop_4_4 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_4_5 }; + assign \$17 = { 1'h0, a[10] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[11] }; + assign \$179 = { 1'h0, pop_4_6 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_4_7 }; + assign \$182 = { 1'h0, pop_5_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_5_1 }; + assign \$185 = { 1'h0, pop_5_2 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_5_3 }; + assign \$188 = { 1'h0, pop_6_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_6_1 }; + assign \$190 = data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" *) 1'h1; + assign \$192 = data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" *) 3'h4; + assign \$194 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_0; + assign \$196 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_1; + assign \$198 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_2; + assign \$200 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_3; + assign \$202 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_4; + assign \$204 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_5; + assign \$206 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_6; + assign \$208 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_7; + assign \$20 = { 1'h0, a[12] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[13] }; + assign \$210 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_6_0; + assign \$212 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_6_1; + assign \$214 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_7_0; + assign \$23 = { 1'h0, a[14] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[15] }; + assign \$26 = { 1'h0, a[16] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[17] }; + assign \$2 = { 1'h0, a[0] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[1] }; + assign \$29 = { 1'h0, a[18] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[19] }; + assign \$32 = { 1'h0, a[20] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[21] }; + assign \$35 = { 1'h0, a[22] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[23] }; + assign \$38 = { 1'h0, a[24] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[25] }; + assign \$41 = { 1'h0, a[26] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[27] }; + assign \$44 = { 1'h0, a[28] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[29] }; + assign \$47 = { 1'h0, a[30] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[31] }; + assign \$50 = { 1'h0, a[32] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[33] }; + assign \$53 = { 1'h0, a[34] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[35] }; + assign \$56 = { 1'h0, a[36] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[37] }; + assign \$5 = { 1'h0, a[2] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[3] }; + assign \$59 = { 1'h0, a[38] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[39] }; + assign \$62 = { 1'h0, a[40] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[41] }; + assign \$65 = { 1'h0, a[42] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[43] }; + assign \$68 = { 1'h0, a[44] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[45] }; + assign \$71 = { 1'h0, a[46] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[47] }; + assign \$74 = { 1'h0, a[48] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[49] }; + assign \$77 = { 1'h0, a[50] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[51] }; + assign \$80 = { 1'h0, a[52] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[53] }; + assign \$83 = { 1'h0, a[54] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[55] }; + assign \$86 = { 1'h0, a[56] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[57] }; + assign \$8 = { 1'h0, a[4] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[5] }; + assign \$89 = { 1'h0, a[58] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[59] }; + assign \$92 = { 1'h0, a[60] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[61] }; + assign \$95 = { 1'h0, a[62] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, a[63] }; + assign \$98 = { 1'h0, pop_2_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_1 }; + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" *) + casez ({ \$192 , \$190 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" */ + 2'b?1: + begin + o[7:0] = \$194 ; + o[15:8] = \$196 ; + o[23:16] = \$198 ; + o[31:24] = \$200 ; + o[39:32] = \$202 ; + o[47:40] = \$204 ; + o[55:48] = \$206 ; + o[63:56] = \$208 ; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" */ + 2'b1?: + begin + o[31:0] = \$210 ; + o[63:32] = \$212 ; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:63" */ + default: + o = \$214 ; + endcase + end + assign \$1 = \$2 ; + assign \$4 = \$5 ; + assign \$7 = \$8 ; + assign \$10 = \$11 ; + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign \$22 = \$23 ; + assign \$25 = \$26 ; + assign \$28 = \$29 ; + assign \$31 = \$32 ; + assign \$34 = \$35 ; + assign \$37 = \$38 ; + assign \$40 = \$41 ; + assign \$43 = \$44 ; + assign \$46 = \$47 ; + assign \$49 = \$50 ; + assign \$52 = \$53 ; + assign \$55 = \$56 ; + assign \$58 = \$59 ; + assign \$61 = \$62 ; + assign \$64 = \$65 ; + assign \$67 = \$68 ; + assign \$70 = \$71 ; + assign \$73 = \$74 ; + assign \$76 = \$77 ; + assign \$79 = \$80 ; + assign \$82 = \$83 ; + assign \$85 = \$86 ; + assign \$88 = \$89 ; + assign \$91 = \$92 ; + assign \$94 = \$95 ; + assign \$97 = \$98 ; + assign \$100 = \$101 ; + assign \$103 = \$104 ; + assign \$106 = \$107 ; + assign \$109 = \$110 ; + assign \$112 = \$113 ; + assign \$115 = \$116 ; + assign \$118 = \$119 ; + assign \$121 = \$122 ; + assign \$124 = \$125 ; + assign \$127 = \$128 ; + assign \$130 = \$131 ; + assign \$133 = \$134 ; + assign \$136 = \$137 ; + assign \$139 = \$140 ; + assign \$142 = \$143 ; + assign \$145 = \$146 ; + assign \$148 = \$149 ; + assign \$151 = \$152 ; + assign \$154 = \$155 ; + assign \$157 = \$158 ; + assign \$160 = \$161 ; + assign \$163 = \$164 ; + assign \$166 = \$167 ; + assign \$169 = \$170 ; + assign \$172 = \$173 ; + assign \$175 = \$176 ; + assign \$178 = \$179 ; + assign \$181 = \$182 ; + assign \$184 = \$185 ; + assign \$187 = \$188 ; + assign pop_7_0 = \$188 [6:0]; + assign pop_6_1 = \$185 [5:0]; + assign pop_6_0 = \$182 [5:0]; + assign pop_5_3 = \$179 [4:0]; + assign pop_5_2 = \$176 [4:0]; + assign pop_5_1 = \$173 [4:0]; + assign pop_5_0 = \$170 [4:0]; + assign pop_4_7 = \$167 [3:0]; + assign pop_4_6 = \$164 [3:0]; + assign pop_4_5 = \$161 [3:0]; + assign pop_4_4 = \$158 [3:0]; + assign pop_4_3 = \$155 [3:0]; + assign pop_4_2 = \$152 [3:0]; + assign pop_4_1 = \$149 [3:0]; + assign pop_4_0 = \$146 [3:0]; + assign pop_3_15 = \$143 [2:0]; + assign pop_3_14 = \$140 [2:0]; + assign pop_3_13 = \$137 [2:0]; + assign pop_3_12 = \$134 [2:0]; + assign pop_3_11 = \$131 [2:0]; + assign pop_3_10 = \$128 [2:0]; + assign pop_3_9 = \$125 [2:0]; + assign pop_3_8 = \$122 [2:0]; + assign pop_3_7 = \$119 [2:0]; + assign pop_3_6 = \$116 [2:0]; + assign pop_3_5 = \$113 [2:0]; + assign pop_3_4 = \$110 [2:0]; + assign pop_3_3 = \$107 [2:0]; + assign pop_3_2 = \$104 [2:0]; + assign pop_3_1 = \$101 [2:0]; + assign pop_3_0 = \$98 [2:0]; + assign pop_2_31 = \$95 [1:0]; + assign pop_2_30 = \$92 [1:0]; + assign pop_2_29 = \$89 [1:0]; + assign pop_2_28 = \$86 [1:0]; + assign pop_2_27 = \$83 [1:0]; + assign pop_2_26 = \$80 [1:0]; + assign pop_2_25 = \$77 [1:0]; + assign pop_2_24 = \$74 [1:0]; + assign pop_2_23 = \$71 [1:0]; + assign pop_2_22 = \$68 [1:0]; + assign pop_2_21 = \$65 [1:0]; + assign pop_2_20 = \$62 [1:0]; + assign pop_2_19 = \$59 [1:0]; + assign pop_2_18 = \$56 [1:0]; + assign pop_2_17 = \$53 [1:0]; + assign pop_2_16 = \$50 [1:0]; + assign pop_2_15 = \$47 [1:0]; + assign pop_2_14 = \$44 [1:0]; + assign pop_2_13 = \$41 [1:0]; + assign pop_2_12 = \$38 [1:0]; + assign pop_2_11 = \$35 [1:0]; + assign pop_2_10 = \$32 [1:0]; + assign pop_2_9 = \$29 [1:0]; + assign pop_2_8 = \$26 [1:0]; + assign pop_2_7 = \$23 [1:0]; + assign pop_2_6 = \$20 [1:0]; + assign pop_2_5 = \$17 [1:0]; + assign pop_2_4 = \$14 [1:0]; + assign pop_2_3 = \$11 [1:0]; + assign pop_2_2 = \$8 [1:0]; + assign pop_2_1 = \$5 [1:0]; + assign pop_2_0 = \$2 [1:0]; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_cr_in.ppick" *) +(* generator = "nMigen" *) +module ppick(o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [7:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [7:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [7:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [7:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t5; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t7; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[5], i[6], i[7], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4], i[5], i[6], i[7], ni[4] }; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) { i[0], i[1], i[2], i[3], i[4], i[5], i[6], i[7] }; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3], i[4], i[5], i[6], i[7], ni[5] }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ; + assign \$24 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2], i[3], i[4], i[5], i[6], i[7], ni[6] }; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$24 ; + assign \$28 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1], i[2], i[3], i[4], i[5], i[6], i[7], ni[7] }; + assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$28 ; + assign \$31 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[7], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[6], i[7], ni[2] }; + assign en_o = \$31 ; + assign o = { t0, t1, t2, t3, t4, t5, t6, t7 }; + assign t7 = \$27 ; + assign t6 = \$23 ; + assign t5 = \$19 ; + assign t4 = \$15 ; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[7]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_cr_out.ppick" *) +(* generator = "nMigen" *) +module \ppick$175 (en_o, o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [7:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [7:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [7:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [7:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t5; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t7; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[5], i[6], i[7], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4], i[5], i[6], i[7], ni[4] }; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) { i[0], i[1], i[2], i[3], i[4], i[5], i[6], i[7] }; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3], i[4], i[5], i[6], i[7], ni[5] }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ; + assign \$24 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2], i[3], i[4], i[5], i[6], i[7], ni[6] }; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$24 ; + assign \$28 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1], i[2], i[3], i[4], i[5], i[6], i[7], ni[7] }; + assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$28 ; + assign \$31 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[7], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[6], i[7], ni[2] }; + assign en_o = \$31 ; + assign o = { t0, t1, t2, t3, t4, t5, t6, t7 }; + assign t7 = \$27 ; + assign t6 = \$23 ; + assign t5 = \$19 ; + assign t4 = \$15 ; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[7]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_CR_cr_a" *) +(* generator = "nMigen" *) +module rdpick_CR_cr_a(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [1:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [1:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [1:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [1:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$7 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$7 ; + assign o = { t1, t0 }; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_CR_cr_b" *) +(* generator = "nMigen" *) +module rdpick_CR_cr_b(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_CR_cr_c" *) +(* generator = "nMigen" *) +module rdpick_CR_cr_c(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_CR_full_cr" *) +(* generator = "nMigen" *) +module rdpick_CR_full_cr(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_FAST_fast1" *) +(* generator = "nMigen" *) +module rdpick_FAST_fast1(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [4:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [4:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [4:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [4:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t4; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] }; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$19 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$19 ; + assign o = { t4, t3, t2, t1, t0 }; + assign t4 = \$15 ; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_INT_rabc" *) +(* generator = "nMigen" *) +module rdpick_INT_rabc(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [18:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$60 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$64 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$68 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$72 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [18:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [18:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [18:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t10; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t11; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t12; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t13; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t14; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t15; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t16; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t17; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t18; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t5; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t8; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t9; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] }; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ; + assign \$24 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[5:0], ni[6] }; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$24 ; + assign \$28 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[6:0], ni[7] }; + assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$28 ; + assign \$32 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[7:0], ni[8] }; + assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$32 ; + assign \$36 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[8:0], ni[9] }; + assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$36 ; + assign \$40 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[9:0], ni[10] }; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$40 ; + assign \$44 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[10:0], ni[11] }; + assign \$43 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$44 ; + assign \$48 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[11:0], ni[12] }; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$48 ; + assign \$52 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[12:0], ni[13] }; + assign \$51 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$52 ; + assign \$56 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[13:0], ni[14] }; + assign \$55 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$56 ; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$60 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[14:0], ni[15] }; + assign \$59 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$60 ; + assign \$64 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[15:0], ni[16] }; + assign \$63 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$64 ; + assign \$68 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[16:0], ni[17] }; + assign \$67 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$68 ; + assign \$72 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[17:0], ni[18] }; + assign \$71 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$72 ; + assign \$75 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$75 ; + assign o = { t18, t17, t16, t15, t14, t13, t12, t11, t10, t9, t8, t7, t6, t5, t4, t3, t2, t1, t0 }; + assign t18 = \$71 ; + assign t17 = \$67 ; + assign t16 = \$63 ; + assign t15 = \$59 ; + assign t14 = \$55 ; + assign t13 = \$51 ; + assign t12 = \$47 ; + assign t11 = \$43 ; + assign t10 = \$39 ; + assign t9 = \$35 ; + assign t8 = \$31 ; + assign t7 = \$27 ; + assign t6 = \$23 ; + assign t5 = \$19 ; + assign t4 = \$15 ; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_SPR_spr1" *) +(* generator = "nMigen" *) +module rdpick_SPR_spr1(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_XER_xer_ca" *) +(* generator = "nMigen" *) +module rdpick_XER_xer_ca(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [2:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [2:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [2:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$11 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$11 ; + assign o = { t2, t1, t0 }; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_XER_xer_ov" *) +(* generator = "nMigen" *) +module rdpick_XER_xer_ov(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.rdpick_XER_xer_so" *) +(* generator = "nMigen" *) +module rdpick_XER_xer_so(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [5:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [5:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [5:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [5:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t5; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] }; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ; + assign \$23 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$23 ; + assign o = { t5, t4, t3, t2, t1, t0 }; + assign t5 = \$19 ; + assign t4 = \$15 ; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr.reg_0" *) +(* generator = "nMigen" *) +module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, src30__ren, src30__data_o, dest10__wen, dest10__data_i, dest20__wen, dest20__data_i, r0__data_o, r0__ren, r20__data_o, r20__ren, w0__data_i, w0__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest10__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest10__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest20__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest20__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r0__data_o; + reg [3:0] r0__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r0__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r0__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r20__data_o; + reg [3:0] r20__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r20__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r20__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src10__data_o; + reg [3:0] src10__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src10__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src10__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src20__data_o; + reg [3:0] src20__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src20__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src20__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src30__data_o; + reg [3:0] src30__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src30__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src30__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] w0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w0__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r20__data_o <= \r20__data_o$next ; + always @(posedge coresync_clk) + r0__data_o <= \r0__data_o$next ; + always @(posedge coresync_clk) + src30__data_o <= \src30__data_o$next ; + always @(posedge coresync_clk) + src20__data_o <= \src20__data_o$next ; + always @(posedge coresync_clk) + src10__data_o <= \src10__data_o$next ; + always @* begin + if (\initial ) begin end + \src10__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src10__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src10__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src10__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src10__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src10__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src10__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src10__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src20__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src20__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src20__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src20__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src20__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src20__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src20__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src20__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src30__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src30__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src30__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src30__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src30__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src30__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src30__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src30__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r0__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r0__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r0__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r0__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r0__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r0__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r20__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r20__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r20__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r20__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r20__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r20__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r20__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r20__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.xer.reg_0" *) +(* generator = "nMigen" *) +module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, src30__ren, src30__data_o, dest10__wen, dest10__data_i, dest20__wen, dest20__data_i, dest30__wen, dest30__data_i, r0__data_o, r0__ren, w0__data_i, w0__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest10__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest10__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest20__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest20__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest30__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest30__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] r0__data_o; + reg [1:0] r0__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \r0__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r0__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [1:0] \reg = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [1:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src10__data_o; + reg [1:0] src10__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src10__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src10__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src20__data_o; + reg [1:0] src20__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src20__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src20__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src30__data_o; + reg [1:0] src30__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src30__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src30__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] w0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w0__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r0__data_o <= \r0__data_o$next ; + always @(posedge coresync_clk) + src30__data_o <= \src30__data_o$next ; + always @(posedge coresync_clk) + src20__data_o <= \src20__data_o$next ; + always @(posedge coresync_clk) + src10__data_o <= \src10__data_o$next ; + always @* begin + if (\initial ) begin end + \src10__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src10__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src10__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src10__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src10__data_o$next = dest30__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src10__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src10__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src10__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src10__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src20__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src20__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src20__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src20__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src20__data_o$next = dest30__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src20__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src20__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src20__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src20__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src30__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src30__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src30__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src30__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src30__data_o$next = dest30__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src30__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src30__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src30__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src30__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r0__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r0__data_o$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r0__data_o$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r0__data_o$next = dest30__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r0__data_o$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r0__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r0__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest20__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest20__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest30__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest30__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 2'h0; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.state.reg_0" *) +(* generator = "nMigen" *) +module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_o, sv0__ren, sv0__data_o, nia0__wen, nia0__data_i, msr0__wen, msr0__data_i, sv0__wen, sv0__data_i, d_wr10__wen, d_wr10__data_i, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] cia0__data_o; + reg [63:0] cia0__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \cia0__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input cia0__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] d_wr10__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input d_wr10__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] msr0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] msr0__data_o; + reg [63:0] msr0__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \msr0__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input msr0__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input msr0__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] nia0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input nia0__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [63:0] \reg = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [63:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] sv0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] sv0__data_o; + reg [63:0] sv0__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \sv0__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input sv0__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input sv0__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + sv0__data_o <= \sv0__data_o$next ; + always @(posedge coresync_clk) + msr0__data_o <= \msr0__data_o$next ; + always @(posedge coresync_clk) + cia0__data_o <= \cia0__data_o$next ; + always @* begin + if (\initial ) begin end + \cia0__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (cia0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia0__data_o$next = nia0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia0__data_o$next = msr0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia0__data_o$next = sv0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia0__data_o$next = d_wr10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \cia0__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cia0__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (cia0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \msr0__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (msr0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr0__data_o$next = nia0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr0__data_o$next = msr0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr0__data_o$next = sv0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr0__data_o$next = d_wr10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \msr0__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \msr0__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (msr0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \sv0__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (sv0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv0__data_o$next = nia0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv0__data_o$next = msr0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv0__data_o$next = sv0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv0__data_o$next = d_wr10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \sv0__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \sv0__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (sv0__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (nia0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = nia0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (msr0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = msr0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (sv0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = sv0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (d_wr10__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = d_wr10__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 64'h0000000000000000; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr.reg_1" *) +(* generator = "nMigen" *) +module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, src31__ren, src31__data_o, dest11__wen, dest11__data_i, dest21__wen, dest21__data_i, r1__data_o, r1__ren, r21__data_o, r21__ren, w1__data_i, w1__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest11__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest11__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest21__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest21__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r1__data_o; + reg [3:0] r1__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r1__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r21__data_o; + reg [3:0] r21__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r21__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r21__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src11__data_o; + reg [3:0] src11__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src11__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src11__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src21__data_o; + reg [3:0] src21__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src21__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src21__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src31__data_o; + reg [3:0] src31__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src31__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src31__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] w1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w1__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r21__data_o <= \r21__data_o$next ; + always @(posedge coresync_clk) + r1__data_o <= \r1__data_o$next ; + always @(posedge coresync_clk) + src31__data_o <= \src31__data_o$next ; + always @(posedge coresync_clk) + src21__data_o <= \src21__data_o$next ; + always @(posedge coresync_clk) + src11__data_o <= \src11__data_o$next ; + always @* begin + if (\initial ) begin end + \src11__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src11__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src11__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src11__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src11__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src11__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src11__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src11__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src21__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src21__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src21__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src21__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src21__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src21__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src21__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src21__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src31__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src31__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src31__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src31__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src31__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src31__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src31__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src31__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r1__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r1__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r1__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r1__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r1__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r1__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r21__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r21__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r21__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r21__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r21__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r21__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r21__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r21__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.xer.reg_1" *) +(* generator = "nMigen" *) +module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, src31__ren, src31__data_o, dest11__wen, dest11__data_i, dest21__wen, dest21__data_i, dest31__wen, dest31__data_i, r1__data_o, r1__ren, w1__data_i, w1__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest11__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest11__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest21__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest21__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest31__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest31__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] r1__data_o; + reg [1:0] r1__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \r1__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r1__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [1:0] \reg = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [1:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src11__data_o; + reg [1:0] src11__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src11__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src11__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src21__data_o; + reg [1:0] src21__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src21__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src21__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src31__data_o; + reg [1:0] src31__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src31__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src31__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] w1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w1__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r1__data_o <= \r1__data_o$next ; + always @(posedge coresync_clk) + src31__data_o <= \src31__data_o$next ; + always @(posedge coresync_clk) + src21__data_o <= \src21__data_o$next ; + always @(posedge coresync_clk) + src11__data_o <= \src11__data_o$next ; + always @* begin + if (\initial ) begin end + \src11__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src11__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src11__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src11__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src11__data_o$next = dest31__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src11__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src11__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src11__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src11__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src21__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src21__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src21__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src21__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src21__data_o$next = dest31__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src21__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src21__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src21__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src21__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src31__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src31__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src31__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src31__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src31__data_o$next = dest31__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src31__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src31__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src31__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src31__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r1__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r1__data_o$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r1__data_o$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r1__data_o$next = dest31__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r1__data_o$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r1__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r1__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest21__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest21__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest31__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest31__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 2'h0; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.state.reg_1" *) +(* generator = "nMigen" *) +module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_o, sv1__ren, sv1__data_o, nia1__wen, nia1__data_i, msr1__wen, msr1__data_i, sv1__wen, sv1__data_i, d_wr11__wen, d_wr11__data_i, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] cia1__data_o; + reg [63:0] cia1__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \cia1__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input cia1__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] d_wr11__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input d_wr11__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] msr1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] msr1__data_o; + reg [63:0] msr1__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \msr1__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input msr1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input msr1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] nia1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input nia1__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [63:0] \reg = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [63:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] sv1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] sv1__data_o; + reg [63:0] sv1__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \sv1__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input sv1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input sv1__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + sv1__data_o <= \sv1__data_o$next ; + always @(posedge coresync_clk) + msr1__data_o <= \msr1__data_o$next ; + always @(posedge coresync_clk) + cia1__data_o <= \cia1__data_o$next ; + always @* begin + if (\initial ) begin end + \cia1__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (cia1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia1__data_o$next = nia1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia1__data_o$next = msr1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia1__data_o$next = sv1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia1__data_o$next = d_wr11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \cia1__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cia1__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (cia1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \msr1__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (msr1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr1__data_o$next = nia1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr1__data_o$next = msr1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr1__data_o$next = sv1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr1__data_o$next = d_wr11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \msr1__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \msr1__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (msr1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \sv1__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (sv1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv1__data_o$next = nia1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv1__data_o$next = msr1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv1__data_o$next = sv1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv1__data_o$next = d_wr11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \sv1__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \sv1__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (sv1__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (nia1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = nia1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (msr1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = msr1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (sv1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = sv1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (d_wr11__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = d_wr11__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 64'h0000000000000000; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr.reg_2" *) +(* generator = "nMigen" *) +module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, src32__ren, src32__data_o, dest12__wen, dest12__data_i, dest22__wen, dest22__data_i, r2__data_o, r2__ren, r22__data_o, r22__ren, w2__data_i, w2__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest12__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest12__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest22__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest22__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r22__data_o; + reg [3:0] r22__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r22__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r22__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r2__data_o; + reg [3:0] r2__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r2__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r2__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src12__data_o; + reg [3:0] src12__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src12__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src12__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src22__data_o; + reg [3:0] src22__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src22__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src22__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src32__data_o; + reg [3:0] src32__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src32__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src32__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] w2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w2__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r22__data_o <= \r22__data_o$next ; + always @(posedge coresync_clk) + r2__data_o <= \r2__data_o$next ; + always @(posedge coresync_clk) + src32__data_o <= \src32__data_o$next ; + always @(posedge coresync_clk) + src22__data_o <= \src22__data_o$next ; + always @(posedge coresync_clk) + src12__data_o <= \src12__data_o$next ; + always @* begin + if (\initial ) begin end + \src12__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src12__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src12__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src12__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src12__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src12__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src12__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src12__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src22__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src22__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src22__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src22__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src22__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src22__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src22__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src22__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src32__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src32__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src32__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src32__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src32__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src32__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src32__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src32__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r2__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r2__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r2__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r2__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r2__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r2__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r22__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r22__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r22__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r22__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r22__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r22__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r22__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r22__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.xer.reg_2" *) +(* generator = "nMigen" *) +module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, src32__ren, src32__data_o, dest12__wen, dest12__data_i, dest22__wen, dest22__data_i, dest32__wen, dest32__data_i, r2__data_o, r2__ren, w2__data_i, w2__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest12__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest12__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest22__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest22__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] dest32__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest32__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] r2__data_o; + reg [1:0] r2__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \r2__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r2__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [1:0] \reg = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [1:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src12__data_o; + reg [1:0] src12__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src12__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src12__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src22__data_o; + reg [1:0] src22__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src22__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src22__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src32__data_o; + reg [1:0] src32__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \src32__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src32__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] w2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w2__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r2__data_o <= \r2__data_o$next ; + always @(posedge coresync_clk) + src32__data_o <= \src32__data_o$next ; + always @(posedge coresync_clk) + src22__data_o <= \src22__data_o$next ; + always @(posedge coresync_clk) + src12__data_o <= \src12__data_o$next ; + always @* begin + if (\initial ) begin end + \src12__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src12__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src12__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src12__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src12__data_o$next = dest32__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src12__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src12__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src12__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src12__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src22__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src22__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src22__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src22__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src22__data_o$next = dest32__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src22__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src22__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src22__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src22__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src32__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src32__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src32__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src32__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src32__data_o$next = dest32__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src32__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src32__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src32__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src32__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r2__data_o$next = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r2__data_o$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r2__data_o$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r2__data_o$next = dest32__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r2__data_o$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r2__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r2__data_o$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest22__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest22__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest32__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest32__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 2'h0; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.state.reg_2" *) +(* generator = "nMigen" *) +module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_o, sv2__ren, sv2__data_o, nia2__wen, nia2__data_i, msr2__wen, msr2__data_i, sv2__wen, sv2__data_i, d_wr12__wen, d_wr12__data_i, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] cia2__data_o; + reg [63:0] cia2__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \cia2__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input cia2__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] d_wr12__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input d_wr12__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] msr2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] msr2__data_o; + reg [63:0] msr2__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \msr2__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input msr2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input msr2__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] nia2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input nia2__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [63:0] \reg = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [63:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] sv2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] sv2__data_o; + reg [63:0] sv2__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \sv2__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input sv2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input sv2__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + sv2__data_o <= \sv2__data_o$next ; + always @(posedge coresync_clk) + msr2__data_o <= \msr2__data_o$next ; + always @(posedge coresync_clk) + cia2__data_o <= \cia2__data_o$next ; + always @* begin + if (\initial ) begin end + \cia2__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (cia2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia2__data_o$next = nia2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia2__data_o$next = msr2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia2__data_o$next = sv2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia2__data_o$next = d_wr12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \cia2__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \cia2__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (cia2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \msr2__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (msr2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr2__data_o$next = nia2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr2__data_o$next = msr2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr2__data_o$next = sv2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr2__data_o$next = d_wr12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \msr2__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \msr2__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (msr2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \sv2__data_o$next = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (sv2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv2__data_o$next = nia2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv2__data_o$next = msr2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv2__data_o$next = sv2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv2__data_o$next = d_wr12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \sv2__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \sv2__data_o$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (sv2__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (nia2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (msr2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (sv2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (d_wr12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (nia2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = nia2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (msr2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = msr2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (sv2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = sv2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (d_wr12__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = d_wr12__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 64'h0000000000000000; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr.reg_3" *) +(* generator = "nMigen" *) +module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, src33__ren, src33__data_o, dest13__wen, dest13__data_i, dest23__wen, dest23__data_i, r3__data_o, r3__ren, r23__data_o, r23__ren, w3__data_i, w3__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest13__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest13__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest23__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest23__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r23__data_o; + reg [3:0] r23__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r23__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r23__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r3__data_o; + reg [3:0] r3__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r3__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r3__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src13__data_o; + reg [3:0] src13__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src13__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src13__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src23__data_o; + reg [3:0] src23__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src23__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src23__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src33__data_o; + reg [3:0] src33__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src33__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src33__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] w3__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w3__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r23__data_o <= \r23__data_o$next ; + always @(posedge coresync_clk) + r3__data_o <= \r3__data_o$next ; + always @(posedge coresync_clk) + src33__data_o <= \src33__data_o$next ; + always @(posedge coresync_clk) + src23__data_o <= \src23__data_o$next ; + always @(posedge coresync_clk) + src13__data_o <= \src13__data_o$next ; + always @* begin + if (\initial ) begin end + \src13__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src13__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src13__data_o$next = dest13__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src13__data_o$next = dest23__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src13__data_o$next = w3__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src13__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src13__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src13__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest13__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest23__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w3__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src23__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src23__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src23__data_o$next = dest13__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src23__data_o$next = dest23__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src23__data_o$next = w3__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src23__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src23__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src23__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src33__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src33__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src33__data_o$next = dest13__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src33__data_o$next = dest23__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src33__data_o$next = w3__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src33__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src33__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src33__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r3__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r3__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r3__data_o$next = dest13__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r3__data_o$next = dest23__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r3__data_o$next = w3__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r3__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r3__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r3__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r23__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r23__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r23__data_o$next = dest13__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r23__data_o$next = dest23__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r23__data_o$next = w3__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r23__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r23__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r23__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest13__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest23__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w3__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr.reg_4" *) +(* generator = "nMigen" *) +module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, src34__ren, src34__data_o, dest14__wen, dest14__data_i, dest24__wen, dest24__data_i, r4__data_o, r4__ren, r24__data_o, r24__ren, w4__data_i, w4__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest14__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest14__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest24__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest24__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r24__data_o; + reg [3:0] r24__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r24__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r24__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r4__data_o; + reg [3:0] r4__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r4__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r4__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src14__data_o; + reg [3:0] src14__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src14__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src14__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src24__data_o; + reg [3:0] src24__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src24__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src24__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src34__data_o; + reg [3:0] src34__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src34__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src34__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] w4__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w4__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r24__data_o <= \r24__data_o$next ; + always @(posedge coresync_clk) + r4__data_o <= \r4__data_o$next ; + always @(posedge coresync_clk) + src34__data_o <= \src34__data_o$next ; + always @(posedge coresync_clk) + src24__data_o <= \src24__data_o$next ; + always @(posedge coresync_clk) + src14__data_o <= \src14__data_o$next ; + always @* begin + if (\initial ) begin end + \src14__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src14__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src14__data_o$next = dest14__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src14__data_o$next = dest24__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src14__data_o$next = w4__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src14__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src14__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src14__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest14__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest24__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w4__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src24__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src24__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src24__data_o$next = dest14__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src24__data_o$next = dest24__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src24__data_o$next = w4__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src24__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src24__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src24__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src34__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src34__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src34__data_o$next = dest14__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src34__data_o$next = dest24__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src34__data_o$next = w4__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src34__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src34__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src34__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r4__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r4__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r4__data_o$next = dest14__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r4__data_o$next = dest24__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r4__data_o$next = w4__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r4__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r4__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r4__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r24__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r24__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r24__data_o$next = dest14__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r24__data_o$next = dest24__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r24__data_o$next = w4__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r24__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r24__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r24__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest14__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest24__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w4__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr.reg_5" *) +(* generator = "nMigen" *) +module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, src35__ren, src35__data_o, dest15__wen, dest15__data_i, dest25__wen, dest25__data_i, r5__data_o, r5__ren, r25__data_o, r25__ren, w5__data_i, w5__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest15__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest15__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest25__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest25__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r25__data_o; + reg [3:0] r25__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r25__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r25__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r5__data_o; + reg [3:0] r5__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r5__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r5__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src15__data_o; + reg [3:0] src15__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src15__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src15__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src25__data_o; + reg [3:0] src25__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src25__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src25__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src35__data_o; + reg [3:0] src35__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src35__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src35__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] w5__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w5__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r25__data_o <= \r25__data_o$next ; + always @(posedge coresync_clk) + r5__data_o <= \r5__data_o$next ; + always @(posedge coresync_clk) + src35__data_o <= \src35__data_o$next ; + always @(posedge coresync_clk) + src25__data_o <= \src25__data_o$next ; + always @(posedge coresync_clk) + src15__data_o <= \src15__data_o$next ; + always @* begin + if (\initial ) begin end + \src15__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src15__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src15__data_o$next = dest15__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src15__data_o$next = dest25__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src15__data_o$next = w5__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src15__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src15__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src15__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest15__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest25__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w5__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src25__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src25__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src25__data_o$next = dest15__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src25__data_o$next = dest25__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src25__data_o$next = w5__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src25__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src25__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src25__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src35__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src35__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src35__data_o$next = dest15__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src35__data_o$next = dest25__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src35__data_o$next = w5__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src35__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src35__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src35__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r5__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r5__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r5__data_o$next = dest15__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r5__data_o$next = dest25__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r5__data_o$next = w5__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r5__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r5__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r5__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r25__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r25__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r25__data_o$next = dest15__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r25__data_o$next = dest25__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r25__data_o$next = w5__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r25__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r25__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r25__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest15__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest25__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w5__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr.reg_6" *) +(* generator = "nMigen" *) +module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, src36__ren, src36__data_o, dest16__wen, dest16__data_i, dest26__wen, dest26__data_i, r6__data_o, r6__ren, r26__data_o, r26__ren, w6__data_i, w6__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest16__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest16__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest26__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest26__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r26__data_o; + reg [3:0] r26__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r26__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r26__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r6__data_o; + reg [3:0] r6__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r6__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r6__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src16__data_o; + reg [3:0] src16__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src16__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src16__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src26__data_o; + reg [3:0] src26__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src26__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src26__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src36__data_o; + reg [3:0] src36__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src36__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src36__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] w6__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w6__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r26__data_o <= \r26__data_o$next ; + always @(posedge coresync_clk) + r6__data_o <= \r6__data_o$next ; + always @(posedge coresync_clk) + src36__data_o <= \src36__data_o$next ; + always @(posedge coresync_clk) + src26__data_o <= \src26__data_o$next ; + always @(posedge coresync_clk) + src16__data_o <= \src16__data_o$next ; + always @* begin + if (\initial ) begin end + \src16__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src16__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src16__data_o$next = dest16__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src16__data_o$next = dest26__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src16__data_o$next = w6__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src16__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src16__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src16__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest16__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest26__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w6__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src26__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src26__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src26__data_o$next = dest16__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src26__data_o$next = dest26__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src26__data_o$next = w6__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src26__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src26__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src26__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src36__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src36__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src36__data_o$next = dest16__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src36__data_o$next = dest26__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src36__data_o$next = w6__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src36__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src36__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src36__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r6__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r6__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r6__data_o$next = dest16__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r6__data_o$next = dest26__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r6__data_o$next = w6__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r6__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r6__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r6__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r26__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r26__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r26__data_o$next = dest16__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r26__data_o$next = dest26__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r26__data_o$next = w6__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r26__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r26__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r26__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest16__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest26__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w6__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.cr.reg_7" *) +(* generator = "nMigen" *) +module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, src37__ren, src37__data_o, dest17__wen, dest17__data_i, dest27__wen, dest27__data_i, r7__data_o, r7__ren, r27__data_o, r27__ren, w7__data_i, w7__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest17__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest17__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] dest27__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input dest27__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r27__data_o; + reg [3:0] r27__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r27__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r27__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] r7__data_o; + reg [3:0] r7__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \r7__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input r7__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *) + reg [3:0] \reg$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src17__data_o; + reg [3:0] src17__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src17__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src17__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src27__data_o; + reg [3:0] src27__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src27__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src27__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [3:0] src37__data_o; + reg [3:0] src37__data_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [3:0] \src37__data_o$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input src37__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] w7__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input w7__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg wr_detect; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) + reg \wr_detect$7 ; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ; + always @(posedge coresync_clk) + \reg <= \reg$next ; + always @(posedge coresync_clk) + r27__data_o <= \r27__data_o$next ; + always @(posedge coresync_clk) + r7__data_o <= \r7__data_o$next ; + always @(posedge coresync_clk) + src37__data_o <= \src37__data_o$next ; + always @(posedge coresync_clk) + src27__data_o <= \src27__data_o$next ; + always @(posedge coresync_clk) + src17__data_o <= \src17__data_o$next ; + always @* begin + if (\initial ) begin end + \src17__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src17__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src17__data_o$next = dest17__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src17__data_o$next = dest27__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src17__data_o$next = w7__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src17__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src17__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src17__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + wr_detect = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \reg$next = \reg ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest17__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = dest27__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = w7__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \reg$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src27__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src27__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src27__data_o$next = dest17__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src27__data_o$next = dest27__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src27__data_o$next = w7__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src27__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src27__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src27__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \src37__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src37__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src37__data_o$next = dest17__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src37__data_o$next = dest27__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \src37__data_o$next = w7__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \src37__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src37__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (src37__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r7__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r7__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r7__data_o$next = dest17__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r7__data_o$next = dest27__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r7__data_o$next = w7__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r7__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r7__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r7__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$10 = 1'h1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + \r27__data_o$next = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r27__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r27__data_o$next = dest17__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r27__data_o$next = dest27__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \r27__data_o$next = w7__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" */ + 1'h1: + \r27__data_o$next = \reg ; + endcase + end + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \r27__data_o$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *) + casez (r27__ren) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" */ + 1'h1: + begin + \wr_detect$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest17__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (dest27__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (w7__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$13 = 1'h1; + endcase + end + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.req_l" *) +(* generator = "nMigen" *) +module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [4:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [4:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [4:0] q_int = 5'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [4:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [4:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [4:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [4:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [4:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [4:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 5'h00; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.req_l" *) +(* generator = "nMigen" *) +module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [3:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [3:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [3:0] q_int = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [3:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [3:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [3:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [3:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [3:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [3:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 4'h0; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.req_l" *) +(* generator = "nMigen" *) +module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] q_int = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [2:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [2:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [2:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [2:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [2:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 3'h0; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.req_l" *) +(* generator = "nMigen" *) +module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] q_int = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [2:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [2:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [2:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [2:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [2:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 3'h0; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.req_l" *) +(* generator = "nMigen" *) +module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] q_int = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [2:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [2:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [2:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [2:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [2:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 3'h0; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.req_l" *) +(* generator = "nMigen" *) +module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [4:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [4:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [4:0] q_int = 5'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [4:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [4:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [4:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [4:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [4:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [4:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 5'h00; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.req_l" *) +(* generator = "nMigen" *) +module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [1:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [1:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [1:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [1:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [1:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [1:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [1:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [1:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [1:0] q_int = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [1:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [1:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [1:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [1:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [1:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [1:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 2'h0; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.req_l" *) +(* generator = "nMigen" *) +module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [5:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [5:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [5:0] q_int = 6'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [5:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [5:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [5:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [5:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [5:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [5:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 6'h00; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.req_l" *) +(* generator = "nMigen" *) +module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [3:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [3:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [3:0] q_int = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [3:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [3:0] q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [3:0] qlq_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [3:0] qn_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [3:0] r_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [3:0] s_req; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; + assign \$15 = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 4'h0; + endcase + end + assign qlq_req = \$15 ; + assign qn_req = \$13 ; + assign q_req = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.reset_l" *) +(* generator = "nMigen" *) +module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_reset; + assign \$9 = q_reset | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_reset; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_reset; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_reset; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_reset = \$9 ; + assign qn_reset = \$7 ; + assign q_reset = q_int; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.l0.reset_l" *) +(* generator = "nMigen" *) +module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_reset; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_reset; + assign \$9 = q_reset | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_reset; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_reset; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_reset; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_reset = \$9 ; + assign qn_reset = \$7 ; + assign q_reset = q_int; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" *) +(* generator = "nMigen" *) +module right_mask(mask, shift); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$117 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$119 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$125 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$127 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$63 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$67 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$69 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" *) + output [63:0] mask; + reg [63:0] mask; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" *) + input [6:0] shift; + assign \$9 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h4; + assign \$99 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h31; + assign \$101 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h32; + assign \$103 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h33; + assign \$105 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h34; + assign \$107 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h35; + assign \$109 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h36; + assign \$111 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h37; + assign \$113 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h38; + assign \$115 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h39; + assign \$117 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3a; + assign \$11 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h5; + assign \$119 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3b; + assign \$121 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3c; + assign \$123 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3d; + assign \$125 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3e; + assign \$127 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3f; + assign \$13 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h6; + assign \$15 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h7; + assign \$17 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'h8; + assign \$1 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 1'h0; + assign \$19 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'h9; + assign \$21 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'ha; + assign \$23 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hb; + assign \$25 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hc; + assign \$27 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hd; + assign \$29 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'he; + assign \$31 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hf; + assign \$33 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h10; + assign \$35 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h11; + assign \$37 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h12; + assign \$3 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 1'h1; + assign \$39 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h13; + assign \$41 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h14; + assign \$43 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h15; + assign \$45 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h16; + assign \$47 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h17; + assign \$49 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h18; + assign \$51 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h19; + assign \$53 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1a; + assign \$55 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1b; + assign \$57 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1c; + assign \$5 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 2'h2; + assign \$59 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1d; + assign \$61 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1e; + assign \$63 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1f; + assign \$65 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h20; + assign \$67 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h21; + assign \$69 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h22; + assign \$71 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h23; + assign \$73 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h24; + assign \$75 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h25; + assign \$77 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h26; + assign \$7 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 2'h3; + assign \$79 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h27; + assign \$81 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h28; + assign \$83 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h29; + assign \$85 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2a; + assign \$87 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2b; + assign \$89 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2c; + assign \$91 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2d; + assign \$93 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2e; + assign \$95 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2f; + assign \$97 = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h30; + always @* begin + if (\initial ) begin end + mask = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$1 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[0] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$3 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[1] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$5 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[2] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$7 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[3] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[4] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$11 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[5] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[6] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[7] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$17 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[8] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[9] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$21 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[10] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$23 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[11] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[12] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[13] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[14] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[15] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$33 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[16] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$35 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[17] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$37 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[18] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$39 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[19] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$41 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[20] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$43 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[21] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$45 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[22] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$47 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[23] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$49 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[24] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$51 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[25] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$53 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[26] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$55 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[27] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$57 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[28] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$59 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[29] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$61 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[30] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$63 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[31] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$65 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[32] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$67 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[33] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$69 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[34] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$71 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[35] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$73 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[36] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$75 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[37] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$77 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[38] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$79 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[39] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$81 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[40] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$83 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[41] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$85 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[42] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$87 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[43] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$89 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[44] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$91 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[45] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$93 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[46] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$95 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[47] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$97 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[48] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$99 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[49] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$101 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[50] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$103 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[51] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$105 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[52] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$107 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[53] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$109 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[54] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$111 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[55] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$113 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[56] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$115 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[57] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$117 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[58] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$119 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[59] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$121 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[60] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$123 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[61] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$125 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[62] = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) + casez (\$127 ) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" */ + 1'h1: + mask[63] = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.rok_l" *) +(* generator = "nMigen" *) +module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.rok_l" *) +(* generator = "nMigen" *) +module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.rok_l" *) +(* generator = "nMigen" *) +module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.rok_l" *) +(* generator = "nMigen" *) +module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.rok_l" *) +(* generator = "nMigen" *) +module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.rok_l" *) +(* generator = "nMigen" *) +module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.rok_l" *) +(* generator = "nMigen" *) +module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.rok_l" *) +(* generator = "nMigen" *) +module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.rok_l" *) +(* generator = "nMigen" *) +module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rdok; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok; + assign \$15 = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rdok = \$15 ; + assign qn_rdok = \$13 ; + assign q_rdok = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" *) +(* generator = "nMigen" *) +module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_left, clear_right, sign_ext_rs, result_o, carry_out_o, me); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" *) + wire [6:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" *) + wire [6:0] \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" *) + wire [5:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" *) + wire [7:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" *) + wire [7:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" *) + wire [7:0] \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" *) + wire [7:0] \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" *) + wire [63:0] \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) + wire [63:0] \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) + wire [63:0] \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) + wire [63:0] \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) + wire [63:0] \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) + wire [63:0] \$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) + wire [63:0] \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) + wire [63:0] \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) + wire [63:0] \$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) + wire [63:0] \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) + wire [63:0] \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) + wire [63:0] \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) + wire [63:0] \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" *) + wire [63:0] \$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" *) + wire [63:0] \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" *) + wire [63:0] \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) + wire \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) + wire [63:0] \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) + wire [63:0] \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *) + wire [6:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" *) + input arith; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" *) + output carry_out_o; + reg carry_out_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" *) + input clear_left; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" *) + input clear_right; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" *) + reg [31:0] hi32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" *) + input is_32bit; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" *) + wire [63:0] left_mask_mask; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" *) + wire [6:0] left_mask_shift; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *) + input [4:0] mb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76" *) + reg [6:0] \mb$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" *) + input mb_extra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" *) + input [4:0] me; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77" *) + reg [6:0] \me$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79" *) + wire [63:0] ml; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78" *) + reg [63:0] mr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:80" *) + reg [1:0] output_mode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82" *) + wire [63:0] repl32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" *) + output [63:0] result_o; + reg [63:0] result_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" *) + wire [63:0] right_mask_mask; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" *) + reg [6:0] right_mask_shift; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" *) + input right_shift; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74" *) + wire [63:0] rot; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73" *) + reg [5:0] rot_count; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" *) + wire [63:0] rotl_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" *) + wire [5:0] rotl_b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" *) + wire [63:0] rotl_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" *) + input [63:0] rs; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75" *) + wire [6:0] sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" *) + input [6:0] shift; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:94" *) + wire [5:0] shift_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" *) + input sign_ext_rs; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *) mb; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" *) sh[5]; + assign \$14 = clear_right & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" *) is_32bit; + assign \$16 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" *) clear_left; + assign \$18 = clear_right & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" *) \$16 ; + assign \$20 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" *) sh[5:0]; + assign \$22 = \mb$8 <= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) 7'h40; + assign \$25 = 7'h40 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" *) \mb$8 ; + assign \$27 = \mb$8 <= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) 7'h40; + assign \$2 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" *) $signed(shift_signed); + assign \$30 = 6'h3f - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" *) \me$13 ; + assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" *) left_mask_mask; + assign \$34 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) clear_right; + assign \$36 = clear_left & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) \$34 ; + assign \$38 = \$36 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) right_shift; + assign \$40 = arith & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" *) repl32[63]; + assign \$42 = \mb$8 [5:0] > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" *) \me$13 [5:0]; + assign \$44 = clear_right & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" *) \$42 ; + assign \$46 = mr & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) ml; + assign \$48 = rot & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) \$46 ; + assign \$4 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" *) is_32bit; + assign \$51 = mr & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) ml; + assign \$50 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) \$51 ; + assign \$54 = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) \$50 ; + assign \$56 = \$48 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) \$54 ; + assign \$58 = mr | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) ml; + assign \$60 = rot & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) \$58 ; + assign \$63 = mr | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) ml; + assign \$62 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) \$63 ; + assign \$66 = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) \$62 ; + assign \$68 = \$60 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) \$66 ; + assign \$6 = shift[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" *) \$4 ; + assign \$70 = rot & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" *) mr; + assign \$72 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" *) mr; + assign \$74 = rot | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" *) \$72 ; + assign \$77 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) ml; + assign \$79 = rs & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) \$77 ; + assign \$76 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) \$79 ; + left_mask left_mask ( + .mask(left_mask_mask), + .shift(left_mask_shift) + ); + right_mask right_mask ( + .mask(right_mask_mask), + .shift(right_mask_shift) + ); + rotl rotl ( + .a(rotl_a), + .b(rotl_b), + .o(rotl_o) + ); + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" *) + casez ({ sign_ext_rs, is_32bit }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" */ + 2'b?1: + hi32 = rs[31:0]; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:87" */ + 2'b1?: + hi32 = { rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31] }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:90" */ + default: + hi32 = rs[63:32]; + endcase + end + always @* begin + if (\initial ) begin end + right_mask_shift = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) + casez (\$22 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" */ + 1'h1: + right_mask_shift = \$24 [6:0]; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" */ + 1'h1: + mr = right_mask_mask; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:146" */ + default: + mr = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) + casez (\$38 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" */ + 1'h1: + output_mode = { 1'h1, \$40 }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:163" */ + default: + output_mode = { 1'h0, \$44 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" *) + casez (output_mode) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:169" */ + 2'h0: + result_o = \$56 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:171" */ + 2'h1: + result_o = \$68 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:173" */ + 2'h2: + result_o = \$70 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:175" */ + 2'h3: + result_o = \$74 ; + endcase + end + always @* begin + if (\initial ) begin end + carry_out_o = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" *) + casez (output_mode) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:169" */ + 2'h0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:171" */ + 2'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:173" */ + 2'h2: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:175" */ + 2'h3: + carry_out_o = \$76 ; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" *) + casez (right_shift) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" */ + 1'h1: + rot_count = \$1 [5:0]; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:100" */ + default: + rot_count = shift[5:0]; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" *) + casez ({ right_shift, clear_left }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" */ + 2'b?1: + begin + \mb$8 = \$9 ; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" *) + casez (is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" */ + 1'h1: + \mb$8 [6:5] = 2'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:120" */ + default: + \mb$8 [6:5] = { 1'h0, mb_extra }; + endcase + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122" */ + 2'b1?: + begin + \mb$8 = sh; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" *) + casez (is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" */ + 1'h1: + \mb$8 [6:5] = { sh[5], \$11 }; + endcase + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:127" */ + default: + \mb$8 = { 1'h0, is_32bit, 5'h00 }; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" *) + casez ({ \$18 , \$14 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" */ + 2'b?1: + \me$13 = { 2'h1, me }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" */ + 2'b1?: + \me$13 = { 1'h0, mb_extra, mb }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:137" */ + default: + \me$13 = { sh[6], \$20 }; + endcase + end + assign \$1 = \$2 ; + assign \$24 = \$25 ; + assign \$29 = \$30 ; + assign ml = \$32 ; + assign left_mask_shift = \$30 [6:0]; + assign sh = { \$6 , shift[5:0] }; + assign rot = rotl_o; + assign rotl_b = rot_count; + assign rotl_a = repl32; + assign shift_signed = shift[5:0]; + assign repl32 = { hi32, rs[31:0] }; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" *) +(* generator = "nMigen" *) +module rotl(b, o, a); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" *) + wire [63:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" *) + wire [7:0] \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" *) + input [63:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" *) + input [5:0] b; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" *) + output [63:0] o; + assign \$2 = 7'h40 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" *) b; + assign \$1 = { a, a } >> \$2 ; + assign o = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.rst_l" *) +(* generator = "nMigen" *) +module rst_l(coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.rst_l" *) +(* generator = "nMigen" *) +module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire q_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_rst; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst; + assign \$15 = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_rst = \$15 ; + assign qn_rst = \$13 ; + assign q_rst = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" *) +(* generator = "nMigen" *) +module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \xer_so$20 , divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) + wire [64:0] \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) + wire [64:0] \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [64:0] \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) + wire [64:0] \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) + wire [64:0] \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) + wire [64:0] \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [64:0] \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) + wire [64:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) + wire [31:0] \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) + wire [31:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) + wire [127:0] \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) + wire [94:0] \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) + wire [190:0] \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) + wire [190:0] \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" *) + wire [63:0] abs_dend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" *) + wire [63:0] abs_dor; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) + output div_by_zero; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) + output dive_abs_ov32; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) + output dive_abs_ov64; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) + output [127:0] dividend; + reg [127:0] dividend; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) + output dividend_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) + output divisor_neg; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) + output [63:0] divisor_radicand; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [3:0] logical_op__data_len; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [3:0] \logical_op__data_len$18 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] logical_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] logical_op__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [63:0] \logical_op__imm_data__data$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__imm_data__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__imm_data__ok$5 ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] logical_op__input_carry; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [1:0] \logical_op__input_carry$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] logical_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \logical_op__insn$19 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] logical_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \logical_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_in$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__invert_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__invert_out$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_32bit$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__is_signed$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__oe$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__oe__ok$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__output_carry$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__ok$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__rc__rc$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__write_cr0$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input logical_op__zero_a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \logical_op__zero_a$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) + output [1:0] operation; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \xer_so$20 ; + assign \$21 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) ra[31] : ra[63]; + assign \$23 = \$21 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) logical_op__is_signed; + assign \$25 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) rb[31] : rb[63]; + assign \$27 = \$25 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) logical_op__is_signed; + assign \$30 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) rb; + assign \$32 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) rb; + assign \$34 = divisor_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) \$30 : \$32 ; + assign \$37 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) ra; + assign \$39 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) ra; + assign \$41 = dividend_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) \$37 : \$39 ; + assign \$43 = abs_dend >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *) abs_dor; + assign \$45 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) 7'h1e; + assign \$47 = \$43 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) \$45 ; + assign \$49 = abs_dend[31:0] >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *) abs_dor[31:0]; + assign \$51 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) 7'h1e; + assign \$53 = \$49 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) \$51 ; + assign \$55 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dor[63:32]; + assign \$57 = divisor_radicand == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) 1'h0; + assign \$59 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dend[63:32]; + assign \$62 = abs_dend[31:0] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) 6'h20; + assign \$61 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) \$62 ; + assign \$66 = abs_dend <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) 7'h40; + always @* begin + if (\initial ) begin end + dividend = 128'h00000000000000000000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" *) + casez (logical_op__insn_type) + /* \nmigen.decoding = "OP_DIV/29|OP_MOD/47" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:74" */ + 7'h1d, 7'h2f: + begin + dividend[31:0] = abs_dend[31:0]; + dividend[63:32] = \$59 ; + end + /* \nmigen.decoding = "OP_DIVE/30" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77" */ + 7'h1e: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" *) + casez (logical_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" */ + 1'h1: + dividend = \$61 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:80" */ + default: + dividend = \$65 [127:0]; + endcase + endcase + end + assign \$29 = \$34 ; + assign \$36 = \$41 ; + assign \$65 = \$66 ; + assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \muxid$1 = muxid; + assign \xer_so$20 = xer_so; + assign div_by_zero = \$57 ; + assign divisor_radicand[63:32] = \$55 ; + assign divisor_radicand[31:0] = abs_dor[31:0]; + assign dive_abs_ov32 = \$53 ; + assign dive_abs_ov64 = \$47 ; + assign abs_dend = \$41 [63:0]; + assign abs_dor = \$34 [63:0]; + assign divisor_neg = \$27 ; + assign dividend_neg = \$23 ; + assign operation = 2'h1; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0" *) +(* generator = "nMigen" *) +module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [4:0] \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [4:0] \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [2:0] \$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [2:0] \$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$114 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$118 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [2:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [2:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [2:0] \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [2:0] \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [4:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [2:0] \$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [4:0] \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [2:0] \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [2:0] \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [4:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) + wire \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) + wire [63:0] \$78 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$80 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$82 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$84 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire \$86 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [1:0] \$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [4:0] \$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) + wire \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [4:0] \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [2:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [3:0] alu_shift_rot0_cr_a; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_shift_rot0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_shift_rot0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_shift_rot0_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_shift_rot0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_shift_rot0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_shift_rot0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_shift_rot0_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_shift_rot0_rc; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_shift_rot0_sr_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_shift_rot0_sr_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_shift_rot0_sr_op__imm_data__data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_shift_rot0_sr_op__imm_data__data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__imm_data__ok$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] alu_shift_rot0_sr_op__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [1:0] \alu_shift_rot0_sr_op__input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__input_cr = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__input_cr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_shift_rot0_sr_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_shift_rot0_sr_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_shift_rot0_sr_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_shift_rot0_sr_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__invert_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__is_signed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__is_signed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__oe__oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__oe__oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__oe__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__output_carry = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__output_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__output_cr = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__output_cr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__rc__ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__rc__rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__rc__rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_shift_rot0_sr_op__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_shift_rot0_sr_op__write_cr0$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] alu_shift_rot0_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \alu_shift_rot0_xer_ca$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire alu_shift_rot0_xer_so; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [4:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [4:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [4:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [2:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [2:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [2:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] data_r1__cr_a = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [3:0] \data_r1__cr_a$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__cr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__cr_a_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] data_r2__xer_ca = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] \data_r2__xer_ca$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r2__xer_ca_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r2__xer_ca_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [3:0] dest2_o; + reg [3:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest3_o; + reg [1:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_shift_rot0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_shift_rot0__imm_data__data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__imm_data__ok; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [1:0] oper_i_alu_shift_rot0__input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__input_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_shift_rot0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_shift_rot0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__invert_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__is_signed; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__oe__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__oe__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__output_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__output_cr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__rc__ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__rc__rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_shift_rot0__write_cr0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [2:0] prev_wr_go = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [2:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [2:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] req_l_r_req = 3'h7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [2:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] req_l_s_req = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [2:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [4:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [2:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src3_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input src4_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [1:0] src5_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [4:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [4:0] src_l_r_src = 5'h1f; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [4:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [4:0] src_l_s_src = 5'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [4:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *) + wire [63:0] src_or_imm; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r2 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg src_r3 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg \src_r3$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [1:0] src_r4 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [1:0] \src_r4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *) + wire src_sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + assign \$100 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + assign \$102 = \$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$100 ; + assign \$104 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$106 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$108 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$10 = \$2 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$4 ; + assign \$110 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$104 , \$106 , \$108 }; + assign \$112 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$114 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$116 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$118 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$14 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$12 ; + assign \$16 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$18 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$16 ; + assign \$20 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$26 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; + assign \$23 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ; + assign \$22 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; + assign \$2 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$30 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$22 ; + assign \$32 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$36 = \$32 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$34 ; + assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_shift_rot0_n_ready_i; + assign \$40 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$38 ; + assign \$42 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$44 = \$42 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$46 = \$40 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$44 ; + assign \$48 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$50 = \$48 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_shift_rot0_n_ready_i; + assign \$52 = \$50 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_shift_rot0_n_valid_o; + assign \$54 = \$52 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$56 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$58 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$60 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$62 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$64 = alu_shift_rot0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$66 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$68 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$70 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$72 = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$74 = xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$76 = alu_shift_rot0_sr_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1]; + assign \$78 = alu_shift_rot0_sr_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_shift_rot0_sr_op__imm_data__data : src2_i; + assign \$7 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$80 = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0; + assign \$82 = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r1; + assign \$84 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$86 = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3; + assign \$88 = src_l_q_src[4] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src5_i : src_r4; + assign \$4 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$7 ; + assign \$90 = alu_shift_rot0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$92 = alu_shift_rot0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$94 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$96 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_shift_rot0_sr_op__imm_data__ok; + assign \$98 = \$94 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 3'h7, \$96 , 1'h1 }; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r4 <= \src_r4$next ; + always @(posedge coresync_clk) + src_r3 <= \src_r3$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r2__xer_ca <= \data_r2__xer_ca$next ; + always @(posedge coresync_clk) + data_r2__xer_ca_ok <= \data_r2__xer_ca_ok$next ; + always @(posedge coresync_clk) + data_r1__cr_a <= \data_r1__cr_a$next ; + always @(posedge coresync_clk) + data_r1__cr_a_ok <= \data_r1__cr_a_ok$next ; + always @(posedge coresync_clk) + data_r0__o <= \data_r0__o$next ; + always @(posedge coresync_clk) + data_r0__o_ok <= \data_r0__o_ok$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__insn_type <= \alu_shift_rot0_sr_op__insn_type$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__fn_unit <= \alu_shift_rot0_sr_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__imm_data__data <= \alu_shift_rot0_sr_op__imm_data__data$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__imm_data__ok <= \alu_shift_rot0_sr_op__imm_data__ok$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__rc__rc <= \alu_shift_rot0_sr_op__rc__rc$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__rc__ok <= \alu_shift_rot0_sr_op__rc__ok$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__oe__oe <= \alu_shift_rot0_sr_op__oe__oe$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__oe__ok <= \alu_shift_rot0_sr_op__oe__ok$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__write_cr0 <= \alu_shift_rot0_sr_op__write_cr0$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__invert_in <= \alu_shift_rot0_sr_op__invert_in$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__input_carry <= \alu_shift_rot0_sr_op__input_carry$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__output_carry <= \alu_shift_rot0_sr_op__output_carry$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__input_cr <= \alu_shift_rot0_sr_op__input_cr$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__output_cr <= \alu_shift_rot0_sr_op__output_cr$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__is_32bit <= \alu_shift_rot0_sr_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__is_signed <= \alu_shift_rot0_sr_op__is_signed$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__insn <= \alu_shift_rot0_sr_op__insn$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_shift_rot0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$10 ; + \alu_l$125 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + alu_shift_rot0 alu_shift_rot0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .cr_a(alu_shift_rot0_cr_a), + .cr_a_ok(cr_a_ok), + .n_ready_i(alu_shift_rot0_n_ready_i), + .n_valid_o(alu_shift_rot0_n_valid_o), + .o(alu_shift_rot0_o), + .o_ok(o_ok), + .p_ready_o(alu_shift_rot0_p_ready_o), + .p_valid_i(alu_shift_rot0_p_valid_i), + .ra(alu_shift_rot0_ra), + .rb(alu_shift_rot0_rb), + .rc(alu_shift_rot0_rc), + .sr_op__fn_unit(alu_shift_rot0_sr_op__fn_unit), + .sr_op__imm_data__data(alu_shift_rot0_sr_op__imm_data__data), + .sr_op__imm_data__ok(alu_shift_rot0_sr_op__imm_data__ok), + .sr_op__input_carry(alu_shift_rot0_sr_op__input_carry), + .sr_op__input_cr(alu_shift_rot0_sr_op__input_cr), + .sr_op__insn(alu_shift_rot0_sr_op__insn), + .sr_op__insn_type(alu_shift_rot0_sr_op__insn_type), + .sr_op__invert_in(alu_shift_rot0_sr_op__invert_in), + .sr_op__is_32bit(alu_shift_rot0_sr_op__is_32bit), + .sr_op__is_signed(alu_shift_rot0_sr_op__is_signed), + .sr_op__oe__oe(alu_shift_rot0_sr_op__oe__oe), + .sr_op__oe__ok(alu_shift_rot0_sr_op__oe__ok), + .sr_op__output_carry(alu_shift_rot0_sr_op__output_carry), + .sr_op__output_cr(alu_shift_rot0_sr_op__output_cr), + .sr_op__rc__ok(alu_shift_rot0_sr_op__rc__ok), + .sr_op__rc__rc(alu_shift_rot0_sr_op__rc__rc), + .sr_op__write_cr0(alu_shift_rot0_sr_op__write_cr0), + .xer_ca(alu_shift_rot0_xer_ca), + .\xer_ca$1 (\alu_shift_rot0_xer_ca$1 ), + .xer_ca_ok(xer_ca_ok), + .xer_so(alu_shift_rot0_xer_so) + ); + \alui_l$124 alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + \opc_l$120 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \req_l$121 req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + \rok_l$123 rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + \rst_l$122 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$119 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$54 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$64 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 5'h00; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 5'h1f; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$66 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$68 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \alu_shift_rot0_sr_op__insn_type$next = alu_shift_rot0_sr_op__insn_type; + \alu_shift_rot0_sr_op__fn_unit$next = alu_shift_rot0_sr_op__fn_unit; + \alu_shift_rot0_sr_op__imm_data__data$next = alu_shift_rot0_sr_op__imm_data__data; + \alu_shift_rot0_sr_op__imm_data__ok$next = alu_shift_rot0_sr_op__imm_data__ok; + \alu_shift_rot0_sr_op__rc__rc$next = alu_shift_rot0_sr_op__rc__rc; + \alu_shift_rot0_sr_op__rc__ok$next = alu_shift_rot0_sr_op__rc__ok; + \alu_shift_rot0_sr_op__oe__oe$next = alu_shift_rot0_sr_op__oe__oe; + \alu_shift_rot0_sr_op__oe__ok$next = alu_shift_rot0_sr_op__oe__ok; + \alu_shift_rot0_sr_op__write_cr0$next = alu_shift_rot0_sr_op__write_cr0; + \alu_shift_rot0_sr_op__invert_in$next = alu_shift_rot0_sr_op__invert_in; + \alu_shift_rot0_sr_op__input_carry$next = alu_shift_rot0_sr_op__input_carry; + \alu_shift_rot0_sr_op__output_carry$next = alu_shift_rot0_sr_op__output_carry; + \alu_shift_rot0_sr_op__input_cr$next = alu_shift_rot0_sr_op__input_cr; + \alu_shift_rot0_sr_op__output_cr$next = alu_shift_rot0_sr_op__output_cr; + \alu_shift_rot0_sr_op__is_32bit$next = alu_shift_rot0_sr_op__is_32bit; + \alu_shift_rot0_sr_op__is_signed$next = alu_shift_rot0_sr_op__is_signed; + \alu_shift_rot0_sr_op__insn$next = alu_shift_rot0_sr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_shift_rot0_sr_op__insn$next , \alu_shift_rot0_sr_op__is_signed$next , \alu_shift_rot0_sr_op__is_32bit$next , \alu_shift_rot0_sr_op__output_cr$next , \alu_shift_rot0_sr_op__input_cr$next , \alu_shift_rot0_sr_op__output_carry$next , \alu_shift_rot0_sr_op__input_carry$next , \alu_shift_rot0_sr_op__invert_in$next , \alu_shift_rot0_sr_op__write_cr0$next , \alu_shift_rot0_sr_op__oe__ok$next , \alu_shift_rot0_sr_op__oe__oe$next , \alu_shift_rot0_sr_op__rc__ok$next , \alu_shift_rot0_sr_op__rc__rc$next , \alu_shift_rot0_sr_op__imm_data__ok$next , \alu_shift_rot0_sr_op__imm_data__data$next , \alu_shift_rot0_sr_op__fn_unit$next , \alu_shift_rot0_sr_op__insn_type$next } = { oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__insn_type }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + begin + \alu_shift_rot0_sr_op__imm_data__data$next = 64'h0000000000000000; + \alu_shift_rot0_sr_op__imm_data__ok$next = 1'h0; + \alu_shift_rot0_sr_op__rc__rc$next = 1'h0; + \alu_shift_rot0_sr_op__rc__ok$next = 1'h0; + \alu_shift_rot0_sr_op__oe__oe$next = 1'h0; + \alu_shift_rot0_sr_op__oe__ok$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__o$next = data_r0__o; + \data_r0__o_ok$next = data_r0__o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = { o_ok, alu_shift_rot0_o }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__cr_a$next = data_r1__cr_a; + \data_r1__cr_a_ok$next = data_r1__cr_a_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = { cr_a_ok, alu_shift_rot0_cr_a }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__cr_a_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r2__xer_ca$next = data_r2__xer_ca; + \data_r2__xer_ca_ok$next = data_r2__xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = { xer_ca_ok, alu_shift_rot0_xer_ca }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r2__xer_ca_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[0]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src1_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_sel) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = src_or_imm; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r3$next = src_r3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[3]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r3$next = src4_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r4$next = src_r4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[4]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r4$next = src5_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$90 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$92 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$114 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__o; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$116 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__cr_a; + endcase + end + always @* begin + if (\initial ) begin end + dest3_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$118 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest3_o = data_r2__xer_ca; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$20 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 3'h0; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$112 ; + assign cu_rd__rel_o = \$102 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_shift_rot0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_shift_rot0_p_valid_i = alui_l_q_alui; + assign \alu_shift_rot0_xer_ca$1 = \$88 ; + assign alu_shift_rot0_xer_so = \$86 ; + assign alu_shift_rot0_rc = \$84 ; + assign alu_shift_rot0_rb = \$82 ; + assign alu_shift_rot0_ra = \$80 ; + assign src_or_imm = \$78 ; + assign src_sel = \$76 ; + assign cu_wrmask_o = { \$74 , \$72 , \$70 }; + assign reset_r = \$62 ; + assign reset_w = \$60 ; + assign rst_r = \$58 ; + assign reset = \$56 ; + assign wr_any = \$36 ; + assign cu_done_o = \$30 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$18 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_shift_rot0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$14 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$10 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.spr" *) +(* generator = "nMigen" *) +module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [3:0] memory_r_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + wire [63:0] memory_r_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire [3:0] memory_w_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire [63:0] memory_w_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + wire memory_w_en; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg ren_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + reg \ren_delay$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] spr1__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [3:0] \spr1__addr$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] spr1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] spr1__data_o; + reg [63:0] spr1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input spr1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input spr1__wen; + reg [63:0] memory [10:0]; + initial begin + memory[0] = 64'h0000000000000000; + memory[1] = 64'h0000000000000000; + memory[2] = 64'h0000000000000000; + memory[3] = 64'h0000000000000000; + memory[4] = 64'h0000000000000000; + memory[5] = 64'h0000000000000000; + memory[6] = 64'h0000000000000000; + memory[7] = 64'h0000000000000000; + memory[8] = 64'h0000000000000000; + memory[9] = 64'h0000000000000000; + memory[10] = 64'h0000000000000000; + end + reg [3:0] _0_; + always @(posedge coresync_clk) begin + _0_ <= memory_r_addr; + if (memory_w_en) memory[memory_w_addr] <= memory_w_data; + end + assign memory_r_data = memory[_0_]; + always @(posedge coresync_clk) + ren_delay <= \ren_delay$next ; + always @* begin + if (\initial ) begin end + \ren_delay$next = spr1__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + spr1__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + casez (ren_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + 1'h1: + spr1__data_o = memory_r_data; + endcase + end + assign memory_w_data = spr1__data_i; + assign memory_w_en = spr1__wen; + assign memory_w_addr = \spr1__addr$1 ; + assign memory_r_addr = spr1__addr; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0" *) +(* generator = "nMigen" *) +module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src1_i, src4_i, src6_i, src5_i, src3_i, src2_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, xer_ca_ok, dest6_o, xer_ov_ok, dest5_o, xer_so_ok, dest4_o, fast1_ok, dest3_o, spr1_ok, dest2_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [5:0] \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [5:0] \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [5:0] \$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [5:0] \$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [5:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$114 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [5:0] \$122 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [5:0] \$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$126 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$130 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$132 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$134 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$14 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$18 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [5:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [5:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [5:0] \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [5:0] \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [5:0] \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [5:0] \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [5:0] \$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [5:0] \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$84 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$86 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [5:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$90 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire \$92 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [1:0] \$94 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [1:0] \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [5:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_spr0_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \alu_spr0_fast1$2 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_spr0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_spr0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_spr0_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_spr0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_spr0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_spr0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_spr0_spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \alu_spr0_spr1$1 ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_spr0_spr_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_spr0_spr_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_spr0_spr_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_spr0_spr_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_spr0_spr_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_spr0_spr_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_spr0_spr_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_spr0_spr_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] alu_spr0_xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \alu_spr0_xer_ca$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] alu_spr0_xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \alu_spr0_xer_ov$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire alu_spr0_xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \alu_spr0_xer_so$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [5:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [5:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [5:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [5:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [5:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [5:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r1__spr1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r1__spr1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__spr1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__spr1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r2__fast1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r2__fast1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r2__fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r2__fast1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__xer_so = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__xer_so$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__xer_so_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] data_r4__xer_ov = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] \data_r4__xer_ov$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r4__xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r4__xer_ov_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] data_r5__xer_ca = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [1:0] \data_r5__xer_ca$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r5__xer_ca_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r5__xer_ca_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest2_o; + reg [63:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest3_o; + reg [63:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output dest4_o; + reg dest4_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest5_o; + reg [1:0] dest5_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [1:0] dest6_o; + reg [1:0] dest6_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_spr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_spr0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_spr0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_spr0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [5:0] prev_wr_go = 6'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [5:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [5:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [5:0] req_l_r_req = 6'h3f; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [5:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [5:0] req_l_s_req = 6'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [5:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [5:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [5:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src3_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input src4_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [1:0] src5_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [1:0] src6_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [5:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [5:0] src_l_r_src = 6'h3f; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [5:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [5:0] src_l_s_src = 6'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [5:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r2 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg src_r3 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg \src_r3$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [1:0] src_r4 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [1:0] \src_r4$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [1:0] src_r5 = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [1:0] \src_r5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$100 = alu_spr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$102 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$104 = \$102 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) 6'h3f; + assign \$106 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + assign \$108 = \$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$106 ; + assign \$110 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$112 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$114 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$116 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$118 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$120 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$122 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$110 , \$112 , \$114 , \$116 , \$118 , \$120 }; + assign \$124 = \$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$126 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$128 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$8 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$11 ; + assign \$130 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$132 = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$134 = cu_wr__go_i[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$136 = cu_wr__go_i[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$14 = \$6 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ; + assign \$16 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$18 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$16 ; + assign \$20 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$22 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$20 ; + assign \$24 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$30 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$28 ; + assign \$27 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$30 ; + assign \$26 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ; + assign \$34 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ; + assign \$36 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$38 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$40 = \$36 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$38 ; + assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_spr0_n_ready_i; + assign \$44 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$42 ; + assign \$46 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$48 = \$46 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$50 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$48 ; + assign \$52 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$54 = \$52 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_spr0_n_ready_i; + assign \$56 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_spr0_n_valid_o; + assign \$58 = \$56 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$60 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$62 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$64 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$66 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$68 = alu_spr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$6 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$70 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$72 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$74 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$76 = spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$78 = fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$80 = xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$82 = xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$84 = xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$86 = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0; + assign \$88 = src_l_q_src[1] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src2_i : src_r1; + assign \$90 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$92 = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3; + assign \$94 = src_l_q_src[4] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src5_i : src_r4; + assign \$96 = src_l_q_src[5] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src6_i : src_r5; + assign \$98 = alu_spr0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r5 <= \src_r5$next ; + always @(posedge coresync_clk) + src_r4 <= \src_r4$next ; + always @(posedge coresync_clk) + src_r3 <= \src_r3$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r5__xer_ca <= \data_r5__xer_ca$next ; + always @(posedge coresync_clk) + data_r5__xer_ca_ok <= \data_r5__xer_ca_ok$next ; + always @(posedge coresync_clk) + data_r4__xer_ov <= \data_r4__xer_ov$next ; + always @(posedge coresync_clk) + data_r4__xer_ov_ok <= \data_r4__xer_ov_ok$next ; + always @(posedge coresync_clk) + data_r3__xer_so <= \data_r3__xer_so$next ; + always @(posedge coresync_clk) + data_r3__xer_so_ok <= \data_r3__xer_so_ok$next ; + always @(posedge coresync_clk) + data_r2__fast1 <= \data_r2__fast1$next ; + always @(posedge coresync_clk) + data_r2__fast1_ok <= \data_r2__fast1_ok$next ; + always @(posedge coresync_clk) + data_r1__spr1 <= \data_r1__spr1$next ; + always @(posedge coresync_clk) + data_r1__spr1_ok <= \data_r1__spr1_ok$next ; + always @(posedge coresync_clk) + data_r0__o <= \data_r0__o$next ; + always @(posedge coresync_clk) + data_r0__o_ok <= \data_r0__o_ok$next ; + always @(posedge coresync_clk) + alu_spr0_spr_op__insn_type <= \alu_spr0_spr_op__insn_type$next ; + always @(posedge coresync_clk) + alu_spr0_spr_op__fn_unit <= \alu_spr0_spr_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_spr0_spr_op__insn <= \alu_spr0_spr_op__insn$next ; + always @(posedge coresync_clk) + alu_spr0_spr_op__is_32bit <= \alu_spr0_spr_op__is_32bit$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_spr0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$14 ; + \alu_l$73 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + alu_spr0 alu_spr0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .fast1(alu_spr0_fast1), + .\fast1$2 (\alu_spr0_fast1$2 ), + .fast1_ok(fast1_ok), + .n_ready_i(alu_spr0_n_ready_i), + .n_valid_o(alu_spr0_n_valid_o), + .o(alu_spr0_o), + .o_ok(o_ok), + .p_ready_o(alu_spr0_p_ready_o), + .p_valid_i(alu_spr0_p_valid_i), + .ra(alu_spr0_ra), + .spr1(alu_spr0_spr1), + .\spr1$1 (\alu_spr0_spr1$1 ), + .spr1_ok(spr1_ok), + .spr_op__fn_unit(alu_spr0_spr_op__fn_unit), + .spr_op__insn(alu_spr0_spr_op__insn), + .spr_op__insn_type(alu_spr0_spr_op__insn_type), + .spr_op__is_32bit(alu_spr0_spr_op__is_32bit), + .xer_ca(alu_spr0_xer_ca), + .\xer_ca$5 (\alu_spr0_xer_ca$5 ), + .xer_ca_ok(xer_ca_ok), + .xer_ov(alu_spr0_xer_ov), + .\xer_ov$4 (\alu_spr0_xer_ov$4 ), + .xer_ov_ok(xer_ov_ok), + .xer_so(alu_spr0_xer_so), + .\xer_so$3 (\alu_spr0_xer_so$3 ), + .xer_so_ok(xer_so_ok) + ); + \alui_l$72 alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + \opc_l$68 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \req_l$69 req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + \rok_l$71 rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + \rst_l$70 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$67 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$58 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$68 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 6'h00; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 6'h3f; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$70 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 6'h00; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$72 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 6'h3f; + endcase + end + always @* begin + if (\initial ) begin end + \alu_spr0_spr_op__insn_type$next = alu_spr0_spr_op__insn_type; + \alu_spr0_spr_op__fn_unit$next = alu_spr0_spr_op__fn_unit; + \alu_spr0_spr_op__insn$next = alu_spr0_spr_op__insn; + \alu_spr0_spr_op__is_32bit$next = alu_spr0_spr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_spr0_spr_op__is_32bit$next , \alu_spr0_spr_op__insn$next , \alu_spr0_spr_op__fn_unit$next , \alu_spr0_spr_op__insn_type$next } = { oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__insn, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn_type }; + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__o$next = data_r0__o; + \data_r0__o_ok$next = data_r0__o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = { o_ok, alu_spr0_o }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__spr1$next = data_r1__spr1; + \data_r1__spr1_ok$next = data_r1__spr1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__spr1_ok$next , \data_r1__spr1$next } = { spr1_ok, alu_spr0_spr1 }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__spr1_ok$next , \data_r1__spr1$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__spr1_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r2__fast1$next = data_r2__fast1; + \data_r2__fast1_ok$next = data_r2__fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r2__fast1_ok$next , \data_r2__fast1$next } = { fast1_ok, alu_spr0_fast1 }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r2__fast1_ok$next , \data_r2__fast1$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r2__fast1_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r3__xer_so$next = data_r3__xer_so; + \data_r3__xer_so_ok$next = data_r3__xer_so_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = { xer_so_ok, alu_spr0_xer_so }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r3__xer_so_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r4__xer_ov$next = data_r4__xer_ov; + \data_r4__xer_ov_ok$next = data_r4__xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r4__xer_ov_ok$next , \data_r4__xer_ov$next } = { xer_ov_ok, alu_spr0_xer_ov }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r4__xer_ov_ok$next , \data_r4__xer_ov$next } = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r4__xer_ov_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r5__xer_ca$next = data_r5__xer_ca; + \data_r5__xer_ca_ok$next = data_r5__xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r5__xer_ca_ok$next , \data_r5__xer_ca$next } = { xer_ca_ok, alu_spr0_xer_ca }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r5__xer_ca_ok$next , \data_r5__xer_ca$next } = 3'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r5__xer_ca_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[0]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src1_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[1]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = src2_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r3$next = src_r3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[3]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r3$next = src4_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r4$next = src_r4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[4]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r4$next = src5_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r5$next = src_r5; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[5]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r5$next = src6_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$98 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$100 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$126 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__o; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$128 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__spr1; + endcase + end + always @* begin + if (\initial ) begin end + dest3_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$130 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest3_o = data_r2__fast1; + endcase + end + always @* begin + if (\initial ) begin end + dest4_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$132 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest4_o = data_r3__xer_so; + endcase + end + always @* begin + if (\initial ) begin end + dest5_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$134 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest5_o = data_r4__xer_ov; + endcase + end + always @* begin + if (\initial ) begin end + dest6_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$136 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest6_o = data_r5__xer_ca; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$24 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 6'h00; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$124 ; + assign cu_rd__rel_o = \$108 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_spr0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_spr0_p_valid_i = alui_l_q_alui; + assign \alu_spr0_xer_ca$5 = \$96 ; + assign \alu_spr0_xer_ov$4 = \$94 ; + assign \alu_spr0_xer_so$3 = \$92 ; + assign \alu_spr0_fast1$2 = \$90 ; + assign \alu_spr0_spr1$1 = \$88 ; + assign alu_spr0_ra = \$86 ; + assign cu_wrmask_o = { \$84 , \$82 , \$80 , \$78 , \$76 , \$74 }; + assign reset_r = \$66 ; + assign reset_w = \$64 ; + assign rst_r = \$62 ; + assign reset = \$60 ; + assign wr_any = \$40 ; + assign cu_done_o = \$34 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$22 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_spr0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$18 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$14 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" *) +(* generator = "nMigen" *) +module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, ra, spr1, fast1, xer_so, xer_ov, xer_ca, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , o, o_ok, \spr1$6 , spr1_ok, \fast1$7 , fast1_ok, \xer_so$8 , xer_so_ok, \xer_ov$9 , xer_ov_ok, \xer_ca$10 , xer_ca_ok, muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \fast1$7 ; + reg [63:0] \fast1$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + reg fast1_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + input [1:0] muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) + output [1:0] \muxid$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] o; + reg [63:0] o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + reg o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:50" *) + wire [9:0] spr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [63:0] spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [63:0] \spr1$6 ; + reg [63:0] \spr1$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr1_ok; + reg spr1_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] spr_op__fn_unit; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [13:0] \spr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] spr_op__insn; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [31:0] \spr_op__insn$4 ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] spr_op__insn_type; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output [6:0] \spr_op__insn_type$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input spr_op__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + output \spr_op__is_32bit$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] xer_ca; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ca$10 ; + reg [1:0] \xer_ca$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ca_ok; + reg xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input [1:0] xer_ov; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [1:0] \xer_ov$9 ; + reg [1:0] \xer_ov$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_ov_ok; + reg xer_ov_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + input xer_so; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output \xer_so$8 ; + reg \xer_so$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output xer_so_ok; + reg xer_so_ok; + assign \$11 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; + assign \$13 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; + assign \$15 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; + assign \$17 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; + assign \$19 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; + assign \$21 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; + assign \$23 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) 10'h001; + always @* begin + if (\initial ) begin end + \fast1$7 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + \fast1$7 = ra; + endcase + endcase + end + always @* begin + if (\initial ) begin end + spr1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:78" */ + default: + spr1_ok = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + o_ok = 1'h0; + o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + /* empty */; + /* \nmigen.decoding = "OP_MFSPR/46" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:83" */ + 7'h2e: + begin + o_ok = 1'h1; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:85" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:88" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016, 10'h10c: + begin + o = fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) + casez (\$23 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" */ + 1'h1: + begin + o[63:32] = 32'd0; + o[28:20] = 9'h000; + o[31] = xer_so; + o[30] = xer_ov[0]; + o[19] = xer_ov[1]; + o[29] = xer_ca[0]; + o[18] = xer_ca[1]; + end + endcase + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:103" */ + 10'h10d: + o[31:0] = fast1[63:32]; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:107" */ + default: + o = spr1; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + fast1_ok = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + casez (\$11 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ + 1'h1: + \xer_so$8 = ra[31]; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + xer_so_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ + 1'h1: + xer_so_ok = 1'h1; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \xer_ov$9 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ + 1'h1: + begin + \xer_ov$9 [0] = ra[30]; + \xer_ov$9 [1] = ra[19]; + end + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + xer_ov_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + casez (\$17 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ + 1'h1: + xer_ov_ok = 1'h1; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$10 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ + 1'h1: + begin + \xer_ca$10 [0] = ra[29]; + \xer_ca$10 [1] = ra[18]; + end + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + xer_ca_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + casez (\$21 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ + 1'h1: + xer_ca_ok = 1'h1; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \spr1$6 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) + casez (spr_op__insn_type) + /* \nmigen.decoding = "OP_MTSPR/49" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ + 7'h31: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) + casez (spr) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ + 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:78" */ + default: + \spr1$6 = ra; + endcase + endcase + end + assign { \spr_op__is_32bit$5 , \spr_op__insn$4 , \spr_op__fn_unit$3 , \spr_op__insn_type$2 } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; + assign \muxid$1 = muxid; + assign spr = { spr_op__insn[15:11], spr_op__insn[20:16] }; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_a.sprmap" *) +(* generator = "nMigen" *) +module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fast_o; + reg [2:0] fast_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast_o_ok; + reg fast_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + input [9:0] spr_i; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [9:0] spr_o; + reg [9:0] spr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr_o_ok; + reg spr_o_ok; + always @* begin + if (\initial ) begin end + fast_o = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + casez (spr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h001: + fast_o = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h003: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h008: + fast_o = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h009: + fast_o = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h00d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h011: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h012: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h013: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h016: + fast_o = 3'h6; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01a: + fast_o = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01b: + fast_o = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h030: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h03d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h080: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h081: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h082: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h083: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h088: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h090: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h098: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h099: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b4: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0ba: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bb: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bc: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0be: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h100: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h103: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h10c: + fast_o = 3'h7; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h10d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h110: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h111: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h112: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h113: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h130: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h131: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h132: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h133: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h134: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h135: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h136: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h139: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h150: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h151: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h152: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h153: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h15d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1be: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1d0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2c0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h300: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h301: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h302: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h303: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h304: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h305: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h306: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h307: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h308: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h310: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h311: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h312: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h313: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h314: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h315: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h316: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h317: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h318: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h320: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h321: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h322: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h323: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h324: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h325: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h326: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h328: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h329: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h32f: + fast_o = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + fast_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + casez (spr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h001: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h003: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h008: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h009: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h00d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h011: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h012: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h013: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h016: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01a: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01b: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h030: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h03d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h080: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h081: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h082: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h083: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h088: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h090: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h098: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h099: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b4: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0ba: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bb: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bc: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0be: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h100: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h103: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h10c: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h10d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h110: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h111: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h112: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h113: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h130: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h131: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h132: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h133: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h134: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h135: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h136: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h139: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h150: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h151: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h152: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h153: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h15d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1be: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1d0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2c0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h300: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h301: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h302: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h303: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h304: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h305: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h306: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h307: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h308: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h310: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h311: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h312: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h313: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h314: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h315: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h316: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h317: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h318: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h320: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h321: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h322: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h323: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h324: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h325: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h326: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h328: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h329: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h32f: + fast_o_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + spr_o = 10'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + casez (spr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h001: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h003: + spr_o = 10'h001; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h008: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h009: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h00d: + spr_o = 10'h004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h011: + spr_o = 10'h005; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h012: + spr_o = 10'h006; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h013: + spr_o = 10'h007; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h016: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01c: + spr_o = 10'h00b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01d: + spr_o = 10'h00c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h030: + spr_o = 10'h00d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h03d: + spr_o = 10'h00e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h080: + spr_o = 10'h00f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h081: + spr_o = 10'h010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h082: + spr_o = 10'h011; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h083: + spr_o = 10'h012; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h088: + spr_o = 10'h013; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h090: + spr_o = 10'h014; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h098: + spr_o = 10'h015; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h099: + spr_o = 10'h016; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09d: + spr_o = 10'h017; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09e: + spr_o = 10'h018; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09f: + spr_o = 10'h019; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b0: + spr_o = 10'h01a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b4: + spr_o = 10'h01b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0ba: + spr_o = 10'h01c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bb: + spr_o = 10'h01d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bc: + spr_o = 10'h01e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0be: + spr_o = 10'h01f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h100: + spr_o = 10'h020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h103: + spr_o = 10'h021; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h10c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h10d: + spr_o = 10'h023; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h110: + spr_o = 10'h024; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h111: + spr_o = 10'h025; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h112: + spr_o = 10'h026; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h113: + spr_o = 10'h027; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11b: + spr_o = 10'h028; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11c: + spr_o = 10'h029; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11d: + spr_o = 10'h02a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11e: + spr_o = 10'h02b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11f: + spr_o = 10'h02c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h130: + spr_o = 10'h02d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h131: + spr_o = 10'h02e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h132: + spr_o = 10'h02f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h133: + spr_o = 10'h030; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h134: + spr_o = 10'h031; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h135: + spr_o = 10'h032; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h136: + spr_o = 10'h033; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h139: + spr_o = 10'h034; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13a: + spr_o = 10'h035; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13b: + spr_o = 10'h036; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13e: + spr_o = 10'h037; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13f: + spr_o = 10'h038; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h150: + spr_o = 10'h039; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h151: + spr_o = 10'h03a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h152: + spr_o = 10'h03b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h153: + spr_o = 10'h03c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h15d: + spr_o = 10'h03d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1be: + spr_o = 10'h03e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1d0: + spr_o = 10'h03f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2c0: + spr_o = 10'h040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d0: + spr_o = 10'h041; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d1: + spr_o = 10'h042; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h300: + spr_o = 10'h043; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h301: + spr_o = 10'h044; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h302: + spr_o = 10'h045; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h303: + spr_o = 10'h046; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h304: + spr_o = 10'h047; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h305: + spr_o = 10'h048; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h306: + spr_o = 10'h049; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h307: + spr_o = 10'h04a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h308: + spr_o = 10'h04b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30b: + spr_o = 10'h04c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30c: + spr_o = 10'h04d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30d: + spr_o = 10'h04e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30e: + spr_o = 10'h04f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h310: + spr_o = 10'h050; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h311: + spr_o = 10'h051; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h312: + spr_o = 10'h052; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h313: + spr_o = 10'h053; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h314: + spr_o = 10'h054; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h315: + spr_o = 10'h055; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h316: + spr_o = 10'h056; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h317: + spr_o = 10'h057; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h318: + spr_o = 10'h058; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31b: + spr_o = 10'h059; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31c: + spr_o = 10'h05a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31d: + spr_o = 10'h05b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31e: + spr_o = 10'h05c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h320: + spr_o = 10'h05d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h321: + spr_o = 10'h05e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h322: + spr_o = 10'h05f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h323: + spr_o = 10'h060; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h324: + spr_o = 10'h061; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h325: + spr_o = 10'h062; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h326: + spr_o = 10'h063; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h328: + spr_o = 10'h064; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h329: + spr_o = 10'h065; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32a: + spr_o = 10'h066; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32b: + spr_o = 10'h067; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h32f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h330: + spr_o = 10'h069; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h337: + spr_o = 10'h06a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h350: + spr_o = 10'h06b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h351: + spr_o = 10'h06c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h357: + spr_o = 10'h06d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h380: + spr_o = 10'h06e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h382: + spr_o = 10'h06f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h3ff: + spr_o = 10'h070; + endcase + end + always @* begin + if (\initial ) begin end + spr_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + casez (spr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h001: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h003: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h008: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h009: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h00d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h011: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h012: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h013: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h016: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01c: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h030: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h03d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h080: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h081: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h082: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h083: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h088: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h090: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h098: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h099: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09f: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b0: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b4: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0ba: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bb: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bc: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0be: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h100: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h103: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h10c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h10d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h110: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h111: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h112: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h113: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11c: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11f: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h130: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h131: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h132: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h133: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h134: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h135: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h136: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h139: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13a: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13f: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h150: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h151: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h152: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h153: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h15d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1be: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1d0: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2c0: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d0: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d1: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h300: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h301: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h302: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h303: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h304: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h305: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h306: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h307: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h308: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30c: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h310: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h311: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h312: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h313: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h314: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h315: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h316: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h317: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h318: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31c: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h320: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h321: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h322: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h323: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h324: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h325: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h326: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h328: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h329: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32a: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h32f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h330: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h337: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h350: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h351: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h357: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h380: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h382: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h3ff: + spr_o_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_o.sprmap" *) +(* generator = "nMigen" *) +module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [2:0] fast_o; + reg [2:0] fast_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast_o_ok; + reg fast_o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + input [9:0] spr_i; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output [9:0] spr_o; + reg [9:0] spr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output spr_o_ok; + reg spr_o_ok; + always @* begin + if (\initial ) begin end + fast_o = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + casez (spr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h001: + fast_o = 3'h5; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h003: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h008: + fast_o = 3'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h009: + fast_o = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h00d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h011: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h012: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h013: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h016: + fast_o = 3'h6; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01a: + fast_o = 3'h3; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01b: + fast_o = 3'h4; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h030: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h03d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h080: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h081: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h082: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h083: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h088: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h090: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h098: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h099: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b4: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0ba: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bb: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bc: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0be: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h100: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h103: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h10c: + fast_o = 3'h7; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h10d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h110: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h111: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h112: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h113: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h130: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h131: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h132: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h133: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h134: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h135: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h136: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h139: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h150: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h151: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h152: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h153: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h15d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1be: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1d0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2c0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h300: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h301: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h302: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h303: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h304: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h305: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h306: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h307: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h308: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h310: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h311: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h312: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h313: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h314: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h315: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h316: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h317: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h318: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h320: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h321: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h322: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h323: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h324: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h325: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h326: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h328: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h329: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h32f: + fast_o = 3'h2; + endcase + end + always @* begin + if (\initial ) begin end + fast_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + casez (spr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h001: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h003: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h008: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h009: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h00d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h011: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h012: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h013: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h016: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01a: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01b: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h030: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h03d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h080: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h081: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h082: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h083: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h088: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h090: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h098: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h099: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b4: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0ba: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bb: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bc: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0be: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h100: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h103: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h10c: + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h10d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h110: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h111: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h112: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h113: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h130: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h131: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h132: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h133: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h134: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h135: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h136: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h139: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h150: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h151: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h152: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h153: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h15d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1be: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1d0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2c0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d0: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h300: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h301: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h302: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h303: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h304: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h305: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h306: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h307: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h308: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h310: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h311: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h312: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h313: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h314: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h315: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h316: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h317: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h318: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31d: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31e: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h320: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h321: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h322: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h323: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h324: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h325: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h326: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h328: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h329: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h32f: + fast_o_ok = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + spr_o = 10'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + casez (spr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h001: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h003: + spr_o = 10'h001; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h008: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h009: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h00d: + spr_o = 10'h004; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h011: + spr_o = 10'h005; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h012: + spr_o = 10'h006; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h013: + spr_o = 10'h007; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h016: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01c: + spr_o = 10'h00b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01d: + spr_o = 10'h00c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h030: + spr_o = 10'h00d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h03d: + spr_o = 10'h00e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h080: + spr_o = 10'h00f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h081: + spr_o = 10'h010; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h082: + spr_o = 10'h011; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h083: + spr_o = 10'h012; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h088: + spr_o = 10'h013; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h090: + spr_o = 10'h014; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h098: + spr_o = 10'h015; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h099: + spr_o = 10'h016; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09d: + spr_o = 10'h017; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09e: + spr_o = 10'h018; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09f: + spr_o = 10'h019; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b0: + spr_o = 10'h01a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b4: + spr_o = 10'h01b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0ba: + spr_o = 10'h01c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bb: + spr_o = 10'h01d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bc: + spr_o = 10'h01e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0be: + spr_o = 10'h01f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h100: + spr_o = 10'h020; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h103: + spr_o = 10'h021; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h10c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h10d: + spr_o = 10'h023; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h110: + spr_o = 10'h024; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h111: + spr_o = 10'h025; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h112: + spr_o = 10'h026; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h113: + spr_o = 10'h027; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11b: + spr_o = 10'h028; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11c: + spr_o = 10'h029; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11d: + spr_o = 10'h02a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11e: + spr_o = 10'h02b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11f: + spr_o = 10'h02c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h130: + spr_o = 10'h02d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h131: + spr_o = 10'h02e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h132: + spr_o = 10'h02f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h133: + spr_o = 10'h030; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h134: + spr_o = 10'h031; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h135: + spr_o = 10'h032; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h136: + spr_o = 10'h033; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h139: + spr_o = 10'h034; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13a: + spr_o = 10'h035; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13b: + spr_o = 10'h036; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13e: + spr_o = 10'h037; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13f: + spr_o = 10'h038; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h150: + spr_o = 10'h039; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h151: + spr_o = 10'h03a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h152: + spr_o = 10'h03b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h153: + spr_o = 10'h03c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h15d: + spr_o = 10'h03d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1be: + spr_o = 10'h03e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1d0: + spr_o = 10'h03f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2c0: + spr_o = 10'h040; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d0: + spr_o = 10'h041; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d1: + spr_o = 10'h042; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h300: + spr_o = 10'h043; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h301: + spr_o = 10'h044; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h302: + spr_o = 10'h045; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h303: + spr_o = 10'h046; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h304: + spr_o = 10'h047; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h305: + spr_o = 10'h048; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h306: + spr_o = 10'h049; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h307: + spr_o = 10'h04a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h308: + spr_o = 10'h04b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30b: + spr_o = 10'h04c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30c: + spr_o = 10'h04d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30d: + spr_o = 10'h04e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30e: + spr_o = 10'h04f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h310: + spr_o = 10'h050; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h311: + spr_o = 10'h051; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h312: + spr_o = 10'h052; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h313: + spr_o = 10'h053; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h314: + spr_o = 10'h054; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h315: + spr_o = 10'h055; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h316: + spr_o = 10'h056; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h317: + spr_o = 10'h057; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h318: + spr_o = 10'h058; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31b: + spr_o = 10'h059; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31c: + spr_o = 10'h05a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31d: + spr_o = 10'h05b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31e: + spr_o = 10'h05c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h320: + spr_o = 10'h05d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h321: + spr_o = 10'h05e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h322: + spr_o = 10'h05f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h323: + spr_o = 10'h060; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h324: + spr_o = 10'h061; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h325: + spr_o = 10'h062; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h326: + spr_o = 10'h063; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h328: + spr_o = 10'h064; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h329: + spr_o = 10'h065; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32a: + spr_o = 10'h066; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32b: + spr_o = 10'h067; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h32f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h330: + spr_o = 10'h069; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h337: + spr_o = 10'h06a; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h350: + spr_o = 10'h06b; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h351: + spr_o = 10'h06c; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h357: + spr_o = 10'h06d; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h380: + spr_o = 10'h06e; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h382: + spr_o = 10'h06f; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h3ff: + spr_o = 10'h070; + endcase + end + always @* begin + if (\initial ) begin end + spr_o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + casez (spr_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h001: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h003: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h008: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h009: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h00d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h011: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h012: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h013: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h016: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01a: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h01b: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01c: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h01d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h030: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h03d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h080: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h081: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h082: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h083: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h088: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h090: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h098: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h099: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h09f: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b0: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0b4: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0ba: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bb: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0bc: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h0be: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h100: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h103: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h10c: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h10d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h110: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h111: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h112: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h113: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11c: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h11f: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h130: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h131: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h132: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h133: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h134: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h135: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h136: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h139: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13a: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h13f: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h150: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h151: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h152: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h153: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h15d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1be: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h1d0: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2c0: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d0: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h2d1: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h300: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h301: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h302: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h303: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h304: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h305: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h306: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h307: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h308: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30c: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h30e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h310: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h311: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h312: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h313: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h314: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h315: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h316: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h317: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h318: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31c: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31d: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h31e: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h320: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h321: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h322: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h323: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h324: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h325: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h326: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h328: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h329: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32a: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h32b: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + 10'h32f: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h330: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h337: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h350: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h351: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h357: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h380: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h382: + spr_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + 10'h3ff: + spr_o_ok = 1'h1; + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.sram4k_0" *) +(* generator = "nMigen" *) +module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *) + reg [8:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *) + reg [63:0] d; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) + input enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *) + wire [63:0] q; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_0_wb__ack; + reg sram4k_0_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + reg \sram4k_0_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_0_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_0_wb__dat_r; + reg [63:0] sram4k_0_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_0_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_0_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" *) + reg wb_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" *) + reg [7:0] we; + assign \$1 = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb; + always @(posedge clk) + sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ; + SPBlock_512W64B8W \U$$0 ( + .a(a), + .clk(clk), + .d(d), + .q(q), + .we(we) + ); + always @* begin + if (\initial ) begin end + wb_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + wb_active = \$1 ; + endcase + end + always @* begin + if (\initial ) begin end + \sram4k_0_wb__ack$next = sram4k_0_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + \sram4k_0_wb__ack$next = wb_active; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sram4k_0_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + a = 9'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + a = sram4k_0_wb__adr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + sram4k_0_wb__dat_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + sram4k_0_wb__dat_r = q; + endcase + endcase + end + always @* begin + if (\initial ) begin end + d = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + d = sram4k_0_wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + we = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" *) + casez (sram4k_0_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" */ + 1'h1: + we = sram4k_0_wb__sel; + endcase + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.sram4k_1" *) +(* generator = "nMigen" *) +module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *) + reg [8:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *) + reg [63:0] d; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) + input enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *) + wire [63:0] q; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_1_wb__ack; + reg sram4k_1_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + reg \sram4k_1_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_1_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_1_wb__dat_r; + reg [63:0] sram4k_1_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_1_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_1_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" *) + reg wb_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" *) + reg [7:0] we; + assign \$1 = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb; + always @(posedge clk) + sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ; + SPBlock_512W64B8W \U$$0 ( + .a(a), + .clk(clk), + .d(d), + .q(q), + .we(we) + ); + always @* begin + if (\initial ) begin end + wb_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + wb_active = \$1 ; + endcase + end + always @* begin + if (\initial ) begin end + \sram4k_1_wb__ack$next = sram4k_1_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + \sram4k_1_wb__ack$next = wb_active; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sram4k_1_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + a = 9'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + a = sram4k_1_wb__adr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + sram4k_1_wb__dat_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + sram4k_1_wb__dat_r = q; + endcase + endcase + end + always @* begin + if (\initial ) begin end + d = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + d = sram4k_1_wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + we = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" *) + casez (sram4k_1_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" */ + 1'h1: + we = sram4k_1_wb__sel; + endcase + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.sram4k_2" *) +(* generator = "nMigen" *) +module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *) + reg [8:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *) + reg [63:0] d; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) + input enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *) + wire [63:0] q; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_2_wb__ack; + reg sram4k_2_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + reg \sram4k_2_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_2_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_2_wb__dat_r; + reg [63:0] sram4k_2_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_2_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_2_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" *) + reg wb_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" *) + reg [7:0] we; + assign \$1 = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb; + always @(posedge clk) + sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ; + SPBlock_512W64B8W \U$$0 ( + .a(a), + .clk(clk), + .d(d), + .q(q), + .we(we) + ); + always @* begin + if (\initial ) begin end + wb_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + wb_active = \$1 ; + endcase + end + always @* begin + if (\initial ) begin end + \sram4k_2_wb__ack$next = sram4k_2_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + \sram4k_2_wb__ack$next = wb_active; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sram4k_2_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + a = 9'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + a = sram4k_2_wb__adr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + sram4k_2_wb__dat_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + sram4k_2_wb__dat_r = q; + endcase + endcase + end + always @* begin + if (\initial ) begin end + d = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + d = sram4k_2_wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + we = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" *) + casez (sram4k_2_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" */ + 1'h1: + we = sram4k_2_wb__sel; + endcase + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.sram4k_3" *) +(* generator = "nMigen" *) +module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *) + reg [8:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *) + reg [63:0] d; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) + input enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *) + wire [63:0] q; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_3_wb__ack; + reg sram4k_3_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + reg \sram4k_3_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_3_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_3_wb__dat_r; + reg [63:0] sram4k_3_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_3_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_3_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" *) + reg wb_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" *) + reg [7:0] we; + assign \$1 = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb; + always @(posedge clk) + sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ; + SPBlock_512W64B8W \U$$0 ( + .a(a), + .clk(clk), + .d(d), + .q(q), + .we(we) + ); + always @* begin + if (\initial ) begin end + wb_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + wb_active = \$1 ; + endcase + end + always @* begin + if (\initial ) begin end + \sram4k_3_wb__ack$next = sram4k_3_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + \sram4k_3_wb__ack$next = wb_active; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sram4k_3_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + a = 9'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + a = sram4k_3_wb__adr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + sram4k_3_wb__dat_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + sram4k_3_wb__dat_r = q; + endcase + endcase + end + always @* begin + if (\initial ) begin end + d = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + d = sram4k_3_wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + we = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" *) + casez (sram4k_3_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" */ + 1'h1: + we = sram4k_3_wb__sel; + endcase + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.src_l" *) +(* generator = "nMigen" *) +module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [3:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [3:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [3:0] q_int = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [3:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [3:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [3:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [3:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [3:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [3:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 4'h0; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.src_l" *) +(* generator = "nMigen" *) +module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [5:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [5:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [5:0] q_int = 6'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [5:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [5:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [5:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [5:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [5:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [5:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 6'h00; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.src_l" *) +(* generator = "nMigen" *) +module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] q_int = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [2:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [2:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [2:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [2:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [2:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 3'h0; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.src_l" *) +(* generator = "nMigen" *) +module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [4:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [4:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [4:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [4:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [4:0] q_int = 5'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [4:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [4:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [4:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [4:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [4:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [4:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 5'h00; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.src_l" *) +(* generator = "nMigen" *) +module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] q_int = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [2:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [2:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [2:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [2:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [2:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 3'h0; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.src_l" *) +(* generator = "nMigen" *) +module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] q_int = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [2:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [2:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [2:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [2:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [2:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 3'h0; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.src_l" *) +(* generator = "nMigen" *) +module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [3:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [3:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [3:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [3:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [3:0] q_int = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [3:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [3:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [3:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [3:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [3:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [3:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 4'h0; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.src_l" *) +(* generator = "nMigen" *) +module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] q_int = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [2:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [2:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [2:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [2:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [2:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 3'h0; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.src_l" *) +(* generator = "nMigen" *) +module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [5:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [5:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [5:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [5:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [5:0] q_int = 6'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [5:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [5:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [5:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [5:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [5:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [5:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 6'h00; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.src_l" *) +(* generator = "nMigen" *) +module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire [2:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire [2:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire [2:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] q_int = 3'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg [2:0] \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output [2:0] q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire [2:0] qlq_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire [2:0] qn_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input [2:0] r_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input [2:0] s_src; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; + assign \$15 = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 3'h0; + endcase + end + assign qlq_src = \$15 ; + assign qn_src = \$13 ; + assign q_src = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.st_active" *) +(* generator = "nMigen" *) +module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_st_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_st_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_st_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_st_active; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_st_active; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_st_active; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_st_active; + assign \$15 = q_st_active | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_st_active; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_st_active; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_st_active; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_st_active = \$15 ; + assign qn_st_active = \$13 ; + assign q_st_active = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.st_done" *) +(* generator = "nMigen" *) +module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_st_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_st_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_st_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_st_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_st_done; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_st_done; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_st_done; + assign \$15 = q_st_done | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_st_done; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_st_done; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_st_done; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_st_done = \$15 ; + assign qn_st_done = \$13 ; + assign q_st_done = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.state" *) +(* generator = "nMigen" *) +module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, msr__data_o, \wen$1 , \data_i$2 , state_nia_wen, \data_i$3 , \data_i$4 , \wen$5 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$10 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [63:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [63:0] \$22 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [63:0] \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] cia__data_o; + reg [63:0] cia__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] cia__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] \data_i$2 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] \data_i$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] \data_i$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] msr__data_o; + reg [63:0] msr__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] msr__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_0_cia0__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_cia0__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_0_d_wr10__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_d_wr10__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_0_msr0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_0_msr0__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_msr0__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_msr0__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_0_nia0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_nia0__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_0_sv0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_0_sv0__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_sv0__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_sv0__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_1_cia1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_cia1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_1_d_wr11__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_d_wr11__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_1_msr1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_1_msr1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_msr1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_msr1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_1_nia1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_nia1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_1_sv1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_1_sv1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_sv1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_sv1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_2_cia2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_cia2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_2_d_wr12__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_d_wr12__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_2_msr2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_2_msr2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_msr2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_msr2__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_2_nia2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_nia2__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_2_sv2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_2_sv2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_sv2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_sv2__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] ren_delay = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$12 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$12$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$19 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$19$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] state_nia_wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [63:0] sv__data_o; + reg [63:0] sv__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] sv__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] \wen$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] \wen$5 ; + assign \$10 = reg_0_cia0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$8 ; + assign \$13 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$12 ; + assign \$15 = reg_1_msr1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_msr2__data_o; + assign \$17 = reg_0_msr0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$15 ; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$19 ; + assign \$22 = reg_1_sv1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_sv2__data_o; + assign \$24 = reg_0_sv0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$22 ; + assign \$6 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) ren_delay; + assign \$8 = reg_1_cia1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_cia2__data_o; + always @(posedge coresync_clk) + \ren_delay$19 <= \ren_delay$19$next ; + always @(posedge coresync_clk) + \ren_delay$12 <= \ren_delay$12$next ; + always @(posedge coresync_clk) + ren_delay <= \ren_delay$next ; + \reg_0$135 reg_0 ( + .cia0__data_o(reg_0_cia0__data_o), + .cia0__ren(reg_0_cia0__ren), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .d_wr10__data_i(reg_0_d_wr10__data_i), + .d_wr10__wen(reg_0_d_wr10__wen), + .msr0__data_i(reg_0_msr0__data_i), + .msr0__data_o(reg_0_msr0__data_o), + .msr0__ren(reg_0_msr0__ren), + .msr0__wen(reg_0_msr0__wen), + .nia0__data_i(reg_0_nia0__data_i), + .nia0__wen(reg_0_nia0__wen), + .sv0__data_i(reg_0_sv0__data_i), + .sv0__data_o(reg_0_sv0__data_o), + .sv0__ren(reg_0_sv0__ren), + .sv0__wen(reg_0_sv0__wen) + ); + \reg_1$136 reg_1 ( + .cia1__data_o(reg_1_cia1__data_o), + .cia1__ren(reg_1_cia1__ren), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .d_wr11__data_i(reg_1_d_wr11__data_i), + .d_wr11__wen(reg_1_d_wr11__wen), + .msr1__data_i(reg_1_msr1__data_i), + .msr1__data_o(reg_1_msr1__data_o), + .msr1__ren(reg_1_msr1__ren), + .msr1__wen(reg_1_msr1__wen), + .nia1__data_i(reg_1_nia1__data_i), + .nia1__wen(reg_1_nia1__wen), + .sv1__data_i(reg_1_sv1__data_i), + .sv1__data_o(reg_1_sv1__data_o), + .sv1__ren(reg_1_sv1__ren), + .sv1__wen(reg_1_sv1__wen) + ); + \reg_2$137 reg_2 ( + .cia2__data_o(reg_2_cia2__data_o), + .cia2__ren(reg_2_cia2__ren), + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .d_wr12__data_i(reg_2_d_wr12__data_i), + .d_wr12__wen(reg_2_d_wr12__wen), + .msr2__data_i(reg_2_msr2__data_i), + .msr2__data_o(reg_2_msr2__data_o), + .msr2__ren(reg_2_msr2__ren), + .msr2__wen(reg_2_msr2__wen), + .nia2__data_i(reg_2_nia2__data_i), + .nia2__wen(reg_2_nia2__wen), + .sv2__data_i(reg_2_sv2__data_i), + .sv2__data_o(reg_2_sv2__data_o), + .sv2__ren(reg_2_sv2__ren), + .sv2__wen(reg_2_sv2__wen) + ); + always @* begin + if (\initial ) begin end + \ren_delay$19$next = sv__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$19$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + sv__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$20 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + sv__data_o = \$24 ; + endcase + end + always @* begin + if (\initial ) begin end + \ren_delay$next = cia__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + cia__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$6 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + cia__data_o = \$10 ; + endcase + end + always @* begin + if (\initial ) begin end + \ren_delay$12$next = msr__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$12$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + msr__data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + msr__data_o = \$17 ; + endcase + end + assign reg_2_d_wr12__data_i = data_i; + assign reg_1_d_wr11__data_i = data_i; + assign reg_0_d_wr10__data_i = data_i; + assign { reg_2_d_wr12__wen, reg_1_d_wr11__wen, reg_0_d_wr10__wen } = wen; + assign reg_2_sv2__data_i = \data_i$2 ; + assign reg_1_sv1__data_i = \data_i$2 ; + assign reg_0_sv0__data_i = \data_i$2 ; + assign { reg_2_sv2__wen, reg_1_sv1__wen, reg_0_sv0__wen } = \wen$1 ; + assign reg_2_msr2__data_i = \data_i$4 ; + assign reg_1_msr1__data_i = \data_i$4 ; + assign reg_0_msr0__data_i = \data_i$4 ; + assign { reg_2_msr2__wen, reg_1_msr1__wen, reg_0_msr0__wen } = \wen$5 ; + assign reg_2_nia2__data_i = \data_i$3 ; + assign reg_1_nia1__data_i = \data_i$3 ; + assign reg_0_nia0__data_i = \data_i$3 ; + assign { reg_2_nia2__wen, reg_1_nia1__wen, reg_0_nia0__wen } = state_nia_wen; + assign { reg_2_sv2__ren, reg_1_sv1__ren, reg_0_sv0__ren } = sv__ren; + assign { reg_2_msr2__ren, reg_1_msr1__ren, reg_0_msr0__ren } = msr__ren; + assign { reg_2_cia2__ren, reg_1_cia1__ren, reg_0_cia0__ren } = cia__ren; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.sto_l" *) +(* generator = "nMigen" *) +module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_sto; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_sto; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_sto; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_sto; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_sto; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_sto; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_sto; + assign \$15 = q_sto | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_sto; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_sto; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_sto; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_sto = \$15 ; + assign qn_sto = \$13 ; + assign q_sto = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer" *) +(* top = 1 *) +(* generator = "nMigen" *) +module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, pll_lck_o, pc_i); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tck; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tdi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + output TAP_bus__tdo; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) + output busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) + input [1:0] clk_sel_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *) + input core_bigendian_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [44:0] dbus__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input [1:0] dbus__bte; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input [2:0] dbus__cti; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input [63:0] dbus__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [63:0] dbus__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [7:0] dbus__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_2__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input ibus__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output [44:0] ibus__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input [1:0] ibus__bte; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input [2:0] ibus__cti; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output ibus__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input [63:0] ibus__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input [63:0] ibus__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input ibus__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output [7:0] ibus__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output ibus__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input ibus__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + output icp_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [27:0] icp_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + output [31:0] icp_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [31:0] icp_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [3:0] icp_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + output ics_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input [27:0] ics_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + output [31:0] ics_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input [31:0] ics_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input [3:0] ics_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *) + input [15:0] int_level_i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + input jtag_wb__ack; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [29:0] jtag_wb__adr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__cyc; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + input [31:0] jtag_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [31:0] jtag_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + input jtag_wb__err; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [3:0] jtag_wb__sel; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__stb; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) + input memerr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_clk__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_clk__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_cs_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_cs_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_miso__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_miso__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_mosi__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_mosi__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_scl__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_scl__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] pc_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input pc_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *) + output [63:0] pc_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1159" *) + output pll_18_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *) + wire pll_clk_24_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *) + wire pll_clk_pll_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *) + output pll_lck_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *) + wire pll_pll_18_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *) + wire pllclk_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *) + wire pllclk_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ba_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ba_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ba_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ba_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cas_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cas_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cke__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cke__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_clock__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_clock__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cs_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cs_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dm_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dm_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dm_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dm_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ras_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ras_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_we_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_we_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_0_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_0_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_0_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_0_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_0_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_1_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_1_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_1_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_1_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_1_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_2_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_2_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_2_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_2_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_2_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_3_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_3_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_3_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_3_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_3_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + wire ti_coresync_clk; + pll pll ( + .clk_24_i(pll_clk_24_i), + .clk_pll_o(pll_clk_pll_o), + .clk_sel_i(clk_sel_i), + .pll_18_o(pll_pll_18_o), + .pll_lck_o(pll_lck_o) + ); + ti ti ( + .TAP_bus__tck(TAP_bus__tck), + .TAP_bus__tdi(TAP_bus__tdi), + .TAP_bus__tdo(TAP_bus__tdo), + .TAP_bus__tms(TAP_bus__tms), + .busy_o(busy_o), + .clk(clk), + .core_bigendian_i(core_bigendian_i), + .coresync_clk(ti_coresync_clk), + .dbus__ack(dbus__ack), + .dbus__adr(dbus__adr), + .dbus__cyc(dbus__cyc), + .dbus__dat_r(dbus__dat_r), + .dbus__dat_w(dbus__dat_w), + .dbus__err(dbus__err), + .dbus__sel(dbus__sel), + .dbus__stb(dbus__stb), + .dbus__we(dbus__we), + .eint_0__core__i(eint_0__core__i), + .eint_0__pad__i(eint_0__pad__i), + .eint_1__core__i(eint_1__core__i), + .eint_1__pad__i(eint_1__pad__i), + .eint_2__core__i(eint_2__core__i), + .eint_2__pad__i(eint_2__pad__i), + .gpio_e10__core__i(gpio_e10__core__i), + .gpio_e10__core__o(gpio_e10__core__o), + .gpio_e10__core__oe(gpio_e10__core__oe), + .gpio_e10__pad__i(gpio_e10__pad__i), + .gpio_e10__pad__o(gpio_e10__pad__o), + .gpio_e10__pad__oe(gpio_e10__pad__oe), + .gpio_e11__core__i(gpio_e11__core__i), + .gpio_e11__core__o(gpio_e11__core__o), + .gpio_e11__core__oe(gpio_e11__core__oe), + .gpio_e11__pad__i(gpio_e11__pad__i), + .gpio_e11__pad__o(gpio_e11__pad__o), + .gpio_e11__pad__oe(gpio_e11__pad__oe), + .gpio_e12__core__i(gpio_e12__core__i), + .gpio_e12__core__o(gpio_e12__core__o), + .gpio_e12__core__oe(gpio_e12__core__oe), + .gpio_e12__pad__i(gpio_e12__pad__i), + .gpio_e12__pad__o(gpio_e12__pad__o), + .gpio_e12__pad__oe(gpio_e12__pad__oe), + .gpio_e13__core__i(gpio_e13__core__i), + .gpio_e13__core__o(gpio_e13__core__o), + .gpio_e13__core__oe(gpio_e13__core__oe), + .gpio_e13__pad__i(gpio_e13__pad__i), + .gpio_e13__pad__o(gpio_e13__pad__o), + .gpio_e13__pad__oe(gpio_e13__pad__oe), + .gpio_e14__core__i(gpio_e14__core__i), + .gpio_e14__core__o(gpio_e14__core__o), + .gpio_e14__core__oe(gpio_e14__core__oe), + .gpio_e14__pad__i(gpio_e14__pad__i), + .gpio_e14__pad__o(gpio_e14__pad__o), + .gpio_e14__pad__oe(gpio_e14__pad__oe), + .gpio_e15__core__i(gpio_e15__core__i), + .gpio_e15__core__o(gpio_e15__core__o), + .gpio_e15__core__oe(gpio_e15__core__oe), + .gpio_e15__pad__i(gpio_e15__pad__i), + .gpio_e15__pad__o(gpio_e15__pad__o), + .gpio_e15__pad__oe(gpio_e15__pad__oe), + .gpio_e8__core__i(gpio_e8__core__i), + .gpio_e8__core__o(gpio_e8__core__o), + .gpio_e8__core__oe(gpio_e8__core__oe), + .gpio_e8__pad__i(gpio_e8__pad__i), + .gpio_e8__pad__o(gpio_e8__pad__o), + .gpio_e8__pad__oe(gpio_e8__pad__oe), + .gpio_e9__core__i(gpio_e9__core__i), + .gpio_e9__core__o(gpio_e9__core__o), + .gpio_e9__core__oe(gpio_e9__core__oe), + .gpio_e9__pad__i(gpio_e9__pad__i), + .gpio_e9__pad__o(gpio_e9__pad__o), + .gpio_e9__pad__oe(gpio_e9__pad__oe), + .gpio_s0__core__i(gpio_s0__core__i), + .gpio_s0__core__o(gpio_s0__core__o), + .gpio_s0__core__oe(gpio_s0__core__oe), + .gpio_s0__pad__i(gpio_s0__pad__i), + .gpio_s0__pad__o(gpio_s0__pad__o), + .gpio_s0__pad__oe(gpio_s0__pad__oe), + .gpio_s1__core__i(gpio_s1__core__i), + .gpio_s1__core__o(gpio_s1__core__o), + .gpio_s1__core__oe(gpio_s1__core__oe), + .gpio_s1__pad__i(gpio_s1__pad__i), + .gpio_s1__pad__o(gpio_s1__pad__o), + .gpio_s1__pad__oe(gpio_s1__pad__oe), + .gpio_s2__core__i(gpio_s2__core__i), + .gpio_s2__core__o(gpio_s2__core__o), + .gpio_s2__core__oe(gpio_s2__core__oe), + .gpio_s2__pad__i(gpio_s2__pad__i), + .gpio_s2__pad__o(gpio_s2__pad__o), + .gpio_s2__pad__oe(gpio_s2__pad__oe), + .gpio_s3__core__i(gpio_s3__core__i), + .gpio_s3__core__o(gpio_s3__core__o), + .gpio_s3__core__oe(gpio_s3__core__oe), + .gpio_s3__pad__i(gpio_s3__pad__i), + .gpio_s3__pad__o(gpio_s3__pad__o), + .gpio_s3__pad__oe(gpio_s3__pad__oe), + .gpio_s4__core__i(gpio_s4__core__i), + .gpio_s4__core__o(gpio_s4__core__o), + .gpio_s4__core__oe(gpio_s4__core__oe), + .gpio_s4__pad__i(gpio_s4__pad__i), + .gpio_s4__pad__o(gpio_s4__pad__o), + .gpio_s4__pad__oe(gpio_s4__pad__oe), + .gpio_s5__core__i(gpio_s5__core__i), + .gpio_s5__core__o(gpio_s5__core__o), + .gpio_s5__core__oe(gpio_s5__core__oe), + .gpio_s5__pad__i(gpio_s5__pad__i), + .gpio_s5__pad__o(gpio_s5__pad__o), + .gpio_s5__pad__oe(gpio_s5__pad__oe), + .gpio_s6__core__i(gpio_s6__core__i), + .gpio_s6__core__o(gpio_s6__core__o), + .gpio_s6__core__oe(gpio_s6__core__oe), + .gpio_s6__pad__i(gpio_s6__pad__i), + .gpio_s6__pad__o(gpio_s6__pad__o), + .gpio_s6__pad__oe(gpio_s6__pad__oe), + .gpio_s7__core__i(gpio_s7__core__i), + .gpio_s7__core__o(gpio_s7__core__o), + .gpio_s7__core__oe(gpio_s7__core__oe), + .gpio_s7__pad__i(gpio_s7__pad__i), + .gpio_s7__pad__o(gpio_s7__pad__o), + .gpio_s7__pad__oe(gpio_s7__pad__oe), + .ibus__ack(ibus__ack), + .ibus__adr(ibus__adr), + .ibus__cyc(ibus__cyc), + .ibus__dat_r(ibus__dat_r), + .ibus__err(ibus__err), + .ibus__sel(ibus__sel), + .ibus__stb(ibus__stb), + .icp_wb__ack(icp_wb__ack), + .icp_wb__adr(icp_wb__adr), + .icp_wb__cyc(icp_wb__cyc), + .icp_wb__dat_r(icp_wb__dat_r), + .icp_wb__dat_w(icp_wb__dat_w), + .icp_wb__sel(icp_wb__sel), + .icp_wb__stb(icp_wb__stb), + .icp_wb__we(icp_wb__we), + .ics_wb__ack(ics_wb__ack), + .ics_wb__adr(ics_wb__adr), + .ics_wb__cyc(ics_wb__cyc), + .ics_wb__dat_r(ics_wb__dat_r), + .ics_wb__dat_w(ics_wb__dat_w), + .ics_wb__stb(ics_wb__stb), + .ics_wb__we(ics_wb__we), + .int_level_i(int_level_i), + .jtag_wb__ack(jtag_wb__ack), + .jtag_wb__adr(jtag_wb__adr), + .jtag_wb__cyc(jtag_wb__cyc), + .jtag_wb__dat_r(jtag_wb__dat_r), + .jtag_wb__dat_w(jtag_wb__dat_w), + .jtag_wb__sel(jtag_wb__sel), + .jtag_wb__stb(jtag_wb__stb), + .jtag_wb__we(jtag_wb__we), + .mspi0_clk__core__o(mspi0_clk__core__o), + .mspi0_clk__pad__o(mspi0_clk__pad__o), + .mspi0_cs_n__core__o(mspi0_cs_n__core__o), + .mspi0_cs_n__pad__o(mspi0_cs_n__pad__o), + .mspi0_miso__core__i(mspi0_miso__core__i), + .mspi0_miso__pad__i(mspi0_miso__pad__i), + .mspi0_mosi__core__o(mspi0_mosi__core__o), + .mspi0_mosi__pad__o(mspi0_mosi__pad__o), + .mtwi_scl__core__o(mtwi_scl__core__o), + .mtwi_scl__pad__o(mtwi_scl__pad__o), + .mtwi_sda__core__i(mtwi_sda__core__i), + .mtwi_sda__core__o(mtwi_sda__core__o), + .mtwi_sda__core__oe(mtwi_sda__core__oe), + .mtwi_sda__pad__i(mtwi_sda__pad__i), + .mtwi_sda__pad__o(mtwi_sda__pad__o), + .mtwi_sda__pad__oe(mtwi_sda__pad__oe), + .pc_i(pc_i), + .pc_i_ok(pc_i_ok), + .pc_o(pc_o), + .rst(rst), + .sdr_a_0__core__o(sdr_a_0__core__o), + .sdr_a_0__pad__o(sdr_a_0__pad__o), + .sdr_a_10__core__o(sdr_a_10__core__o), + .sdr_a_10__pad__o(sdr_a_10__pad__o), + .sdr_a_11__core__o(sdr_a_11__core__o), + .sdr_a_11__pad__o(sdr_a_11__pad__o), + .sdr_a_12__core__o(sdr_a_12__core__o), + .sdr_a_12__pad__o(sdr_a_12__pad__o), + .sdr_a_1__core__o(sdr_a_1__core__o), + .sdr_a_1__pad__o(sdr_a_1__pad__o), + .sdr_a_2__core__o(sdr_a_2__core__o), + .sdr_a_2__pad__o(sdr_a_2__pad__o), + .sdr_a_3__core__o(sdr_a_3__core__o), + .sdr_a_3__pad__o(sdr_a_3__pad__o), + .sdr_a_4__core__o(sdr_a_4__core__o), + .sdr_a_4__pad__o(sdr_a_4__pad__o), + .sdr_a_5__core__o(sdr_a_5__core__o), + .sdr_a_5__pad__o(sdr_a_5__pad__o), + .sdr_a_6__core__o(sdr_a_6__core__o), + .sdr_a_6__pad__o(sdr_a_6__pad__o), + .sdr_a_7__core__o(sdr_a_7__core__o), + .sdr_a_7__pad__o(sdr_a_7__pad__o), + .sdr_a_8__core__o(sdr_a_8__core__o), + .sdr_a_8__pad__o(sdr_a_8__pad__o), + .sdr_a_9__core__o(sdr_a_9__core__o), + .sdr_a_9__pad__o(sdr_a_9__pad__o), + .sdr_ba_0__core__o(sdr_ba_0__core__o), + .sdr_ba_0__pad__o(sdr_ba_0__pad__o), + .sdr_ba_1__core__o(sdr_ba_1__core__o), + .sdr_ba_1__pad__o(sdr_ba_1__pad__o), + .sdr_cas_n__core__o(sdr_cas_n__core__o), + .sdr_cas_n__pad__o(sdr_cas_n__pad__o), + .sdr_cke__core__o(sdr_cke__core__o), + .sdr_cke__pad__o(sdr_cke__pad__o), + .sdr_clock__core__o(sdr_clock__core__o), + .sdr_clock__pad__o(sdr_clock__pad__o), + .sdr_cs_n__core__o(sdr_cs_n__core__o), + .sdr_cs_n__pad__o(sdr_cs_n__pad__o), + .sdr_dm_0__core__o(sdr_dm_0__core__o), + .sdr_dm_0__pad__o(sdr_dm_0__pad__o), + .sdr_dm_1__core__o(sdr_dm_1__core__o), + .sdr_dm_1__pad__o(sdr_dm_1__pad__o), + .sdr_dq_0__core__i(sdr_dq_0__core__i), + .sdr_dq_0__core__o(sdr_dq_0__core__o), + .sdr_dq_0__core__oe(sdr_dq_0__core__oe), + .sdr_dq_0__pad__i(sdr_dq_0__pad__i), + .sdr_dq_0__pad__o(sdr_dq_0__pad__o), + .sdr_dq_0__pad__oe(sdr_dq_0__pad__oe), + .sdr_dq_10__core__i(sdr_dq_10__core__i), + .sdr_dq_10__core__o(sdr_dq_10__core__o), + .sdr_dq_10__core__oe(sdr_dq_10__core__oe), + .sdr_dq_10__pad__i(sdr_dq_10__pad__i), + .sdr_dq_10__pad__o(sdr_dq_10__pad__o), + .sdr_dq_10__pad__oe(sdr_dq_10__pad__oe), + .sdr_dq_11__core__i(sdr_dq_11__core__i), + .sdr_dq_11__core__o(sdr_dq_11__core__o), + .sdr_dq_11__core__oe(sdr_dq_11__core__oe), + .sdr_dq_11__pad__i(sdr_dq_11__pad__i), + .sdr_dq_11__pad__o(sdr_dq_11__pad__o), + .sdr_dq_11__pad__oe(sdr_dq_11__pad__oe), + .sdr_dq_12__core__i(sdr_dq_12__core__i), + .sdr_dq_12__core__o(sdr_dq_12__core__o), + .sdr_dq_12__core__oe(sdr_dq_12__core__oe), + .sdr_dq_12__pad__i(sdr_dq_12__pad__i), + .sdr_dq_12__pad__o(sdr_dq_12__pad__o), + .sdr_dq_12__pad__oe(sdr_dq_12__pad__oe), + .sdr_dq_13__core__i(sdr_dq_13__core__i), + .sdr_dq_13__core__o(sdr_dq_13__core__o), + .sdr_dq_13__core__oe(sdr_dq_13__core__oe), + .sdr_dq_13__pad__i(sdr_dq_13__pad__i), + .sdr_dq_13__pad__o(sdr_dq_13__pad__o), + .sdr_dq_13__pad__oe(sdr_dq_13__pad__oe), + .sdr_dq_14__core__i(sdr_dq_14__core__i), + .sdr_dq_14__core__o(sdr_dq_14__core__o), + .sdr_dq_14__core__oe(sdr_dq_14__core__oe), + .sdr_dq_14__pad__i(sdr_dq_14__pad__i), + .sdr_dq_14__pad__o(sdr_dq_14__pad__o), + .sdr_dq_14__pad__oe(sdr_dq_14__pad__oe), + .sdr_dq_15__core__i(sdr_dq_15__core__i), + .sdr_dq_15__core__o(sdr_dq_15__core__o), + .sdr_dq_15__core__oe(sdr_dq_15__core__oe), + .sdr_dq_15__pad__i(sdr_dq_15__pad__i), + .sdr_dq_15__pad__o(sdr_dq_15__pad__o), + .sdr_dq_15__pad__oe(sdr_dq_15__pad__oe), + .sdr_dq_1__core__i(sdr_dq_1__core__i), + .sdr_dq_1__core__o(sdr_dq_1__core__o), + .sdr_dq_1__core__oe(sdr_dq_1__core__oe), + .sdr_dq_1__pad__i(sdr_dq_1__pad__i), + .sdr_dq_1__pad__o(sdr_dq_1__pad__o), + .sdr_dq_1__pad__oe(sdr_dq_1__pad__oe), + .sdr_dq_2__core__i(sdr_dq_2__core__i), + .sdr_dq_2__core__o(sdr_dq_2__core__o), + .sdr_dq_2__core__oe(sdr_dq_2__core__oe), + .sdr_dq_2__pad__i(sdr_dq_2__pad__i), + .sdr_dq_2__pad__o(sdr_dq_2__pad__o), + .sdr_dq_2__pad__oe(sdr_dq_2__pad__oe), + .sdr_dq_3__core__i(sdr_dq_3__core__i), + .sdr_dq_3__core__o(sdr_dq_3__core__o), + .sdr_dq_3__core__oe(sdr_dq_3__core__oe), + .sdr_dq_3__pad__i(sdr_dq_3__pad__i), + .sdr_dq_3__pad__o(sdr_dq_3__pad__o), + .sdr_dq_3__pad__oe(sdr_dq_3__pad__oe), + .sdr_dq_4__core__i(sdr_dq_4__core__i), + .sdr_dq_4__core__o(sdr_dq_4__core__o), + .sdr_dq_4__core__oe(sdr_dq_4__core__oe), + .sdr_dq_4__pad__i(sdr_dq_4__pad__i), + .sdr_dq_4__pad__o(sdr_dq_4__pad__o), + .sdr_dq_4__pad__oe(sdr_dq_4__pad__oe), + .sdr_dq_5__core__i(sdr_dq_5__core__i), + .sdr_dq_5__core__o(sdr_dq_5__core__o), + .sdr_dq_5__core__oe(sdr_dq_5__core__oe), + .sdr_dq_5__pad__i(sdr_dq_5__pad__i), + .sdr_dq_5__pad__o(sdr_dq_5__pad__o), + .sdr_dq_5__pad__oe(sdr_dq_5__pad__oe), + .sdr_dq_6__core__i(sdr_dq_6__core__i), + .sdr_dq_6__core__o(sdr_dq_6__core__o), + .sdr_dq_6__core__oe(sdr_dq_6__core__oe), + .sdr_dq_6__pad__i(sdr_dq_6__pad__i), + .sdr_dq_6__pad__o(sdr_dq_6__pad__o), + .sdr_dq_6__pad__oe(sdr_dq_6__pad__oe), + .sdr_dq_7__core__i(sdr_dq_7__core__i), + .sdr_dq_7__core__o(sdr_dq_7__core__o), + .sdr_dq_7__core__oe(sdr_dq_7__core__oe), + .sdr_dq_7__pad__i(sdr_dq_7__pad__i), + .sdr_dq_7__pad__o(sdr_dq_7__pad__o), + .sdr_dq_7__pad__oe(sdr_dq_7__pad__oe), + .sdr_dq_8__core__i(sdr_dq_8__core__i), + .sdr_dq_8__core__o(sdr_dq_8__core__o), + .sdr_dq_8__core__oe(sdr_dq_8__core__oe), + .sdr_dq_8__pad__i(sdr_dq_8__pad__i), + .sdr_dq_8__pad__o(sdr_dq_8__pad__o), + .sdr_dq_8__pad__oe(sdr_dq_8__pad__oe), + .sdr_dq_9__core__i(sdr_dq_9__core__i), + .sdr_dq_9__core__o(sdr_dq_9__core__o), + .sdr_dq_9__core__oe(sdr_dq_9__core__oe), + .sdr_dq_9__pad__i(sdr_dq_9__pad__i), + .sdr_dq_9__pad__o(sdr_dq_9__pad__o), + .sdr_dq_9__pad__oe(sdr_dq_9__pad__oe), + .sdr_ras_n__core__o(sdr_ras_n__core__o), + .sdr_ras_n__pad__o(sdr_ras_n__pad__o), + .sdr_we_n__core__o(sdr_we_n__core__o), + .sdr_we_n__pad__o(sdr_we_n__pad__o), + .sram4k_0_wb__ack(sram4k_0_wb__ack), + .sram4k_0_wb__adr(sram4k_0_wb__adr), + .sram4k_0_wb__cyc(sram4k_0_wb__cyc), + .sram4k_0_wb__dat_r(sram4k_0_wb__dat_r), + .sram4k_0_wb__dat_w(sram4k_0_wb__dat_w), + .sram4k_0_wb__sel(sram4k_0_wb__sel), + .sram4k_0_wb__stb(sram4k_0_wb__stb), + .sram4k_0_wb__we(sram4k_0_wb__we), + .sram4k_1_wb__ack(sram4k_1_wb__ack), + .sram4k_1_wb__adr(sram4k_1_wb__adr), + .sram4k_1_wb__cyc(sram4k_1_wb__cyc), + .sram4k_1_wb__dat_r(sram4k_1_wb__dat_r), + .sram4k_1_wb__dat_w(sram4k_1_wb__dat_w), + .sram4k_1_wb__sel(sram4k_1_wb__sel), + .sram4k_1_wb__stb(sram4k_1_wb__stb), + .sram4k_1_wb__we(sram4k_1_wb__we), + .sram4k_2_wb__ack(sram4k_2_wb__ack), + .sram4k_2_wb__adr(sram4k_2_wb__adr), + .sram4k_2_wb__cyc(sram4k_2_wb__cyc), + .sram4k_2_wb__dat_r(sram4k_2_wb__dat_r), + .sram4k_2_wb__dat_w(sram4k_2_wb__dat_w), + .sram4k_2_wb__sel(sram4k_2_wb__sel), + .sram4k_2_wb__stb(sram4k_2_wb__stb), + .sram4k_2_wb__we(sram4k_2_wb__we), + .sram4k_3_wb__ack(sram4k_3_wb__ack), + .sram4k_3_wb__adr(sram4k_3_wb__adr), + .sram4k_3_wb__cyc(sram4k_3_wb__cyc), + .sram4k_3_wb__dat_r(sram4k_3_wb__dat_r), + .sram4k_3_wb__dat_w(sram4k_3_wb__dat_w), + .sram4k_3_wb__sel(sram4k_3_wb__sel), + .sram4k_3_wb__stb(sram4k_3_wb__stb), + .sram4k_3_wb__we(sram4k_3_wb__we) + ); + assign ti_coresync_clk = pll_clk_pll_o; + assign pllclk_rst = rst; + assign pll_18_o = pll_pll_18_o; + assign pll_clk_24_i = clk; + assign pllclk_clk = pll_clk_pll_o; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti" *) +(* generator = "nMigen" *) +module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + wire \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) + wire [64:0] \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) + wire [64:0] \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *) + wire [31:0] \$107 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) + wire [6:0] \$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *) + wire [31:0] \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) + wire [64:0] \$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) + wire [64:0] \$113 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) + wire [6:0] \$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$118 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$122 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$126 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + wire \$130 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$132 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$134 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) + wire [7:0] \$136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) + wire [7:0] \$137 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) + wire [7:0] \$139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) + wire [7:0] \$140 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$142 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$144 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$146 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$148 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$150 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$152 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + wire \$154 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + wire \$156 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) + wire \$158 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$160 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$162 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$164 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + wire \$166 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$168 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$170 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$172 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$174 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$176 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$178 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$180 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$182 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$184 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$186 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$188 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$190 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$192 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$194 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$196 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$198 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$200 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$202 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$204 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$206 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$208 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) + wire [2:0] \$209 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$212 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$214 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$216 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$218 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$220 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$222 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + wire \$224 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$226 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$228 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$230 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$232 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$234 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$236 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$238 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$240 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$242 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) + wire [2:0] \$243 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + wire \$246 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + wire \$248 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + wire \$250 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$252 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$254 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$256 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$258 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$260 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$262 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" *) + wire \$264 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) + wire [63:0] \$266 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) + wire \$268 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) + wire [2:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + wire \$270 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + wire \$272 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] \$274 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] \$276 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) + wire [64:0] \$278 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) + wire [64:0] \$279 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) + wire [2:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) + wire [64:0] \$281 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) + wire [64:0] \$282 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] \$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + wire \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + wire \$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + wire \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + wire \$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + wire \$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + wire \$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + wire \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) + wire \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tck; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tdi; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + output TAP_bus__tdo; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tms; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) + output busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + reg [7:0] core_asmcode = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + reg [7:0] \core_asmcode$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *) + input core_bigendian_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *) + reg \core_bigendian_i$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *) + reg \core_bigendian_i$10$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] core_cia__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [2:0] core_cia__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + reg [63:0] core_core_core_cia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + reg [63:0] \core_core_core_cia$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [7:0] core_core_core_cr_rd = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [7:0] \core_core_core_cr_rd$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_core_cr_rd_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_core_cr_rd_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [7:0] core_core_core_cr_wr = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [7:0] \core_core_core_cr_wr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$3 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$4 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$9 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$9$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + reg \core_core_core_exc_$signal$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + reg [13:0] core_core_core_fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + reg [13:0] \core_core_core_fn_unit$next ; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + reg [1:0] core_core_core_input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + reg [1:0] \core_core_core_input_carry$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + reg [31:0] core_core_core_insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + reg [31:0] \core_core_core_insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + reg [6:0] core_core_core_insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + reg [6:0] \core_core_core_insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + reg core_core_core_is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + reg \core_core_core_is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + reg [63:0] core_core_core_msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + reg [63:0] \core_core_core_msr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_core_oe = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_core_oe$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_core_oe_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_core_oe_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_core_rc = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_core_rc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_core_rc_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_core_rc_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + reg [12:0] core_core_core_trapaddr = 13'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + reg [12:0] \core_core_core_trapaddr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + reg [7:0] core_core_core_traptype = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + reg [7:0] \core_core_core_traptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] core_core_cr_in1 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_cr_in1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_cr_in1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_cr_in1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] core_core_cr_in2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_cr_in2$1 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_cr_in2$1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_cr_in2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_cr_in2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_cr_in2_ok$2 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_cr_in2_ok$2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_cr_in2_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] core_core_cr_out = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_cr_out$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_cr_wr_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_cr_wr_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + reg [6:0] core_core_dststep = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + reg [6:0] \core_core_dststep$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] core_core_ea = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_ea$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [2:0] core_core_fast1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [2:0] \core_core_fast1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_fast1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [2:0] core_core_fast2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [2:0] \core_core_fast2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_fast2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_fast2_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [2:0] core_core_fasto1 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [2:0] \core_core_fasto1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [2:0] core_core_fasto2 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [2:0] \core_core_fasto2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + reg core_core_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + reg \core_core_lk$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + reg [6:0] core_core_maxvl = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + reg [6:0] \core_core_maxvl$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + reg [63:0] core_core_pc = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + reg [63:0] \core_core_pc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] core_core_reg1 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_reg1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_reg1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_reg1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] core_core_reg2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_reg2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_reg2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_reg2_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] core_core_reg3 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_reg3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_reg3_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_reg3_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] core_core_rego = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [6:0] \core_core_rego$next ; + (* enum_base_type = "SPR" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [9:0] core_core_spr1 = 10'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [9:0] \core_core_spr1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_core_spr1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_core_spr1_ok$next ; + (* enum_base_type = "SPR" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [9:0] core_core_spro = 10'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg [9:0] \core_core_spro$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + reg [6:0] core_core_srcstep = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + reg [6:0] \core_core_srcstep$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + reg [1:0] core_core_subvl = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + reg [1:0] \core_core_subvl$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + reg [1:0] core_core_svstep = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + reg [1:0] \core_core_svstep$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) + wire core_core_terminate_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + reg [6:0] core_core_vl = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + reg [6:0] \core_core_vl$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + reg [2:0] core_core_xer_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + reg [2:0] \core_core_xer_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *) + wire core_corebusy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + wire core_coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_cr_out_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_cr_out_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire core_cu_ad__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire core_cu_ad__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire core_cu_st__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + wire core_cu_st__rel_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] core_data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] \core_data_i$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + reg [63:0] core_dec = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + reg [63:0] \core_dec$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [4:0] core_dmi__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] core_dmi__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg core_dmi__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_ea_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_ea_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + reg core_eint = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + reg \core_eint$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_fasto1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_fasto1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_fasto2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_fasto2_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [31:0] core_full_rd2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [7:0] core_full_rd2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [5:0] core_full_rd__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [2:0] core_full_rd__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [2:0] core_issue__addr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [2:0] \core_issue__addr$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [63:0] core_issue__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] core_issue__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg core_issue__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg core_issue__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" *) + reg core_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" *) + reg core_ivalid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + reg [63:0] core_msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + reg [63:0] \core_msr$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] core_msr__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [2:0] core_msr__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *) + reg [31:0] core_raw_insn_i = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *) + reg [31:0] \core_raw_insn_i$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_rego_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_rego_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg core_spro_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + reg \core_spro_ok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] core_state_nia_wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) + reg core_stopped_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] core_sv__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [2:0] core_sv__ren; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *) + reg core_sv_a_nz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *) + reg \core_sv_a_nz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + wire core_wb_dcache_en; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [2:0] core_wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [2:0] \core_wen$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + reg core_xer_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + reg \core_xer_out$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg cu_st__rel_o_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \cu_st__rel_o_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire cu_st__rel_o_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + reg [6:0] cur_cur_dststep = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + reg [6:0] \cur_cur_dststep$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + reg [6:0] cur_cur_maxvl = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + reg [6:0] \cur_cur_maxvl$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + reg [6:0] cur_cur_srcstep = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + reg [6:0] \cur_cur_srcstep$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + reg [1:0] cur_cur_subvl = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + reg [1:0] \cur_cur_subvl$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + reg [1:0] cur_cur_svstep = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + reg [1:0] \cur_cur_svstep$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + reg [6:0] cur_cur_vl = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + reg [6:0] \cur_cur_vl$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) + reg d_cr_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) + reg \d_cr_delay$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *) + reg d_reg_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *) + reg \d_reg_delay$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *) + reg d_xer_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *) + reg \d_xer_delay$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + wire [6:0] dbg_core_dbg_core_dbg_dststep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + wire [6:0] dbg_core_dbg_core_dbg_maxvl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + wire [6:0] dbg_core_dbg_core_dbg_srcstep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + wire [1:0] dbg_core_dbg_core_dbg_subvl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + wire [1:0] dbg_core_dbg_core_dbg_svstep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + wire [6:0] dbg_core_dbg_core_dbg_vl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + wire [63:0] dbg_core_dbg_msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + wire [63:0] dbg_core_dbg_pc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" *) + wire dbg_core_rst_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" *) + wire dbg_core_stop_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" *) + reg dbg_core_stopped_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *) + reg dbg_d_cr_ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *) + reg [63:0] dbg_d_cr_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *) + wire dbg_d_cr_req; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *) + reg dbg_d_gpr_ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" *) + wire [6:0] dbg_d_gpr_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *) + reg [63:0] dbg_d_gpr_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *) + wire dbg_d_gpr_req; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *) + reg dbg_d_xer_ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *) + reg [63:0] dbg_d_xer_data; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *) + wire dbg_d_xer_req; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" *) + wire dbg_dmi_ack_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" *) + reg [3:0] dbg_dmi_addr_i = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" *) + reg [3:0] \dbg_dmi_addr_i$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" *) + reg [63:0] dbg_dmi_din = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" *) + reg [63:0] \dbg_dmi_din$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" *) + wire [63:0] dbg_dmi_dout; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" *) + reg dbg_dmi_req_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" *) + reg \dbg_dmi_req_i$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" *) + reg dbg_dmi_we_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" *) + reg \dbg_dmi_we_i$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" *) + wire dbg_terminate_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [44:0] dbus__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input [63:0] dbus__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [63:0] dbus__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + input dbus__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output [7:0] dbus__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) + output dbus__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + wire [7:0] dec2_asmcode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + wire dec2_bigendian; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + wire [63:0] dec2_cia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec2_cr_in1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_cr_in1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec2_cr_in2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] \dec2_cr_in2$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_cr_in2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \dec2_cr_in2_ok$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec2_cr_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_cr_out_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [7:0] dec2_cr_rd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_cr_rd_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [7:0] dec2_cr_wr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_cr_wr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + reg [63:0] dec2_cur_dec = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + reg [63:0] \dec2_cur_dec$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + reg dec2_cur_eint = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + reg \dec2_cur_eint$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + reg [63:0] dec2_cur_msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + reg [63:0] \dec2_cur_msr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + reg [63:0] dec2_cur_pc = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + reg [63:0] \dec2_cur_pc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec2_ea; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_ea_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + wire \dec2_exc_$signal$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec2_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec2_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec2_fasto1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_fasto1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [2:0] dec2_fasto2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_fasto2_ok; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) + wire [13:0] dec2_fn_unit; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + wire [1:0] dec2_input_carry; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + wire [31:0] dec2_insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + wire [6:0] dec2_insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + wire dec2_is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + wire dec2_lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + wire [63:0] dec2_msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_oe_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + reg [31:0] dec2_raw_opcode_in = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + reg [31:0] \dec2_raw_opcode_in$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_rc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_rc_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec2_reg1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_reg1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec2_reg2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_reg2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec2_reg3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_reg3_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] dec2_rego; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_rego_ok; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [9:0] dec2_spr1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_spr1_ok; + (* enum_base_type = "SPR" *) + (* enum_value_0000000001 = "XER" *) + (* enum_value_0000000011 = "DSCR" *) + (* enum_value_0000001000 = "LR" *) + (* enum_value_0000001001 = "CTR" *) + (* enum_value_0000001101 = "AMR" *) + (* enum_value_0000010001 = "DSCR_priv" *) + (* enum_value_0000010010 = "DSISR" *) + (* enum_value_0000010011 = "DAR" *) + (* enum_value_0000010110 = "DEC" *) + (* enum_value_0000011010 = "SRR0" *) + (* enum_value_0000011011 = "SRR1" *) + (* enum_value_0000011100 = "CFAR" *) + (* enum_value_0000011101 = "AMR_priv" *) + (* enum_value_0000110000 = "PIDR" *) + (* enum_value_0000111101 = "IAMR" *) + (* enum_value_0010000000 = "TFHAR" *) + (* enum_value_0010000001 = "TFIAR" *) + (* enum_value_0010000010 = "TEXASR" *) + (* enum_value_0010000011 = "TEXASRU" *) + (* enum_value_0010001000 = "CTRL" *) + (* enum_value_0010010000 = "TIDR" *) + (* enum_value_0010011000 = "CTRL_priv" *) + (* enum_value_0010011001 = "FSCR" *) + (* enum_value_0010011101 = "UAMOR" *) + (* enum_value_0010011110 = "GSR" *) + (* enum_value_0010011111 = "PSPB" *) + (* enum_value_0010110000 = "DPDES" *) + (* enum_value_0010110100 = "DAWR0" *) + (* enum_value_0010111010 = "RPR" *) + (* enum_value_0010111011 = "CIABR" *) + (* enum_value_0010111100 = "DAWRX0" *) + (* enum_value_0010111110 = "HFSCR" *) + (* enum_value_0100000000 = "VRSAVE" *) + (* enum_value_0100000011 = "SPRG3" *) + (* enum_value_0100001100 = "TB" *) + (* enum_value_0100001101 = "TBU" *) + (* enum_value_0100010000 = "SPRG0_priv" *) + (* enum_value_0100010001 = "SPRG1_priv" *) + (* enum_value_0100010010 = "SPRG2_priv" *) + (* enum_value_0100010011 = "SPRG3_priv" *) + (* enum_value_0100011011 = "CIR" *) + (* enum_value_0100011100 = "TBL" *) + (* enum_value_0100011101 = "TBU_hypv" *) + (* enum_value_0100011110 = "TBU40" *) + (* enum_value_0100011111 = "PVR" *) + (* enum_value_0100110000 = "HSPRG0" *) + (* enum_value_0100110001 = "HSPRG1" *) + (* enum_value_0100110010 = "HDSISR" *) + (* enum_value_0100110011 = "HDAR" *) + (* enum_value_0100110100 = "SPURR" *) + (* enum_value_0100110101 = "PURR" *) + (* enum_value_0100110110 = "HDEC" *) + (* enum_value_0100111001 = "HRMOR" *) + (* enum_value_0100111010 = "HSRR0" *) + (* enum_value_0100111011 = "HSRR1" *) + (* enum_value_0100111110 = "LPCR" *) + (* enum_value_0100111111 = "LPIDR" *) + (* enum_value_0101010000 = "HMER" *) + (* enum_value_0101010001 = "HMEER" *) + (* enum_value_0101010010 = "PCR" *) + (* enum_value_0101010011 = "HEIR" *) + (* enum_value_0101011101 = "AMOR" *) + (* enum_value_0110111110 = "TIR" *) + (* enum_value_0111010000 = "PTCR" *) + (* enum_value_1011000000 = "SVSTATE" *) + (* enum_value_1011010000 = "PRTBL" *) + (* enum_value_1011010001 = "SVSRR0" *) + (* enum_value_1100000000 = "SIER" *) + (* enum_value_1100000001 = "MMCR2" *) + (* enum_value_1100000010 = "MMCRA" *) + (* enum_value_1100000011 = "PMC1" *) + (* enum_value_1100000100 = "PMC2" *) + (* enum_value_1100000101 = "PMC3" *) + (* enum_value_1100000110 = "PMC4" *) + (* enum_value_1100000111 = "PMC5" *) + (* enum_value_1100001000 = "PMC6" *) + (* enum_value_1100001011 = "MMCR0" *) + (* enum_value_1100001100 = "SIAR" *) + (* enum_value_1100001101 = "SDAR" *) + (* enum_value_1100001110 = "MMCR1" *) + (* enum_value_1100010000 = "SIER_priv" *) + (* enum_value_1100010001 = "MMCR2_priv" *) + (* enum_value_1100010010 = "MMCRA_priv" *) + (* enum_value_1100010011 = "PMC1_priv" *) + (* enum_value_1100010100 = "PMC2_priv" *) + (* enum_value_1100010101 = "PMC3_priv" *) + (* enum_value_1100010110 = "PMC4_priv" *) + (* enum_value_1100010111 = "PMC5_priv" *) + (* enum_value_1100011000 = "PMC6_priv" *) + (* enum_value_1100011011 = "MMCR0_priv" *) + (* enum_value_1100011100 = "SIAR_priv" *) + (* enum_value_1100011101 = "SDAR_priv" *) + (* enum_value_1100011110 = "MMCR1_priv" *) + (* enum_value_1100100000 = "BESCRS" *) + (* enum_value_1100100001 = "BESCRSU" *) + (* enum_value_1100100010 = "BESCRR" *) + (* enum_value_1100100011 = "BESCRRU" *) + (* enum_value_1100100100 = "EBBHR" *) + (* enum_value_1100100101 = "EBBRR" *) + (* enum_value_1100100110 = "BESCR" *) + (* enum_value_1100101000 = "reserved808" *) + (* enum_value_1100101001 = "reserved809" *) + (* enum_value_1100101010 = "reserved810" *) + (* enum_value_1100101011 = "reserved811" *) + (* enum_value_1100101111 = "TAR" *) + (* enum_value_1100110000 = "ASDR" *) + (* enum_value_1100110111 = "PSSCR" *) + (* enum_value_1101010000 = "IC" *) + (* enum_value_1101010001 = "VTB" *) + (* enum_value_1101010111 = "PSSCR_hypv" *) + (* enum_value_1110000000 = "PPR" *) + (* enum_value_1110000010 = "PPR32" *) + (* enum_value_1111111111 = "PIR" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [9:0] dec2_spro; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire dec2_spro_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + wire dec2_sv_a_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + wire [12:0] dec2_trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + wire [7:0] dec2_traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + wire [2:0] dec2_xer_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + wire dec2_xer_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) + reg [1:0] delay = 2'h3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) + reg [1:0] \delay$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output eint_2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input eint_2__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + reg exec_fsm_state = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + reg \exec_fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" *) + reg exec_insn_ready_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955" *) + reg exec_insn_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960" *) + reg exec_pc_ready_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:959" *) + reg exec_pc_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + reg [1:0] fetch_fsm_state = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + reg [1:0] \fetch_fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:944" *) + reg fetch_insn_ready_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) + reg fetch_insn_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:940" *) + reg fetch_pc_ready_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:939" *) + reg fetch_pc_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + reg [1:0] fsm_state = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + reg [1:0] \fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e10__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e10__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e11__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e11__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e12__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e12__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e13__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e13__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e14__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e14__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e15__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e15__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e8__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e8__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_e9__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_e9__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s0__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s1__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s2__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s2__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s3__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s3__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s4__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s4__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s5__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s5__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s6__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s6__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input gpio_s7__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output gpio_s7__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input ibus__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output [44:0] ibus__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output ibus__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input [63:0] ibus__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + input ibus__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output [7:0] ibus__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *) + output ibus__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + output icp_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [27:0] icp_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + output [31:0] icp_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [31:0] icp_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [3:0] icp_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + output ics_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input [27:0] ics_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + output [31:0] ics_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input [31:0] ics_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" *) + reg [47:0] imem_a_pc_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *) + reg imem_a_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" *) + wire imem_f_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" *) + wire [63:0] imem_f_instr_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" *) + reg imem_f_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + wire imem_wb_icache_en; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268" *) + reg insn_done; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *) + input [15:0] int_level_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:698" *) + reg is_last; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:933" *) + wire is_svp64_mode; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + reg [2:0] issue_fsm_state = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + reg [2:0] \issue_fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + reg jtag_dmi0__ack_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + reg \jtag_dmi0__ack_o$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + wire [3:0] jtag_dmi0__addr_i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + wire [63:0] jtag_dmi0__din; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + reg [63:0] jtag_dmi0__dout = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + reg [63:0] \jtag_dmi0__dout$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + wire jtag_dmi0__req_i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) + wire jtag_dmi0__we_i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + input jtag_wb__ack; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [29:0] jtag_wb__adr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__cyc; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + input [31:0] jtag_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [31:0] jtag_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output [3:0] jtag_wb__sel; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__stb; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) + output jtag_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + wire jtag_wb_sram_en; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_clk__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_clk__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_cs_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_cs_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_miso__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_miso__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mspi0_mosi__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mspi0_mosi__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" *) + reg msr_read = 1'h1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" *) + reg \msr_read$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_scl__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_scl__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input mtwi_sda__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output mtwi_sda__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *) + reg [63:0] new_dec; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + reg [6:0] new_svstate_dststep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + reg [6:0] new_svstate_maxvl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + reg [6:0] new_svstate_srcstep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + reg [1:0] new_svstate_subvl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + reg [1:0] new_svstate_svstep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + reg [6:0] new_svstate_vl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1096" *) + reg [63:0] new_tb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + wire [6:0] next_dststep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" *) + wire [6:0] next_srcstep; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" *) + reg [63:0] nia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" *) + reg [63:0] \nia$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *) + reg [63:0] pc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:901" *) + reg pc_changed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:901" *) + reg \pc_changed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input [63:0] pc_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + input pc_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *) + output [63:0] pc_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + reg pc_ok_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + reg \pc_ok_delay$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire por_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" *) + wire pred_insn_ready_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947" *) + reg pred_insn_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952" *) + reg pred_mask_ready_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:951" *) + wire pred_mask_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_a_9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_a_9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ba_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ba_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ba_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ba_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cas_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cas_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cke__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cke__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_clock__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_clock__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_cs_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_cs_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dm_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dm_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dm_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dm_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_0__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_0__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_10__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_10__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_11__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_11__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_12__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_12__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_13__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_13__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_14__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_14__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_15__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_15__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_1__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_1__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_2__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_2__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_3__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_3__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_4__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_4__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_5__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_5__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_6__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_6__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_7__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_7__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_8__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_8__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__core__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__core__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_dq_9__pad__i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_dq_9__pad__oe; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_ras_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_ras_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + input sdr_we_n__core__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) + output sdr_we_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) + wire sram4k_0_enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_0_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_0_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_0_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_0_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_0_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_0_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) + wire sram4k_1_enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_1_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_1_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_1_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_1_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_1_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_1_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) + wire sram4k_2_enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_2_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_2_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_2_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_2_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_2_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_2_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) + wire sram4k_3_enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output sram4k_3_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [8:0] sram4k_3_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + output [63:0] sram4k_3_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [63:0] sram4k_3_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input [7:0] sram4k_3_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) + input sram4k_3_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" *) + reg sv_changed = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" *) + reg \sv_changed$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *) + reg [63:0] svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [31:0] svstate_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire svstate_i_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + reg svstate_ok_delay = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + reg \svstate_ok_delay$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) + wire ti_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + reg update_svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) + wire xics_icp_core_irq_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *) + wire [7:0] xics_icp_ics_i_pri; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) + wire [3:0] xics_icp_ics_i_src; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *) + wire [7:0] xics_ics_icp_o_pri; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) + wire [3:0] xics_ics_icp_o_src; + assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; + assign \$105 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) 3'h4; + assign \$108 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; + assign \$107 = imem_f_instr_o >> \$108 ; + assign \$113 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) 3'h4; + assign \$115 = \$112 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; + assign \$111 = imem_f_instr_o >> \$115 ; + assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$122 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$120 ; + assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$126 ; + assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$137 = cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) 1'h1; + assign \$140 = cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) 1'h1; + assign \$142 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$146 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$144 ; + assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$150 ; + assign \$154 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; + assign \$156 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$154 ; + assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) is_svp64_mode; + assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$162 ; + assign \$166 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$170 = \$168 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$174 ; + assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$180 ; + assign \$184 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$186 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$188 = \$184 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$186 ; + assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$194 = \$190 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$192 ; + assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$198 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$200 = \$196 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$198 ; + assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$204 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$206 = \$202 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$204 ; + assign \$209 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) 1'h1; + assign \$208 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$209 ; + assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$214 ; + assign \$218 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$222 = \$218 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$220 ; + assign \$224 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$228 = \$226 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$232 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$234 = \$230 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$232 ; + assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$238 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; + assign \$240 = \$236 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$238 ; + assign \$243 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) 3'h4; + assign \$242 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$243 ; + assign \$246 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; + assign \$248 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$246 ; + assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; + assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$256 = \$252 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$254 ; + assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) 1'h0; + assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$262 = \$258 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$260 ; + assign \$264 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" *) cur_cur_vl; + assign \$266 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; + assign \$268 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) 7'h01; + assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; + assign \$272 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; + assign \$274 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o; + assign \$276 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o; + assign \$279 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) 1'h1; + assign \$282 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) 1'h1; + assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) 1'h1; + assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) dbg_core_rst_o; + assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) rst; + assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) \$32 ; + assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly; + assign \$38 = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$36 ; + assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; + assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) pc_i_ok; + assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; + assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; + assign \$50 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) svstate_i_ok; + assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; + assign \$54 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) svstate_i; + assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; + assign \$58 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$60 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$62 = \$58 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$60 ; + assign \$64 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; + assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$64 ; + assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$70 ; + assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$82 ; + assign \$86 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; + assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$86 ; + assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$92 ; + assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + always @(posedge clk) + fsm_state <= \fsm_state$next ; + always @(posedge clk) + core_msr <= \core_msr$next ; + always @(posedge clk) + jtag_dmi0__ack_o <= \jtag_dmi0__ack_o$next ; + always @(posedge clk) + dbg_dmi_din <= \dbg_dmi_din$next ; + always @(posedge clk) + dbg_dmi_we_i <= \dbg_dmi_we_i$next ; + always @(posedge clk) + dbg_dmi_req_i <= \dbg_dmi_req_i$next ; + always @(posedge clk) + dbg_dmi_addr_i <= \dbg_dmi_addr_i$next ; + always @(posedge clk) + core_eint <= \core_eint$next ; + always @(posedge clk) + core_dec <= \core_dec$next ; + always @(posedge clk) + core_core_svstep <= \core_core_svstep$next ; + always @(posedge clk) + core_core_subvl <= \core_core_subvl$next ; + always @(posedge clk) + core_core_dststep <= \core_core_dststep$next ; + always @(posedge clk) + core_core_srcstep <= \core_core_srcstep$next ; + always @(posedge clk) + core_core_vl <= \core_core_vl$next ; + always @(posedge clk) + core_core_maxvl <= \core_core_maxvl$next ; + always @(posedge clk) + core_asmcode <= \core_asmcode$next ; + always @(posedge clk) + d_xer_delay <= \d_xer_delay$next ; + always @(posedge clk) + core_core_rego <= \core_core_rego$next ; + always @(posedge clk) + core_rego_ok <= \core_rego_ok$next ; + always @(posedge clk) + core_core_ea <= \core_core_ea$next ; + always @(posedge clk) + core_ea_ok <= \core_ea_ok$next ; + always @(posedge clk) + core_core_reg1 <= \core_core_reg1$next ; + always @(posedge clk) + core_core_reg1_ok <= \core_core_reg1_ok$next ; + always @(posedge clk) + core_core_reg2 <= \core_core_reg2$next ; + always @(posedge clk) + core_core_reg2_ok <= \core_core_reg2_ok$next ; + always @(posedge clk) + core_core_reg3 <= \core_core_reg3$next ; + always @(posedge clk) + core_core_reg3_ok <= \core_core_reg3_ok$next ; + always @(posedge clk) + d_cr_delay <= \d_cr_delay$next ; + always @(posedge clk) + core_core_spro <= \core_core_spro$next ; + always @(posedge clk) + core_spro_ok <= \core_spro_ok$next ; + always @(posedge clk) + core_core_spr1 <= \core_core_spr1$next ; + always @(posedge clk) + core_core_spr1_ok <= \core_core_spr1_ok$next ; + always @(posedge clk) + core_core_xer_in <= \core_core_xer_in$next ; + always @(posedge clk) + core_xer_out <= \core_xer_out$next ; + always @(posedge clk) + core_core_fast1 <= \core_core_fast1$next ; + always @(posedge clk) + core_core_fast1_ok <= \core_core_fast1_ok$next ; + always @(posedge clk) + core_core_fast2 <= \core_core_fast2$next ; + always @(posedge clk) + core_core_fast2_ok <= \core_core_fast2_ok$next ; + always @(posedge clk) + d_reg_delay <= \d_reg_delay$next ; + always @(posedge clk) + core_core_fasto1 <= \core_core_fasto1$next ; + always @(posedge clk) + core_fasto1_ok <= \core_fasto1_ok$next ; + always @(posedge clk) + core_core_fasto2 <= \core_core_fasto2$next ; + always @(posedge clk) + core_fasto2_ok <= \core_fasto2_ok$next ; + always @(posedge clk) + core_core_cr_in1 <= \core_core_cr_in1$next ; + always @(posedge clk) + core_core_cr_in1_ok <= \core_core_cr_in1_ok$next ; + always @(posedge clk) + core_core_cr_in2 <= \core_core_cr_in2$next ; + always @(posedge clk) + core_core_cr_in2_ok <= \core_core_cr_in2_ok$next ; + always @(posedge clk) + \core_core_cr_in2$1 <= \core_core_cr_in2$1$next ; + always @(posedge clk) + \core_core_cr_in2_ok$2 <= \core_core_cr_in2_ok$2$next ; + always @(posedge clk) + exec_fsm_state <= \exec_fsm_state$next ; + always @(posedge clk) + core_core_cr_out <= \core_core_cr_out$next ; + always @(posedge clk) + core_cr_out_ok <= \core_cr_out_ok$next ; + always @(posedge clk) + core_core_core_msr <= \core_core_core_msr$next ; + always @(posedge clk) + core_core_core_cia <= \core_core_core_cia$next ; + always @(posedge clk) + core_core_core_insn <= \core_core_core_insn$next ; + always @(posedge clk) + core_core_core_insn_type <= \core_core_core_insn_type$next ; + always @(posedge clk) + core_core_core_fn_unit <= \core_core_core_fn_unit$next ; + always @(posedge clk) + core_core_lk <= \core_core_lk$next ; + always @(posedge clk) + core_core_core_rc <= \core_core_core_rc$next ; + always @(posedge clk) + core_core_core_rc_ok <= \core_core_core_rc_ok$next ; + always @(posedge clk) + core_sv_a_nz <= \core_sv_a_nz$next ; + always @(posedge clk) + core_core_core_oe <= \core_core_core_oe$next ; + always @(posedge clk) + core_core_core_oe_ok <= \core_core_core_oe_ok$next ; + always @(posedge clk) + core_core_core_input_carry <= \core_core_core_input_carry$next ; + always @(posedge clk) + core_core_core_traptype <= \core_core_core_traptype$next ; + always @(posedge clk) + \core_core_core_exc_$signal <= \core_core_core_exc_$signal$next ; + always @(posedge clk) + \core_core_core_exc_$signal$3 <= \core_core_core_exc_$signal$3$next ; + always @(posedge clk) + \core_core_core_exc_$signal$4 <= \core_core_core_exc_$signal$4$next ; + always @(posedge clk) + \core_core_core_exc_$signal$5 <= \core_core_core_exc_$signal$5$next ; + always @(posedge clk) + \core_core_core_exc_$signal$6 <= \core_core_core_exc_$signal$6$next ; + always @(posedge clk) + \core_core_core_exc_$signal$7 <= \core_core_core_exc_$signal$7$next ; + always @(posedge clk) + \core_bigendian_i$10 <= \core_bigendian_i$10$next ; + always @(posedge clk) + \core_core_core_exc_$signal$8 <= \core_core_core_exc_$signal$8$next ; + always @(posedge clk) + \core_core_core_exc_$signal$9 <= \core_core_core_exc_$signal$9$next ; + always @(posedge clk) + core_core_core_trapaddr <= \core_core_core_trapaddr$next ; + always @(posedge clk) + core_core_core_cr_rd <= \core_core_core_cr_rd$next ; + always @(posedge clk) + core_core_core_cr_rd_ok <= \core_core_core_cr_rd_ok$next ; + always @(posedge clk) + core_core_core_cr_wr <= \core_core_core_cr_wr$next ; + always @(posedge clk) + core_core_cr_wr_ok <= \core_core_cr_wr_ok$next ; + always @(posedge clk) + core_core_core_is_32bit <= \core_core_core_is_32bit$next ; + always @(posedge clk) + sv_changed <= \sv_changed$next ; + always @(posedge clk) + pc_changed <= \pc_changed$next ; + always @(posedge clk) + core_raw_insn_i <= \core_raw_insn_i$next ; + always @(posedge clk) + issue_fsm_state <= \issue_fsm_state$next ; + always @(posedge clk) + dec2_raw_opcode_in <= \dec2_raw_opcode_in$next ; + always @(posedge clk) + nia <= \nia$next ; + always @(posedge clk) + fetch_fsm_state <= \fetch_fsm_state$next ; + always @(posedge clk) + msr_read <= \msr_read$next ; + always @(posedge clk) + svstate_ok_delay <= \svstate_ok_delay$next ; + always @(posedge clk) + pc_ok_delay <= \pc_ok_delay$next ; + always @(posedge clk) + cu_st__rel_o_dly <= core_cu_st__rel_o; + always @(posedge por_clk) + delay <= \delay$next ; + always @(posedge clk) + dec2_cur_eint <= \dec2_cur_eint$next ; + always @(posedge clk) + core_core_pc <= \core_core_pc$next ; + always @(posedge clk) + dec2_cur_pc <= \dec2_cur_pc$next ; + always @(posedge clk) + dec2_cur_msr <= \dec2_cur_msr$next ; + always @(posedge clk) + dec2_cur_dec <= \dec2_cur_dec$next ; + always @(posedge clk) + cur_cur_svstep <= \cur_cur_svstep$next ; + always @(posedge clk) + cur_cur_subvl <= \cur_cur_subvl$next ; + always @(posedge clk) + cur_cur_dststep <= \cur_cur_dststep$next ; + always @(posedge clk) + cur_cur_srcstep <= \cur_cur_srcstep$next ; + always @(posedge clk) + cur_cur_vl <= \cur_cur_vl$next ; + always @(posedge clk) + cur_cur_maxvl <= \cur_cur_maxvl$next ; + always @(posedge clk) + jtag_dmi0__dout <= \jtag_dmi0__dout$next ; + core core ( + .bigendian_i(\core_bigendian_i$10 ), + .cia__data_o(core_cia__data_o), + .cia__ren(core_cia__ren), + .core_core_cia(core_core_core_cia), + .core_core_cr_rd(core_core_core_cr_rd), + .core_core_cr_rd_ok(core_core_core_cr_rd_ok), + .core_core_cr_wr(core_core_core_cr_wr), + .\core_core_exc_$signal (\core_core_core_exc_$signal ), + .\core_core_exc_$signal$3 (\core_core_core_exc_$signal$3 ), + .\core_core_exc_$signal$4 (\core_core_core_exc_$signal$4 ), + .\core_core_exc_$signal$5 (\core_core_core_exc_$signal$5 ), + .\core_core_exc_$signal$6 (\core_core_core_exc_$signal$6 ), + .\core_core_exc_$signal$7 (\core_core_core_exc_$signal$7 ), + .\core_core_exc_$signal$8 (\core_core_core_exc_$signal$8 ), + .\core_core_exc_$signal$9 (\core_core_core_exc_$signal$9 ), + .core_core_fn_unit(core_core_core_fn_unit), + .core_core_input_carry(core_core_core_input_carry), + .core_core_insn(core_core_core_insn), + .core_core_insn_type(core_core_core_insn_type), + .core_core_is_32bit(core_core_core_is_32bit), + .core_core_msr(core_core_core_msr), + .core_core_oe(core_core_core_oe), + .core_core_oe_ok(core_core_core_oe_ok), + .core_core_rc(core_core_core_rc), + .core_core_rc_ok(core_core_core_rc_ok), + .core_core_trapaddr(core_core_core_trapaddr), + .core_core_traptype(core_core_core_traptype), + .core_cr_in1(core_core_cr_in1), + .core_cr_in1_ok(core_core_cr_in1_ok), + .core_cr_in2(core_core_cr_in2), + .\core_cr_in2$1 (\core_core_cr_in2$1 ), + .core_cr_in2_ok(core_core_cr_in2_ok), + .\core_cr_in2_ok$2 (\core_core_cr_in2_ok$2 ), + .core_cr_out(core_core_cr_out), + .core_ea(core_core_ea), + .core_fast1(core_core_fast1), + .core_fast1_ok(core_core_fast1_ok), + .core_fast2(core_core_fast2), + .core_fast2_ok(core_core_fast2_ok), + .core_fasto1(core_core_fasto1), + .core_fasto2(core_core_fasto2), + .core_pc(core_core_pc), + .core_reg1(core_core_reg1), + .core_reg1_ok(core_core_reg1_ok), + .core_reg2(core_core_reg2), + .core_reg2_ok(core_core_reg2_ok), + .core_reg3(core_core_reg3), + .core_reg3_ok(core_core_reg3_ok), + .core_rego(core_core_rego), + .core_spr1(core_core_spr1), + .core_spr1_ok(core_core_spr1_ok), + .core_spro(core_core_spro), + .core_terminate_o(core_core_terminate_o), + .core_xer_in(core_core_xer_in), + .corebusy_o(core_corebusy_o), + .coresync_clk(coresync_clk), + .coresync_rst(core_coresync_rst), + .cu_ad__go_i(core_cu_ad__go_i), + .cu_ad__rel_o(core_cu_ad__rel_o), + .cu_st__go_i(core_cu_st__go_i), + .cu_st__rel_o(core_cu_st__rel_o), + .data_i(core_data_i), + .\data_i$11 (\core_data_i$12 ), + .dbus__ack(dbus__ack), + .dbus__adr(dbus__adr), + .dbus__cyc(dbus__cyc), + .dbus__dat_r(dbus__dat_r), + .dbus__dat_w(dbus__dat_w), + .dbus__err(dbus__err), + .dbus__sel(dbus__sel), + .dbus__stb(dbus__stb), + .dbus__we(dbus__we), + .dmi__addr(core_dmi__addr), + .dmi__data_o(core_dmi__data_o), + .dmi__ren(core_dmi__ren), + .full_rd2__data_o(core_full_rd2__data_o), + .full_rd2__ren(core_full_rd2__ren), + .full_rd__data_o(core_full_rd__data_o), + .full_rd__ren(core_full_rd__ren), + .issue__addr(core_issue__addr), + .\issue__addr$12 (\core_issue__addr$13 ), + .issue__data_i(core_issue__data_i), + .issue__data_o(core_issue__data_o), + .issue__ren(core_issue__ren), + .issue__wen(core_issue__wen), + .issue_i(core_issue_i), + .ivalid_i(core_ivalid_i), + .msr__data_o(core_msr__data_o), + .msr__ren(core_msr__ren), + .raw_insn_i(core_raw_insn_i), + .state_nia_wen(core_state_nia_wen), + .sv__data_o(core_sv__data_o), + .sv__ren(core_sv__ren), + .sv_a_nz(core_sv_a_nz), + .wb_dcache_en(core_wb_dcache_en), + .wen(core_wen), + .\wen$10 (\core_wen$11 ) + ); + dbg dbg ( + .clk(clk), + .core_dbg_core_dbg_dststep(dbg_core_dbg_core_dbg_dststep), + .core_dbg_core_dbg_maxvl(dbg_core_dbg_core_dbg_maxvl), + .core_dbg_core_dbg_srcstep(dbg_core_dbg_core_dbg_srcstep), + .core_dbg_core_dbg_subvl(dbg_core_dbg_core_dbg_subvl), + .core_dbg_core_dbg_svstep(dbg_core_dbg_core_dbg_svstep), + .core_dbg_core_dbg_vl(dbg_core_dbg_core_dbg_vl), + .core_dbg_msr(dbg_core_dbg_msr), + .core_dbg_pc(dbg_core_dbg_pc), + .core_rst_o(dbg_core_rst_o), + .core_stop_o(dbg_core_stop_o), + .core_stopped_i(dbg_core_stopped_i), + .d_cr_ack(dbg_d_cr_ack), + .d_cr_data(dbg_d_cr_data), + .d_cr_req(dbg_d_cr_req), + .d_gpr_ack(dbg_d_gpr_ack), + .d_gpr_addr(dbg_d_gpr_addr), + .d_gpr_data(dbg_d_gpr_data), + .d_gpr_req(dbg_d_gpr_req), + .d_xer_ack(dbg_d_xer_ack), + .d_xer_data(dbg_d_xer_data), + .d_xer_req(dbg_d_xer_req), + .dmi_ack_o(dbg_dmi_ack_o), + .dmi_addr_i(dbg_dmi_addr_i), + .dmi_din(dbg_dmi_din), + .dmi_dout(dbg_dmi_dout), + .dmi_req_i(dbg_dmi_req_i), + .dmi_we_i(dbg_dmi_we_i), + .rst(rst), + .terminate_i(dbg_terminate_i) + ); + dec2 dec2 ( + .asmcode(dec2_asmcode), + .bigendian(dec2_bigendian), + .cia(dec2_cia), + .cr_in1(dec2_cr_in1), + .cr_in1_ok(dec2_cr_in1_ok), + .cr_in2(dec2_cr_in2), + .\cr_in2$1 (\dec2_cr_in2$14 ), + .cr_in2_ok(dec2_cr_in2_ok), + .\cr_in2_ok$2 (\dec2_cr_in2_ok$15 ), + .cr_out(dec2_cr_out), + .cr_out_ok(dec2_cr_out_ok), + .cr_rd(dec2_cr_rd), + .cr_rd_ok(dec2_cr_rd_ok), + .cr_wr(dec2_cr_wr), + .cr_wr_ok(dec2_cr_wr_ok), + .cur_dec(dec2_cur_dec), + .cur_eint(dec2_cur_eint), + .cur_msr(dec2_cur_msr), + .cur_pc(dec2_cur_pc), + .ea(dec2_ea), + .ea_ok(dec2_ea_ok), + .\exc_$signal (\dec2_exc_$signal ), + .\exc_$signal$3 (\dec2_exc_$signal$16 ), + .\exc_$signal$4 (\dec2_exc_$signal$17 ), + .\exc_$signal$5 (\dec2_exc_$signal$18 ), + .\exc_$signal$6 (\dec2_exc_$signal$19 ), + .\exc_$signal$7 (\dec2_exc_$signal$20 ), + .\exc_$signal$8 (\dec2_exc_$signal$21 ), + .\exc_$signal$9 (\dec2_exc_$signal$22 ), + .fast1(dec2_fast1), + .fast1_ok(dec2_fast1_ok), + .fast2(dec2_fast2), + .fast2_ok(dec2_fast2_ok), + .fasto1(dec2_fasto1), + .fasto1_ok(dec2_fasto1_ok), + .fasto2(dec2_fasto2), + .fasto2_ok(dec2_fasto2_ok), + .fn_unit(dec2_fn_unit), + .input_carry(dec2_input_carry), + .insn(dec2_insn), + .insn_type(dec2_insn_type), + .is_32bit(dec2_is_32bit), + .lk(dec2_lk), + .msr(dec2_msr), + .oe(dec2_oe), + .oe_ok(dec2_oe_ok), + .raw_opcode_in(dec2_raw_opcode_in), + .rc(dec2_rc), + .rc_ok(dec2_rc_ok), + .reg1(dec2_reg1), + .reg1_ok(dec2_reg1_ok), + .reg2(dec2_reg2), + .reg2_ok(dec2_reg2_ok), + .reg3(dec2_reg3), + .reg3_ok(dec2_reg3_ok), + .rego(dec2_rego), + .rego_ok(dec2_rego_ok), + .spr1(dec2_spr1), + .spr1_ok(dec2_spr1_ok), + .spro(dec2_spro), + .spro_ok(dec2_spro_ok), + .sv_a_nz(dec2_sv_a_nz), + .trapaddr(dec2_trapaddr), + .traptype(dec2_traptype), + .xer_in(dec2_xer_in), + .xer_out(dec2_xer_out) + ); + imem imem ( + .a_pc_i(imem_a_pc_i), + .a_valid_i(imem_a_valid_i), + .clk(clk), + .f_busy_o(imem_f_busy_o), + .f_instr_o(imem_f_instr_o), + .f_valid_i(imem_f_valid_i), + .ibus__ack(ibus__ack), + .ibus__adr(ibus__adr), + .ibus__cyc(ibus__cyc), + .ibus__dat_r(ibus__dat_r), + .ibus__err(ibus__err), + .ibus__sel(ibus__sel), + .ibus__stb(ibus__stb), + .rst(rst), + .wb_icache_en(imem_wb_icache_en) + ); + jtag jtag ( + .TAP_bus__tck(TAP_bus__tck), + .TAP_bus__tdi(TAP_bus__tdi), + .TAP_bus__tdo(TAP_bus__tdo), + .TAP_bus__tms(TAP_bus__tms), + .clk(clk), + .dmi0__ack_o(jtag_dmi0__ack_o), + .dmi0__addr_i(jtag_dmi0__addr_i), + .dmi0__din(jtag_dmi0__din), + .dmi0__dout(jtag_dmi0__dout), + .dmi0__req_i(jtag_dmi0__req_i), + .dmi0__we_i(jtag_dmi0__we_i), + .eint_0__core__i(eint_0__core__i), + .eint_0__pad__i(eint_0__pad__i), + .eint_1__core__i(eint_1__core__i), + .eint_1__pad__i(eint_1__pad__i), + .eint_2__core__i(eint_2__core__i), + .eint_2__pad__i(eint_2__pad__i), + .gpio_e10__core__i(gpio_e10__core__i), + .gpio_e10__core__o(gpio_e10__core__o), + .gpio_e10__core__oe(gpio_e10__core__oe), + .gpio_e10__pad__i(gpio_e10__pad__i), + .gpio_e10__pad__o(gpio_e10__pad__o), + .gpio_e10__pad__oe(gpio_e10__pad__oe), + .gpio_e11__core__i(gpio_e11__core__i), + .gpio_e11__core__o(gpio_e11__core__o), + .gpio_e11__core__oe(gpio_e11__core__oe), + .gpio_e11__pad__i(gpio_e11__pad__i), + .gpio_e11__pad__o(gpio_e11__pad__o), + .gpio_e11__pad__oe(gpio_e11__pad__oe), + .gpio_e12__core__i(gpio_e12__core__i), + .gpio_e12__core__o(gpio_e12__core__o), + .gpio_e12__core__oe(gpio_e12__core__oe), + .gpio_e12__pad__i(gpio_e12__pad__i), + .gpio_e12__pad__o(gpio_e12__pad__o), + .gpio_e12__pad__oe(gpio_e12__pad__oe), + .gpio_e13__core__i(gpio_e13__core__i), + .gpio_e13__core__o(gpio_e13__core__o), + .gpio_e13__core__oe(gpio_e13__core__oe), + .gpio_e13__pad__i(gpio_e13__pad__i), + .gpio_e13__pad__o(gpio_e13__pad__o), + .gpio_e13__pad__oe(gpio_e13__pad__oe), + .gpio_e14__core__i(gpio_e14__core__i), + .gpio_e14__core__o(gpio_e14__core__o), + .gpio_e14__core__oe(gpio_e14__core__oe), + .gpio_e14__pad__i(gpio_e14__pad__i), + .gpio_e14__pad__o(gpio_e14__pad__o), + .gpio_e14__pad__oe(gpio_e14__pad__oe), + .gpio_e15__core__i(gpio_e15__core__i), + .gpio_e15__core__o(gpio_e15__core__o), + .gpio_e15__core__oe(gpio_e15__core__oe), + .gpio_e15__pad__i(gpio_e15__pad__i), + .gpio_e15__pad__o(gpio_e15__pad__o), + .gpio_e15__pad__oe(gpio_e15__pad__oe), + .gpio_e8__core__i(gpio_e8__core__i), + .gpio_e8__core__o(gpio_e8__core__o), + .gpio_e8__core__oe(gpio_e8__core__oe), + .gpio_e8__pad__i(gpio_e8__pad__i), + .gpio_e8__pad__o(gpio_e8__pad__o), + .gpio_e8__pad__oe(gpio_e8__pad__oe), + .gpio_e9__core__i(gpio_e9__core__i), + .gpio_e9__core__o(gpio_e9__core__o), + .gpio_e9__core__oe(gpio_e9__core__oe), + .gpio_e9__pad__i(gpio_e9__pad__i), + .gpio_e9__pad__o(gpio_e9__pad__o), + .gpio_e9__pad__oe(gpio_e9__pad__oe), + .gpio_s0__core__i(gpio_s0__core__i), + .gpio_s0__core__o(gpio_s0__core__o), + .gpio_s0__core__oe(gpio_s0__core__oe), + .gpio_s0__pad__i(gpio_s0__pad__i), + .gpio_s0__pad__o(gpio_s0__pad__o), + .gpio_s0__pad__oe(gpio_s0__pad__oe), + .gpio_s1__core__i(gpio_s1__core__i), + .gpio_s1__core__o(gpio_s1__core__o), + .gpio_s1__core__oe(gpio_s1__core__oe), + .gpio_s1__pad__i(gpio_s1__pad__i), + .gpio_s1__pad__o(gpio_s1__pad__o), + .gpio_s1__pad__oe(gpio_s1__pad__oe), + .gpio_s2__core__i(gpio_s2__core__i), + .gpio_s2__core__o(gpio_s2__core__o), + .gpio_s2__core__oe(gpio_s2__core__oe), + .gpio_s2__pad__i(gpio_s2__pad__i), + .gpio_s2__pad__o(gpio_s2__pad__o), + .gpio_s2__pad__oe(gpio_s2__pad__oe), + .gpio_s3__core__i(gpio_s3__core__i), + .gpio_s3__core__o(gpio_s3__core__o), + .gpio_s3__core__oe(gpio_s3__core__oe), + .gpio_s3__pad__i(gpio_s3__pad__i), + .gpio_s3__pad__o(gpio_s3__pad__o), + .gpio_s3__pad__oe(gpio_s3__pad__oe), + .gpio_s4__core__i(gpio_s4__core__i), + .gpio_s4__core__o(gpio_s4__core__o), + .gpio_s4__core__oe(gpio_s4__core__oe), + .gpio_s4__pad__i(gpio_s4__pad__i), + .gpio_s4__pad__o(gpio_s4__pad__o), + .gpio_s4__pad__oe(gpio_s4__pad__oe), + .gpio_s5__core__i(gpio_s5__core__i), + .gpio_s5__core__o(gpio_s5__core__o), + .gpio_s5__core__oe(gpio_s5__core__oe), + .gpio_s5__pad__i(gpio_s5__pad__i), + .gpio_s5__pad__o(gpio_s5__pad__o), + .gpio_s5__pad__oe(gpio_s5__pad__oe), + .gpio_s6__core__i(gpio_s6__core__i), + .gpio_s6__core__o(gpio_s6__core__o), + .gpio_s6__core__oe(gpio_s6__core__oe), + .gpio_s6__pad__i(gpio_s6__pad__i), + .gpio_s6__pad__o(gpio_s6__pad__o), + .gpio_s6__pad__oe(gpio_s6__pad__oe), + .gpio_s7__core__i(gpio_s7__core__i), + .gpio_s7__core__o(gpio_s7__core__o), + .gpio_s7__core__oe(gpio_s7__core__oe), + .gpio_s7__pad__i(gpio_s7__pad__i), + .gpio_s7__pad__o(gpio_s7__pad__o), + .gpio_s7__pad__oe(gpio_s7__pad__oe), + .jtag_wb__ack(jtag_wb__ack), + .jtag_wb__adr(jtag_wb__adr), + .jtag_wb__cyc(jtag_wb__cyc), + .jtag_wb__dat_r(jtag_wb__dat_r), + .jtag_wb__dat_w(jtag_wb__dat_w), + .jtag_wb__sel(jtag_wb__sel), + .jtag_wb__stb(jtag_wb__stb), + .jtag_wb__we(jtag_wb__we), + .mspi0_clk__core__o(mspi0_clk__core__o), + .mspi0_clk__pad__o(mspi0_clk__pad__o), + .mspi0_cs_n__core__o(mspi0_cs_n__core__o), + .mspi0_cs_n__pad__o(mspi0_cs_n__pad__o), + .mspi0_miso__core__i(mspi0_miso__core__i), + .mspi0_miso__pad__i(mspi0_miso__pad__i), + .mspi0_mosi__core__o(mspi0_mosi__core__o), + .mspi0_mosi__pad__o(mspi0_mosi__pad__o), + .mtwi_scl__core__o(mtwi_scl__core__o), + .mtwi_scl__pad__o(mtwi_scl__pad__o), + .mtwi_sda__core__i(mtwi_sda__core__i), + .mtwi_sda__core__o(mtwi_sda__core__o), + .mtwi_sda__core__oe(mtwi_sda__core__oe), + .mtwi_sda__pad__i(mtwi_sda__pad__i), + .mtwi_sda__pad__o(mtwi_sda__pad__o), + .mtwi_sda__pad__oe(mtwi_sda__pad__oe), + .rst(rst), + .sdr_a_0__core__o(sdr_a_0__core__o), + .sdr_a_0__pad__o(sdr_a_0__pad__o), + .sdr_a_10__core__o(sdr_a_10__core__o), + .sdr_a_10__pad__o(sdr_a_10__pad__o), + .sdr_a_11__core__o(sdr_a_11__core__o), + .sdr_a_11__pad__o(sdr_a_11__pad__o), + .sdr_a_12__core__o(sdr_a_12__core__o), + .sdr_a_12__pad__o(sdr_a_12__pad__o), + .sdr_a_1__core__o(sdr_a_1__core__o), + .sdr_a_1__pad__o(sdr_a_1__pad__o), + .sdr_a_2__core__o(sdr_a_2__core__o), + .sdr_a_2__pad__o(sdr_a_2__pad__o), + .sdr_a_3__core__o(sdr_a_3__core__o), + .sdr_a_3__pad__o(sdr_a_3__pad__o), + .sdr_a_4__core__o(sdr_a_4__core__o), + .sdr_a_4__pad__o(sdr_a_4__pad__o), + .sdr_a_5__core__o(sdr_a_5__core__o), + .sdr_a_5__pad__o(sdr_a_5__pad__o), + .sdr_a_6__core__o(sdr_a_6__core__o), + .sdr_a_6__pad__o(sdr_a_6__pad__o), + .sdr_a_7__core__o(sdr_a_7__core__o), + .sdr_a_7__pad__o(sdr_a_7__pad__o), + .sdr_a_8__core__o(sdr_a_8__core__o), + .sdr_a_8__pad__o(sdr_a_8__pad__o), + .sdr_a_9__core__o(sdr_a_9__core__o), + .sdr_a_9__pad__o(sdr_a_9__pad__o), + .sdr_ba_0__core__o(sdr_ba_0__core__o), + .sdr_ba_0__pad__o(sdr_ba_0__pad__o), + .sdr_ba_1__core__o(sdr_ba_1__core__o), + .sdr_ba_1__pad__o(sdr_ba_1__pad__o), + .sdr_cas_n__core__o(sdr_cas_n__core__o), + .sdr_cas_n__pad__o(sdr_cas_n__pad__o), + .sdr_cke__core__o(sdr_cke__core__o), + .sdr_cke__pad__o(sdr_cke__pad__o), + .sdr_clock__core__o(sdr_clock__core__o), + .sdr_clock__pad__o(sdr_clock__pad__o), + .sdr_cs_n__core__o(sdr_cs_n__core__o), + .sdr_cs_n__pad__o(sdr_cs_n__pad__o), + .sdr_dm_0__core__o(sdr_dm_0__core__o), + .sdr_dm_0__pad__o(sdr_dm_0__pad__o), + .sdr_dm_1__core__o(sdr_dm_1__core__o), + .sdr_dm_1__pad__o(sdr_dm_1__pad__o), + .sdr_dq_0__core__i(sdr_dq_0__core__i), + .sdr_dq_0__core__o(sdr_dq_0__core__o), + .sdr_dq_0__core__oe(sdr_dq_0__core__oe), + .sdr_dq_0__pad__i(sdr_dq_0__pad__i), + .sdr_dq_0__pad__o(sdr_dq_0__pad__o), + .sdr_dq_0__pad__oe(sdr_dq_0__pad__oe), + .sdr_dq_10__core__i(sdr_dq_10__core__i), + .sdr_dq_10__core__o(sdr_dq_10__core__o), + .sdr_dq_10__core__oe(sdr_dq_10__core__oe), + .sdr_dq_10__pad__i(sdr_dq_10__pad__i), + .sdr_dq_10__pad__o(sdr_dq_10__pad__o), + .sdr_dq_10__pad__oe(sdr_dq_10__pad__oe), + .sdr_dq_11__core__i(sdr_dq_11__core__i), + .sdr_dq_11__core__o(sdr_dq_11__core__o), + .sdr_dq_11__core__oe(sdr_dq_11__core__oe), + .sdr_dq_11__pad__i(sdr_dq_11__pad__i), + .sdr_dq_11__pad__o(sdr_dq_11__pad__o), + .sdr_dq_11__pad__oe(sdr_dq_11__pad__oe), + .sdr_dq_12__core__i(sdr_dq_12__core__i), + .sdr_dq_12__core__o(sdr_dq_12__core__o), + .sdr_dq_12__core__oe(sdr_dq_12__core__oe), + .sdr_dq_12__pad__i(sdr_dq_12__pad__i), + .sdr_dq_12__pad__o(sdr_dq_12__pad__o), + .sdr_dq_12__pad__oe(sdr_dq_12__pad__oe), + .sdr_dq_13__core__i(sdr_dq_13__core__i), + .sdr_dq_13__core__o(sdr_dq_13__core__o), + .sdr_dq_13__core__oe(sdr_dq_13__core__oe), + .sdr_dq_13__pad__i(sdr_dq_13__pad__i), + .sdr_dq_13__pad__o(sdr_dq_13__pad__o), + .sdr_dq_13__pad__oe(sdr_dq_13__pad__oe), + .sdr_dq_14__core__i(sdr_dq_14__core__i), + .sdr_dq_14__core__o(sdr_dq_14__core__o), + .sdr_dq_14__core__oe(sdr_dq_14__core__oe), + .sdr_dq_14__pad__i(sdr_dq_14__pad__i), + .sdr_dq_14__pad__o(sdr_dq_14__pad__o), + .sdr_dq_14__pad__oe(sdr_dq_14__pad__oe), + .sdr_dq_15__core__i(sdr_dq_15__core__i), + .sdr_dq_15__core__o(sdr_dq_15__core__o), + .sdr_dq_15__core__oe(sdr_dq_15__core__oe), + .sdr_dq_15__pad__i(sdr_dq_15__pad__i), + .sdr_dq_15__pad__o(sdr_dq_15__pad__o), + .sdr_dq_15__pad__oe(sdr_dq_15__pad__oe), + .sdr_dq_1__core__i(sdr_dq_1__core__i), + .sdr_dq_1__core__o(sdr_dq_1__core__o), + .sdr_dq_1__core__oe(sdr_dq_1__core__oe), + .sdr_dq_1__pad__i(sdr_dq_1__pad__i), + .sdr_dq_1__pad__o(sdr_dq_1__pad__o), + .sdr_dq_1__pad__oe(sdr_dq_1__pad__oe), + .sdr_dq_2__core__i(sdr_dq_2__core__i), + .sdr_dq_2__core__o(sdr_dq_2__core__o), + .sdr_dq_2__core__oe(sdr_dq_2__core__oe), + .sdr_dq_2__pad__i(sdr_dq_2__pad__i), + .sdr_dq_2__pad__o(sdr_dq_2__pad__o), + .sdr_dq_2__pad__oe(sdr_dq_2__pad__oe), + .sdr_dq_3__core__i(sdr_dq_3__core__i), + .sdr_dq_3__core__o(sdr_dq_3__core__o), + .sdr_dq_3__core__oe(sdr_dq_3__core__oe), + .sdr_dq_3__pad__i(sdr_dq_3__pad__i), + .sdr_dq_3__pad__o(sdr_dq_3__pad__o), + .sdr_dq_3__pad__oe(sdr_dq_3__pad__oe), + .sdr_dq_4__core__i(sdr_dq_4__core__i), + .sdr_dq_4__core__o(sdr_dq_4__core__o), + .sdr_dq_4__core__oe(sdr_dq_4__core__oe), + .sdr_dq_4__pad__i(sdr_dq_4__pad__i), + .sdr_dq_4__pad__o(sdr_dq_4__pad__o), + .sdr_dq_4__pad__oe(sdr_dq_4__pad__oe), + .sdr_dq_5__core__i(sdr_dq_5__core__i), + .sdr_dq_5__core__o(sdr_dq_5__core__o), + .sdr_dq_5__core__oe(sdr_dq_5__core__oe), + .sdr_dq_5__pad__i(sdr_dq_5__pad__i), + .sdr_dq_5__pad__o(sdr_dq_5__pad__o), + .sdr_dq_5__pad__oe(sdr_dq_5__pad__oe), + .sdr_dq_6__core__i(sdr_dq_6__core__i), + .sdr_dq_6__core__o(sdr_dq_6__core__o), + .sdr_dq_6__core__oe(sdr_dq_6__core__oe), + .sdr_dq_6__pad__i(sdr_dq_6__pad__i), + .sdr_dq_6__pad__o(sdr_dq_6__pad__o), + .sdr_dq_6__pad__oe(sdr_dq_6__pad__oe), + .sdr_dq_7__core__i(sdr_dq_7__core__i), + .sdr_dq_7__core__o(sdr_dq_7__core__o), + .sdr_dq_7__core__oe(sdr_dq_7__core__oe), + .sdr_dq_7__pad__i(sdr_dq_7__pad__i), + .sdr_dq_7__pad__o(sdr_dq_7__pad__o), + .sdr_dq_7__pad__oe(sdr_dq_7__pad__oe), + .sdr_dq_8__core__i(sdr_dq_8__core__i), + .sdr_dq_8__core__o(sdr_dq_8__core__o), + .sdr_dq_8__core__oe(sdr_dq_8__core__oe), + .sdr_dq_8__pad__i(sdr_dq_8__pad__i), + .sdr_dq_8__pad__o(sdr_dq_8__pad__o), + .sdr_dq_8__pad__oe(sdr_dq_8__pad__oe), + .sdr_dq_9__core__i(sdr_dq_9__core__i), + .sdr_dq_9__core__o(sdr_dq_9__core__o), + .sdr_dq_9__core__oe(sdr_dq_9__core__oe), + .sdr_dq_9__pad__i(sdr_dq_9__pad__i), + .sdr_dq_9__pad__o(sdr_dq_9__pad__o), + .sdr_dq_9__pad__oe(sdr_dq_9__pad__oe), + .sdr_ras_n__core__o(sdr_ras_n__core__o), + .sdr_ras_n__pad__o(sdr_ras_n__pad__o), + .sdr_we_n__core__o(sdr_we_n__core__o), + .sdr_we_n__pad__o(sdr_we_n__pad__o), + .wb_dcache_en(core_wb_dcache_en), + .wb_icache_en(imem_wb_icache_en), + .wb_sram_en(jtag_wb_sram_en) + ); + sram4k_0 sram4k_0 ( + .clk(clk), + .enable(sram4k_0_enable), + .rst(rst), + .sram4k_0_wb__ack(sram4k_0_wb__ack), + .sram4k_0_wb__adr(sram4k_0_wb__adr), + .sram4k_0_wb__cyc(sram4k_0_wb__cyc), + .sram4k_0_wb__dat_r(sram4k_0_wb__dat_r), + .sram4k_0_wb__dat_w(sram4k_0_wb__dat_w), + .sram4k_0_wb__sel(sram4k_0_wb__sel), + .sram4k_0_wb__stb(sram4k_0_wb__stb), + .sram4k_0_wb__we(sram4k_0_wb__we) + ); + sram4k_1 sram4k_1 ( + .clk(clk), + .enable(sram4k_1_enable), + .rst(rst), + .sram4k_1_wb__ack(sram4k_1_wb__ack), + .sram4k_1_wb__adr(sram4k_1_wb__adr), + .sram4k_1_wb__cyc(sram4k_1_wb__cyc), + .sram4k_1_wb__dat_r(sram4k_1_wb__dat_r), + .sram4k_1_wb__dat_w(sram4k_1_wb__dat_w), + .sram4k_1_wb__sel(sram4k_1_wb__sel), + .sram4k_1_wb__stb(sram4k_1_wb__stb), + .sram4k_1_wb__we(sram4k_1_wb__we) + ); + sram4k_2 sram4k_2 ( + .clk(clk), + .enable(sram4k_2_enable), + .rst(rst), + .sram4k_2_wb__ack(sram4k_2_wb__ack), + .sram4k_2_wb__adr(sram4k_2_wb__adr), + .sram4k_2_wb__cyc(sram4k_2_wb__cyc), + .sram4k_2_wb__dat_r(sram4k_2_wb__dat_r), + .sram4k_2_wb__dat_w(sram4k_2_wb__dat_w), + .sram4k_2_wb__sel(sram4k_2_wb__sel), + .sram4k_2_wb__stb(sram4k_2_wb__stb), + .sram4k_2_wb__we(sram4k_2_wb__we) + ); + sram4k_3 sram4k_3 ( + .clk(clk), + .enable(sram4k_3_enable), + .rst(rst), + .sram4k_3_wb__ack(sram4k_3_wb__ack), + .sram4k_3_wb__adr(sram4k_3_wb__adr), + .sram4k_3_wb__cyc(sram4k_3_wb__cyc), + .sram4k_3_wb__dat_r(sram4k_3_wb__dat_r), + .sram4k_3_wb__dat_w(sram4k_3_wb__dat_w), + .sram4k_3_wb__sel(sram4k_3_wb__sel), + .sram4k_3_wb__stb(sram4k_3_wb__stb), + .sram4k_3_wb__we(sram4k_3_wb__we) + ); + xics_icp xics_icp ( + .clk(clk), + .core_irq_o(xics_icp_core_irq_o), + .icp_wb__ack(icp_wb__ack), + .icp_wb__adr(icp_wb__adr), + .icp_wb__cyc(icp_wb__cyc), + .icp_wb__dat_r(icp_wb__dat_r), + .icp_wb__dat_w(icp_wb__dat_w), + .icp_wb__sel(icp_wb__sel), + .icp_wb__stb(icp_wb__stb), + .icp_wb__we(icp_wb__we), + .ics_i_pri(xics_icp_ics_i_pri), + .ics_i_src(xics_icp_ics_i_src), + .rst(rst) + ); + xics_ics xics_ics ( + .clk(clk), + .icp_o_pri(xics_ics_icp_o_pri), + .icp_o_src(xics_ics_icp_o_src), + .ics_wb__ack(ics_wb__ack), + .ics_wb__adr(ics_wb__adr), + .ics_wb__cyc(ics_wb__cyc), + .ics_wb__dat_r(ics_wb__dat_r), + .ics_wb__dat_w(ics_wb__dat_w), + .ics_wb__stb(ics_wb__stb), + .ics_wb__we(ics_wb__we), + .int_level_i(int_level_i), + .rst(rst) + ); + always @* begin + if (\initial ) begin end + \dbg_dmi_addr_i$next = jtag_dmi0__addr_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dbg_dmi_addr_i$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dbg_dmi_req_i$next = jtag_dmi0__req_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dbg_dmi_req_i$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \delay$next = delay; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" */ + 1'h1: + \delay$next = \$27 [1:0]; + endcase + end + always @* begin + if (\initial ) begin end + \core_core_pc$next = core_core_pc; + \core_msr$next = core_msr; + \core_eint$next = core_eint; + \core_dec$next = core_dec; + \core_core_svstep$next = core_core_svstep; + \core_core_subvl$next = core_core_subvl; + \core_core_dststep$next = core_core_dststep; + \core_core_srcstep$next = core_core_srcstep; + \core_core_vl$next = core_core_vl; + \core_core_maxvl$next = core_core_maxvl; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + { \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_msr$next , \core_core_pc$next } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + begin + \core_core_pc$next = 64'h0000000000000000; + \core_msr$next = 64'h0000000000000000; + \core_eint$next = 1'h0; + \core_dec$next = 64'h0000000000000000; + \core_core_svstep$next = 2'h0; + \core_core_subvl$next = 2'h0; + \core_core_dststep$next = 7'h00; + \core_core_srcstep$next = 7'h00; + \core_core_vl$next = 7'h00; + \core_core_maxvl$next = 7'h00; + end + endcase + end + always @* begin + if (\initial ) begin end + \core_raw_insn_i$next = core_raw_insn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + \core_raw_insn_i$next = dec2_raw_opcode_in; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \core_raw_insn_i$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \core_bigendian_i$10$next = \core_bigendian_i$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + \core_bigendian_i$10$next = core_bigendian_i; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \core_bigendian_i$10$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \core_sv_a_nz$next = core_sv_a_nz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + \core_sv_a_nz$next = dec2_sv_a_nz; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \core_sv_a_nz$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + exec_insn_valid_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + exec_insn_valid_i = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + exec_pc_ready_i = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$256 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + exec_pc_ready_i = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + is_last = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$262 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + casez (exec_pc_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + 1'h1: + is_last = \$264 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \core_wen$11 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) + casez (update_svstate) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ + 1'h1: + \core_wen$11 = 3'h4; + endcase + end + always @* begin + if (\initial ) begin end + \core_data_i$12 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) + casez (update_svstate) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ + 1'h1: + \core_data_i$12 = \$266 ; + endcase + end + always @* begin + if (\initial ) begin end + exec_insn_ready_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + casez (exec_fsm_state) + /* \nmigen.decoding = "INSN_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + 1'h0: + exec_insn_ready_o = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + core_ivalid_i = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + casez (exec_fsm_state) + /* \nmigen.decoding = "INSN_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + 1'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + casez (exec_insn_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + 1'h1: + core_ivalid_i = 1'h1; + endcase + /* \nmigen.decoding = "INSN_ACTIVE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) + casez (\$268 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" */ + 1'h1: + core_ivalid_i = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + core_issue_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + casez (exec_fsm_state) + /* \nmigen.decoding = "INSN_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + 1'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + casez (exec_insn_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + 1'h1: + core_issue_i = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \exec_fsm_state$next = exec_fsm_state; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + casez (exec_fsm_state) + /* \nmigen.decoding = "INSN_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + 1'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + casez (exec_insn_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + 1'h1: + \exec_fsm_state$next = 1'h1; + endcase + /* \nmigen.decoding = "INSN_ACTIVE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + casez (\$270 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" *) + casez (exec_pc_ready_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" */ + 1'h1: + \exec_fsm_state$next = 1'h0; + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \exec_fsm_state$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + exec_pc_valid_o = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + casez (exec_fsm_state) + /* \nmigen.decoding = "INSN_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + 1'h0: + /* empty */; + /* \nmigen.decoding = "INSN_ACTIVE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + casez (\$272 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ + 1'h1: + exec_pc_valid_o = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + core_dmi__addr = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" *) + casez (dbg_d_gpr_req) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" */ + 1'h1: + core_dmi__addr = dbg_d_gpr_addr[4:0]; + endcase + end + always @* begin + if (\initial ) begin end + core_dmi__ren = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" *) + casez (dbg_d_gpr_req) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" */ + 1'h1: + core_dmi__ren = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \d_reg_delay$next = dbg_d_gpr_req; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \d_reg_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dbg_d_gpr_data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) + casez (d_reg_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" */ + 1'h1: + dbg_d_gpr_data = core_dmi__data_o; + endcase + end + always @* begin + if (\initial ) begin end + dbg_d_gpr_ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) + casez (d_reg_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" */ + 1'h1: + dbg_d_gpr_ack = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + core_full_rd2__ren = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *) + casez (dbg_d_cr_req) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" */ + 1'h1: + core_full_rd2__ren = 8'hff; + endcase + end + always @* begin + if (\initial ) begin end + \d_cr_delay$next = dbg_d_cr_req; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \d_cr_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dbg_d_cr_data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *) + casez (d_cr_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */ + 1'h1: + dbg_d_cr_data = \$274 ; + endcase + end + always @* begin + if (\initial ) begin end + dbg_d_cr_ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *) + casez (d_cr_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */ + 1'h1: + dbg_d_cr_ack = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + core_full_rd__ren = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" *) + casez (dbg_d_xer_req) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" */ + 1'h1: + core_full_rd__ren = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + \d_xer_delay$next = dbg_d_xer_req; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \d_xer_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + dbg_d_xer_data = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" *) + casez (d_xer_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" */ + 1'h1: + dbg_d_xer_data = \$276 ; + endcase + end + always @* begin + if (\initial ) begin end + dbg_d_xer_ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" *) + casez (d_xer_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" */ + 1'h1: + dbg_d_xer_ack = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + core_issue__addr = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + core_issue__addr = 3'h6; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + /* empty */; + /* \nmigen.decoding = "TB_READ/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + 2'h2: + core_issue__addr = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + core_issue__ren = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + core_issue__ren = 1'h1; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + /* empty */; + /* \nmigen.decoding = "TB_READ/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + 2'h2: + core_issue__ren = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + \fsm_state$next = 2'h1; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + \fsm_state$next = 2'h2; + /* \nmigen.decoding = "TB_READ/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + 2'h2: + \fsm_state$next = 2'h3; + /* \nmigen.decoding = "TB_WRITE/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + 2'h3: + \fsm_state$next = 2'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \fsm_state$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + new_dec = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + new_dec = \$278 [63:0]; + endcase + end + always @* begin + if (\initial ) begin end + \core_issue__addr$13 = 3'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + \core_issue__addr$13 = 3'h6; + /* \nmigen.decoding = "TB_READ/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + 2'h2: + /* empty */; + /* \nmigen.decoding = "TB_WRITE/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + 2'h3: + \core_issue__addr$13 = 3'h7; + endcase + end + always @* begin + if (\initial ) begin end + core_issue__wen = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + core_issue__wen = 1'h1; + /* \nmigen.decoding = "TB_READ/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + 2'h2: + /* empty */; + /* \nmigen.decoding = "TB_WRITE/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + 2'h3: + core_issue__wen = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + core_issue__data_i = 64'h0000000000000000; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + core_issue__data_i = new_dec; + /* \nmigen.decoding = "TB_READ/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + 2'h2: + /* empty */; + /* \nmigen.decoding = "TB_WRITE/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + 2'h3: + core_issue__data_i = new_tb; + endcase + end + always @* begin + if (\initial ) begin end + new_tb = 64'h0000000000000000; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + /* empty */; + /* \nmigen.decoding = "TB_READ/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ + 2'h2: + /* empty */; + /* \nmigen.decoding = "TB_WRITE/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ + 2'h3: + new_tb = \$281 [63:0]; + endcase + end + always @* begin + if (\initial ) begin end + \dbg_dmi_we_i$next = jtag_dmi0__we_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dbg_dmi_we_i$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \dec2_cur_pc$next = dec2_cur_pc; + \dec2_cur_msr$next = dec2_cur_msr; + \dec2_cur_dec$next = dec2_cur_dec; + \cur_cur_svstep$next = cur_cur_svstep; + \cur_cur_subvl$next = cur_cur_subvl; + \cur_cur_dststep$next = cur_cur_dststep; + \cur_cur_srcstep$next = cur_cur_srcstep; + \cur_cur_vl$next = cur_cur_vl; + \cur_cur_maxvl$next = cur_cur_maxvl; + \dec2_cur_eint$next = xics_icp_core_irq_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" *) + casez (core_coresync_rst) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" */ + 1'h1: + { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + casez (fetch_pc_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + 1'h1: + begin + \dec2_cur_pc$next = pc; + { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next } = svstate[31:0]; + end + endcase + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + casez (\$23 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ + 1'h1: + \dec2_cur_msr$next = core_msr__data_o; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) + casez (update_svstate) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ + 1'h1: + { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) + casez (fsm_state) + /* \nmigen.decoding = "DEC_READ/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "DEC_WRITE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ + 2'h1: + \dec2_cur_dec$next = new_dec; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + begin + \dec2_cur_eint$next = 1'h0; + \dec2_cur_pc$next = 64'h0000000000000000; + \dec2_cur_msr$next = 64'h0000000000000000; + \dec2_cur_dec$next = 64'h0000000000000000; + \cur_cur_svstep$next = 2'h0; + \cur_cur_subvl$next = 2'h0; + \cur_cur_dststep$next = 7'h00; + \cur_cur_srcstep$next = 7'h00; + \cur_cur_vl$next = 7'h00; + \cur_cur_maxvl$next = 7'h00; + end + endcase + end + always @* begin + if (\initial ) begin end + \dbg_dmi_din$next = jtag_dmi0__din; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dbg_dmi_din$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \pc_ok_delay$next = pc_ok_delay; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + casez (\$40 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + 1'h1: + \pc_ok_delay$next = \$42 ; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \pc_ok_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + pc = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + casez (\$44 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + casez (pc_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + 1'h1: + pc = pc_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" *) + casez (pc_ok_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" */ + 1'h1: + pc = core_cia__data_o; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + core_cia__ren = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + casez (\$46 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + casez (pc_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:70" */ + default: + core_cia__ren = 3'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \svstate_ok_delay$next = svstate_ok_delay; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + casez (\$48 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + 1'h1: + \svstate_ok_delay$next = \$50 ; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \svstate_ok_delay$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + svstate = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + casez (\$52 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + 1'h1: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + casez (svstate_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + 1'h1: + svstate = \$54 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" *) + casez (svstate_ok_delay) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" */ + 1'h1: + svstate = core_sv__data_o; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + core_sv__ren = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + casez (\$56 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + casez (svstate_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:70" */ + default: + core_sv__ren = 3'h4; + endcase + endcase + end + always @* begin + if (\initial ) begin end + core_wen = 3'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$62 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + casez (pc_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + 1'h1: + core_wen = 3'h1; + endcase + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) + casez (fetch_insn_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + casez (\$66 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ + 1'h1: + core_wen = 3'h1; + endcase + endcase + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$72 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + casez (exec_pc_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + casez ({ \$78 , \$74 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + 2'b?1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + 2'b1?: + core_wen = 3'h1; + endcase + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) + casez (pc_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ + 1'h1: + core_wen = 3'h1; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \jtag_dmi0__ack_o$next = dbg_dmi_ack_o; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_dmi0__ack_o$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + core_data_i = 64'h0000000000000000; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$84 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + casez (pc_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + 1'h1: + core_data_i = pc_i; + endcase + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) + casez (fetch_insn_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + casez (\$88 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ + 1'h1: + core_data_i = nia; + endcase + endcase + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$94 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + casez (exec_pc_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + casez ({ \$100 , \$96 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + 2'b?1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + 2'b1?: + core_data_i = nia; + endcase + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) + casez (pc_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ + 1'h1: + core_data_i = pc_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + core_msr__ren = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + casez (fetch_pc_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + 1'h1: + core_msr__ren = 3'h2; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \jtag_dmi0__dout$next = dbg_dmi_dout; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_dmi0__dout$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + fetch_pc_ready_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + fetch_pc_ready_o = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + imem_a_pc_i = 48'h000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + casez (fetch_pc_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + 1'h1: + imem_a_pc_i = pc[47:0]; + endcase + endcase + end + always @* begin + if (\initial ) begin end + imem_a_valid_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + casez (fetch_pc_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + 1'h1: + imem_a_valid_i = 1'h1; + endcase + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + 1'h1: + imem_a_valid_i = 1'h1; + endcase + /* \nmigen.decoding = "INSN_READ2/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + 2'h3: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + 1'h1: + imem_a_valid_i = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + imem_f_valid_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + casez (fetch_pc_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + 1'h1: + imem_f_valid_i = 1'h1; + endcase + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + 1'h1: + imem_f_valid_i = 1'h1; + endcase + /* \nmigen.decoding = "INSN_READ2/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + 2'h3: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + 1'h1: + imem_f_valid_i = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \msr_read$next = msr_read; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + casez (fetch_pc_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + 1'h1: + \msr_read$next = 1'h0; + endcase + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + casez (\$102 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ + 1'h1: + \msr_read$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \msr_read$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \fetch_fsm_state$next = fetch_fsm_state; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + casez (fetch_pc_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + 1'h1: + \fetch_fsm_state$next = 2'h1; + endcase + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + default: + \fetch_fsm_state$next = 2'h2; + endcase + /* \nmigen.decoding = "INSN_READ2/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + 2'h3: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:362" */ + default: + \fetch_fsm_state$next = 2'h2; + endcase + /* \nmigen.decoding = "INSN_READY/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383" */ + 2'h2: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" *) + casez (fetch_insn_ready_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" */ + 1'h1: + \fetch_fsm_state$next = 2'h0; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \fetch_fsm_state$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \nia$next = nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + default: + \nia$next = \$104 [63:0]; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:994" *) + casez (core_coresync_rst) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:994" */ + 1'h1: + \nia$next = 64'h0000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \nia$next = 64'h0000000000000000; + endcase + end + always @* begin + if (\initial ) begin end + \dec2_raw_opcode_in$next = dec2_raw_opcode_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + default: + \dec2_raw_opcode_in$next = \$107 ; + endcase + /* \nmigen.decoding = "INSN_READ2/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + 2'h3: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:362" */ + default: + \dec2_raw_opcode_in$next = \$111 ; + endcase + endcase + end + always @* begin + if (\initial ) begin end + fetch_insn_valid_o = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + /* empty */; + /* \nmigen.decoding = "INSN_READ2/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + 2'h3: + /* empty */; + /* \nmigen.decoding = "INSN_READY/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383" */ + 2'h2: + fetch_insn_valid_o = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$122 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) + casez (svstate_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ + 1'h1: + { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; + endcase + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$128 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + casez (exec_pc_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + casez ({ \$134 , \$130 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + 2'b?1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + 2'b1?: + begin + new_svstate_srcstep = 7'h00; + new_svstate_dststep = 7'h00; + end + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ + default: + begin + new_svstate_srcstep = next_srcstep; + new_svstate_dststep = next_dststep; + end + endcase + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) + casez (svstate_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + 1'h1: + { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fetch_pc_valid_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$146 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + fetch_pc_valid_i = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \issue_fsm_state$next = issue_fsm_state; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$152 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" *) + casez (fetch_pc_ready_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" */ + 1'h1: + \issue_fsm_state$next = 3'h1; + endcase + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) + casez (fetch_insn_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + casez (\$156 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ + 1'h1: + \issue_fsm_state$next = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" */ + default: + \issue_fsm_state$next = 3'h2; + endcase + endcase + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:601" *) + casez (pred_insn_ready_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:601" */ + 1'h1: + \issue_fsm_state$next = 3'h4; + endcase + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + casez (pred_mask_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" */ + 1'h1: + \issue_fsm_state$next = 3'h5; + endcase + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) + casez (\$158 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + 1'h1: + \issue_fsm_state$next = 3'h2; + endcase + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + \issue_fsm_state$next = 3'h6; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687" *) + casez (exec_insn_ready_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687" */ + 1'h1: + \issue_fsm_state$next = 3'h7; + endcase + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$164 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + casez (exec_pc_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + casez ({ \$170 , \$166 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + 2'b?1: + \issue_fsm_state$next = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + 2'b1?: + \issue_fsm_state$next = 3'h0; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ + default: + \issue_fsm_state$next = 3'h5; + endcase + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \issue_fsm_state$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + core_stopped_i = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$176 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + default: + core_stopped_i = 1'h1; + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$182 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + default: + core_stopped_i = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + dbg_core_stopped_i = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$188 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + default: + dbg_core_stopped_i = 1'h1; + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$194 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + default: + dbg_core_stopped_i = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \pc_changed$next = pc_changed; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$200 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + casez (pc_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + 1'h1: + \pc_changed$next = 1'h1; + endcase + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$206 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) + casez (pc_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ + 1'h1: + \pc_changed$next = 1'h1; + endcase + endcase + endcase + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + casez (exec_fsm_state) + /* \nmigen.decoding = "INSN_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + 1'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + casez (exec_insn_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + 1'h1: + \pc_changed$next = 1'h0; + endcase + /* \nmigen.decoding = "INSN_ACTIVE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) + casez (\$208 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */ + 1'h1: + \pc_changed$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \pc_changed$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + update_svstate = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$216 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) + casez (svstate_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ + 1'h1: + update_svstate = 1'h1; + endcase + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$222 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) + casez (exec_pc_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) + casez ({ \$228 , \$224 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ + 2'b?1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ + 2'b1?: + update_svstate = 1'h1; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ + default: + update_svstate = 1'h1; + endcase + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) + casez (svstate_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + 1'h1: + update_svstate = 1'h1; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \sv_changed$next = sv_changed; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + casez (\$234 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) + casez (svstate_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ + 1'h1: + \sv_changed$next = 1'h1; + endcase + endcase + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + /* empty */; + /* \nmigen.decoding = "INSN_EXECUTE/6" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ + 3'h6: + /* empty */; + /* \nmigen.decoding = "EXECUTE_WAIT/7" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ + 3'h7: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + casez (\$240 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) + casez (svstate_i_ok) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + 1'h1: + \sv_changed$next = 1'h1; + endcase + endcase + endcase + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + casez (exec_fsm_state) + /* \nmigen.decoding = "INSN_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + 1'h0: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + casez (exec_insn_valid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + 1'h1: + \sv_changed$next = 1'h0; + endcase + /* \nmigen.decoding = "INSN_ACTIVE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) + casez (\$242 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" */ + 1'h1: + \sv_changed$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sv_changed$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fetch_insn_ready_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + fetch_insn_ready_i = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + insn_done = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) + casez (fetch_insn_valid_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + casez (\$248 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ + 1'h1: + insn_done = 1'h1; + endcase + endcase + endcase + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) + casez (exec_fsm_state) + /* \nmigen.decoding = "INSN_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + 1'h0: + /* empty */; + /* \nmigen.decoding = "INSN_ACTIVE/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + casez (\$250 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" *) + casez (exec_pc_ready_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" */ + 1'h1: + insn_done = 1'h1; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + pred_insn_valid_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + pred_insn_valid_i = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + pred_mask_ready_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + pred_mask_ready_i = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \core_asmcode$next = core_asmcode; + \core_core_rego$next = core_core_rego; + \core_rego_ok$next = core_rego_ok; + \core_core_ea$next = core_core_ea; + \core_ea_ok$next = core_ea_ok; + \core_core_reg1$next = core_core_reg1; + \core_core_reg1_ok$next = core_core_reg1_ok; + \core_core_reg2$next = core_core_reg2; + \core_core_reg2_ok$next = core_core_reg2_ok; + \core_core_reg3$next = core_core_reg3; + \core_core_reg3_ok$next = core_core_reg3_ok; + \core_core_spro$next = core_core_spro; + \core_spro_ok$next = core_spro_ok; + \core_core_spr1$next = core_core_spr1; + \core_core_spr1_ok$next = core_core_spr1_ok; + \core_core_xer_in$next = core_core_xer_in; + \core_xer_out$next = core_xer_out; + \core_core_fast1$next = core_core_fast1; + \core_core_fast1_ok$next = core_core_fast1_ok; + \core_core_fast2$next = core_core_fast2; + \core_core_fast2_ok$next = core_core_fast2_ok; + \core_core_fasto1$next = core_core_fasto1; + \core_fasto1_ok$next = core_fasto1_ok; + \core_core_fasto2$next = core_core_fasto2; + \core_fasto2_ok$next = core_fasto2_ok; + \core_core_cr_in1$next = core_core_cr_in1; + \core_core_cr_in1_ok$next = core_core_cr_in1_ok; + \core_core_cr_in2$next = core_core_cr_in2; + \core_core_cr_in2_ok$next = core_core_cr_in2_ok; + \core_core_cr_in2$1$next = \core_core_cr_in2$1 ; + \core_core_cr_in2_ok$2$next = \core_core_cr_in2_ok$2 ; + \core_core_cr_out$next = core_core_cr_out; + \core_cr_out_ok$next = core_cr_out_ok; + \core_core_core_msr$next = core_core_core_msr; + \core_core_core_cia$next = core_core_core_cia; + \core_core_core_insn$next = core_core_core_insn; + \core_core_core_insn_type$next = core_core_core_insn_type; + \core_core_core_fn_unit$next = core_core_core_fn_unit; + \core_core_lk$next = core_core_lk; + \core_core_core_rc$next = core_core_core_rc; + \core_core_core_rc_ok$next = core_core_core_rc_ok; + \core_core_core_oe$next = core_core_core_oe; + \core_core_core_oe_ok$next = core_core_core_oe_ok; + \core_core_core_input_carry$next = core_core_core_input_carry; + \core_core_core_traptype$next = core_core_core_traptype; + \core_core_core_exc_$signal$next = \core_core_core_exc_$signal ; + \core_core_core_exc_$signal$3$next = \core_core_core_exc_$signal$3 ; + \core_core_core_exc_$signal$4$next = \core_core_core_exc_$signal$4 ; + \core_core_core_exc_$signal$5$next = \core_core_core_exc_$signal$5 ; + \core_core_core_exc_$signal$6$next = \core_core_core_exc_$signal$6 ; + \core_core_core_exc_$signal$7$next = \core_core_core_exc_$signal$7 ; + \core_core_core_exc_$signal$8$next = \core_core_core_exc_$signal$8 ; + \core_core_core_exc_$signal$9$next = \core_core_core_exc_$signal$9 ; + \core_core_core_trapaddr$next = core_core_core_trapaddr; + \core_core_core_cr_rd$next = core_core_core_cr_rd; + \core_core_core_cr_rd_ok$next = core_core_core_cr_rd_ok; + \core_core_core_cr_wr$next = core_core_core_cr_wr; + \core_core_cr_wr_ok$next = core_core_cr_wr_ok; + \core_core_core_is_32bit$next = core_core_core_is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + casez (issue_fsm_state) + /* \nmigen.decoding = "ISSUE_START/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + 3'h0: + /* empty */; + /* \nmigen.decoding = "INSN_WAIT/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ + 3'h1: + /* empty */; + /* \nmigen.decoding = "PRED_START/3" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + 3'h3: + /* empty */; + /* \nmigen.decoding = "MASK_WAIT/4" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ + 3'h4: + /* empty */; + /* \nmigen.decoding = "PRED_SKIP/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + 3'h5: + /* empty */; + /* \nmigen.decoding = "DECODE_SV/2" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ + 3'h2: + { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_$signal$9$next , \core_core_core_exc_$signal$8$next , \core_core_core_exc_$signal$7$next , \core_core_core_exc_$signal$6$next , \core_core_core_exc_$signal$5$next , \core_core_core_exc_$signal$4$next , \core_core_core_exc_$signal$3$next , \core_core_core_exc_$signal$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, \dec2_exc_$signal$22 , \dec2_exc_$signal$21 , \dec2_exc_$signal$20 , \dec2_exc_$signal$19 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal , dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_cia, dec2_msr, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$15 , \dec2_cr_in2$14 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + begin + \core_rego_ok$next = 1'h0; + \core_ea_ok$next = 1'h0; + \core_core_reg1_ok$next = 1'h0; + \core_core_reg2_ok$next = 1'h0; + \core_core_reg3_ok$next = 1'h0; + \core_spro_ok$next = 1'h0; + \core_core_spr1_ok$next = 1'h0; + \core_core_fast1_ok$next = 1'h0; + \core_core_fast2_ok$next = 1'h0; + \core_fasto1_ok$next = 1'h0; + \core_fasto2_ok$next = 1'h0; + \core_core_cr_in1_ok$next = 1'h0; + \core_core_cr_in2_ok$next = 1'h0; + \core_core_cr_in2_ok$2$next = 1'h0; + \core_cr_out_ok$next = 1'h0; + \core_core_core_rc_ok$next = 1'h0; + \core_core_core_oe_ok$next = 1'h0; + \core_core_core_exc_$signal$next = 1'h0; + \core_core_core_exc_$signal$3$next = 1'h0; + \core_core_core_exc_$signal$4$next = 1'h0; + \core_core_core_exc_$signal$5$next = 1'h0; + \core_core_core_exc_$signal$6$next = 1'h0; + \core_core_core_exc_$signal$7$next = 1'h0; + \core_core_core_exc_$signal$8$next = 1'h0; + \core_core_core_exc_$signal$9$next = 1'h0; + \core_core_core_cr_rd_ok$next = 1'h0; + \core_core_cr_wr_ok$next = 1'h0; + end + endcase + end + assign \$27 = \$28 ; + assign \$104 = \$105 ; + assign \$112 = \$113 ; + assign \$136 = \$137 ; + assign \$139 = \$140 ; + assign \$278 = \$279 ; + assign \$281 = \$282 ; + assign dec2_sv_a_nz = 1'h0; + assign svstate_i_ok = 1'h0; + assign svstate_i = 32'd0; + assign is_svp64_mode = 1'h0; + assign pred_insn_ready_o = 1'h0; + assign pred_mask_valid_o = 1'h0; + assign next_dststep = \$140 [6:0]; + assign next_srcstep = \$137 [6:0]; + assign dbg_core_dbg_msr = dec2_cur_msr; + assign { dbg_core_dbg_core_dbg_maxvl, dbg_core_dbg_core_dbg_vl, dbg_core_dbg_core_dbg_srcstep, dbg_core_dbg_core_dbg_dststep, dbg_core_dbg_core_dbg_subvl, dbg_core_dbg_core_dbg_svstep } = svstate[31:0]; + assign dbg_core_dbg_pc = pc; + assign dbg_terminate_i = core_core_terminate_o; + assign pc_o = dec2_cur_pc; + assign core_cu_st__go_i = cu_st__rel_o_rise; + assign core_cu_ad__go_i = core_cu_ad__rel_o; + assign cu_st__rel_o_rise = \$38 ; + assign \cu_st__rel_o_dly$next = core_cu_st__rel_o; + assign dec2_bigendian = core_bigendian_i; + assign busy_o = core_corebusy_o; + assign core_coresync_rst = ti_rst; + assign ti_rst = \$34 ; + assign por_clk = clk; + assign { xics_icp_ics_i_pri, xics_icp_ics_i_src } = { xics_ics_icp_o_pri, xics_ics_icp_o_src }; + assign sram4k_3_enable = jtag_wb_sram_en; + assign sram4k_2_enable = jtag_wb_sram_en; + assign sram4k_1_enable = jtag_wb_sram_en; + assign sram4k_0_enable = jtag_wb_sram_en; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0" *) +(* generator = "nMigen" *) +module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, fast1_ok, fast2_ok, dest2_o, dest3_o, nia_ok, dest4_o, msr_ok, dest5_o, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [4:0] \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) + wire [4:0] \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$117 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$119 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) + wire [4:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [4:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire [4:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) + wire \$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire [4:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + wire \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [3:0] \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) + wire [4:0] \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) + wire [3:0] \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) + wire \$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) + wire [4:0] \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) + wire [4:0] \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [3:0] \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$81 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$83 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$85 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [3:0] \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [3:0] \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [3:0] \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [3:0] \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) + wire all_rd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg all_rd_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \all_rd_dly$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *) + wire all_rd_pulse; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire all_rd_rise; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) + wire alu_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg alu_done_dly = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + wire \alu_done_dly$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire alu_done_rise; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alu_l_q_alu; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alu_l_r_alu = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alu_l_r_alu$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alu_l_s_alu; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) + wire alu_pulse; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) + wire [4:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_trap0_fast1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \alu_trap0_fast1$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_trap0_fast2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] \alu_trap0_fast2$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_trap0_msr; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) + wire alu_trap0_n_ready_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) + wire alu_trap0_n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_trap0_nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [63:0] alu_trap0_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) + wire alu_trap0_p_ready_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) + wire alu_trap0_p_valid_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_trap0_ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [63:0] alu_trap0_rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_trap0_trap_op__cia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_trap0_trap_op__cia$next ; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] alu_trap0_trap_op__fn_unit = 14'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [13:0] \alu_trap0_trap_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] alu_trap0_trap_op__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [31:0] \alu_trap0_trap_op__insn$next ; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] alu_trap0_trap_op__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [6:0] \alu_trap0_trap_op__insn_type$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg alu_trap0_trap_op__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg \alu_trap0_trap_op__is_32bit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] alu_trap0_trap_op__ldst_exc = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] \alu_trap0_trap_op__ldst_exc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] alu_trap0_trap_op__msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [63:0] \alu_trap0_trap_op__msr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [12:0] alu_trap0_trap_op__trapaddr = 13'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [12:0] \alu_trap0_trap_op__trapaddr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] alu_trap0_trap_op__traptype = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + reg [7:0] \alu_trap0_trap_op__traptype$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire alui_l_q_alui; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg alui_l_r_alui = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \alui_l_r_alui$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + wire alui_l_s_alui; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) + output cu_busy_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *) + wire cu_done_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *) + wire cu_go_die_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) + input cu_issue_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [3:0] cu_rd__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [3:0] cu_rd__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) + input [3:0] cu_rdmaskn_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) + wire cu_shadown_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + input [4:0] cu_wr__go_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) + output [4:0] cu_wr__rel_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) + wire [4:0] cu_wrmask_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r0__o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r0__o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r0__o_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r0__o_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r1__fast1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r1__fast1$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r1__fast1_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r1__fast1_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r2__fast2 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r2__fast2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r2__fast2_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r2__fast2_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r3__nia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r3__nia$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__nia_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__nia_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r4__msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r4__msr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r4__msr_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r4__msr_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest1_o; + reg [63:0] dest1_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest2_o; + reg [63:0] dest2_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest3_o; + reg [63:0] dest3_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest4_o; + reg [63:0] dest4_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest5_o; + reg [63:0] dest5_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output msr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + output o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire opc_l_q_opc; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg opc_l_r_opc = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \opc_l_r_opc$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg opc_l_s_opc = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \opc_l_s_opc$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_trap0__cia; + (* enum_base_type = "Function" *) + (* enum_value_00000000000000 = "NONE" *) + (* enum_value_00000000000010 = "ALU" *) + (* enum_value_00000000000100 = "LDST" *) + (* enum_value_00000000001000 = "SHIFT_ROT" *) + (* enum_value_00000000010000 = "LOGICAL" *) + (* enum_value_00000000100000 = "BRANCH" *) + (* enum_value_00000001000000 = "CR" *) + (* enum_value_00000010000000 = "TRAP" *) + (* enum_value_00000100000000 = "MUL" *) + (* enum_value_00001000000000 = "DIV" *) + (* enum_value_00010000000000 = "SPR" *) + (* enum_value_00100000000000 = "MMU" *) + (* enum_value_01000000000000 = "SV" *) + (* enum_value_10000000000000 = "VL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [13:0] oper_i_alu_trap0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [31:0] oper_i_alu_trap0__insn; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [6:0] oper_i_alu_trap0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input oper_i_alu_trap0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] oper_i_alu_trap0__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [63:0] oper_i_alu_trap0__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [12:0] oper_i_alu_trap0__trapaddr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + input [7:0] oper_i_alu_trap0__traptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [4:0] prev_wr_go = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) + reg [4:0] \prev_wr_go$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) + reg req_done; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [4:0] req_l_q_req; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [4:0] req_l_r_req = 5'h1f; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [4:0] \req_l_r_req$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [4:0] req_l_s_req = 5'h00; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [4:0] \req_l_s_req$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) + wire reset; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) + wire [3:0] reset_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) + wire [4:0] reset_w; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire rok_l_q_rdok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rok_l_r_rdok = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rok_l_r_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rok_l_s_rdok = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rok_l_s_rdok$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg rst_l_r_rst = 1'h1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg \rst_l_r_rst$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg rst_l_s_rst = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg \rst_l_s_rst$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) + wire rst_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src1_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src2_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src3_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src4_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + wire [3:0] src_l_q_src; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [3:0] src_l_r_src = 4'hf; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + reg [3:0] \src_l_r_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [3:0] src_l_s_src = 4'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + reg [3:0] \src_l_s_src$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r0 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r0$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r1 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r1$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r2 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r2$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r3 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) + wire wr_any; + assign \$5 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ; + assign \$99 = \$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$97 ; + assign \$101 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$103 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$105 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$107 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$109 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$111 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$101 , \$103 , \$105 , \$107 , \$109 }; + assign \$113 = \$111 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$115 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$117 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ; + assign \$119 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$121 = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$123 = cu_wr__go_i[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$15 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ; + assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$19 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ; + assign \$21 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$27 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ; + assign \$24 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; + assign \$31 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; + assign \$33 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$35 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ; + assign \$3 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_trap0_n_ready_i; + assign \$41 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ; + assign \$43 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$45 = \$43 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$47 = \$41 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ; + assign \$49 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$51 = \$49 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_trap0_n_ready_i; + assign \$53 = \$51 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_trap0_n_valid_o; + assign \$55 = \$53 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$57 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$59 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$61 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$63 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$65 = alu_trap0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$67 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$69 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$71 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$73 = fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$75 = fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$77 = nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$79 = msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$81 = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0; + assign \$83 = src_l_q_src[1] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src2_i : src_r1; + assign \$85 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$87 = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3; + assign \$8 = \$6 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$89 = alu_trap0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$91 = alu_trap0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; + assign \$93 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$95 = \$93 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) 4'hf; + assign \$97 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + always @(posedge coresync_clk) + alu_l_r_alu <= \alu_l_r_alu$next ; + always @(posedge coresync_clk) + alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r3 <= \src_r3$next ; + always @(posedge coresync_clk) + src_r2 <= \src_r2$next ; + always @(posedge coresync_clk) + src_r1 <= \src_r1$next ; + always @(posedge coresync_clk) + src_r0 <= \src_r0$next ; + always @(posedge coresync_clk) + data_r4__msr <= \data_r4__msr$next ; + always @(posedge coresync_clk) + data_r4__msr_ok <= \data_r4__msr_ok$next ; + always @(posedge coresync_clk) + data_r3__nia <= \data_r3__nia$next ; + always @(posedge coresync_clk) + data_r3__nia_ok <= \data_r3__nia_ok$next ; + always @(posedge coresync_clk) + data_r2__fast2 <= \data_r2__fast2$next ; + always @(posedge coresync_clk) + data_r2__fast2_ok <= \data_r2__fast2_ok$next ; + always @(posedge coresync_clk) + data_r1__fast1 <= \data_r1__fast1$next ; + always @(posedge coresync_clk) + data_r1__fast1_ok <= \data_r1__fast1_ok$next ; + always @(posedge coresync_clk) + data_r0__o <= \data_r0__o$next ; + always @(posedge coresync_clk) + data_r0__o_ok <= \data_r0__o_ok$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__insn_type <= \alu_trap0_trap_op__insn_type$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__fn_unit <= \alu_trap0_trap_op__fn_unit$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__insn <= \alu_trap0_trap_op__insn$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__msr <= \alu_trap0_trap_op__msr$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__cia <= \alu_trap0_trap_op__cia$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__is_32bit <= \alu_trap0_trap_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__traptype <= \alu_trap0_trap_op__traptype$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__trapaddr <= \alu_trap0_trap_op__trapaddr$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__ldst_exc <= \alu_trap0_trap_op__ldst_exc$next ; + always @(posedge coresync_clk) + req_l_r_req <= \req_l_r_req$next ; + always @(posedge coresync_clk) + req_l_s_req <= \req_l_s_req$next ; + always @(posedge coresync_clk) + src_l_r_src <= \src_l_r_src$next ; + always @(posedge coresync_clk) + src_l_s_src <= \src_l_s_src$next ; + always @(posedge coresync_clk) + opc_l_r_opc <= \opc_l_r_opc$next ; + always @(posedge coresync_clk) + opc_l_s_opc <= \opc_l_s_opc$next ; + always @(posedge coresync_clk) + rst_l_r_rst <= \rst_l_r_rst$next ; + always @(posedge coresync_clk) + rst_l_s_rst <= \rst_l_s_rst$next ; + always @(posedge coresync_clk) + rok_l_r_rdok <= \rok_l_r_rdok$next ; + always @(posedge coresync_clk) + rok_l_s_rdok <= \rok_l_s_rdok$next ; + always @(posedge coresync_clk) + prev_wr_go <= \prev_wr_go$next ; + always @(posedge coresync_clk) + alu_done_dly <= alu_trap0_n_valid_o; + always @(posedge coresync_clk) + all_rd_dly <= \$11 ; + \alu_l$45 alu_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alu(alu_l_q_alu), + .r_alu(alu_l_r_alu), + .s_alu(alu_l_s_alu) + ); + alu_trap0 alu_trap0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .fast1(alu_trap0_fast1), + .\fast1$1 (\alu_trap0_fast1$1 ), + .fast1_ok(fast1_ok), + .fast2(alu_trap0_fast2), + .\fast2$2 (\alu_trap0_fast2$2 ), + .fast2_ok(fast2_ok), + .msr(alu_trap0_msr), + .msr_ok(msr_ok), + .n_ready_i(alu_trap0_n_ready_i), + .n_valid_o(alu_trap0_n_valid_o), + .nia(alu_trap0_nia), + .nia_ok(nia_ok), + .o(alu_trap0_o), + .o_ok(o_ok), + .p_ready_o(alu_trap0_p_ready_o), + .p_valid_i(alu_trap0_p_valid_i), + .ra(alu_trap0_ra), + .rb(alu_trap0_rb), + .trap_op__cia(alu_trap0_trap_op__cia), + .trap_op__fn_unit(alu_trap0_trap_op__fn_unit), + .trap_op__insn(alu_trap0_trap_op__insn), + .trap_op__insn_type(alu_trap0_trap_op__insn_type), + .trap_op__is_32bit(alu_trap0_trap_op__is_32bit), + .trap_op__ldst_exc(alu_trap0_trap_op__ldst_exc), + .trap_op__msr(alu_trap0_trap_op__msr), + .trap_op__trapaddr(alu_trap0_trap_op__trapaddr), + .trap_op__traptype(alu_trap0_trap_op__traptype) + ); + \alui_l$44 alui_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_alui(alui_l_q_alui), + .r_alui(alui_l_r_alui), + .s_alui(alui_l_s_alui) + ); + \opc_l$40 opc_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_opc(opc_l_q_opc), + .r_opc(opc_l_r_opc), + .s_opc(opc_l_s_opc) + ); + \req_l$41 req_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_req(req_l_q_req), + .r_req(req_l_r_req), + .s_req(req_l_s_req) + ); + \rok_l$43 rok_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_rdok(rok_l_q_rdok), + .r_rdok(rok_l_r_rdok), + .s_rdok(rok_l_s_rdok) + ); + \rst_l$42 rst_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .r_rst(rst_l_r_rst), + .s_rst(rst_l_s_rst) + ); + \src_l$39 src_l ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .q_src(src_l_q_src), + .r_src(src_l_r_src), + .s_src(src_l_s_src) + ); + always @* begin + if (\initial ) begin end + req_done = \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) + casez (\$55 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ + 1'h1: + req_done = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_s_rdok$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_s_rdok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rok_l_r_rdok$next = \$65 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rok_l_r_rdok$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_s_rst$next = all_rd; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_s_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \rst_l_r_rst$next = rst_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \rst_l_r_rst$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_s_opc$next = cu_issue_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_s_opc$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \opc_l_r_opc$next = req_done; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \opc_l_r_opc$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_s_src$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_l_r_src$next = reset_r; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \src_l_r_src$next = 4'hf; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_s_req$next = \$67 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_s_req$next = 5'h00; + endcase + end + always @* begin + if (\initial ) begin end + \req_l_r_req$next = \$69 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \req_l_r_req$next = 5'h1f; + endcase + end + always @* begin + if (\initial ) begin end + \alu_trap0_trap_op__insn_type$next = alu_trap0_trap_op__insn_type; + \alu_trap0_trap_op__fn_unit$next = alu_trap0_trap_op__fn_unit; + \alu_trap0_trap_op__insn$next = alu_trap0_trap_op__insn; + \alu_trap0_trap_op__msr$next = alu_trap0_trap_op__msr; + \alu_trap0_trap_op__cia$next = alu_trap0_trap_op__cia; + \alu_trap0_trap_op__is_32bit$next = alu_trap0_trap_op__is_32bit; + \alu_trap0_trap_op__traptype$next = alu_trap0_trap_op__traptype; + \alu_trap0_trap_op__trapaddr$next = alu_trap0_trap_op__trapaddr; + \alu_trap0_trap_op__ldst_exc$next = alu_trap0_trap_op__ldst_exc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ + 1'h1: + { \alu_trap0_trap_op__ldst_exc$next , \alu_trap0_trap_op__trapaddr$next , \alu_trap0_trap_op__traptype$next , \alu_trap0_trap_op__is_32bit$next , \alu_trap0_trap_op__cia$next , \alu_trap0_trap_op__msr$next , \alu_trap0_trap_op__insn$next , \alu_trap0_trap_op__fn_unit$next , \alu_trap0_trap_op__insn_type$next } = { oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__traptype, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__cia, oper_i_alu_trap0__msr, oper_i_alu_trap0__insn, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn_type }; + endcase + end + always @* begin + if (\initial ) begin end + \data_r0__o$next = data_r0__o; + \data_r0__o_ok$next = data_r0__o_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = { o_ok, alu_trap0_o }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r0__o_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r1__fast1$next = data_r1__fast1; + \data_r1__fast1_ok$next = data_r1__fast1_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r1__fast1_ok$next , \data_r1__fast1$next } = { fast1_ok, alu_trap0_fast1 }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r1__fast1_ok$next , \data_r1__fast1$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r1__fast1_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r2__fast2$next = data_r2__fast2; + \data_r2__fast2_ok$next = data_r2__fast2_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r2__fast2_ok$next , \data_r2__fast2$next } = { fast2_ok, alu_trap0_fast2 }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r2__fast2_ok$next , \data_r2__fast2$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r2__fast2_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r3__nia$next = data_r3__nia; + \data_r3__nia_ok$next = data_r3__nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r3__nia_ok$next , \data_r3__nia$next } = { nia_ok, alu_trap0_nia }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r3__nia_ok$next , \data_r3__nia$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r3__nia_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r4__msr$next = data_r4__msr; + \data_r4__msr_ok$next = data_r4__msr_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r4__msr_ok$next , \data_r4__msr$next } = { msr_ok, alu_trap0_msr }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r4__msr_ok$next , \data_r4__msr$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \data_r4__msr_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \src_r0$next = src_r0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[0]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r0$next = src1_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r1$next = src_r1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[1]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r1$next = src2_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r2$next = src_r2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[2]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r2$next = src3_i; + endcase + end + always @* begin + if (\initial ) begin end + \src_r3$next = src_r3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[3]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r3$next = src4_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$89 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alui_l_r_alui$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \alu_l_r_alu$next = \$91 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \alu_l_r_alu$next = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + dest1_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$115 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest1_o = data_r0__o; + endcase + end + always @* begin + if (\initial ) begin end + dest2_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$117 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest2_o = data_r1__fast1; + endcase + end + always @* begin + if (\initial ) begin end + dest3_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$119 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest3_o = data_r2__fast2; + endcase + end + always @* begin + if (\initial ) begin end + dest4_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$121 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest4_o = data_r3__nia; + endcase + end + always @* begin + if (\initial ) begin end + dest5_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$123 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest5_o = data_r4__msr; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$21 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \prev_wr_go$next = 5'h00; + endcase + end + assign cu_go_die_i = 1'h0; + assign cu_shadown_i = 1'h1; + assign cu_wr__rel_o = \$113 ; + assign cu_rd__rel_o = \$99 ; + assign cu_busy_o = opc_l_q_opc; + assign alu_l_s_alu = all_rd_pulse; + assign alu_trap0_n_ready_i = alu_l_q_alu; + assign alui_l_s_alui = all_rd_pulse; + assign alu_trap0_p_valid_i = alui_l_q_alui; + assign \alu_trap0_fast2$2 = \$87 ; + assign \alu_trap0_fast1$1 = \$85 ; + assign alu_trap0_rb = \$83 ; + assign alu_trap0_ra = \$81 ; + assign cu_wrmask_o = { \$79 , \$77 , \$75 , \$73 , \$71 }; + assign reset_r = \$63 ; + assign reset_w = \$61 ; + assign rst_r = \$59 ; + assign reset = \$57 ; + assign wr_any = \$37 ; + assign cu_done_o = \$31 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse }; + assign alu_pulse = alu_done_rise; + assign alu_done_rise = \$19 ; + assign \alu_done_dly$next = alu_done; + assign alu_done = alu_trap0_n_valid_o; + assign all_rd_pulse = all_rd_rise; + assign all_rd_rise = \$15 ; + assign \all_rd_dly$next = all_rd; + assign all_rd = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.upd_l" *) +(* generator = "nMigen" *) +module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_upd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_upd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_upd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_upd; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_upd; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_upd; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_upd; + assign \$15 = q_upd | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_upd; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_upd; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_upd; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_upd = \$15 ; + assign qn_upd = \$13 ; + assign q_upd = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.valid_l" *) +(* generator = "nMigen" *) +module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_valid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_valid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_valid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_valid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_valid; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_valid; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_valid; + assign \$15 = q_valid | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_valid; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_valid; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_valid; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_valid = \$15 ; + assign qn_valid = \$13 ; + assign q_valid = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.wri_l" *) +(* generator = "nMigen" *) +module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg q_int = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) + reg \q_int$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) + output q_wri; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) + wire qlq_wri; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) + wire qn_wri; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) + input r_wri; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) + input s_wri; + assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; + assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_wri; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_wri; + assign \$15 = q_wri | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_wri; + assign \$3 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ; + assign \$5 = \$3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_wri; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_wri; + always @(posedge coresync_clk) + q_int <= \q_int$next ; + always @* begin + if (\initial ) begin end + \q_int$next = \$5 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \q_int$next = 1'h0; + endcase + end + assign qlq_wri = \$15 ; + assign qn_wri = \$13 ; + assign q_wri = \$11 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_CR_cr_a" *) +(* generator = "nMigen" *) +module wrpick_CR_cr_a(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [5:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [5:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [5:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [5:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t5; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] }; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ; + assign \$23 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$23 ; + assign o = { t5, t4, t3, t2, t1, t0 }; + assign t5 = \$19 ; + assign t4 = \$15 ; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_CR_full_cr" *) +(* generator = "nMigen" *) +module wrpick_CR_full_cr(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_FAST_fast1" *) +(* generator = "nMigen" *) +module wrpick_FAST_fast1(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [4:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [4:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [4:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [4:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t4; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] }; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$19 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$19 ; + assign o = { t4, t3, t2, t1, t0 }; + assign t4 = \$15 ; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_INT_o" *) +(* generator = "nMigen" *) +module wrpick_INT_o(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [9:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$35 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [9:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [9:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [9:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t5; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t6; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t7; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t8; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t9; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] }; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ; + assign \$24 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[5:0], ni[6] }; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$24 ; + assign \$28 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[6:0], ni[7] }; + assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$28 ; + assign \$32 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[7:0], ni[8] }; + assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$32 ; + assign \$36 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[8:0], ni[9] }; + assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$36 ; + assign \$39 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$39 ; + assign o = { t9, t8, t7, t6, t5, t4, t3, t2, t1, t0 }; + assign t9 = \$35 ; + assign t8 = \$31 ; + assign t7 = \$27 ; + assign t6 = \$23 ; + assign t5 = \$19 ; + assign t4 = \$15 ; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_SPR_spr1" *) +(* generator = "nMigen" *) +module wrpick_SPR_spr1(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_STATE_msr" *) +(* generator = "nMigen" *) +module wrpick_STATE_msr(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_STATE_nia" *) +(* generator = "nMigen" *) +module wrpick_STATE_nia(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [1:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [1:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [1:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [1:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$7 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$7 ; + assign o = { t1, t0 }; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_XER_xer_ca" *) +(* generator = "nMigen" *) +module wrpick_XER_xer_ca(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [2:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [2:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [2:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [2:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$11 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$11 ; + assign o = { t2, t1, t0 }; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_XER_xer_ov" *) +(* generator = "nMigen" *) +module wrpick_XER_xer_ov(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [3:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [3:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [3:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [3:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$15 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$15 ; + assign o = { t3, t2, t1, t0 }; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_XER_xer_so" *) +(* generator = "nMigen" *) +module wrpick_XER_xer_so(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire [3:0] \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$4 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input [3:0] i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire [3:0] ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output [3:0] o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t1; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t2; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t3; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; + assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; + assign \$15 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; + assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; + assign en_o = \$15 ; + assign o = { t3, t2, t1, t0 }; + assign t3 = \$11 ; + assign t2 = \$7 ; + assign t1 = \$3 ; + assign t0 = i[0]; + assign ni = \$1 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.core.xer" *) +(* generator = "nMigen" *) +module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, src2__data_o, src2__ren, src3__data_o, src3__ren, data_i, wen, \data_i$1 , \wen$2 , \data_i$3 , \wen$4 , coresync_clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [1:0] \$14 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [1:0] \$16 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [1:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [1:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [1:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [1:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) + input coresync_rst; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] \data_i$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] \data_i$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [5:0] full_rd__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] full_rd__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [5:0] full_wr__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] full_wr__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_0_dest10__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_dest10__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_0_dest20__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_dest20__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_0_dest30__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_dest30__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_0_r0__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_r0__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_0_src10__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_src10__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_0_src20__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_src20__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_0_src30__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_src30__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_0_w0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_w0__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_1_dest11__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_dest11__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_1_dest21__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_dest21__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_1_dest31__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_dest31__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_1_r1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_r1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_1_src11__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_src11__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_1_src21__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_src21__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_1_src31__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_src31__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_1_w1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_w1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_2_dest12__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_dest12__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_2_dest22__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_dest22__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_2_dest32__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_dest32__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_2_r2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_r2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_2_src12__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_src12__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_2_src22__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_src22__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_2_src32__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_src32__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] reg_2_w2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_w2__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] ren_delay = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$11 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$18 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$18$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + reg [2:0] \ren_delay$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src1__data_o; + reg [1:0] src1__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] src1__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src2__data_o; + reg [1:0] src2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] src2__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] src3__data_o; + reg [1:0] src3__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] src3__ren; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] \wen$2 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] \wen$4 ; + assign \$9 = reg_0_src10__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$7 ; + assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$11 ; + assign \$14 = reg_1_src21__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_src22__data_o; + assign \$16 = reg_0_src20__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$14 ; + assign \$19 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$18 ; + assign \$21 = reg_1_src31__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_src32__data_o; + assign \$23 = reg_0_src30__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$21 ; + assign \$5 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) ren_delay; + assign \$7 = reg_1_src11__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_src12__data_o; + always @(posedge coresync_clk) + \ren_delay$18 <= \ren_delay$18$next ; + always @(posedge coresync_clk) + \ren_delay$11 <= \ren_delay$11$next ; + always @(posedge coresync_clk) + ren_delay <= \ren_delay$next ; + \reg_0$132 reg_0 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest10__data_i(reg_0_dest10__data_i), + .dest10__wen(reg_0_dest10__wen), + .dest20__data_i(reg_0_dest20__data_i), + .dest20__wen(reg_0_dest20__wen), + .dest30__data_i(reg_0_dest30__data_i), + .dest30__wen(reg_0_dest30__wen), + .r0__data_o(reg_0_r0__data_o), + .r0__ren(reg_0_r0__ren), + .src10__data_o(reg_0_src10__data_o), + .src10__ren(reg_0_src10__ren), + .src20__data_o(reg_0_src20__data_o), + .src20__ren(reg_0_src20__ren), + .src30__data_o(reg_0_src30__data_o), + .src30__ren(reg_0_src30__ren), + .w0__data_i(reg_0_w0__data_i), + .w0__wen(reg_0_w0__wen) + ); + \reg_1$133 reg_1 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest11__data_i(reg_1_dest11__data_i), + .dest11__wen(reg_1_dest11__wen), + .dest21__data_i(reg_1_dest21__data_i), + .dest21__wen(reg_1_dest21__wen), + .dest31__data_i(reg_1_dest31__data_i), + .dest31__wen(reg_1_dest31__wen), + .r1__data_o(reg_1_r1__data_o), + .r1__ren(reg_1_r1__ren), + .src11__data_o(reg_1_src11__data_o), + .src11__ren(reg_1_src11__ren), + .src21__data_o(reg_1_src21__data_o), + .src21__ren(reg_1_src21__ren), + .src31__data_o(reg_1_src31__data_o), + .src31__ren(reg_1_src31__ren), + .w1__data_i(reg_1_w1__data_i), + .w1__wen(reg_1_w1__wen) + ); + \reg_2$134 reg_2 ( + .coresync_clk(coresync_clk), + .coresync_rst(coresync_rst), + .dest12__data_i(reg_2_dest12__data_i), + .dest12__wen(reg_2_dest12__wen), + .dest22__data_i(reg_2_dest22__data_i), + .dest22__wen(reg_2_dest22__wen), + .dest32__data_i(reg_2_dest32__data_i), + .dest32__wen(reg_2_dest32__wen), + .r2__data_o(reg_2_r2__data_o), + .r2__ren(reg_2_r2__ren), + .src12__data_o(reg_2_src12__data_o), + .src12__ren(reg_2_src12__ren), + .src22__data_o(reg_2_src22__data_o), + .src22__ren(reg_2_src22__ren), + .src32__data_o(reg_2_src32__data_o), + .src32__ren(reg_2_src32__ren), + .w2__data_i(reg_2_w2__data_i), + .w2__wen(reg_2_w2__wen) + ); + always @* begin + if (\initial ) begin end + \ren_delay$18$next = src3__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$18$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + src3__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + src3__data_o = \$23 ; + endcase + end + always @* begin + if (\initial ) begin end + \ren_delay$next = src1__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + src1__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$5 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + src1__data_o = \$9 ; + endcase + end + always @* begin + if (\initial ) begin end + \ren_delay$11$next = src2__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (coresync_rst) + 1'h1: + \ren_delay$11$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + src2__data_o = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + casez (\$12 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + 1'h1: + src2__data_o = \$16 ; + endcase + end + assign full_wr__data_i = 6'h00; + assign full_wr__wen = 3'h0; + assign { reg_2_w2__wen, reg_1_w1__wen, reg_0_w0__wen } = 3'h0; + assign { reg_2_w2__data_i, reg_1_w1__data_i, reg_0_w0__data_i } = 6'h00; + assign { reg_2_r2__ren, reg_1_r1__ren, reg_0_r0__ren } = full_rd__ren; + assign full_rd__data_o = { reg_2_r2__data_o, reg_1_r1__data_o, reg_0_r0__data_o }; + assign reg_2_dest32__data_i = \data_i$1 ; + assign reg_1_dest31__data_i = \data_i$1 ; + assign reg_0_dest30__data_i = \data_i$1 ; + assign { reg_2_dest32__wen, reg_1_dest31__wen, reg_0_dest30__wen } = \wen$2 ; + assign reg_2_dest22__data_i = data_i; + assign reg_1_dest21__data_i = data_i; + assign reg_0_dest20__data_i = data_i; + assign { reg_2_dest22__wen, reg_1_dest21__wen, reg_0_dest20__wen } = wen; + assign reg_2_dest12__data_i = \data_i$3 ; + assign reg_1_dest11__data_i = \data_i$3 ; + assign reg_0_dest10__data_i = \data_i$3 ; + assign { reg_2_dest12__wen, reg_1_dest11__wen, reg_0_dest10__wen } = \wen$4 ; + assign { reg_2_src32__ren, reg_1_src31__ren, reg_0_src30__ren } = src3__ren; + assign { reg_2_src22__ren, reg_1_src21__ren, reg_0_src20__ren } = src2__ren; + assign { reg_2_src12__ren, reg_1_src11__ren, reg_0_src10__ren } = src1__ren; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.xics_icp" *) +(* generator = "nMigen" *) +module xics_icp(rst, ics_i_src, ics_i_pri, core_irq_o, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" *) + wire [31:0] be_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *) + reg [31:0] be_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) + output core_irq_o; + reg core_irq_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) + reg \core_irq_o$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *) + reg [7:0] cppr = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *) + reg [7:0] \cppr$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *) + wire [7:0] \cppr$2 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *) + reg [7:0] \cppr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + output icp_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [27:0] icp_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + output [31:0] icp_wb__dat_r; + reg [31:0] icp_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [31:0] icp_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input [3:0] icp_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *) + input icp_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *) + input [7:0] ics_i_pri; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) + input [3:0] ics_i_src; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" *) + reg irq = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" *) + reg \irq$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" *) + wire \irq$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" *) + reg \irq$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" *) + reg [7:0] mfrr = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" *) + reg [7:0] \mfrr$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" *) + wire [7:0] \mfrr$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" *) + reg [7:0] \mfrr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" *) + reg [7:0] min_pri; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *) + reg [7:0] pending_priority; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *) + reg wb_ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *) + reg \wb_ack$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *) + wire \wb_ack$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *) + reg \wb_ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" *) + reg [31:0] wb_rd_data = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" *) + reg [31:0] \wb_rd_data$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" *) + wire [31:0] \wb_rd_data$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" *) + reg [31:0] \wb_rd_data$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" *) + reg xirr_accept_rd; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" *) + reg [23:0] xisr = 24'h000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" *) + wire [23:0] \xisr$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" *) + reg [23:0] \xisr$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" *) + reg [23:0] \xisr$next ; + assign \$15 = icp_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) icp_wb__stb; + assign \$17 = ics_i_pri != (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) 8'hff; + assign \$19 = mfrr < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) pending_priority; + assign \$21 = min_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" *) \cppr$10 ; + assign \$23 = icp_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) icp_wb__stb; + assign \$25 = icp_wb__sel == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" *) 4'hf; + assign \$27 = icp_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) icp_wb__stb; + assign \$29 = ics_i_pri != (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) 8'hff; + assign \$31 = mfrr < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) pending_priority; + assign \$7 = wb_ack & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" *) icp_wb__cyc; + always @(posedge clk) + core_irq_o <= \core_irq_o$next ; + always @(posedge clk) + xisr <= \xisr$next ; + always @(posedge clk) + cppr <= \cppr$next ; + always @(posedge clk) + mfrr <= \mfrr$next ; + always @(posedge clk) + irq <= \irq$next ; + always @(posedge clk) + wb_rd_data <= \wb_rd_data$next ; + always @(posedge clk) + wb_ack <= \wb_ack$next ; + always @* begin + if (\initial ) begin end + { \wb_ack$next , \wb_rd_data$next , \irq$next , \mfrr$next , \cppr$next , \xisr$next } = { \wb_ack$6 , \wb_rd_data$5 , \irq$4 , \mfrr$3 , \cppr$2 , \xisr$1 }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + begin + \xisr$next = 24'h000000; + \cppr$next = 8'h00; + \mfrr$next = 8'hff; + \irq$next = 1'h0; + \wb_rd_data$next = 32'd0; + \wb_ack$next = 1'h0; + end + endcase + end + always @* begin + if (\initial ) begin end + xirr_accept_rd = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) + casez (\$23 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" *) + casez (icp_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:153" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" *) + casez (icp_wb__adr[5:0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:156" */ + 6'h00: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:159" */ + 6'h01: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" */ + 1'h1: + xirr_accept_rd = 1'h1; + endcase + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + be_out = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" *) + casez (icp_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:153" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" *) + casez (icp_wb__adr[5:0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:156" */ + 6'h00: + be_out = { cppr, xisr }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:159" */ + 6'h01: + be_out = { cppr, xisr }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:164" */ + 6'h03: + be_out[31:24] = mfrr; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + pending_priority = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" */ + 1'h1: + pending_priority = ics_i_pri; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" */ + 1'h1: + min_pri = mfrr; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:181" */ + default: + min_pri = pending_priority; + endcase + end + always @* begin + if (\initial ) begin end + \core_irq_o$next = irq; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \core_irq_o$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + icp_wb__dat_r = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" *) + casez (icp_wb__ack) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" */ + 1'h1: + icp_wb__dat_r = wb_rd_data; + endcase + end + always @* begin + if (\initial ) begin end + { \wb_ack$14 , \wb_rd_data$13 , \irq$12 , \mfrr$11 , \cppr$10 , \xisr$9 } = { wb_ack, wb_rd_data, irq, mfrr, cppr, xisr }; + \wb_ack$14 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" */ + 1'h1: + begin + \wb_ack$14 = 1'h1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" *) + casez (icp_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" *) + casez (icp_wb__adr[5:0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:122" */ + 6'h00: + \cppr$10 = be_in[31:24]; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:125" */ + 6'h01: + \cppr$10 = be_in[31:24]; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:139" */ + 6'h03: + \mfrr$11 = be_in[31:24]; + endcase + endcase + end + endcase + begin + \xisr$9 = 24'h000000; + end + begin + \irq$12 = 1'h0; + end + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) + casez (\$17 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" */ + 1'h1: + \xisr$9 = { 20'h00001, ics_i_src }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" */ + 1'h1: + \xisr$9 = 24'h000002; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" *) + casez (xirr_accept_rd) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" */ + 1'h1: + \cppr$10 = min_pri; + endcase + begin + \wb_rd_data$13 = { be_out[7:0], be_out[15:8], be_out[23:16], be_out[31:24] }; + end + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" *) + casez ({ irq, \$21 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" */ + 2'b?1: + \irq$12 = 1'h1; + endcase + end + assign { \wb_ack$6 , \wb_rd_data$5 , \irq$4 , \mfrr$3 , \cppr$2 , \xisr$1 } = { \wb_ack$14 , \wb_rd_data$13 , \irq$12 , \mfrr$11 , \cppr$10 , \xisr$9 }; + assign be_in = { icp_wb__dat_w[7:0], icp_wb__dat_w[15:8], icp_wb__dat_w[23:16], icp_wb__dat_w[31:24] }; + assign icp_wb__ack = \$7 ; +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.xics_ics" *) +(* generator = "nMigen" *) +module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$109 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$111 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$113 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$117 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$119 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$125 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$127 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$129 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$131 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$133 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$135 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$137 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$141 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$143 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$145 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$147 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$149 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$151 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$153 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$155 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$157 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$159 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$161 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$163 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$165 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$167 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$169 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$171 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$173 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$175 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$177 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$179 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$181 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$183 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$185 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$187 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$189 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$191 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$193 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$195 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$197 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$199 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$201 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$203 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$204 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire [7:0] \$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:315" *) + wire \$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" *) + wire \$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + wire \$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + wire \$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) + wire \$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:337" *) + wire [31:0] be_in; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *) + reg [31:0] be_out; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx15; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) + reg [3:0] cur_idx9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri15; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *) + reg [7:0] cur_pri9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" *) + reg ibit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *) + output [7:0] icp_o_pri; + reg [7:0] icp_o_pri = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *) + wire [7:0] \icp_o_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) + output [3:0] icp_o_src; + reg [3:0] icp_o_src = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) + wire [3:0] \icp_o_src$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *) + wire [7:0] icp_r_pri; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) + wire [3:0] icp_r_src; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + output ics_wb__ack; + reg ics_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + reg \ics_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input [27:0] ics_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + output [31:0] ics_wb__dat_r; + reg [31:0] ics_wb__dat_r = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + reg [31:0] \ics_wb__dat_r$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input [31:0] ics_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *) + input ics_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *) + input [15:0] int_level_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" *) + reg [15:0] int_level_l = 16'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" *) + reg [15:0] \int_level_l$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:358" *) + wire [3:0] max_idx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:359" *) + wire [7:0] max_pri; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:261" *) + wire [3:0] reg_idx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:287" *) + wire reg_is_config; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:288" *) + wire reg_is_debug; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *) + wire reg_is_xive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *) + wire wb_valid; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive0_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive0_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive10_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive10_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive11_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive11_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive12_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive12_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive13_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive13_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive14_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive14_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive15_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive15_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive1_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive1_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive2_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive2_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive3_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive3_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive4_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive4_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive5_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive5_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive6_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive6_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive7_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive7_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive8_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive8_pri$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] xive9_pri = 8'hff; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *) + reg [7:0] \xive9_pri$next ; + assign \$7 = \$8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive0_pri; + assign \$99 = xive3_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri2; + assign \$101 = int_level_l[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$99 ; + assign \$103 = xive3_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri2; + assign \$105 = int_level_l[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$103 ; + assign \$107 = xive4_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri3; + assign \$109 = int_level_l[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$107 ; + assign \$111 = xive4_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri3; + assign \$113 = int_level_l[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$111 ; + assign \$115 = xive5_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri4; + assign \$117 = int_level_l[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$115 ; + assign \$119 = xive5_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri4; + assign \$121 = int_level_l[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$119 ; + assign \$123 = xive6_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri5; + assign \$125 = int_level_l[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$123 ; + assign \$127 = xive6_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri5; + assign \$12 = xive1_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$129 = int_level_l[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$127 ; + assign \$131 = xive7_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri6; + assign \$133 = int_level_l[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$131 ; + assign \$135 = xive7_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri6; + assign \$137 = int_level_l[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$135 ; + assign \$11 = \$12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive1_pri; + assign \$139 = xive8_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri7; + assign \$141 = int_level_l[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$139 ; + assign \$143 = xive8_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri7; + assign \$145 = int_level_l[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$143 ; + assign \$147 = xive9_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri8; + assign \$149 = int_level_l[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$147 ; + assign \$151 = xive9_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri8; + assign \$153 = int_level_l[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$151 ; + assign \$155 = xive10_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri9; + assign \$157 = int_level_l[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$155 ; + assign \$159 = xive10_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri9; + assign \$161 = int_level_l[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$159 ; + assign \$163 = xive11_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri10; + assign \$165 = int_level_l[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$163 ; + assign \$167 = xive11_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri10; + assign \$16 = xive2_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$169 = int_level_l[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$167 ; + assign \$171 = xive12_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri11; + assign \$173 = int_level_l[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$171 ; + assign \$175 = xive12_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri11; + assign \$177 = int_level_l[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$175 ; + assign \$15 = \$16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive2_pri; + assign \$179 = xive13_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri12; + assign \$181 = int_level_l[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$179 ; + assign \$183 = xive13_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri12; + assign \$185 = int_level_l[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$183 ; + assign \$187 = xive14_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri13; + assign \$189 = int_level_l[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$187 ; + assign \$191 = xive14_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri13; + assign \$193 = int_level_l[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$191 ; + assign \$195 = xive15_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri14; + assign \$197 = int_level_l[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$195 ; + assign \$1 = ics_wb__adr[9:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" *) 1'h0; + assign \$199 = xive15_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri14; + assign \$201 = int_level_l[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$199 ; + assign \$204 = cur_pri15 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$203 = \$204 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : cur_pri15; + assign \$20 = xive3_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$19 = \$20 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive3_pri; + assign \$24 = xive4_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$23 = \$24 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive4_pri; + assign \$28 = xive5_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$27 = \$28 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive5_pri; + assign \$32 = xive6_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$31 = \$32 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive6_pri; + assign \$36 = xive7_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$35 = \$36 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive7_pri; + assign \$3 = ics_wb__adr[9:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" *) 3'h4; + assign \$40 = xive8_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$39 = \$40 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive8_pri; + assign \$44 = xive9_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$43 = \$44 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive9_pri; + assign \$48 = xive10_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$47 = \$48 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive10_pri; + assign \$52 = xive11_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$51 = \$52 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive11_pri; + assign \$56 = xive12_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$55 = \$56 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive12_pri; + assign \$5 = ics_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" *) ics_wb__stb; + assign \$60 = xive13_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$59 = \$60 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive13_pri; + assign \$64 = xive14_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$63 = \$64 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive14_pri; + assign \$68 = xive15_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$67 = \$68 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive15_pri; + assign \$71 = int_level_l >> reg_idx; + assign \$73 = wb_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" *) ics_wb__we; + assign \$75 = xive0_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) max_pri; + assign \$77 = int_level_l[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$75 ; + assign \$79 = xive0_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) max_pri; + assign \$81 = int_level_l[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$79 ; + assign \$83 = xive1_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri0; + assign \$85 = int_level_l[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$83 ; + assign \$87 = xive1_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri0; + assign \$8 = xive0_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff; + assign \$89 = int_level_l[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$87 ; + assign \$91 = xive2_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri1; + assign \$93 = int_level_l[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$91 ; + assign \$95 = xive2_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri1; + assign \$97 = int_level_l[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$95 ; + always @(posedge clk) + icp_o_src <= cur_idx15; + always @(posedge clk) + icp_o_pri <= \$203 ; + always @(posedge clk) + xive0_pri <= \xive0_pri$next ; + always @(posedge clk) + xive1_pri <= \xive1_pri$next ; + always @(posedge clk) + xive2_pri <= \xive2_pri$next ; + always @(posedge clk) + xive3_pri <= \xive3_pri$next ; + always @(posedge clk) + xive4_pri <= \xive4_pri$next ; + always @(posedge clk) + xive5_pri <= \xive5_pri$next ; + always @(posedge clk) + xive6_pri <= \xive6_pri$next ; + always @(posedge clk) + xive7_pri <= \xive7_pri$next ; + always @(posedge clk) + xive8_pri <= \xive8_pri$next ; + always @(posedge clk) + xive9_pri <= \xive9_pri$next ; + always @(posedge clk) + xive10_pri <= \xive10_pri$next ; + always @(posedge clk) + xive11_pri <= \xive11_pri$next ; + always @(posedge clk) + xive12_pri <= \xive12_pri$next ; + always @(posedge clk) + xive13_pri <= \xive13_pri$next ; + always @(posedge clk) + xive14_pri <= \xive14_pri$next ; + always @(posedge clk) + xive15_pri <= \xive15_pri$next ; + always @(posedge clk) + ics_wb__ack <= \ics_wb__ack$next ; + always @(posedge clk) + ics_wb__dat_r <= \ics_wb__dat_r$next ; + always @(posedge clk) + int_level_l <= \int_level_l$next ; + always @* begin + if (\initial ) begin end + \xive0_pri$next = xive0_pri; + \xive1_pri$next = xive1_pri; + \xive2_pri$next = xive2_pri; + \xive3_pri$next = xive3_pri; + \xive4_pri$next = xive4_pri; + \xive5_pri$next = xive5_pri; + \xive6_pri$next = xive6_pri; + \xive7_pri$next = xive7_pri; + \xive8_pri$next = xive8_pri; + \xive9_pri$next = xive9_pri; + \xive10_pri$next = xive10_pri; + \xive11_pri$next = xive11_pri; + \xive12_pri$next = xive12_pri; + \xive13_pri$next = xive13_pri; + \xive14_pri$next = xive14_pri; + \xive15_pri$next = xive15_pri; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" *) + casez (\$73 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" *) + casez (reg_is_xive) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" *) + casez (reg_idx) + 4'h0: + \xive0_pri$next = be_in[7:0]; + 4'h1: + \xive1_pri$next = be_in[7:0]; + 4'h2: + \xive2_pri$next = be_in[7:0]; + 4'h3: + \xive3_pri$next = be_in[7:0]; + 4'h4: + \xive4_pri$next = be_in[7:0]; + 4'h5: + \xive5_pri$next = be_in[7:0]; + 4'h6: + \xive6_pri$next = be_in[7:0]; + 4'h7: + \xive7_pri$next = be_in[7:0]; + 4'h8: + \xive8_pri$next = be_in[7:0]; + 4'h9: + \xive9_pri$next = be_in[7:0]; + 4'ha: + \xive10_pri$next = be_in[7:0]; + 4'hb: + \xive11_pri$next = be_in[7:0]; + 4'hc: + \xive12_pri$next = be_in[7:0]; + 4'hd: + \xive13_pri$next = be_in[7:0]; + 4'he: + \xive14_pri$next = be_in[7:0]; + 4'h?: + \xive15_pri$next = be_in[7:0]; + endcase + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + begin + \xive0_pri$next = 8'hff; + \xive1_pri$next = 8'hff; + \xive2_pri$next = 8'hff; + \xive3_pri$next = 8'hff; + \xive4_pri$next = 8'hff; + \xive5_pri$next = 8'hff; + \xive6_pri$next = 8'hff; + \xive7_pri$next = 8'hff; + \xive8_pri$next = 8'hff; + \xive9_pri$next = 8'hff; + \xive10_pri$next = 8'hff; + \xive11_pri$next = 8'hff; + \xive12_pri$next = 8'hff; + \xive13_pri$next = 8'hff; + \xive14_pri$next = 8'hff; + \xive15_pri$next = 8'hff; + end + endcase + end + always @* begin + if (\initial ) begin end + cur_pri0 = max_pri; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$77 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri0 = xive0_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx0 = max_idx; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$81 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx0 = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri1 = cur_pri0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$85 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri1 = xive1_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx1 = cur_idx0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$89 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx1 = 4'h1; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri2 = cur_pri1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$93 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri2 = xive2_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx2 = cur_idx1; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$97 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx2 = 4'h2; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri3 = cur_pri2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$101 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri3 = xive3_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx3 = cur_idx2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$105 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx3 = 4'h3; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri4 = cur_pri3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$109 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri4 = xive4_pri; + endcase + end + always @* begin + if (\initial ) begin end + \int_level_l$next = int_level_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \int_level_l$next = 16'h0000; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx4 = cur_idx3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$113 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx4 = 4'h4; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri5 = cur_pri4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$117 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri5 = xive5_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx5 = cur_idx4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$121 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx5 = 4'h5; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri6 = cur_pri5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$125 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri6 = xive6_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx6 = cur_idx5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$129 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx6 = 4'h6; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri7 = cur_pri6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$133 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri7 = xive7_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx7 = cur_idx6; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$137 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx7 = 4'h7; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri8 = cur_pri7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$141 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri8 = xive8_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx8 = cur_idx7; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$145 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx8 = 4'h8; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri9 = cur_pri8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$149 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri9 = xive9_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx9 = cur_idx8; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$153 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx9 = 4'h9; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri10 = cur_pri9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$157 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri10 = xive10_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx10 = cur_idx9; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$161 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx10 = 4'ha; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri11 = cur_pri10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$165 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri11 = xive11_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx11 = cur_idx10; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$169 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx11 = 4'hb; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri12 = cur_pri11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$173 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri12 = xive12_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx12 = cur_idx11; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$177 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx12 = 4'hc; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri13 = cur_pri12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$181 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri13 = xive13_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx13 = cur_idx12; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$185 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx13 = 4'hd; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri14 = cur_pri13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$189 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri14 = xive14_pri; + endcase + end + always @* begin + if (\initial ) begin end + be_out = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" *) + casez ({ reg_is_debug, reg_is_config, reg_is_xive }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" */ + 3'b??1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) + casez (reg_idx) + 4'h0: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$7 }; + 4'h1: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$11 }; + 4'h2: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$15 }; + 4'h3: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$19 }; + 4'h4: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$23 }; + 4'h5: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$27 }; + 4'h6: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$31 }; + 4'h7: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$35 }; + 4'h8: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$39 }; + 4'h9: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$43 }; + 4'ha: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$47 }; + 4'hb: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$51 }; + 4'hc: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$55 }; + 4'hd: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$59 }; + 4'he: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$63 }; + 4'h?: + be_out = { ibit, 1'h0, ibit, 21'h000000, \$67 }; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:323" */ + 3'b?1?: + be_out = 32'd134217744; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:328" */ + 3'b1??: + be_out = { icp_r_src, 20'h00000, icp_r_pri }; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx14 = cur_idx13; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$193 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx14 = 4'he; + endcase + end + always @* begin + if (\initial ) begin end + cur_pri15 = cur_pri14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$197 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_pri15 = xive15_pri; + endcase + end + always @* begin + if (\initial ) begin end + cur_idx15 = cur_idx14; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) + casez (\$201 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" */ + 1'h1: + cur_idx15 = 4'hf; + endcase + end + always @* begin + if (\initial ) begin end + ibit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" *) + casez ({ reg_is_debug, reg_is_config, reg_is_xive }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" */ + 3'b??1: + ibit = \$71 ; + endcase + end + always @* begin + if (\initial ) begin end + \ics_wb__dat_r$next = { be_out[7:0], be_out[15:8], be_out[23:16], be_out[31:24] }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ics_wb__dat_r$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \ics_wb__ack$next = wb_valid; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ics_wb__ack$next = 1'h0; + endcase + end + assign icp_r_pri = \$203 ; + assign icp_r_src = cur_idx15; + assign max_idx = 4'h0; + assign max_pri = 8'hff; + assign { \icp_o_pri$next , \icp_o_src$next } = { icp_r_pri, icp_r_src }; + assign be_in = { ics_wb__dat_w[7:0], ics_wb__dat_w[15:8], ics_wb__dat_w[23:16], ics_wb__dat_w[31:24] }; + assign wb_valid = \$5 ; + assign reg_idx = ics_wb__adr[3:0]; + assign reg_is_debug = \$3 ; + assign reg_is_config = \$1 ; + assign reg_is_xive = ics_wb__adr[9]; +endmodule diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v new file mode 100644 index 0000000..c54b8dd --- /dev/null +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v @@ -0,0 +1,5899 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-18 11:23:13 +//-------------------------------------------------------------------------------- +module ls180sram4k( + input wire [15:0] gpio_i, + output wire [15:0] gpio_o, + output wire [15:0] gpio_oe, + input wire eint_0, + input wire eint_1, + input wire eint_2, + output wire [12:0] sdram_a, + input wire [15:0] sdram_dq_i, + output wire [15:0] sdram_dq_o, + output wire [15:0] sdram_dq_oe, + output wire sdram_we_n, + output wire sdram_ras_n, + output wire sdram_cas_n, + output wire sdram_cs_n, + output wire sdram_cke, + output wire [1:0] sdram_ba, + output wire [1:0] sdram_dm, + output wire sdram_clock, + output wire i2c_scl, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_oe, + output wire spimaster_clk, + output wire spimaster_mosi, + output wire spimaster_cs_n, + input wire spimaster_miso, + input wire uart_tx, + input wire uart_rx, + input wire sys_clk, + input wire sys_rst, + input wire jtag_tms, + input wire jtag_tck, + input wire jtag_tdi, + output wire jtag_tdo, + input wire [39:0] nc +); + +(* ram_style = "distributed" *) reg libresocsim_reset_storage = 1'd0; +reg libresocsim_reset_re = 1'd0; +(* ram_style = "distributed" *) reg [31:0] libresocsim_scratch_storage = 32'd305419896; +reg libresocsim_scratch_re = 1'd0; +wire [31:0] libresocsim_bus_errors_status; +wire libresocsim_bus_errors_we; +wire libresocsim_reset; +wire libresocsim_bus_error; +reg [31:0] libresocsim_bus_errors = 32'd0; +wire libresocsim_libresoc_reset; +reg [15:0] libresocsim_libresoc_interrupt = 16'd0; +wire [28:0] libresocsim_libresoc_dbus_adr; +wire [63:0] libresocsim_libresoc_dbus_dat_w; +wire [63:0] libresocsim_libresoc_dbus_dat_r; +wire [7:0] libresocsim_libresoc_dbus_sel; +wire libresocsim_libresoc_dbus_cyc; +wire libresocsim_libresoc_dbus_stb; +reg libresocsim_libresoc_dbus_ack = 1'd0; +wire libresocsim_libresoc_dbus_we; +reg libresocsim_libresoc_dbus_err = 1'd0; +wire [28:0] libresocsim_libresoc_ibus_adr; +wire [63:0] libresocsim_libresoc_ibus_dat_w; +wire [63:0] libresocsim_libresoc_ibus_dat_r; +wire [7:0] libresocsim_libresoc_ibus_sel; +wire libresocsim_libresoc_ibus_cyc; +wire libresocsim_libresoc_ibus_stb; +reg libresocsim_libresoc_ibus_ack = 1'd0; +wire libresocsim_libresoc_ibus_we; +reg libresocsim_libresoc_ibus_err = 1'd0; +wire [29:0] libresocsim_libresoc_xics_icp_adr; +wire [31:0] libresocsim_libresoc_xics_icp_dat_w; +wire [31:0] libresocsim_libresoc_xics_icp_dat_r; +wire [3:0] libresocsim_libresoc_xics_icp_sel; +wire libresocsim_libresoc_xics_icp_cyc; +wire libresocsim_libresoc_xics_icp_stb; +wire libresocsim_libresoc_xics_icp_ack; +wire libresocsim_libresoc_xics_icp_we; +wire [2:0] libresocsim_libresoc_xics_icp_cti; +wire [1:0] libresocsim_libresoc_xics_icp_bte; +wire libresocsim_libresoc_xics_icp_err; +wire [29:0] libresocsim_libresoc_xics_ics_adr; +wire [31:0] libresocsim_libresoc_xics_ics_dat_w; +wire [31:0] libresocsim_libresoc_xics_ics_dat_r; +wire [3:0] libresocsim_libresoc_xics_ics_sel; +wire libresocsim_libresoc_xics_ics_cyc; +wire libresocsim_libresoc_xics_ics_stb; +wire libresocsim_libresoc_xics_ics_ack; +wire libresocsim_libresoc_xics_ics_we; +wire [2:0] libresocsim_libresoc_xics_ics_cti; +wire [1:0] libresocsim_libresoc_xics_ics_bte; +wire libresocsim_libresoc_xics_ics_err; +wire [29:0] libresocsim_libresoc_jtag_wb_adr; +wire [31:0] libresocsim_libresoc_jtag_wb_dat_w; +wire [31:0] libresocsim_libresoc_jtag_wb_dat_r; +wire [3:0] libresocsim_libresoc_jtag_wb_sel; +wire libresocsim_libresoc_jtag_wb_cyc; +wire libresocsim_libresoc_jtag_wb_stb; +wire libresocsim_libresoc_jtag_wb_ack; +wire libresocsim_libresoc_jtag_wb_we; +reg [2:0] libresocsim_libresoc_jtag_wb_cti = 3'd0; +reg [1:0] libresocsim_libresoc_jtag_wb_bte = 2'd0; +wire libresocsim_libresoc_jtag_wb_err; +wire libresocsim_libresoc_jtag_tck; +wire libresocsim_libresoc_jtag_tms; +wire libresocsim_libresoc_jtag_tdi; +wire libresocsim_libresoc_jtag_tdo; +reg [63:0] libresocsim_libresoc0 = 64'd0; +wire libresocsim_libresoc1; +wire libresocsim_libresoc2; +wire [63:0] libresocsim_libresoc3; +wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; +wire libresocsim_libresoc_constraintmanager_eint_0; +wire libresocsim_libresoc_constraintmanager_eint_1; +wire libresocsim_libresoc_constraintmanager_eint_2; +reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; +wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i; +reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; +reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_oe = 16'd0; +reg libresocsim_libresoc_constraintmanager_sdram_we_n = 1'd0; +reg libresocsim_libresoc_constraintmanager_sdram_ras_n = 1'd0; +reg libresocsim_libresoc_constraintmanager_sdram_cas_n = 1'd0; +reg libresocsim_libresoc_constraintmanager_sdram_cs_n = 1'd0; +reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; +reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; +reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; +reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; +wire libresocsim_libresoc_constraintmanager_i2c_scl; +wire libresocsim_libresoc_constraintmanager_i2c_sda_i; +wire libresocsim_libresoc_constraintmanager_i2c_sda_o; +wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; +reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; +wire libresocsim_libresoc_constraintmanager_spimaster_miso; +reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; +reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; +reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; +reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; +wire [31:0] libresocsim_interface0_converted_interface_dat_r; +reg [3:0] libresocsim_interface0_converted_interface_sel = 4'd0; +reg libresocsim_interface0_converted_interface_cyc = 1'd0; +reg libresocsim_interface0_converted_interface_stb = 1'd0; +wire libresocsim_interface0_converted_interface_ack; +reg libresocsim_interface0_converted_interface_we = 1'd0; +reg [2:0] libresocsim_interface0_converted_interface_cti = 3'd0; +reg [1:0] libresocsim_interface0_converted_interface_bte = 2'd0; +wire libresocsim_interface0_converted_interface_err; +reg libresocsim_converter0_skip = 1'd0; +reg libresocsim_converter0_counter = 1'd0; +wire libresocsim_converter0_reset; +reg [63:0] libresocsim_converter0_dat_r = 64'd0; +reg [29:0] libresocsim_interface1_converted_interface_adr = 30'd0; +reg [31:0] libresocsim_interface1_converted_interface_dat_w = 32'd0; +wire [31:0] libresocsim_interface1_converted_interface_dat_r; +reg [3:0] libresocsim_interface1_converted_interface_sel = 4'd0; +reg libresocsim_interface1_converted_interface_cyc = 1'd0; +reg libresocsim_interface1_converted_interface_stb = 1'd0; +wire libresocsim_interface1_converted_interface_ack; +reg libresocsim_interface1_converted_interface_we = 1'd0; +reg [2:0] libresocsim_interface1_converted_interface_cti = 3'd0; +reg [1:0] libresocsim_interface1_converted_interface_bte = 2'd0; +wire libresocsim_interface1_converted_interface_err; +reg libresocsim_converter1_skip = 1'd0; +reg libresocsim_converter1_counter = 1'd0; +wire libresocsim_converter1_reset; +reg [63:0] libresocsim_converter1_dat_r = 64'd0; +wire [29:0] libresocsim_ram_bus_adr; +wire [31:0] libresocsim_ram_bus_dat_w; +wire [31:0] libresocsim_ram_bus_dat_r; +wire [3:0] libresocsim_ram_bus_sel; +wire libresocsim_ram_bus_cyc; +wire libresocsim_ram_bus_stb; +reg libresocsim_ram_bus_ack = 1'd0; +wire libresocsim_ram_bus_we; +wire [2:0] libresocsim_ram_bus_cti; +wire [1:0] libresocsim_ram_bus_bte; +reg libresocsim_ram_bus_err = 1'd0; +wire [6:0] libresocsim_adr; +wire [31:0] libresocsim_dat_r; +reg [3:0] libresocsim_we = 4'd0; +wire [31:0] libresocsim_dat_w; +(* ram_style = "distributed" *) reg [31:0] libresocsim_load_storage = 32'd0; +reg libresocsim_load_re = 1'd0; +(* ram_style = "distributed" *) reg [31:0] libresocsim_reload_storage = 32'd0; +reg libresocsim_reload_re = 1'd0; +(* ram_style = "distributed" *) reg libresocsim_en_storage = 1'd0; +reg libresocsim_en_re = 1'd0; +(* ram_style = "distributed" *) reg libresocsim_update_value_storage = 1'd0; +reg libresocsim_update_value_re = 1'd0; +reg [31:0] libresocsim_value_status = 32'd0; +wire libresocsim_value_we; +wire libresocsim_irq; +wire libresocsim_zero_status; +reg libresocsim_zero_pending = 1'd0; +wire libresocsim_zero_trigger; +reg libresocsim_zero_clear = 1'd0; +reg libresocsim_zero_old_trigger = 1'd0; +wire libresocsim_eventmanager_status_re; +wire libresocsim_eventmanager_status_r; +wire libresocsim_eventmanager_status_we; +wire libresocsim_eventmanager_status_w; +wire libresocsim_eventmanager_pending_re; +wire libresocsim_eventmanager_pending_r; +wire libresocsim_eventmanager_pending_we; +wire libresocsim_eventmanager_pending_w; +(* ram_style = "distributed" *) reg libresocsim_eventmanager_storage = 1'd0; +reg libresocsim_eventmanager_re = 1'd0; +reg [31:0] libresocsim_value = 32'd0; +wire [29:0] ram_bus_ram_bus_adr; +wire [31:0] ram_bus_ram_bus_dat_w; +wire [31:0] ram_bus_ram_bus_dat_r; +wire [3:0] ram_bus_ram_bus_sel; +wire ram_bus_ram_bus_cyc; +wire ram_bus_ram_bus_stb; +reg ram_bus_ram_bus_ack = 1'd0; +wire ram_bus_ram_bus_we; +wire [2:0] ram_bus_ram_bus_cti; +wire [1:0] ram_bus_ram_bus_bte; +reg ram_bus_ram_bus_err = 1'd0; +wire [4:0] ram_adr; +wire [31:0] ram_dat_r; +reg [3:0] ram_we = 4'd0; +wire [31:0] ram_dat_w; +wire sys_clk_1; +wire sys_rst_1; +wire por_clk; +reg int_rst = 1'd1; +wire [12:0] dfi_p0_address; +wire [1:0] dfi_p0_bank; +wire dfi_p0_cas_n; +wire dfi_p0_cs_n; +wire dfi_p0_ras_n; +wire dfi_p0_we_n; +wire dfi_p0_cke; +wire dfi_p0_odt; +wire dfi_p0_reset_n; +wire dfi_p0_act_n; +wire [15:0] dfi_p0_wrdata; +wire dfi_p0_wrdata_en; +wire [1:0] dfi_p0_wrdata_mask; +wire dfi_p0_rddata_en; +reg [15:0] dfi_p0_rddata = 16'd0; +reg dfi_p0_rddata_valid = 1'd0; +reg [2:0] rddata_en = 3'd0; +wire [12:0] sdram_inti_p0_address; +wire [1:0] sdram_inti_p0_bank; +reg sdram_inti_p0_cas_n = 1'd1; +reg sdram_inti_p0_cs_n = 1'd1; +reg sdram_inti_p0_ras_n = 1'd1; +reg sdram_inti_p0_we_n = 1'd1; +wire sdram_inti_p0_cke; +wire sdram_inti_p0_odt; +wire sdram_inti_p0_reset_n; +reg sdram_inti_p0_act_n = 1'd1; +wire [15:0] sdram_inti_p0_wrdata; +wire sdram_inti_p0_wrdata_en; +wire [1:0] sdram_inti_p0_wrdata_mask; +wire sdram_inti_p0_rddata_en; +reg [15:0] sdram_inti_p0_rddata = 16'd0; +reg sdram_inti_p0_rddata_valid = 1'd0; +wire [12:0] sdram_slave_p0_address; +wire [1:0] sdram_slave_p0_bank; +wire sdram_slave_p0_cas_n; +wire sdram_slave_p0_cs_n; +wire sdram_slave_p0_ras_n; +wire sdram_slave_p0_we_n; +wire sdram_slave_p0_cke; +wire sdram_slave_p0_odt; +wire sdram_slave_p0_reset_n; +wire sdram_slave_p0_act_n; +wire [15:0] sdram_slave_p0_wrdata; +wire sdram_slave_p0_wrdata_en; +wire [1:0] sdram_slave_p0_wrdata_mask; +wire sdram_slave_p0_rddata_en; +reg [15:0] sdram_slave_p0_rddata = 16'd0; +reg sdram_slave_p0_rddata_valid = 1'd0; +reg [12:0] sdram_master_p0_address = 13'd0; +reg [1:0] sdram_master_p0_bank = 2'd0; +reg sdram_master_p0_cas_n = 1'd1; +reg sdram_master_p0_cs_n = 1'd1; +reg sdram_master_p0_ras_n = 1'd1; +reg sdram_master_p0_we_n = 1'd1; +reg sdram_master_p0_cke = 1'd0; +reg sdram_master_p0_odt = 1'd0; +reg sdram_master_p0_reset_n = 1'd0; +reg sdram_master_p0_act_n = 1'd1; +reg [15:0] sdram_master_p0_wrdata = 16'd0; +reg sdram_master_p0_wrdata_en = 1'd0; +reg [1:0] sdram_master_p0_wrdata_mask = 2'd0; +reg sdram_master_p0_rddata_en = 1'd0; +wire [15:0] sdram_master_p0_rddata; +wire sdram_master_p0_rddata_valid; +wire sdram_sel; +wire sdram_cke_1; +wire sdram_odt; +wire sdram_reset_n; +(* ram_style = "distributed" *) reg [3:0] sdram_storage = 4'd1; +reg sdram_re = 1'd0; +(* ram_style = "distributed" *) reg [5:0] sdram_command_storage = 6'd0; +reg sdram_command_re = 1'd0; +wire sdram_command_issue_re; +wire sdram_command_issue_r; +wire sdram_command_issue_we; +reg sdram_command_issue_w = 1'd0; +(* ram_style = "distributed" *) reg [12:0] sdram_address_storage = 13'd0; +reg sdram_address_re = 1'd0; +(* ram_style = "distributed" *) reg [1:0] sdram_baddress_storage = 2'd0; +reg sdram_baddress_re = 1'd0; +(* ram_style = "distributed" *) reg [15:0] sdram_wrdata_storage = 16'd0; +reg sdram_wrdata_re = 1'd0; +reg [15:0] sdram_status = 16'd0; +wire sdram_we; +wire sdram_interface_bank0_valid; +wire sdram_interface_bank0_ready; +wire sdram_interface_bank0_we; +wire [21:0] sdram_interface_bank0_addr; +wire sdram_interface_bank0_lock; +wire sdram_interface_bank0_wdata_ready; +wire sdram_interface_bank0_rdata_valid; +wire sdram_interface_bank1_valid; +wire sdram_interface_bank1_ready; +wire sdram_interface_bank1_we; +wire [21:0] sdram_interface_bank1_addr; +wire sdram_interface_bank1_lock; +wire sdram_interface_bank1_wdata_ready; +wire sdram_interface_bank1_rdata_valid; +wire sdram_interface_bank2_valid; +wire sdram_interface_bank2_ready; +wire sdram_interface_bank2_we; +wire [21:0] sdram_interface_bank2_addr; +wire sdram_interface_bank2_lock; +wire sdram_interface_bank2_wdata_ready; +wire sdram_interface_bank2_rdata_valid; +wire sdram_interface_bank3_valid; +wire sdram_interface_bank3_ready; +wire sdram_interface_bank3_we; +wire [21:0] sdram_interface_bank3_addr; +wire sdram_interface_bank3_lock; +wire sdram_interface_bank3_wdata_ready; +wire sdram_interface_bank3_rdata_valid; +reg [15:0] sdram_interface_wdata = 16'd0; +reg [1:0] sdram_interface_wdata_we = 2'd0; +wire [15:0] sdram_interface_rdata; +reg [12:0] sdram_dfi_p0_address = 13'd0; +reg [1:0] sdram_dfi_p0_bank = 2'd0; +reg sdram_dfi_p0_cas_n = 1'd1; +reg sdram_dfi_p0_cs_n = 1'd1; +reg sdram_dfi_p0_ras_n = 1'd1; +reg sdram_dfi_p0_we_n = 1'd1; +wire sdram_dfi_p0_cke; +wire sdram_dfi_p0_odt; +wire sdram_dfi_p0_reset_n; +reg sdram_dfi_p0_act_n = 1'd1; +wire [15:0] sdram_dfi_p0_wrdata; +reg sdram_dfi_p0_wrdata_en = 1'd0; +wire [1:0] sdram_dfi_p0_wrdata_mask; +reg sdram_dfi_p0_rddata_en = 1'd0; +wire [15:0] sdram_dfi_p0_rddata; +wire sdram_dfi_p0_rddata_valid; +reg sdram_cmd_valid = 1'd0; +reg sdram_cmd_ready = 1'd0; +reg sdram_cmd_last = 1'd0; +reg [12:0] sdram_cmd_payload_a = 13'd0; +reg [1:0] sdram_cmd_payload_ba = 2'd0; +reg sdram_cmd_payload_cas = 1'd0; +reg sdram_cmd_payload_ras = 1'd0; +reg sdram_cmd_payload_we = 1'd0; +reg sdram_cmd_payload_is_read = 1'd0; +reg sdram_cmd_payload_is_write = 1'd0; +wire sdram_wants_refresh; +wire sdram_timer_wait; +wire sdram_timer_done0; +wire [9:0] sdram_timer_count0; +wire sdram_timer_done1; +reg [9:0] sdram_timer_count1 = 10'd781; +wire sdram_postponer_req_i; +reg sdram_postponer_req_o = 1'd0; +reg sdram_postponer_count = 1'd0; +reg sdram_sequencer_start0 = 1'd0; +wire sdram_sequencer_done0; +wire sdram_sequencer_start1; +reg sdram_sequencer_done1 = 1'd0; +reg [3:0] sdram_sequencer_counter = 4'd0; +reg sdram_sequencer_count = 1'd0; +wire sdram_bankmachine0_req_valid; +wire sdram_bankmachine0_req_ready; +wire sdram_bankmachine0_req_we; +wire [21:0] sdram_bankmachine0_req_addr; +wire sdram_bankmachine0_req_lock; +reg sdram_bankmachine0_req_wdata_ready = 1'd0; +reg sdram_bankmachine0_req_rdata_valid = 1'd0; +wire sdram_bankmachine0_refresh_req; +reg sdram_bankmachine0_refresh_gnt = 1'd0; +reg sdram_bankmachine0_cmd_valid = 1'd0; +reg sdram_bankmachine0_cmd_ready = 1'd0; +reg [12:0] sdram_bankmachine0_cmd_payload_a = 13'd0; +wire [1:0] sdram_bankmachine0_cmd_payload_ba; +reg sdram_bankmachine0_cmd_payload_cas = 1'd0; +reg sdram_bankmachine0_cmd_payload_ras = 1'd0; +reg sdram_bankmachine0_cmd_payload_we = 1'd0; +reg sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine0_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine0_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine0_auto_precharge = 1'd0; +wire sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine0_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine0_cmd_buffer_sink_valid; +wire sdram_bankmachine0_cmd_buffer_sink_ready; +wire sdram_bankmachine0_cmd_buffer_sink_first; +wire sdram_bankmachine0_cmd_buffer_sink_last; +wire sdram_bankmachine0_cmd_buffer_sink_payload_we; +wire [21:0] sdram_bankmachine0_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine0_cmd_buffer_source_ready; +reg sdram_bankmachine0_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine0_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [12:0] sdram_bankmachine0_row = 13'd0; +reg sdram_bankmachine0_row_opened = 1'd0; +wire sdram_bankmachine0_row_hit; +reg sdram_bankmachine0_row_open = 1'd0; +reg sdram_bankmachine0_row_close = 1'd0; +reg sdram_bankmachine0_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine0_twtpcon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine0_twtpcon_count = 3'd0; +wire sdram_bankmachine0_trccon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine0_trccon_ready = 1'd1; +wire sdram_bankmachine0_trascon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine0_trascon_ready = 1'd1; +wire sdram_bankmachine1_req_valid; +wire sdram_bankmachine1_req_ready; +wire sdram_bankmachine1_req_we; +wire [21:0] sdram_bankmachine1_req_addr; +wire sdram_bankmachine1_req_lock; +reg sdram_bankmachine1_req_wdata_ready = 1'd0; +reg sdram_bankmachine1_req_rdata_valid = 1'd0; +wire sdram_bankmachine1_refresh_req; +reg sdram_bankmachine1_refresh_gnt = 1'd0; +reg sdram_bankmachine1_cmd_valid = 1'd0; +reg sdram_bankmachine1_cmd_ready = 1'd0; +reg [12:0] sdram_bankmachine1_cmd_payload_a = 13'd0; +wire [1:0] sdram_bankmachine1_cmd_payload_ba; +reg sdram_bankmachine1_cmd_payload_cas = 1'd0; +reg sdram_bankmachine1_cmd_payload_ras = 1'd0; +reg sdram_bankmachine1_cmd_payload_we = 1'd0; +reg sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine1_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine1_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine1_auto_precharge = 1'd0; +wire sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [3:0] sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine1_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine1_cmd_buffer_sink_valid; +wire sdram_bankmachine1_cmd_buffer_sink_ready; +wire sdram_bankmachine1_cmd_buffer_sink_first; +wire sdram_bankmachine1_cmd_buffer_sink_last; +wire sdram_bankmachine1_cmd_buffer_sink_payload_we; +wire [21:0] sdram_bankmachine1_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine1_cmd_buffer_source_ready; +reg sdram_bankmachine1_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine1_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [12:0] sdram_bankmachine1_row = 13'd0; +reg sdram_bankmachine1_row_opened = 1'd0; +wire sdram_bankmachine1_row_hit; +reg sdram_bankmachine1_row_open = 1'd0; +reg sdram_bankmachine1_row_close = 1'd0; +reg sdram_bankmachine1_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine1_twtpcon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine1_twtpcon_count = 3'd0; +wire sdram_bankmachine1_trccon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine1_trccon_ready = 1'd1; +wire sdram_bankmachine1_trascon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine1_trascon_ready = 1'd1; +wire sdram_bankmachine2_req_valid; +wire sdram_bankmachine2_req_ready; +wire sdram_bankmachine2_req_we; +wire [21:0] sdram_bankmachine2_req_addr; +wire sdram_bankmachine2_req_lock; +reg sdram_bankmachine2_req_wdata_ready = 1'd0; +reg sdram_bankmachine2_req_rdata_valid = 1'd0; +wire sdram_bankmachine2_refresh_req; +reg sdram_bankmachine2_refresh_gnt = 1'd0; +reg sdram_bankmachine2_cmd_valid = 1'd0; +reg sdram_bankmachine2_cmd_ready = 1'd0; +reg [12:0] sdram_bankmachine2_cmd_payload_a = 13'd0; +wire [1:0] sdram_bankmachine2_cmd_payload_ba; +reg sdram_bankmachine2_cmd_payload_cas = 1'd0; +reg sdram_bankmachine2_cmd_payload_ras = 1'd0; +reg sdram_bankmachine2_cmd_payload_we = 1'd0; +reg sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine2_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine2_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine2_auto_precharge = 1'd0; +wire sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [3:0] sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine2_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine2_cmd_buffer_sink_valid; +wire sdram_bankmachine2_cmd_buffer_sink_ready; +wire sdram_bankmachine2_cmd_buffer_sink_first; +wire sdram_bankmachine2_cmd_buffer_sink_last; +wire sdram_bankmachine2_cmd_buffer_sink_payload_we; +wire [21:0] sdram_bankmachine2_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine2_cmd_buffer_source_ready; +reg sdram_bankmachine2_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine2_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [12:0] sdram_bankmachine2_row = 13'd0; +reg sdram_bankmachine2_row_opened = 1'd0; +wire sdram_bankmachine2_row_hit; +reg sdram_bankmachine2_row_open = 1'd0; +reg sdram_bankmachine2_row_close = 1'd0; +reg sdram_bankmachine2_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine2_twtpcon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine2_twtpcon_count = 3'd0; +wire sdram_bankmachine2_trccon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine2_trccon_ready = 1'd1; +wire sdram_bankmachine2_trascon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine2_trascon_ready = 1'd1; +wire sdram_bankmachine3_req_valid; +wire sdram_bankmachine3_req_ready; +wire sdram_bankmachine3_req_we; +wire [21:0] sdram_bankmachine3_req_addr; +wire sdram_bankmachine3_req_lock; +reg sdram_bankmachine3_req_wdata_ready = 1'd0; +reg sdram_bankmachine3_req_rdata_valid = 1'd0; +wire sdram_bankmachine3_refresh_req; +reg sdram_bankmachine3_refresh_gnt = 1'd0; +reg sdram_bankmachine3_cmd_valid = 1'd0; +reg sdram_bankmachine3_cmd_ready = 1'd0; +reg [12:0] sdram_bankmachine3_cmd_payload_a = 13'd0; +wire [1:0] sdram_bankmachine3_cmd_payload_ba; +reg sdram_bankmachine3_cmd_payload_cas = 1'd0; +reg sdram_bankmachine3_cmd_payload_ras = 1'd0; +reg sdram_bankmachine3_cmd_payload_we = 1'd0; +reg sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg sdram_bankmachine3_cmd_payload_is_read = 1'd0; +reg sdram_bankmachine3_cmd_payload_is_write = 1'd0; +reg sdram_bankmachine3_auto_precharge = 1'd0; +wire sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_first; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_last; +wire sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [3:0] sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0; +reg sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire sdram_bankmachine3_cmd_buffer_lookahead_do_read; +wire [2:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire sdram_bankmachine3_cmd_buffer_sink_valid; +wire sdram_bankmachine3_cmd_buffer_sink_ready; +wire sdram_bankmachine3_cmd_buffer_sink_first; +wire sdram_bankmachine3_cmd_buffer_sink_last; +wire sdram_bankmachine3_cmd_buffer_sink_payload_we; +wire [21:0] sdram_bankmachine3_cmd_buffer_sink_payload_addr; +reg sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire sdram_bankmachine3_cmd_buffer_source_ready; +reg sdram_bankmachine3_cmd_buffer_source_first = 1'd0; +reg sdram_bankmachine3_cmd_buffer_source_last = 1'd0; +reg sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [12:0] sdram_bankmachine3_row = 13'd0; +reg sdram_bankmachine3_row_opened = 1'd0; +wire sdram_bankmachine3_row_hit; +reg sdram_bankmachine3_row_open = 1'd0; +reg sdram_bankmachine3_row_close = 1'd0; +reg sdram_bankmachine3_row_col_n_addr_sel = 1'd0; +wire sdram_bankmachine3_twtpcon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] sdram_bankmachine3_twtpcon_count = 3'd0; +wire sdram_bankmachine3_trccon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine3_trccon_ready = 1'd1; +wire sdram_bankmachine3_trascon_valid; +(* no_retiming = "true" *) reg sdram_bankmachine3_trascon_ready = 1'd1; +wire sdram_ras_allowed; +wire sdram_cas_allowed; +reg sdram_choose_cmd_want_reads = 1'd0; +reg sdram_choose_cmd_want_writes = 1'd0; +reg sdram_choose_cmd_want_cmds = 1'd0; +reg sdram_choose_cmd_want_activates = 1'd0; +wire sdram_choose_cmd_cmd_valid; +reg sdram_choose_cmd_cmd_ready = 1'd0; +wire [12:0] sdram_choose_cmd_cmd_payload_a; +wire [1:0] sdram_choose_cmd_cmd_payload_ba; +reg sdram_choose_cmd_cmd_payload_cas = 1'd0; +reg sdram_choose_cmd_cmd_payload_ras = 1'd0; +reg sdram_choose_cmd_cmd_payload_we = 1'd0; +wire sdram_choose_cmd_cmd_payload_is_cmd; +wire sdram_choose_cmd_cmd_payload_is_read; +wire sdram_choose_cmd_cmd_payload_is_write; +reg [3:0] sdram_choose_cmd_valids = 4'd0; +wire [3:0] sdram_choose_cmd_request; +reg [1:0] sdram_choose_cmd_grant = 2'd0; +wire sdram_choose_cmd_ce; +reg sdram_choose_req_want_reads = 1'd0; +reg sdram_choose_req_want_writes = 1'd0; +wire sdram_choose_req_want_cmds; +reg sdram_choose_req_want_activates = 1'd0; +wire sdram_choose_req_cmd_valid; +reg sdram_choose_req_cmd_ready = 1'd0; +wire [12:0] sdram_choose_req_cmd_payload_a; +wire [1:0] sdram_choose_req_cmd_payload_ba; +reg sdram_choose_req_cmd_payload_cas = 1'd0; +reg sdram_choose_req_cmd_payload_ras = 1'd0; +reg sdram_choose_req_cmd_payload_we = 1'd0; +wire sdram_choose_req_cmd_payload_is_cmd; +wire sdram_choose_req_cmd_payload_is_read; +wire sdram_choose_req_cmd_payload_is_write; +reg [3:0] sdram_choose_req_valids = 4'd0; +wire [3:0] sdram_choose_req_request; +reg [1:0] sdram_choose_req_grant = 2'd0; +wire sdram_choose_req_ce; +reg [12:0] sdram_nop_a = 13'd0; +reg [1:0] sdram_nop_ba = 2'd0; +reg [1:0] sdram_steerer_sel = 2'd0; +reg sdram_steerer0 = 1'd1; +reg sdram_steerer1 = 1'd1; +wire sdram_trrdcon_valid; +(* no_retiming = "true" *) reg sdram_trrdcon_ready = 1'd1; +wire sdram_tfawcon_valid; +(* no_retiming = "true" *) reg sdram_tfawcon_ready = 1'd1; +wire sdram_tccdcon_valid; +(* no_retiming = "true" *) reg sdram_tccdcon_ready = 1'd0; +reg sdram_tccdcon_count = 1'd0; +wire sdram_twtrcon_valid; +(* no_retiming = "true" *) reg sdram_twtrcon_ready = 1'd0; +reg [2:0] sdram_twtrcon_count = 3'd0; +wire sdram_read_available; +wire sdram_write_available; +reg sdram_en0 = 1'd0; +wire sdram_max_time0; +reg [4:0] sdram_time0 = 5'd0; +reg sdram_en1 = 1'd0; +wire sdram_max_time1; +reg [3:0] sdram_time1 = 4'd0; +wire sdram_go_to_refresh; +wire port_flush; +wire port_cmd_valid; +wire port_cmd_ready; +wire port_cmd_last; +wire port_cmd_payload_we; +wire [23:0] port_cmd_payload_addr; +wire port_wdata_valid; +wire port_wdata_ready; +wire [15:0] port_wdata_payload_data; +wire [1:0] port_wdata_payload_we; +wire port_rdata_valid; +wire port_rdata_ready; +wire [15:0] port_rdata_payload_data; +wire [29:0] wb_sdram_adr; +wire [31:0] wb_sdram_dat_w; +wire [31:0] wb_sdram_dat_r; +wire [3:0] wb_sdram_sel; +wire wb_sdram_cyc; +wire wb_sdram_stb; +reg wb_sdram_ack = 1'd0; +wire wb_sdram_we; +wire [2:0] wb_sdram_cti; +wire [1:0] wb_sdram_bte; +reg wb_sdram_err = 1'd0; +reg [29:0] litedram_wb_adr = 30'd0; +reg [15:0] litedram_wb_dat_w = 16'd0; +wire [15:0] litedram_wb_dat_r; +reg [1:0] litedram_wb_sel = 2'd0; +reg litedram_wb_cyc = 1'd0; +reg litedram_wb_stb = 1'd0; +wire litedram_wb_ack; +reg litedram_wb_we = 1'd0; +reg converter_skip = 1'd0; +reg converter_counter = 1'd0; +wire converter_reset; +reg [31:0] converter_dat_r = 32'd0; +reg cmd_consumed = 1'd0; +reg wdata_consumed = 1'd0; +wire ack_cmd; +wire ack_wdata; +wire ack_rdata; +(* ram_style = "distributed" *) reg [31:0] uart_phy_storage = 32'd9895604; +reg uart_phy_re = 1'd0; +wire uart_phy_sink_valid; +reg uart_phy_sink_ready = 1'd0; +wire uart_phy_sink_first; +wire uart_phy_sink_last; +wire [7:0] uart_phy_sink_payload_data; +reg uart_phy_uart_clk_txen = 1'd0; +reg [31:0] uart_phy_phase_accumulator_tx = 32'd0; +reg [7:0] uart_phy_tx_reg = 8'd0; +reg [3:0] uart_phy_tx_bitcount = 4'd0; +reg uart_phy_tx_busy = 1'd0; +reg uart_phy_source_valid = 1'd0; +wire uart_phy_source_ready; +reg uart_phy_source_first = 1'd0; +reg uart_phy_source_last = 1'd0; +reg [7:0] uart_phy_source_payload_data = 8'd0; +reg uart_phy_uart_clk_rxen = 1'd0; +reg [31:0] uart_phy_phase_accumulator_rx = 32'd0; +wire uart_phy_rx; +reg uart_phy_rx_r = 1'd0; +reg [7:0] uart_phy_rx_reg = 8'd0; +reg [3:0] uart_phy_rx_bitcount = 4'd0; +reg uart_phy_rx_busy = 1'd0; +wire rxtx_re; +wire [7:0] rxtx_r; +wire rxtx_we; +wire [7:0] rxtx_w; +wire txfull_status; +wire txfull_we; +wire rxempty_status; +wire rxempty_we; +wire irq; +wire tx_status; +reg tx_pending = 1'd0; +wire tx_trigger; +reg tx_clear = 1'd0; +reg tx_old_trigger = 1'd0; +wire rx_status; +reg rx_pending = 1'd0; +wire rx_trigger; +reg rx_clear = 1'd0; +reg rx_old_trigger = 1'd0; +wire eventmanager_status_re; +wire [1:0] eventmanager_status_r; +wire eventmanager_status_we; +reg [1:0] eventmanager_status_w = 2'd0; +wire eventmanager_pending_re; +wire [1:0] eventmanager_pending_r; +wire eventmanager_pending_we; +reg [1:0] eventmanager_pending_w = 2'd0; +(* ram_style = "distributed" *) reg [1:0] eventmanager_storage = 2'd0; +reg eventmanager_re = 1'd0; +wire txempty_status; +wire txempty_we; +wire rxfull_status; +wire rxfull_we; +wire uart_sink_valid; +wire uart_sink_ready; +wire uart_sink_first; +wire uart_sink_last; +wire [7:0] uart_sink_payload_data; +wire uart_source_valid; +wire uart_source_ready; +wire uart_source_first; +wire uart_source_last; +wire [7:0] uart_source_payload_data; +wire tx_fifo_sink_valid; +wire tx_fifo_sink_ready; +reg tx_fifo_sink_first = 1'd0; +reg tx_fifo_sink_last = 1'd0; +wire [7:0] tx_fifo_sink_payload_data; +wire tx_fifo_source_valid; +wire tx_fifo_source_ready; +wire tx_fifo_source_first; +wire tx_fifo_source_last; +wire [7:0] tx_fifo_source_payload_data; +wire tx_fifo_re; +reg tx_fifo_readable = 1'd0; +wire tx_fifo_syncfifo_we; +wire tx_fifo_syncfifo_writable; +wire tx_fifo_syncfifo_re; +wire tx_fifo_syncfifo_readable; +wire [9:0] tx_fifo_syncfifo_din; +wire [9:0] tx_fifo_syncfifo_dout; +reg [4:0] tx_fifo_level0 = 5'd0; +reg tx_fifo_replace = 1'd0; +reg [3:0] tx_fifo_produce = 4'd0; +reg [3:0] tx_fifo_consume = 4'd0; +reg [3:0] tx_fifo_wrport_adr = 4'd0; +wire [9:0] tx_fifo_wrport_dat_r; +wire tx_fifo_wrport_we; +wire [9:0] tx_fifo_wrport_dat_w; +wire tx_fifo_do_read; +wire [3:0] tx_fifo_rdport_adr; +wire [9:0] tx_fifo_rdport_dat_r; +wire tx_fifo_rdport_re; +wire [4:0] tx_fifo_level1; +wire [7:0] tx_fifo_fifo_in_payload_data; +wire tx_fifo_fifo_in_first; +wire tx_fifo_fifo_in_last; +wire [7:0] tx_fifo_fifo_out_payload_data; +wire tx_fifo_fifo_out_first; +wire tx_fifo_fifo_out_last; +wire rx_fifo_sink_valid; +wire rx_fifo_sink_ready; +wire rx_fifo_sink_first; +wire rx_fifo_sink_last; +wire [7:0] rx_fifo_sink_payload_data; +wire rx_fifo_source_valid; +wire rx_fifo_source_ready; +wire rx_fifo_source_first; +wire rx_fifo_source_last; +wire [7:0] rx_fifo_source_payload_data; +wire rx_fifo_re; +reg rx_fifo_readable = 1'd0; +wire rx_fifo_syncfifo_we; +wire rx_fifo_syncfifo_writable; +wire rx_fifo_syncfifo_re; +wire rx_fifo_syncfifo_readable; +wire [9:0] rx_fifo_syncfifo_din; +wire [9:0] rx_fifo_syncfifo_dout; +reg [4:0] rx_fifo_level0 = 5'd0; +reg rx_fifo_replace = 1'd0; +reg [3:0] rx_fifo_produce = 4'd0; +reg [3:0] rx_fifo_consume = 4'd0; +reg [3:0] rx_fifo_wrport_adr = 4'd0; +wire [9:0] rx_fifo_wrport_dat_r; +wire rx_fifo_wrport_we; +wire [9:0] rx_fifo_wrport_dat_w; +wire rx_fifo_do_read; +wire [3:0] rx_fifo_rdport_adr; +wire [9:0] rx_fifo_rdport_dat_r; +wire rx_fifo_rdport_re; +wire [4:0] rx_fifo_level1; +wire [7:0] rx_fifo_fifo_in_payload_data; +wire rx_fifo_fifo_in_first; +wire rx_fifo_fifo_in_last; +wire [7:0] rx_fifo_fifo_out_payload_data; +wire rx_fifo_fifo_out_first; +wire rx_fifo_fifo_out_last; +reg reset = 1'd0; +(* ram_style = "distributed" *) reg [7:0] gpio0_oe_storage = 8'd0; +reg gpio0_oe_re = 1'd0; +reg [7:0] gpio0_status = 8'd0; +wire gpio0_we; +(* ram_style = "distributed" *) reg [7:0] gpio0_out_storage = 8'd0; +reg gpio0_out_re = 1'd0; +reg [7:0] gpio0_pads_gpio0i = 8'd0; +reg [7:0] gpio0_pads_gpio0o = 8'd0; +reg [7:0] gpio0_pads_gpio0oe = 8'd0; +(* ram_style = "distributed" *) reg [7:0] gpio1_oe_storage = 8'd0; +reg gpio1_oe_re = 1'd0; +reg [7:0] gpio1_status = 8'd0; +wire gpio1_we; +(* ram_style = "distributed" *) reg [7:0] gpio1_out_storage = 8'd0; +reg gpio1_out_re = 1'd0; +reg [7:0] gpio1_pads_gpio1i = 8'd0; +reg [7:0] gpio1_pads_gpio1o = 8'd0; +reg [7:0] gpio1_pads_gpio1oe = 8'd0; +reg [2:0] eint_tmp = 3'd0; +wire [39:0] nc_1; +reg [39:0] dummy = 40'd0; +wire i2c_scl_1; +wire i2c_oe; +wire i2c_sda0; +(* ram_style = "distributed" *) reg [2:0] i2c_storage = 3'd0; +reg i2c_re = 1'd0; +wire i2c_sda1; +wire i2c_status; +wire i2c_we; +reg subfragments_converter0_state = 1'd0; +reg subfragments_converter0_next_state = 1'd0; +reg libresocsim_converter0_counter_subfragments_converter0_next_value = 1'd0; +reg libresocsim_converter0_counter_subfragments_converter0_next_value_ce = 1'd0; +reg subfragments_converter1_state = 1'd0; +reg subfragments_converter1_next_state = 1'd0; +reg libresocsim_converter1_counter_subfragments_converter1_next_value = 1'd0; +reg libresocsim_converter1_counter_subfragments_converter1_next_value_ce = 1'd0; +reg [1:0] subfragments_refresher_state = 2'd0; +reg [1:0] subfragments_refresher_next_state = 2'd0; +reg [2:0] subfragments_bankmachine0_state = 3'd0; +reg [2:0] subfragments_bankmachine0_next_state = 3'd0; +reg [2:0] subfragments_bankmachine1_state = 3'd0; +reg [2:0] subfragments_bankmachine1_next_state = 3'd0; +reg [2:0] subfragments_bankmachine2_state = 3'd0; +reg [2:0] subfragments_bankmachine2_next_state = 3'd0; +reg [2:0] subfragments_bankmachine3_state = 3'd0; +reg [2:0] subfragments_bankmachine3_next_state = 3'd0; +reg [2:0] subfragments_multiplexer_state = 3'd0; +reg [2:0] subfragments_multiplexer_next_state = 3'd0; +wire subfragments_roundrobin0_request; +wire subfragments_roundrobin0_grant; +wire subfragments_roundrobin0_ce; +wire subfragments_roundrobin1_request; +wire subfragments_roundrobin1_grant; +wire subfragments_roundrobin1_ce; +wire subfragments_roundrobin2_request; +wire subfragments_roundrobin2_grant; +wire subfragments_roundrobin2_ce; +wire subfragments_roundrobin3_request; +wire subfragments_roundrobin3_grant; +wire subfragments_roundrobin3_ce; +reg subfragments_locked0 = 1'd0; +reg subfragments_locked1 = 1'd0; +reg subfragments_locked2 = 1'd0; +reg subfragments_locked3 = 1'd0; +reg subfragments_new_master_wdata_ready = 1'd0; +reg subfragments_new_master_rdata_valid0 = 1'd0; +reg subfragments_new_master_rdata_valid1 = 1'd0; +reg subfragments_new_master_rdata_valid2 = 1'd0; +reg subfragments_new_master_rdata_valid3 = 1'd0; +reg subfragments_state = 1'd0; +reg subfragments_next_state = 1'd0; +reg converter_counter_subfragments_next_value = 1'd0; +reg converter_counter_subfragments_next_value_ce = 1'd0; +reg [12:0] libresocsim_libresocsim_adr = 13'd0; +reg libresocsim_libresocsim_we = 1'd0; +reg [7:0] libresocsim_libresocsim_dat_w = 8'd0; +wire [7:0] libresocsim_libresocsim_dat_r; +wire [29:0] libresocsim_libresocsim_wishbone_adr; +wire [31:0] libresocsim_libresocsim_wishbone_dat_w; +reg [31:0] libresocsim_libresocsim_wishbone_dat_r = 32'd0; +wire [3:0] libresocsim_libresocsim_wishbone_sel; +wire libresocsim_libresocsim_wishbone_cyc; +wire libresocsim_libresocsim_wishbone_stb; +reg libresocsim_libresocsim_wishbone_ack = 1'd0; +wire libresocsim_libresocsim_wishbone_we; +wire [2:0] libresocsim_libresocsim_wishbone_cti; +wire [1:0] libresocsim_libresocsim_wishbone_bte; +reg libresocsim_libresocsim_wishbone_err = 1'd0; +wire [29:0] libresocsim_shared_adr; +wire [31:0] libresocsim_shared_dat_w; +reg [31:0] libresocsim_shared_dat_r = 32'd0; +wire [3:0] libresocsim_shared_sel; +wire libresocsim_shared_cyc; +wire libresocsim_shared_stb; +reg libresocsim_shared_ack = 1'd0; +wire libresocsim_shared_we; +wire [2:0] libresocsim_shared_cti; +wire [1:0] libresocsim_shared_bte; +wire libresocsim_shared_err; +wire [2:0] libresocsim_request; +reg [1:0] libresocsim_grant = 2'd0; +reg [5:0] libresocsim_slave_sel = 6'd0; +reg [5:0] libresocsim_slave_sel_r = 6'd0; +reg libresocsim_error = 1'd0; +wire libresocsim_wait; +wire libresocsim_done; +reg [19:0] libresocsim_count = 20'd1000000; +wire [12:0] libresocsim_interface0_bank_bus_adr; +wire libresocsim_interface0_bank_bus_we; +wire [7:0] libresocsim_interface0_bank_bus_dat_w; +reg [7:0] libresocsim_interface0_bank_bus_dat_r = 8'd0; +wire libresocsim_csrbank0_reset0_re; +wire libresocsim_csrbank0_reset0_r; +wire libresocsim_csrbank0_reset0_we; +wire libresocsim_csrbank0_reset0_w; +wire libresocsim_csrbank0_scratch3_re; +wire [7:0] libresocsim_csrbank0_scratch3_r; +wire libresocsim_csrbank0_scratch3_we; +wire [7:0] libresocsim_csrbank0_scratch3_w; +wire libresocsim_csrbank0_scratch2_re; +wire [7:0] libresocsim_csrbank0_scratch2_r; +wire libresocsim_csrbank0_scratch2_we; +wire [7:0] libresocsim_csrbank0_scratch2_w; +wire libresocsim_csrbank0_scratch1_re; +wire [7:0] libresocsim_csrbank0_scratch1_r; +wire libresocsim_csrbank0_scratch1_we; +wire [7:0] libresocsim_csrbank0_scratch1_w; +wire libresocsim_csrbank0_scratch0_re; +wire [7:0] libresocsim_csrbank0_scratch0_r; +wire libresocsim_csrbank0_scratch0_we; +wire [7:0] libresocsim_csrbank0_scratch0_w; +wire libresocsim_csrbank0_bus_errors3_re; +wire [7:0] libresocsim_csrbank0_bus_errors3_r; +wire libresocsim_csrbank0_bus_errors3_we; +wire [7:0] libresocsim_csrbank0_bus_errors3_w; +wire libresocsim_csrbank0_bus_errors2_re; +wire [7:0] libresocsim_csrbank0_bus_errors2_r; +wire libresocsim_csrbank0_bus_errors2_we; +wire [7:0] libresocsim_csrbank0_bus_errors2_w; +wire libresocsim_csrbank0_bus_errors1_re; +wire [7:0] libresocsim_csrbank0_bus_errors1_r; +wire libresocsim_csrbank0_bus_errors1_we; +wire [7:0] libresocsim_csrbank0_bus_errors1_w; +wire libresocsim_csrbank0_bus_errors0_re; +wire [7:0] libresocsim_csrbank0_bus_errors0_r; +wire libresocsim_csrbank0_bus_errors0_we; +wire [7:0] libresocsim_csrbank0_bus_errors0_w; +wire libresocsim_csrbank0_sel; +wire [12:0] libresocsim_interface1_bank_bus_adr; +wire libresocsim_interface1_bank_bus_we; +wire [7:0] libresocsim_interface1_bank_bus_dat_w; +reg [7:0] libresocsim_interface1_bank_bus_dat_r = 8'd0; +wire libresocsim_csrbank1_oe0_re; +wire [7:0] libresocsim_csrbank1_oe0_r; +wire libresocsim_csrbank1_oe0_we; +wire [7:0] libresocsim_csrbank1_oe0_w; +wire libresocsim_csrbank1_in_re; +wire [7:0] libresocsim_csrbank1_in_r; +wire libresocsim_csrbank1_in_we; +wire [7:0] libresocsim_csrbank1_in_w; +wire libresocsim_csrbank1_out0_re; +wire [7:0] libresocsim_csrbank1_out0_r; +wire libresocsim_csrbank1_out0_we; +wire [7:0] libresocsim_csrbank1_out0_w; +wire libresocsim_csrbank1_sel; +wire [12:0] libresocsim_interface2_bank_bus_adr; +wire libresocsim_interface2_bank_bus_we; +wire [7:0] libresocsim_interface2_bank_bus_dat_w; +reg [7:0] libresocsim_interface2_bank_bus_dat_r = 8'd0; +wire libresocsim_csrbank2_oe0_re; +wire [7:0] libresocsim_csrbank2_oe0_r; +wire libresocsim_csrbank2_oe0_we; +wire [7:0] libresocsim_csrbank2_oe0_w; +wire libresocsim_csrbank2_in_re; +wire [7:0] libresocsim_csrbank2_in_r; +wire libresocsim_csrbank2_in_we; +wire [7:0] libresocsim_csrbank2_in_w; +wire libresocsim_csrbank2_out0_re; +wire [7:0] libresocsim_csrbank2_out0_r; +wire libresocsim_csrbank2_out0_we; +wire [7:0] libresocsim_csrbank2_out0_w; +wire libresocsim_csrbank2_sel; +wire [12:0] libresocsim_interface3_bank_bus_adr; +wire libresocsim_interface3_bank_bus_we; +wire [7:0] libresocsim_interface3_bank_bus_dat_w; +reg [7:0] libresocsim_interface3_bank_bus_dat_r = 8'd0; +wire libresocsim_csrbank3_w0_re; +wire [2:0] libresocsim_csrbank3_w0_r; +wire libresocsim_csrbank3_w0_we; +wire [2:0] libresocsim_csrbank3_w0_w; +wire libresocsim_csrbank3_r_re; +wire libresocsim_csrbank3_r_r; +wire libresocsim_csrbank3_r_we; +wire libresocsim_csrbank3_r_w; +wire libresocsim_csrbank3_sel; +wire [12:0] libresocsim_interface4_bank_bus_adr; +wire libresocsim_interface4_bank_bus_we; +wire [7:0] libresocsim_interface4_bank_bus_dat_w; +reg [7:0] libresocsim_interface4_bank_bus_dat_r = 8'd0; +wire libresocsim_csrbank4_dfii_control0_re; +wire [3:0] libresocsim_csrbank4_dfii_control0_r; +wire libresocsim_csrbank4_dfii_control0_we; +wire [3:0] libresocsim_csrbank4_dfii_control0_w; +wire libresocsim_csrbank4_dfii_pi0_command0_re; +wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_r; +wire libresocsim_csrbank4_dfii_pi0_command0_we; +wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_w; +wire libresocsim_csrbank4_dfii_pi0_address1_re; +wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_r; +wire libresocsim_csrbank4_dfii_pi0_address1_we; +wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_w; +wire libresocsim_csrbank4_dfii_pi0_address0_re; +wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_r; +wire libresocsim_csrbank4_dfii_pi0_address0_we; +wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_w; +wire libresocsim_csrbank4_dfii_pi0_baddress0_re; +wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_r; +wire libresocsim_csrbank4_dfii_pi0_baddress0_we; +wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_w; +wire libresocsim_csrbank4_dfii_pi0_wrdata1_re; +wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_r; +wire libresocsim_csrbank4_dfii_pi0_wrdata1_we; +wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_w; +wire libresocsim_csrbank4_dfii_pi0_wrdata0_re; +wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_r; +wire libresocsim_csrbank4_dfii_pi0_wrdata0_we; +wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_w; +wire libresocsim_csrbank4_dfii_pi0_rddata1_re; +wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_r; +wire libresocsim_csrbank4_dfii_pi0_rddata1_we; +wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_w; +wire libresocsim_csrbank4_dfii_pi0_rddata0_re; +wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_r; +wire libresocsim_csrbank4_dfii_pi0_rddata0_we; +wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_w; +wire libresocsim_csrbank4_sel; +wire [12:0] libresocsim_interface5_bank_bus_adr; +wire libresocsim_interface5_bank_bus_we; +wire [7:0] libresocsim_interface5_bank_bus_dat_w; +reg [7:0] libresocsim_interface5_bank_bus_dat_r = 8'd0; +wire libresocsim_csrbank5_load3_re; +wire [7:0] libresocsim_csrbank5_load3_r; +wire libresocsim_csrbank5_load3_we; +wire [7:0] libresocsim_csrbank5_load3_w; +wire libresocsim_csrbank5_load2_re; +wire [7:0] libresocsim_csrbank5_load2_r; +wire libresocsim_csrbank5_load2_we; +wire [7:0] libresocsim_csrbank5_load2_w; +wire libresocsim_csrbank5_load1_re; +wire [7:0] libresocsim_csrbank5_load1_r; +wire libresocsim_csrbank5_load1_we; +wire [7:0] libresocsim_csrbank5_load1_w; +wire libresocsim_csrbank5_load0_re; +wire [7:0] libresocsim_csrbank5_load0_r; +wire libresocsim_csrbank5_load0_we; +wire [7:0] libresocsim_csrbank5_load0_w; +wire libresocsim_csrbank5_reload3_re; +wire [7:0] libresocsim_csrbank5_reload3_r; +wire libresocsim_csrbank5_reload3_we; +wire [7:0] libresocsim_csrbank5_reload3_w; +wire libresocsim_csrbank5_reload2_re; +wire [7:0] libresocsim_csrbank5_reload2_r; +wire libresocsim_csrbank5_reload2_we; +wire [7:0] libresocsim_csrbank5_reload2_w; +wire libresocsim_csrbank5_reload1_re; +wire [7:0] libresocsim_csrbank5_reload1_r; +wire libresocsim_csrbank5_reload1_we; +wire [7:0] libresocsim_csrbank5_reload1_w; +wire libresocsim_csrbank5_reload0_re; +wire [7:0] libresocsim_csrbank5_reload0_r; +wire libresocsim_csrbank5_reload0_we; +wire [7:0] libresocsim_csrbank5_reload0_w; +wire libresocsim_csrbank5_en0_re; +wire libresocsim_csrbank5_en0_r; +wire libresocsim_csrbank5_en0_we; +wire libresocsim_csrbank5_en0_w; +wire libresocsim_csrbank5_update_value0_re; +wire libresocsim_csrbank5_update_value0_r; +wire libresocsim_csrbank5_update_value0_we; +wire libresocsim_csrbank5_update_value0_w; +wire libresocsim_csrbank5_value3_re; +wire [7:0] libresocsim_csrbank5_value3_r; +wire libresocsim_csrbank5_value3_we; +wire [7:0] libresocsim_csrbank5_value3_w; +wire libresocsim_csrbank5_value2_re; +wire [7:0] libresocsim_csrbank5_value2_r; +wire libresocsim_csrbank5_value2_we; +wire [7:0] libresocsim_csrbank5_value2_w; +wire libresocsim_csrbank5_value1_re; +wire [7:0] libresocsim_csrbank5_value1_r; +wire libresocsim_csrbank5_value1_we; +wire [7:0] libresocsim_csrbank5_value1_w; +wire libresocsim_csrbank5_value0_re; +wire [7:0] libresocsim_csrbank5_value0_r; +wire libresocsim_csrbank5_value0_we; +wire [7:0] libresocsim_csrbank5_value0_w; +wire libresocsim_csrbank5_ev_enable0_re; +wire libresocsim_csrbank5_ev_enable0_r; +wire libresocsim_csrbank5_ev_enable0_we; +wire libresocsim_csrbank5_ev_enable0_w; +wire libresocsim_csrbank5_sel; +wire [12:0] libresocsim_interface6_bank_bus_adr; +wire libresocsim_interface6_bank_bus_we; +wire [7:0] libresocsim_interface6_bank_bus_dat_w; +reg [7:0] libresocsim_interface6_bank_bus_dat_r = 8'd0; +wire libresocsim_csrbank6_txfull_re; +wire libresocsim_csrbank6_txfull_r; +wire libresocsim_csrbank6_txfull_we; +wire libresocsim_csrbank6_txfull_w; +wire libresocsim_csrbank6_rxempty_re; +wire libresocsim_csrbank6_rxempty_r; +wire libresocsim_csrbank6_rxempty_we; +wire libresocsim_csrbank6_rxempty_w; +wire libresocsim_csrbank6_ev_enable0_re; +wire [1:0] libresocsim_csrbank6_ev_enable0_r; +wire libresocsim_csrbank6_ev_enable0_we; +wire [1:0] libresocsim_csrbank6_ev_enable0_w; +wire libresocsim_csrbank6_txempty_re; +wire libresocsim_csrbank6_txempty_r; +wire libresocsim_csrbank6_txempty_we; +wire libresocsim_csrbank6_txempty_w; +wire libresocsim_csrbank6_rxfull_re; +wire libresocsim_csrbank6_rxfull_r; +wire libresocsim_csrbank6_rxfull_we; +wire libresocsim_csrbank6_rxfull_w; +wire libresocsim_csrbank6_sel; +wire [12:0] libresocsim_interface7_bank_bus_adr; +wire libresocsim_interface7_bank_bus_we; +wire [7:0] libresocsim_interface7_bank_bus_dat_w; +reg [7:0] libresocsim_interface7_bank_bus_dat_r = 8'd0; +wire libresocsim_csrbank7_tuning_word3_re; +wire [7:0] libresocsim_csrbank7_tuning_word3_r; +wire libresocsim_csrbank7_tuning_word3_we; +wire [7:0] libresocsim_csrbank7_tuning_word3_w; +wire libresocsim_csrbank7_tuning_word2_re; +wire [7:0] libresocsim_csrbank7_tuning_word2_r; +wire libresocsim_csrbank7_tuning_word2_we; +wire [7:0] libresocsim_csrbank7_tuning_word2_w; +wire libresocsim_csrbank7_tuning_word1_re; +wire [7:0] libresocsim_csrbank7_tuning_word1_r; +wire libresocsim_csrbank7_tuning_word1_we; +wire [7:0] libresocsim_csrbank7_tuning_word1_w; +wire libresocsim_csrbank7_tuning_word0_re; +wire [7:0] libresocsim_csrbank7_tuning_word0_r; +wire libresocsim_csrbank7_tuning_word0_we; +wire [7:0] libresocsim_csrbank7_tuning_word0_w; +wire libresocsim_csrbank7_sel; +wire [12:0] libresocsim_csr_interconnect_adr; +wire libresocsim_csr_interconnect_we; +wire [7:0] libresocsim_csr_interconnect_dat_w; +wire [7:0] libresocsim_csr_interconnect_dat_r; +reg [1:0] libresocsim_state = 2'd0; +reg [1:0] libresocsim_next_state = 2'd0; +reg [7:0] libresocsim_libresocsim_dat_w_libresocsim_next_value0 = 8'd0; +reg libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 = 1'd0; +reg [12:0] libresocsim_libresocsim_adr_libresocsim_next_value1 = 13'd0; +reg libresocsim_libresocsim_adr_libresocsim_next_value_ce1 = 1'd0; +reg libresocsim_libresocsim_we_libresocsim_next_value2 = 1'd0; +reg libresocsim_libresocsim_we_libresocsim_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [12:0] rhs_array_muxed1 = 13'd0; +reg [1:0] rhs_array_muxed2 = 2'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [12:0] rhs_array_muxed7 = 13'd0; +reg [1:0] rhs_array_muxed8 = 2'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [21:0] rhs_array_muxed12 = 22'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [21:0] rhs_array_muxed15 = 22'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [21:0] rhs_array_muxed18 = 22'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [21:0] rhs_array_muxed21 = 22'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [29:0] rhs_array_muxed24 = 30'd0; +reg [31:0] rhs_array_muxed25 = 32'd0; +reg [3:0] rhs_array_muxed26 = 4'd0; +reg rhs_array_muxed27 = 1'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [2:0] rhs_array_muxed30 = 3'd0; +reg [1:0] rhs_array_muxed31 = 2'd0; +reg [1:0] array_muxed0 = 2'd0; +reg [12:0] array_muxed1 = 13'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +wire sdrio_clk; +wire sdrio_clk_1; +wire sdrio_clk_2; +wire sdrio_clk_3; +wire sdrio_clk_4; +wire sdrio_clk_5; +wire sdrio_clk_6; +wire sdrio_clk_7; +wire sdrio_clk_8; +wire sdrio_clk_9; +wire sdrio_clk_10; +wire sdrio_clk_11; +wire sdrio_clk_12; +wire sdrio_clk_13; +wire sdrio_clk_14; +wire sdrio_clk_15; +wire sdrio_clk_16; +wire sdrio_clk_17; +wire sdrio_clk_18; +wire sdrio_clk_19; +wire sdrio_clk_20; +wire sdrio_clk_21; +wire sdrio_clk_22; +wire sdrio_clk_23; +wire sdrio_clk_24; +wire sdrio_clk_25; +wire sdrio_clk_26; +wire sdrio_clk_27; +wire sdrio_clk_28; +wire sdrio_clk_29; +wire sdrio_clk_30; +wire sdrio_clk_31; +wire sdrio_clk_32; +wire sdrio_clk_33; +wire sdrio_clk_34; +wire sdrio_clk_35; +wire sdrio_clk_36; +wire sdrio_clk_37; +wire sdrio_clk_38; +wire sdrio_clk_39; +wire sdrio_clk_40; +wire sdrio_clk_41; +wire sdrio_clk_42; +wire sdrio_clk_43; +wire sdrio_clk_44; +wire sdrio_clk_45; +wire sdrio_clk_46; +wire sdrio_clk_47; +wire sdrio_clk_48; +wire sdrio_clk_49; +wire sdrio_clk_50; +wire sdrio_clk_51; +wire sdrio_clk_52; +wire sdrio_clk_53; +wire sdrio_clk_54; +wire sdrio_clk_55; +wire sdrio_clk_56; +wire sdrio_clk_57; +wire sdrio_clk_58; +wire sdrio_clk_59; +wire sdrio_clk_60; +wire sdrio_clk_61; +wire sdrio_clk_62; +wire sdrio_clk_63; +wire sdrio_clk_64; +wire sdrio_clk_65; +wire sdrio_clk_66; +wire sdrio_clk_67; +wire sdrio_clk_68; +wire sdrio_clk_69; +wire sdrio_clk_70; +(* no_retiming = "true" *) reg regs0 = 1'd0; +(* no_retiming = "true" *) reg regs1 = 1'd0; +wire sdrio_clk_71; +wire sdrio_clk_72; +wire sdrio_clk_73; +wire sdrio_clk_74; +wire sdrio_clk_75; +wire sdrio_clk_76; +wire sdrio_clk_77; +wire sdrio_clk_78; +wire sdrio_clk_79; +wire sdrio_clk_80; +wire sdrio_clk_81; +wire sdrio_clk_82; +wire sdrio_clk_83; +wire sdrio_clk_84; +wire sdrio_clk_85; +wire sdrio_clk_86; +wire sdrio_clk_87; +wire sdrio_clk_88; +wire sdrio_clk_89; +wire sdrio_clk_90; +wire sdrio_clk_91; +wire sdrio_clk_92; +wire sdrio_clk_93; +wire sdrio_clk_94; +wire sdrio_clk_95; +wire sdrio_clk_96; +wire sdrio_clk_97; +wire sdrio_clk_98; +wire sdrio_clk_99; +wire sdrio_clk_100; +wire sdrio_clk_101; +wire sdrio_clk_102; +wire sdrio_clk_103; +wire sdrio_clk_104; +wire sdrio_clk_105; +wire sdrio_clk_106; +wire sdrio_clk_107; +wire sdrio_clk_108; +wire sdrio_clk_109; +wire sdrio_clk_110; +wire sdrio_clk_111; +wire sdrio_clk_112; +wire sdrio_clk_113; +wire sdrio_clk_114; +wire sdrio_clk_115; +wire sdrio_clk_116; +wire sdrio_clk_117; +wire sdrio_clk_118; + +assign libresocsim_libresoc_reset = libresocsim_reset; +always @(*) begin + eint_tmp <= 3'd0; + eint_tmp[0] <= libresocsim_libresoc_constraintmanager_eint_0; + eint_tmp[1] <= libresocsim_libresoc_constraintmanager_eint_1; + eint_tmp[2] <= libresocsim_libresoc_constraintmanager_eint_2; +end +assign libresocsim_libresoc_jtag_tck = jtag_tck; +assign libresocsim_libresoc_jtag_tms = jtag_tms; +assign libresocsim_libresoc_jtag_tdi = jtag_tdi; +assign jtag_tdo = libresocsim_libresoc_jtag_tdo; +assign nc_1 = nc; +assign libresocsim_bus_error = libresocsim_error; +always @(*) begin + libresocsim_libresoc_interrupt <= 16'd0; + libresocsim_libresoc_interrupt[13] <= eint_tmp[0]; + libresocsim_libresoc_interrupt[14] <= eint_tmp[1]; + libresocsim_libresoc_interrupt[15] <= eint_tmp[2]; + libresocsim_libresoc_interrupt[0] <= libresocsim_irq; + libresocsim_libresoc_interrupt[1] <= irq; +end +assign libresocsim_converter0_reset = (~libresocsim_libresoc_ibus_cyc); +always @(*) begin + libresocsim_interface0_converted_interface_dat_w <= 32'd0; + case (libresocsim_converter0_counter) + 1'd0: begin + libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:0]; + end + 1'd1: begin + libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:32]; + end + endcase +end +assign libresocsim_libresoc_ibus_dat_r = {libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32]}; +always @(*) begin + libresocsim_interface0_converted_interface_sel <= 4'd0; + libresocsim_interface0_converted_interface_cyc <= 1'd0; + libresocsim_libresoc_ibus_ack <= 1'd0; + libresocsim_interface0_converted_interface_stb <= 1'd0; + subfragments_converter0_next_state <= 1'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; + libresocsim_interface0_converted_interface_we <= 1'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0; + libresocsim_converter0_skip <= 1'd0; + libresocsim_interface0_converted_interface_adr <= 30'd0; + subfragments_converter0_next_state <= subfragments_converter0_state; + case (subfragments_converter0_state) + 1'd1: begin + libresocsim_interface0_converted_interface_adr <= {libresocsim_libresoc_ibus_adr, libresocsim_converter0_counter}; + case (libresocsim_converter0_counter) + 1'd0: begin + libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:0]; + end + 1'd1: begin + libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:4]; + end + endcase + if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin + libresocsim_converter0_skip <= (libresocsim_interface0_converted_interface_sel == 1'd0); + libresocsim_interface0_converted_interface_we <= libresocsim_libresoc_ibus_we; + libresocsim_interface0_converted_interface_cyc <= (~libresocsim_converter0_skip); + libresocsim_interface0_converted_interface_stb <= (~libresocsim_converter0_skip); + if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin + libresocsim_converter0_counter_subfragments_converter0_next_value <= (libresocsim_converter0_counter + 1'd1); + libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1; + if ((libresocsim_converter0_counter == 1'd1)) begin + libresocsim_libresoc_ibus_ack <= 1'd1; + subfragments_converter0_next_state <= 1'd0; + end + end + end + end + default: begin + libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1; + if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin + subfragments_converter0_next_state <= 1'd1; + end + end + endcase +end +assign libresocsim_converter1_reset = (~libresocsim_libresoc_dbus_cyc); +always @(*) begin + libresocsim_interface1_converted_interface_dat_w <= 32'd0; + case (libresocsim_converter1_counter) + 1'd0: begin + libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:0]; + end + 1'd1: begin + libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:32]; + end + endcase +end +assign libresocsim_libresoc_dbus_dat_r = {libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32]}; +always @(*) begin + libresocsim_interface1_converted_interface_we <= 1'd0; + subfragments_converter1_next_state <= 1'd0; + libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; + libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0; + libresocsim_converter1_skip <= 1'd0; + libresocsim_libresoc_dbus_ack <= 1'd0; + libresocsim_interface1_converted_interface_adr <= 30'd0; + libresocsim_interface1_converted_interface_sel <= 4'd0; + libresocsim_interface1_converted_interface_cyc <= 1'd0; + libresocsim_interface1_converted_interface_stb <= 1'd0; + subfragments_converter1_next_state <= subfragments_converter1_state; + case (subfragments_converter1_state) + 1'd1: begin + libresocsim_interface1_converted_interface_adr <= {libresocsim_libresoc_dbus_adr, libresocsim_converter1_counter}; + case (libresocsim_converter1_counter) + 1'd0: begin + libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:0]; + end + 1'd1: begin + libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:4]; + end + endcase + if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin + libresocsim_converter1_skip <= (libresocsim_interface1_converted_interface_sel == 1'd0); + libresocsim_interface1_converted_interface_we <= libresocsim_libresoc_dbus_we; + libresocsim_interface1_converted_interface_cyc <= (~libresocsim_converter1_skip); + libresocsim_interface1_converted_interface_stb <= (~libresocsim_converter1_skip); + if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin + libresocsim_converter1_counter_subfragments_converter1_next_value <= (libresocsim_converter1_counter + 1'd1); + libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1; + if ((libresocsim_converter1_counter == 1'd1)) begin + libresocsim_libresoc_dbus_ack <= 1'd1; + subfragments_converter1_next_state <= 1'd0; + end + end + end + end + default: begin + libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; + libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1; + if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin + subfragments_converter1_next_state <= 1'd1; + end + end + endcase +end +assign libresocsim_reset = libresocsim_reset_re; +assign libresocsim_bus_errors_status = libresocsim_bus_errors; +always @(*) begin + libresocsim_we <= 4'd0; + libresocsim_we[0] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[0]); + libresocsim_we[1] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[1]); + libresocsim_we[2] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[2]); + libresocsim_we[3] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[3]); +end +assign libresocsim_adr = libresocsim_ram_bus_adr[6:0]; +assign libresocsim_ram_bus_dat_r = libresocsim_dat_r; +assign libresocsim_dat_w = libresocsim_ram_bus_dat_w; +assign libresocsim_zero_trigger = (libresocsim_value != 1'd0); +assign libresocsim_eventmanager_status_w = libresocsim_zero_status; +always @(*) begin + libresocsim_zero_clear <= 1'd0; + if ((libresocsim_eventmanager_pending_re & libresocsim_eventmanager_pending_r)) begin + libresocsim_zero_clear <= 1'd1; + end +end +assign libresocsim_eventmanager_pending_w = libresocsim_zero_pending; +assign libresocsim_irq = (libresocsim_eventmanager_pending_w & libresocsim_eventmanager_storage); +assign libresocsim_zero_status = libresocsim_zero_trigger; +always @(*) begin + ram_we <= 4'd0; + ram_we[0] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[0]); + ram_we[1] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[1]); + ram_we[2] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[2]); + ram_we[3] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[3]); +end +assign ram_adr = ram_bus_ram_bus_adr[4:0]; +assign ram_bus_ram_bus_dat_r = ram_dat_r; +assign ram_dat_w = ram_bus_ram_bus_dat_w; +assign sys_clk_1 = sys_clk; +assign por_clk = sys_clk; +assign sys_rst_1 = int_rst; +assign dfi_p0_address = sdram_master_p0_address; +assign dfi_p0_bank = sdram_master_p0_bank; +assign dfi_p0_cas_n = sdram_master_p0_cas_n; +assign dfi_p0_cs_n = sdram_master_p0_cs_n; +assign dfi_p0_ras_n = sdram_master_p0_ras_n; +assign dfi_p0_we_n = sdram_master_p0_we_n; +assign dfi_p0_cke = sdram_master_p0_cke; +assign dfi_p0_odt = sdram_master_p0_odt; +assign dfi_p0_reset_n = sdram_master_p0_reset_n; +assign dfi_p0_act_n = sdram_master_p0_act_n; +assign dfi_p0_wrdata = sdram_master_p0_wrdata; +assign dfi_p0_wrdata_en = sdram_master_p0_wrdata_en; +assign dfi_p0_wrdata_mask = sdram_master_p0_wrdata_mask; +assign dfi_p0_rddata_en = sdram_master_p0_rddata_en; +assign sdram_master_p0_rddata = dfi_p0_rddata; +assign sdram_master_p0_rddata_valid = dfi_p0_rddata_valid; +assign sdram_slave_p0_address = sdram_dfi_p0_address; +assign sdram_slave_p0_bank = sdram_dfi_p0_bank; +assign sdram_slave_p0_cas_n = sdram_dfi_p0_cas_n; +assign sdram_slave_p0_cs_n = sdram_dfi_p0_cs_n; +assign sdram_slave_p0_ras_n = sdram_dfi_p0_ras_n; +assign sdram_slave_p0_we_n = sdram_dfi_p0_we_n; +assign sdram_slave_p0_cke = sdram_dfi_p0_cke; +assign sdram_slave_p0_odt = sdram_dfi_p0_odt; +assign sdram_slave_p0_reset_n = sdram_dfi_p0_reset_n; +assign sdram_slave_p0_act_n = sdram_dfi_p0_act_n; +assign sdram_slave_p0_wrdata = sdram_dfi_p0_wrdata; +assign sdram_slave_p0_wrdata_en = sdram_dfi_p0_wrdata_en; +assign sdram_slave_p0_wrdata_mask = sdram_dfi_p0_wrdata_mask; +assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en; +assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata; +assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid; +always @(*) begin + sdram_master_p0_ras_n <= 1'd1; + sdram_master_p0_we_n <= 1'd1; + sdram_master_p0_cke <= 1'd0; + sdram_master_p0_odt <= 1'd0; + sdram_master_p0_reset_n <= 1'd0; + sdram_master_p0_act_n <= 1'd1; + sdram_inti_p0_rddata <= 16'd0; + sdram_master_p0_wrdata <= 16'd0; + sdram_inti_p0_rddata_valid <= 1'd0; + sdram_master_p0_wrdata_en <= 1'd0; + sdram_master_p0_wrdata_mask <= 2'd0; + sdram_master_p0_rddata_en <= 1'd0; + sdram_slave_p0_rddata <= 16'd0; + sdram_slave_p0_rddata_valid <= 1'd0; + sdram_master_p0_address <= 13'd0; + sdram_master_p0_bank <= 2'd0; + sdram_master_p0_cas_n <= 1'd1; + sdram_master_p0_cs_n <= 1'd1; + if (sdram_sel) begin + sdram_master_p0_address <= sdram_slave_p0_address; + sdram_master_p0_bank <= sdram_slave_p0_bank; + sdram_master_p0_cas_n <= sdram_slave_p0_cas_n; + sdram_master_p0_cs_n <= sdram_slave_p0_cs_n; + sdram_master_p0_ras_n <= sdram_slave_p0_ras_n; + sdram_master_p0_we_n <= sdram_slave_p0_we_n; + sdram_master_p0_cke <= sdram_slave_p0_cke; + sdram_master_p0_odt <= sdram_slave_p0_odt; + sdram_master_p0_reset_n <= sdram_slave_p0_reset_n; + sdram_master_p0_act_n <= sdram_slave_p0_act_n; + sdram_master_p0_wrdata <= sdram_slave_p0_wrdata; + sdram_master_p0_wrdata_en <= sdram_slave_p0_wrdata_en; + sdram_master_p0_wrdata_mask <= sdram_slave_p0_wrdata_mask; + sdram_master_p0_rddata_en <= sdram_slave_p0_rddata_en; + sdram_slave_p0_rddata <= sdram_master_p0_rddata; + sdram_slave_p0_rddata_valid <= sdram_master_p0_rddata_valid; + end else begin + sdram_master_p0_address <= sdram_inti_p0_address; + sdram_master_p0_bank <= sdram_inti_p0_bank; + sdram_master_p0_cas_n <= sdram_inti_p0_cas_n; + sdram_master_p0_cs_n <= sdram_inti_p0_cs_n; + sdram_master_p0_ras_n <= sdram_inti_p0_ras_n; + sdram_master_p0_we_n <= sdram_inti_p0_we_n; + sdram_master_p0_cke <= sdram_inti_p0_cke; + sdram_master_p0_odt <= sdram_inti_p0_odt; + sdram_master_p0_reset_n <= sdram_inti_p0_reset_n; + sdram_master_p0_act_n <= sdram_inti_p0_act_n; + sdram_master_p0_wrdata <= sdram_inti_p0_wrdata; + sdram_master_p0_wrdata_en <= sdram_inti_p0_wrdata_en; + sdram_master_p0_wrdata_mask <= sdram_inti_p0_wrdata_mask; + sdram_master_p0_rddata_en <= sdram_inti_p0_rddata_en; + sdram_inti_p0_rddata <= sdram_master_p0_rddata; + sdram_inti_p0_rddata_valid <= sdram_master_p0_rddata_valid; + end +end +assign sdram_inti_p0_cke = sdram_cke_1; +assign sdram_inti_p0_odt = sdram_odt; +assign sdram_inti_p0_reset_n = sdram_reset_n; +always @(*) begin + sdram_inti_p0_we_n <= 1'd1; + sdram_inti_p0_cas_n <= 1'd1; + sdram_inti_p0_cs_n <= 1'd1; + sdram_inti_p0_ras_n <= 1'd1; + if (sdram_command_issue_re) begin + sdram_inti_p0_cs_n <= {1{(~sdram_command_storage[0])}}; + sdram_inti_p0_we_n <= (~sdram_command_storage[1]); + sdram_inti_p0_cas_n <= (~sdram_command_storage[2]); + sdram_inti_p0_ras_n <= (~sdram_command_storage[3]); + end else begin + sdram_inti_p0_cs_n <= {1{1'd1}}; + sdram_inti_p0_we_n <= 1'd1; + sdram_inti_p0_cas_n <= 1'd1; + sdram_inti_p0_ras_n <= 1'd1; + end +end +assign sdram_inti_p0_address = sdram_address_storage; +assign sdram_inti_p0_bank = sdram_baddress_storage; +assign sdram_inti_p0_wrdata_en = (sdram_command_issue_re & sdram_command_storage[4]); +assign sdram_inti_p0_rddata_en = (sdram_command_issue_re & sdram_command_storage[5]); +assign sdram_inti_p0_wrdata = sdram_wrdata_storage; +assign sdram_inti_p0_wrdata_mask = 1'd0; +assign sdram_bankmachine0_req_valid = sdram_interface_bank0_valid; +assign sdram_interface_bank0_ready = sdram_bankmachine0_req_ready; +assign sdram_bankmachine0_req_we = sdram_interface_bank0_we; +assign sdram_bankmachine0_req_addr = sdram_interface_bank0_addr; +assign sdram_interface_bank0_lock = sdram_bankmachine0_req_lock; +assign sdram_interface_bank0_wdata_ready = sdram_bankmachine0_req_wdata_ready; +assign sdram_interface_bank0_rdata_valid = sdram_bankmachine0_req_rdata_valid; +assign sdram_bankmachine1_req_valid = sdram_interface_bank1_valid; +assign sdram_interface_bank1_ready = sdram_bankmachine1_req_ready; +assign sdram_bankmachine1_req_we = sdram_interface_bank1_we; +assign sdram_bankmachine1_req_addr = sdram_interface_bank1_addr; +assign sdram_interface_bank1_lock = sdram_bankmachine1_req_lock; +assign sdram_interface_bank1_wdata_ready = sdram_bankmachine1_req_wdata_ready; +assign sdram_interface_bank1_rdata_valid = sdram_bankmachine1_req_rdata_valid; +assign sdram_bankmachine2_req_valid = sdram_interface_bank2_valid; +assign sdram_interface_bank2_ready = sdram_bankmachine2_req_ready; +assign sdram_bankmachine2_req_we = sdram_interface_bank2_we; +assign sdram_bankmachine2_req_addr = sdram_interface_bank2_addr; +assign sdram_interface_bank2_lock = sdram_bankmachine2_req_lock; +assign sdram_interface_bank2_wdata_ready = sdram_bankmachine2_req_wdata_ready; +assign sdram_interface_bank2_rdata_valid = sdram_bankmachine2_req_rdata_valid; +assign sdram_bankmachine3_req_valid = sdram_interface_bank3_valid; +assign sdram_interface_bank3_ready = sdram_bankmachine3_req_ready; +assign sdram_bankmachine3_req_we = sdram_interface_bank3_we; +assign sdram_bankmachine3_req_addr = sdram_interface_bank3_addr; +assign sdram_interface_bank3_lock = sdram_bankmachine3_req_lock; +assign sdram_interface_bank3_wdata_ready = sdram_bankmachine3_req_wdata_ready; +assign sdram_interface_bank3_rdata_valid = sdram_bankmachine3_req_rdata_valid; +assign sdram_timer_wait = (~sdram_timer_done0); +assign sdram_postponer_req_i = sdram_timer_done0; +assign sdram_wants_refresh = sdram_postponer_req_o; +assign sdram_timer_done1 = (sdram_timer_count1 == 1'd0); +assign sdram_timer_done0 = sdram_timer_done1; +assign sdram_timer_count0 = sdram_timer_count1; +assign sdram_sequencer_start1 = (sdram_sequencer_start0 | (sdram_sequencer_count != 1'd0)); +assign sdram_sequencer_done0 = (sdram_sequencer_done1 & (sdram_sequencer_count == 1'd0)); +always @(*) begin + sdram_sequencer_start0 <= 1'd0; + subfragments_refresher_next_state <= 2'd0; + sdram_cmd_valid <= 1'd0; + sdram_cmd_last <= 1'd0; + subfragments_refresher_next_state <= subfragments_refresher_state; + case (subfragments_refresher_state) + 1'd1: begin + sdram_cmd_valid <= 1'd1; + if (sdram_cmd_ready) begin + sdram_sequencer_start0 <= 1'd1; + subfragments_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + sdram_cmd_valid <= 1'd1; + if (sdram_sequencer_done0) begin + sdram_cmd_valid <= 1'd0; + sdram_cmd_last <= 1'd1; + subfragments_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (sdram_wants_refresh) begin + subfragments_refresher_next_state <= 1'd1; + end + end + end + endcase +end +assign sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = sdram_bankmachine0_req_valid; +assign sdram_bankmachine0_req_ready = sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine0_req_we; +assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine0_req_addr; +assign sdram_bankmachine0_cmd_buffer_sink_valid = sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_ready = sdram_bankmachine0_cmd_buffer_sink_ready; +assign sdram_bankmachine0_cmd_buffer_sink_first = sdram_bankmachine0_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine0_cmd_buffer_sink_last = sdram_bankmachine0_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine0_cmd_buffer_sink_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine0_cmd_buffer_sink_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine0_cmd_buffer_source_ready = (sdram_bankmachine0_req_wdata_ready | sdram_bankmachine0_req_rdata_valid); +assign sdram_bankmachine0_req_lock = (sdram_bankmachine0_cmd_buffer_lookahead_source_valid | sdram_bankmachine0_cmd_buffer_source_valid); +assign sdram_bankmachine0_row_hit = (sdram_bankmachine0_row == sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]); +assign sdram_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + sdram_bankmachine0_cmd_payload_a <= 13'd0; + if (sdram_bankmachine0_row_col_n_addr_sel) begin + sdram_bankmachine0_cmd_payload_a <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]; + end else begin + sdram_bankmachine0_cmd_payload_a <= ((sdram_bankmachine0_auto_precharge <<< 4'd10) | {sdram_bankmachine0_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}}); + end +end +assign sdram_bankmachine0_twtpcon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_cmd_payload_is_write); +assign sdram_bankmachine0_trccon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open); +assign sdram_bankmachine0_trascon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open); +always @(*) begin + sdram_bankmachine0_auto_precharge <= 1'd0; + if ((sdram_bankmachine0_cmd_buffer_lookahead_source_valid & sdram_bankmachine0_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9])) begin + sdram_bankmachine0_auto_precharge <= (sdram_bankmachine0_row_close == 1'd0); + end + end +end +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine0_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine0_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_valid = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_first = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_last = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine0_cmd_buffer_lookahead_replace) begin + sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine0_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | sdram_bankmachine0_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine0_cmd_buffer_lookahead_do_read = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine0_cmd_buffer_lookahead_consume; +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine0_cmd_payload_cas <= 1'd0; + sdram_bankmachine0_cmd_payload_ras <= 1'd0; + sdram_bankmachine0_cmd_payload_we <= 1'd0; + sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine0_cmd_payload_is_read <= 1'd0; + sdram_bankmachine0_cmd_payload_is_write <= 1'd0; + sdram_bankmachine0_req_wdata_ready <= 1'd0; + sdram_bankmachine0_req_rdata_valid <= 1'd0; + sdram_bankmachine0_refresh_gnt <= 1'd0; + subfragments_bankmachine0_next_state <= 3'd0; + sdram_bankmachine0_cmd_valid <= 1'd0; + sdram_bankmachine0_row_open <= 1'd0; + sdram_bankmachine0_row_close <= 1'd0; + subfragments_bankmachine0_next_state <= subfragments_bankmachine0_state; + case (subfragments_bankmachine0_state) + 1'd1: begin + if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin + sdram_bankmachine0_cmd_valid <= 1'd1; + if (sdram_bankmachine0_cmd_ready) begin + subfragments_bankmachine0_next_state <= 3'd5; + end + sdram_bankmachine0_cmd_payload_ras <= 1'd1; + sdram_bankmachine0_cmd_payload_we <= 1'd1; + sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin + subfragments_bankmachine0_next_state <= 3'd5; + end + sdram_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine0_trccon_ready) begin + sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine0_row_open <= 1'd1; + sdram_bankmachine0_cmd_valid <= 1'd1; + sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine0_cmd_ready) begin + subfragments_bankmachine0_next_state <= 3'd6; + end + sdram_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine0_twtpcon_ready) begin + sdram_bankmachine0_refresh_gnt <= 1'd1; + end + sdram_bankmachine0_row_close <= 1'd1; + sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine0_refresh_req)) begin + subfragments_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine0_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine0_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine0_refresh_req) begin + subfragments_bankmachine0_next_state <= 3'd4; + end else begin + if (sdram_bankmachine0_cmd_buffer_source_valid) begin + if (sdram_bankmachine0_row_opened) begin + if (sdram_bankmachine0_row_hit) begin + sdram_bankmachine0_cmd_valid <= 1'd1; + if (sdram_bankmachine0_cmd_buffer_source_payload_we) begin + sdram_bankmachine0_req_wdata_ready <= sdram_bankmachine0_cmd_ready; + sdram_bankmachine0_cmd_payload_is_write <= 1'd1; + sdram_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine0_req_rdata_valid <= sdram_bankmachine0_cmd_ready; + sdram_bankmachine0_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine0_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine0_cmd_ready & sdram_bankmachine0_auto_precharge)) begin + subfragments_bankmachine0_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine0_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = sdram_bankmachine1_req_valid; +assign sdram_bankmachine1_req_ready = sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine1_req_we; +assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine1_req_addr; +assign sdram_bankmachine1_cmd_buffer_sink_valid = sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_ready = sdram_bankmachine1_cmd_buffer_sink_ready; +assign sdram_bankmachine1_cmd_buffer_sink_first = sdram_bankmachine1_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine1_cmd_buffer_sink_last = sdram_bankmachine1_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine1_cmd_buffer_sink_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine1_cmd_buffer_sink_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine1_cmd_buffer_source_ready = (sdram_bankmachine1_req_wdata_ready | sdram_bankmachine1_req_rdata_valid); +assign sdram_bankmachine1_req_lock = (sdram_bankmachine1_cmd_buffer_lookahead_source_valid | sdram_bankmachine1_cmd_buffer_source_valid); +assign sdram_bankmachine1_row_hit = (sdram_bankmachine1_row == sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]); +assign sdram_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + sdram_bankmachine1_cmd_payload_a <= 13'd0; + if (sdram_bankmachine1_row_col_n_addr_sel) begin + sdram_bankmachine1_cmd_payload_a <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]; + end else begin + sdram_bankmachine1_cmd_payload_a <= ((sdram_bankmachine1_auto_precharge <<< 4'd10) | {sdram_bankmachine1_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}}); + end +end +assign sdram_bankmachine1_twtpcon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_cmd_payload_is_write); +assign sdram_bankmachine1_trccon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open); +assign sdram_bankmachine1_trascon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open); +always @(*) begin + sdram_bankmachine1_auto_precharge <= 1'd0; + if ((sdram_bankmachine1_cmd_buffer_lookahead_source_valid & sdram_bankmachine1_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9])) begin + sdram_bankmachine1_auto_precharge <= (sdram_bankmachine1_row_close == 1'd0); + end + end +end +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine1_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine1_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_valid = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_first = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_last = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine1_cmd_buffer_lookahead_replace) begin + sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine1_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | sdram_bankmachine1_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine1_cmd_buffer_lookahead_do_read = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine1_cmd_buffer_lookahead_consume; +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine1_cmd_buffer_sink_ready = ((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine1_row_open <= 1'd0; + sdram_bankmachine1_row_close <= 1'd0; + sdram_bankmachine1_cmd_payload_cas <= 1'd0; + sdram_bankmachine1_cmd_payload_ras <= 1'd0; + sdram_bankmachine1_cmd_payload_we <= 1'd0; + sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; + subfragments_bankmachine1_next_state <= 3'd0; + sdram_bankmachine1_cmd_payload_is_read <= 1'd0; + sdram_bankmachine1_cmd_payload_is_write <= 1'd0; + sdram_bankmachine1_req_wdata_ready <= 1'd0; + sdram_bankmachine1_req_rdata_valid <= 1'd0; + sdram_bankmachine1_refresh_gnt <= 1'd0; + sdram_bankmachine1_cmd_valid <= 1'd0; + subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state; + case (subfragments_bankmachine1_state) + 1'd1: begin + if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin + sdram_bankmachine1_cmd_valid <= 1'd1; + if (sdram_bankmachine1_cmd_ready) begin + subfragments_bankmachine1_next_state <= 3'd5; + end + sdram_bankmachine1_cmd_payload_ras <= 1'd1; + sdram_bankmachine1_cmd_payload_we <= 1'd1; + sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin + subfragments_bankmachine1_next_state <= 3'd5; + end + sdram_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine1_trccon_ready) begin + sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine1_row_open <= 1'd1; + sdram_bankmachine1_cmd_valid <= 1'd1; + sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine1_cmd_ready) begin + subfragments_bankmachine1_next_state <= 3'd6; + end + sdram_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine1_twtpcon_ready) begin + sdram_bankmachine1_refresh_gnt <= 1'd1; + end + sdram_bankmachine1_row_close <= 1'd1; + sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine1_refresh_req)) begin + subfragments_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine1_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine1_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine1_refresh_req) begin + subfragments_bankmachine1_next_state <= 3'd4; + end else begin + if (sdram_bankmachine1_cmd_buffer_source_valid) begin + if (sdram_bankmachine1_row_opened) begin + if (sdram_bankmachine1_row_hit) begin + sdram_bankmachine1_cmd_valid <= 1'd1; + if (sdram_bankmachine1_cmd_buffer_source_payload_we) begin + sdram_bankmachine1_req_wdata_ready <= sdram_bankmachine1_cmd_ready; + sdram_bankmachine1_cmd_payload_is_write <= 1'd1; + sdram_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine1_req_rdata_valid <= sdram_bankmachine1_cmd_ready; + sdram_bankmachine1_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine1_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine1_cmd_ready & sdram_bankmachine1_auto_precharge)) begin + subfragments_bankmachine1_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine1_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = sdram_bankmachine2_req_valid; +assign sdram_bankmachine2_req_ready = sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine2_req_we; +assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine2_req_addr; +assign sdram_bankmachine2_cmd_buffer_sink_valid = sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_ready = sdram_bankmachine2_cmd_buffer_sink_ready; +assign sdram_bankmachine2_cmd_buffer_sink_first = sdram_bankmachine2_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine2_cmd_buffer_sink_last = sdram_bankmachine2_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine2_cmd_buffer_sink_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine2_cmd_buffer_sink_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine2_cmd_buffer_source_ready = (sdram_bankmachine2_req_wdata_ready | sdram_bankmachine2_req_rdata_valid); +assign sdram_bankmachine2_req_lock = (sdram_bankmachine2_cmd_buffer_lookahead_source_valid | sdram_bankmachine2_cmd_buffer_source_valid); +assign sdram_bankmachine2_row_hit = (sdram_bankmachine2_row == sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]); +assign sdram_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + sdram_bankmachine2_cmd_payload_a <= 13'd0; + if (sdram_bankmachine2_row_col_n_addr_sel) begin + sdram_bankmachine2_cmd_payload_a <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]; + end else begin + sdram_bankmachine2_cmd_payload_a <= ((sdram_bankmachine2_auto_precharge <<< 4'd10) | {sdram_bankmachine2_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}}); + end +end +assign sdram_bankmachine2_twtpcon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_cmd_payload_is_write); +assign sdram_bankmachine2_trccon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open); +assign sdram_bankmachine2_trascon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open); +always @(*) begin + sdram_bankmachine2_auto_precharge <= 1'd0; + if ((sdram_bankmachine2_cmd_buffer_lookahead_source_valid & sdram_bankmachine2_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9])) begin + sdram_bankmachine2_auto_precharge <= (sdram_bankmachine2_row_close == 1'd0); + end + end +end +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine2_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine2_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_valid = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_first = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_last = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine2_cmd_buffer_lookahead_replace) begin + sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine2_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | sdram_bankmachine2_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine2_cmd_buffer_lookahead_do_read = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine2_cmd_buffer_lookahead_consume; +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine2_cmd_buffer_sink_ready = ((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine2_refresh_gnt <= 1'd0; + sdram_bankmachine2_cmd_valid <= 1'd0; + subfragments_bankmachine2_next_state <= 3'd0; + sdram_bankmachine2_row_open <= 1'd0; + sdram_bankmachine2_row_close <= 1'd0; + sdram_bankmachine2_cmd_payload_cas <= 1'd0; + sdram_bankmachine2_cmd_payload_ras <= 1'd0; + sdram_bankmachine2_cmd_payload_we <= 1'd0; + sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; + sdram_bankmachine2_cmd_payload_is_read <= 1'd0; + sdram_bankmachine2_cmd_payload_is_write <= 1'd0; + sdram_bankmachine2_req_wdata_ready <= 1'd0; + sdram_bankmachine2_req_rdata_valid <= 1'd0; + subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state; + case (subfragments_bankmachine2_state) + 1'd1: begin + if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin + sdram_bankmachine2_cmd_valid <= 1'd1; + if (sdram_bankmachine2_cmd_ready) begin + subfragments_bankmachine2_next_state <= 3'd5; + end + sdram_bankmachine2_cmd_payload_ras <= 1'd1; + sdram_bankmachine2_cmd_payload_we <= 1'd1; + sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin + subfragments_bankmachine2_next_state <= 3'd5; + end + sdram_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine2_trccon_ready) begin + sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine2_row_open <= 1'd1; + sdram_bankmachine2_cmd_valid <= 1'd1; + sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine2_cmd_ready) begin + subfragments_bankmachine2_next_state <= 3'd6; + end + sdram_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine2_twtpcon_ready) begin + sdram_bankmachine2_refresh_gnt <= 1'd1; + end + sdram_bankmachine2_row_close <= 1'd1; + sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine2_refresh_req)) begin + subfragments_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine2_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine2_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine2_refresh_req) begin + subfragments_bankmachine2_next_state <= 3'd4; + end else begin + if (sdram_bankmachine2_cmd_buffer_source_valid) begin + if (sdram_bankmachine2_row_opened) begin + if (sdram_bankmachine2_row_hit) begin + sdram_bankmachine2_cmd_valid <= 1'd1; + if (sdram_bankmachine2_cmd_buffer_source_payload_we) begin + sdram_bankmachine2_req_wdata_ready <= sdram_bankmachine2_cmd_ready; + sdram_bankmachine2_cmd_payload_is_write <= 1'd1; + sdram_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine2_req_rdata_valid <= sdram_bankmachine2_cmd_ready; + sdram_bankmachine2_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine2_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine2_cmd_ready & sdram_bankmachine2_auto_precharge)) begin + subfragments_bankmachine2_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine2_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = sdram_bankmachine3_req_valid; +assign sdram_bankmachine3_req_ready = sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine3_req_we; +assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine3_req_addr; +assign sdram_bankmachine3_cmd_buffer_sink_valid = sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_ready = sdram_bankmachine3_cmd_buffer_sink_ready; +assign sdram_bankmachine3_cmd_buffer_sink_first = sdram_bankmachine3_cmd_buffer_lookahead_source_first; +assign sdram_bankmachine3_cmd_buffer_sink_last = sdram_bankmachine3_cmd_buffer_lookahead_source_last; +assign sdram_bankmachine3_cmd_buffer_sink_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign sdram_bankmachine3_cmd_buffer_sink_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign sdram_bankmachine3_cmd_buffer_source_ready = (sdram_bankmachine3_req_wdata_ready | sdram_bankmachine3_req_rdata_valid); +assign sdram_bankmachine3_req_lock = (sdram_bankmachine3_cmd_buffer_lookahead_source_valid | sdram_bankmachine3_cmd_buffer_source_valid); +assign sdram_bankmachine3_row_hit = (sdram_bankmachine3_row == sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]); +assign sdram_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + sdram_bankmachine3_cmd_payload_a <= 13'd0; + if (sdram_bankmachine3_row_col_n_addr_sel) begin + sdram_bankmachine3_cmd_payload_a <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]; + end else begin + sdram_bankmachine3_cmd_payload_a <= ((sdram_bankmachine3_auto_precharge <<< 4'd10) | {sdram_bankmachine3_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}}); + end +end +assign sdram_bankmachine3_twtpcon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_cmd_payload_is_write); +assign sdram_bankmachine3_trccon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open); +assign sdram_bankmachine3_trascon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open); +always @(*) begin + sdram_bankmachine3_auto_precharge <= 1'd0; + if ((sdram_bankmachine3_cmd_buffer_lookahead_source_valid & sdram_bankmachine3_cmd_buffer_source_valid)) begin + if ((sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9])) begin + sdram_bankmachine3_auto_precharge <= (sdram_bankmachine3_row_close == 1'd0); + end + end +end +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine3_cmd_buffer_lookahead_sink_first; +assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine3_cmd_buffer_lookahead_sink_last; +assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_valid = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_first = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_last = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +always @(*) begin + sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (sdram_bankmachine3_cmd_buffer_lookahead_replace) begin + sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine3_cmd_buffer_lookahead_produce; + end +end +assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | sdram_bankmachine3_cmd_buffer_lookahead_replace)); +assign sdram_bankmachine3_cmd_buffer_lookahead_do_read = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine3_cmd_buffer_lookahead_consume; +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8); +assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready); +always @(*) begin + sdram_bankmachine3_cmd_payload_is_read <= 1'd0; + sdram_bankmachine3_cmd_payload_is_write <= 1'd0; + sdram_bankmachine3_req_wdata_ready <= 1'd0; + sdram_bankmachine3_req_rdata_valid <= 1'd0; + subfragments_bankmachine3_next_state <= 3'd0; + sdram_bankmachine3_refresh_gnt <= 1'd0; + sdram_bankmachine3_cmd_valid <= 1'd0; + sdram_bankmachine3_row_open <= 1'd0; + sdram_bankmachine3_row_close <= 1'd0; + sdram_bankmachine3_cmd_payload_cas <= 1'd0; + sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine3_cmd_payload_ras <= 1'd0; + sdram_bankmachine3_cmd_payload_we <= 1'd0; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; + subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state; + case (subfragments_bankmachine3_state) + 1'd1: begin + if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin + sdram_bankmachine3_cmd_valid <= 1'd1; + if (sdram_bankmachine3_cmd_ready) begin + subfragments_bankmachine3_next_state <= 3'd5; + end + sdram_bankmachine3_cmd_payload_ras <= 1'd1; + sdram_bankmachine3_cmd_payload_we <= 1'd1; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + sdram_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin + subfragments_bankmachine3_next_state <= 3'd5; + end + sdram_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + if (sdram_bankmachine3_trccon_ready) begin + sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; + sdram_bankmachine3_row_open <= 1'd1; + sdram_bankmachine3_cmd_valid <= 1'd1; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (sdram_bankmachine3_cmd_ready) begin + subfragments_bankmachine3_next_state <= 3'd6; + end + sdram_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (sdram_bankmachine3_twtpcon_ready) begin + sdram_bankmachine3_refresh_gnt <= 1'd1; + end + sdram_bankmachine3_row_close <= 1'd1; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((~sdram_bankmachine3_refresh_req)) begin + subfragments_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + subfragments_bankmachine3_next_state <= 2'd3; + end + 3'd6: begin + subfragments_bankmachine3_next_state <= 1'd0; + end + default: begin + if (sdram_bankmachine3_refresh_req) begin + subfragments_bankmachine3_next_state <= 3'd4; + end else begin + if (sdram_bankmachine3_cmd_buffer_source_valid) begin + if (sdram_bankmachine3_row_opened) begin + if (sdram_bankmachine3_row_hit) begin + sdram_bankmachine3_cmd_valid <= 1'd1; + if (sdram_bankmachine3_cmd_buffer_source_payload_we) begin + sdram_bankmachine3_req_wdata_ready <= sdram_bankmachine3_cmd_ready; + sdram_bankmachine3_cmd_payload_is_write <= 1'd1; + sdram_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + sdram_bankmachine3_req_rdata_valid <= sdram_bankmachine3_cmd_ready; + sdram_bankmachine3_cmd_payload_is_read <= 1'd1; + end + sdram_bankmachine3_cmd_payload_cas <= 1'd1; + if ((sdram_bankmachine3_cmd_ready & sdram_bankmachine3_auto_precharge)) begin + subfragments_bankmachine3_next_state <= 2'd2; + end + end else begin + subfragments_bankmachine3_next_state <= 1'd1; + end + end else begin + subfragments_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +assign sdram_choose_req_want_cmds = 1'd1; +assign sdram_trrdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))); +assign sdram_tfawcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))); +assign sdram_ras_allowed = (sdram_trrdcon_ready & sdram_tfawcon_ready); +assign sdram_tccdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_cmd_payload_is_write | sdram_choose_req_cmd_payload_is_read)); +assign sdram_cas_allowed = sdram_tccdcon_ready; +assign sdram_twtrcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); +assign sdram_read_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_read) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_read)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_read)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_read)); +assign sdram_write_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_write) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_write)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_write)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_write)); +assign sdram_max_time0 = (sdram_time0 == 1'd0); +assign sdram_max_time1 = (sdram_time1 == 1'd0); +assign sdram_bankmachine0_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine1_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine2_refresh_req = sdram_cmd_valid; +assign sdram_bankmachine3_refresh_req = sdram_cmd_valid; +assign sdram_go_to_refresh = (((sdram_bankmachine0_refresh_gnt & sdram_bankmachine1_refresh_gnt) & sdram_bankmachine2_refresh_gnt) & sdram_bankmachine3_refresh_gnt); +assign sdram_interface_rdata = {sdram_dfi_p0_rddata}; +assign {sdram_dfi_p0_wrdata} = sdram_interface_wdata; +assign {sdram_dfi_p0_wrdata_mask} = (~sdram_interface_wdata_we); +always @(*) begin + sdram_choose_cmd_valids <= 4'd0; + sdram_choose_cmd_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); + sdram_choose_cmd_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); +end +assign sdram_choose_cmd_request = sdram_choose_cmd_valids; +assign sdram_choose_cmd_cmd_valid = rhs_array_muxed0; +assign sdram_choose_cmd_cmd_payload_a = rhs_array_muxed1; +assign sdram_choose_cmd_cmd_payload_ba = rhs_array_muxed2; +assign sdram_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; +assign sdram_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; +assign sdram_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +always @(*) begin + sdram_choose_cmd_cmd_payload_cas <= 1'd0; + if (sdram_choose_cmd_cmd_valid) begin + sdram_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end +end +always @(*) begin + sdram_choose_cmd_cmd_payload_ras <= 1'd0; + if (sdram_choose_cmd_cmd_valid) begin + sdram_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end +end +always @(*) begin + sdram_choose_cmd_cmd_payload_we <= 1'd0; + if (sdram_choose_cmd_cmd_valid) begin + sdram_choose_cmd_cmd_payload_we <= t_array_muxed2; + end +end +assign sdram_choose_cmd_ce = (sdram_choose_cmd_cmd_ready | (~sdram_choose_cmd_cmd_valid)); +always @(*) begin + sdram_choose_req_valids <= 4'd0; + sdram_choose_req_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_req_want_writes)))); + sdram_choose_req_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_req_want_writes)))); +end +assign sdram_choose_req_request = sdram_choose_req_valids; +assign sdram_choose_req_cmd_valid = rhs_array_muxed6; +assign sdram_choose_req_cmd_payload_a = rhs_array_muxed7; +assign sdram_choose_req_cmd_payload_ba = rhs_array_muxed8; +assign sdram_choose_req_cmd_payload_is_read = rhs_array_muxed9; +assign sdram_choose_req_cmd_payload_is_write = rhs_array_muxed10; +assign sdram_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +always @(*) begin + sdram_choose_req_cmd_payload_cas <= 1'd0; + if (sdram_choose_req_cmd_valid) begin + sdram_choose_req_cmd_payload_cas <= t_array_muxed3; + end +end +always @(*) begin + sdram_choose_req_cmd_payload_ras <= 1'd0; + if (sdram_choose_req_cmd_valid) begin + sdram_choose_req_cmd_payload_ras <= t_array_muxed4; + end +end +always @(*) begin + sdram_choose_req_cmd_payload_we <= 1'd0; + if (sdram_choose_req_cmd_valid) begin + sdram_choose_req_cmd_payload_we <= t_array_muxed5; + end +end +always @(*) begin + sdram_bankmachine0_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd0))) begin + sdram_bankmachine0_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd0))) begin + sdram_bankmachine0_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine1_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd1))) begin + sdram_bankmachine1_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd1))) begin + sdram_bankmachine1_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine2_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd2))) begin + sdram_bankmachine2_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd2))) begin + sdram_bankmachine2_cmd_ready <= 1'd1; + end +end +always @(*) begin + sdram_bankmachine3_cmd_ready <= 1'd0; + if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd3))) begin + sdram_bankmachine3_cmd_ready <= 1'd1; + end + if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd3))) begin + sdram_bankmachine3_cmd_ready <= 1'd1; + end +end +assign sdram_choose_req_ce = (sdram_choose_req_cmd_ready | (~sdram_choose_req_cmd_valid)); +assign sdram_dfi_p0_reset_n = 1'd1; +assign sdram_dfi_p0_cke = {1{sdram_steerer0}}; +assign sdram_dfi_p0_odt = {1{sdram_steerer1}}; +always @(*) begin + subfragments_multiplexer_next_state <= 3'd0; + sdram_en1 <= 1'd0; + sdram_choose_req_want_reads <= 1'd0; + sdram_choose_req_want_writes <= 1'd0; + sdram_cmd_ready <= 1'd0; + sdram_choose_req_want_activates <= 1'd0; + sdram_steerer_sel <= 2'd0; + sdram_choose_req_cmd_ready <= 1'd0; + sdram_en0 <= 1'd0; + sdram_choose_req_want_activates <= sdram_ras_allowed; + subfragments_multiplexer_next_state <= subfragments_multiplexer_state; + case (subfragments_multiplexer_state) + 1'd1: begin + sdram_en1 <= 1'd1; + sdram_choose_req_want_writes <= 1'd1; + if (1'd1) begin + sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed)); + end else begin + sdram_choose_req_want_activates <= sdram_ras_allowed; + sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed); + sdram_choose_req_cmd_ready <= sdram_cas_allowed; + end + sdram_steerer_sel <= 2'd2; + if (sdram_read_available) begin + if (((~sdram_write_available) | sdram_max_time1)) begin + subfragments_multiplexer_next_state <= 2'd3; + end + end + if (sdram_go_to_refresh) begin + subfragments_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + sdram_steerer_sel <= 2'd3; + sdram_cmd_ready <= 1'd1; + if (sdram_cmd_last) begin + subfragments_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (sdram_twtrcon_ready) begin + subfragments_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + subfragments_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + subfragments_multiplexer_next_state <= 1'd1; + end + default: begin + sdram_en0 <= 1'd1; + sdram_choose_req_want_reads <= 1'd1; + if (1'd1) begin + sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed)); + end else begin + sdram_choose_req_want_activates <= sdram_ras_allowed; + sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed); + sdram_choose_req_cmd_ready <= sdram_cas_allowed; + end + sdram_steerer_sel <= 2'd2; + if (sdram_write_available) begin + if (((~sdram_read_available) | sdram_max_time0)) begin + subfragments_multiplexer_next_state <= 3'd4; + end + end + if (sdram_go_to_refresh) begin + subfragments_multiplexer_next_state <= 2'd2; + end + end + endcase +end +assign subfragments_roundrobin0_request = {(((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin0_ce = ((~sdram_interface_bank0_valid) & (~sdram_interface_bank0_lock)); +assign sdram_interface_bank0_addr = rhs_array_muxed12; +assign sdram_interface_bank0_we = rhs_array_muxed13; +assign sdram_interface_bank0_valid = rhs_array_muxed14; +assign subfragments_roundrobin1_request = {(((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin1_ce = ((~sdram_interface_bank1_valid) & (~sdram_interface_bank1_lock)); +assign sdram_interface_bank1_addr = rhs_array_muxed15; +assign sdram_interface_bank1_we = rhs_array_muxed16; +assign sdram_interface_bank1_valid = rhs_array_muxed17; +assign subfragments_roundrobin2_request = {(((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin2_ce = ((~sdram_interface_bank2_valid) & (~sdram_interface_bank2_lock)); +assign sdram_interface_bank2_addr = rhs_array_muxed18; +assign sdram_interface_bank2_we = rhs_array_muxed19; +assign sdram_interface_bank2_valid = rhs_array_muxed20; +assign subfragments_roundrobin3_request = {(((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid)}; +assign subfragments_roundrobin3_ce = ((~sdram_interface_bank3_valid) & (~sdram_interface_bank3_lock)); +assign sdram_interface_bank3_addr = rhs_array_muxed21; +assign sdram_interface_bank3_we = rhs_array_muxed22; +assign sdram_interface_bank3_valid = rhs_array_muxed23; +assign port_cmd_ready = ((((1'd0 | (((subfragments_roundrobin0_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank0_ready)) | (((subfragments_roundrobin1_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank1_ready)) | (((subfragments_roundrobin2_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank2_ready)) | (((subfragments_roundrobin3_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0)))))) & sdram_interface_bank3_ready)); +assign port_wdata_ready = subfragments_new_master_wdata_ready; +assign port_rdata_valid = subfragments_new_master_rdata_valid3; +always @(*) begin + sdram_interface_wdata <= 16'd0; + sdram_interface_wdata_we <= 2'd0; + case ({subfragments_new_master_wdata_ready}) + 1'd1: begin + sdram_interface_wdata <= port_wdata_payload_data; + sdram_interface_wdata_we <= port_wdata_payload_we; + end + default: begin + sdram_interface_wdata <= 1'd0; + sdram_interface_wdata_we <= 1'd0; + end + endcase +end +assign port_rdata_payload_data = sdram_interface_rdata; +assign subfragments_roundrobin0_grant = 1'd0; +assign subfragments_roundrobin1_grant = 1'd0; +assign subfragments_roundrobin2_grant = 1'd0; +assign subfragments_roundrobin3_grant = 1'd0; +assign converter_reset = (~wb_sdram_cyc); +always @(*) begin + litedram_wb_dat_w <= 16'd0; + case (converter_counter) + 1'd0: begin + litedram_wb_dat_w <= wb_sdram_dat_w[31:0]; + end + 1'd1: begin + litedram_wb_dat_w <= wb_sdram_dat_w[31:16]; + end + endcase +end +assign wb_sdram_dat_r = {litedram_wb_dat_r, converter_dat_r[31:16]}; +always @(*) begin + litedram_wb_sel <= 2'd0; + litedram_wb_cyc <= 1'd0; + litedram_wb_stb <= 1'd0; + subfragments_next_state <= 1'd0; + converter_counter_subfragments_next_value <= 1'd0; + litedram_wb_we <= 1'd0; + converter_counter_subfragments_next_value_ce <= 1'd0; + converter_skip <= 1'd0; + wb_sdram_ack <= 1'd0; + litedram_wb_adr <= 30'd0; + subfragments_next_state <= subfragments_state; + case (subfragments_state) + 1'd1: begin + litedram_wb_adr <= {wb_sdram_adr, converter_counter}; + case (converter_counter) + 1'd0: begin + litedram_wb_sel <= wb_sdram_sel[3:0]; + end + 1'd1: begin + litedram_wb_sel <= wb_sdram_sel[3:2]; + end + endcase + if ((wb_sdram_stb & wb_sdram_cyc)) begin + converter_skip <= (litedram_wb_sel == 1'd0); + litedram_wb_we <= wb_sdram_we; + litedram_wb_cyc <= (~converter_skip); + litedram_wb_stb <= (~converter_skip); + if ((litedram_wb_ack | converter_skip)) begin + converter_counter_subfragments_next_value <= (converter_counter + 1'd1); + converter_counter_subfragments_next_value_ce <= 1'd1; + if ((converter_counter == 1'd1)) begin + wb_sdram_ack <= 1'd1; + subfragments_next_state <= 1'd0; + end + end + end + end + default: begin + converter_counter_subfragments_next_value <= 1'd0; + converter_counter_subfragments_next_value_ce <= 1'd1; + if ((wb_sdram_stb & wb_sdram_cyc)) begin + subfragments_next_state <= 1'd1; + end + end + endcase +end +assign port_cmd_payload_addr = (litedram_wb_adr - 31'd1207959552); +assign port_cmd_payload_we = litedram_wb_we; +assign port_wdata_payload_data = litedram_wb_dat_w; +assign port_wdata_payload_we = litedram_wb_sel; +assign litedram_wb_dat_r = port_rdata_payload_data; +assign port_flush = (~litedram_wb_cyc); +assign port_cmd_last = (~litedram_wb_we); +assign port_cmd_valid = ((litedram_wb_cyc & litedram_wb_stb) & (~cmd_consumed)); +assign port_wdata_valid = (((port_cmd_valid | cmd_consumed) & port_cmd_payload_we) & (~wdata_consumed)); +assign port_rdata_ready = ((port_cmd_valid | cmd_consumed) & (~port_cmd_payload_we)); +assign litedram_wb_ack = (ack_cmd & ((litedram_wb_we & ack_wdata) | ((~litedram_wb_we) & ack_rdata))); +assign ack_cmd = ((port_cmd_valid & port_cmd_ready) | cmd_consumed); +assign ack_wdata = ((port_wdata_valid & port_wdata_ready) | wdata_consumed); +assign ack_rdata = (port_rdata_valid & port_rdata_ready); +assign uart_sink_valid = uart_phy_source_valid; +assign uart_phy_source_ready = uart_sink_ready; +assign uart_sink_first = uart_phy_source_first; +assign uart_sink_last = uart_phy_source_last; +assign uart_sink_payload_data = uart_phy_source_payload_data; +assign uart_phy_sink_valid = uart_source_valid; +assign uart_source_ready = uart_phy_sink_ready; +assign uart_phy_sink_first = uart_source_first; +assign uart_phy_sink_last = uart_source_last; +assign uart_phy_sink_payload_data = uart_source_payload_data; +assign tx_fifo_sink_valid = rxtx_re; +assign tx_fifo_sink_payload_data = rxtx_r; +assign txfull_status = (~tx_fifo_sink_ready); +assign txempty_status = (~tx_fifo_source_valid); +assign uart_source_valid = tx_fifo_source_valid; +assign tx_fifo_source_ready = uart_source_ready; +assign uart_source_first = tx_fifo_source_first; +assign uart_source_last = tx_fifo_source_last; +assign uart_source_payload_data = tx_fifo_source_payload_data; +assign tx_trigger = (~tx_fifo_sink_ready); +assign rx_fifo_sink_valid = uart_sink_valid; +assign uart_sink_ready = rx_fifo_sink_ready; +assign rx_fifo_sink_first = uart_sink_first; +assign rx_fifo_sink_last = uart_sink_last; +assign rx_fifo_sink_payload_data = uart_sink_payload_data; +assign rxempty_status = (~rx_fifo_source_valid); +assign rxfull_status = (~rx_fifo_sink_ready); +assign rxtx_w = rx_fifo_source_payload_data; +assign rx_fifo_source_ready = (rx_clear | (1'd0 & rxtx_we)); +assign rx_trigger = (~rx_fifo_source_valid); +always @(*) begin + tx_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin + tx_clear <= 1'd1; + end +end +always @(*) begin + eventmanager_status_w <= 2'd0; + eventmanager_status_w[0] <= tx_status; + eventmanager_status_w[1] <= rx_status; +end +always @(*) begin + rx_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin + rx_clear <= 1'd1; + end +end +always @(*) begin + eventmanager_pending_w <= 2'd0; + eventmanager_pending_w[0] <= tx_pending; + eventmanager_pending_w[1] <= rx_pending; +end +assign irq = ((eventmanager_pending_w[0] & eventmanager_storage[0]) | (eventmanager_pending_w[1] & eventmanager_storage[1])); +assign tx_status = tx_trigger; +assign rx_status = rx_trigger; +assign tx_fifo_syncfifo_din = {tx_fifo_fifo_in_last, tx_fifo_fifo_in_first, tx_fifo_fifo_in_payload_data}; +assign {tx_fifo_fifo_out_last, tx_fifo_fifo_out_first, tx_fifo_fifo_out_payload_data} = tx_fifo_syncfifo_dout; +assign tx_fifo_sink_ready = tx_fifo_syncfifo_writable; +assign tx_fifo_syncfifo_we = tx_fifo_sink_valid; +assign tx_fifo_fifo_in_first = tx_fifo_sink_first; +assign tx_fifo_fifo_in_last = tx_fifo_sink_last; +assign tx_fifo_fifo_in_payload_data = tx_fifo_sink_payload_data; +assign tx_fifo_source_valid = tx_fifo_readable; +assign tx_fifo_source_first = tx_fifo_fifo_out_first; +assign tx_fifo_source_last = tx_fifo_fifo_out_last; +assign tx_fifo_source_payload_data = tx_fifo_fifo_out_payload_data; +assign tx_fifo_re = tx_fifo_source_ready; +assign tx_fifo_syncfifo_re = (tx_fifo_syncfifo_readable & ((~tx_fifo_readable) | tx_fifo_re)); +assign tx_fifo_level1 = (tx_fifo_level0 + tx_fifo_readable); +always @(*) begin + tx_fifo_wrport_adr <= 4'd0; + if (tx_fifo_replace) begin + tx_fifo_wrport_adr <= (tx_fifo_produce - 1'd1); + end else begin + tx_fifo_wrport_adr <= tx_fifo_produce; + end +end +assign tx_fifo_wrport_dat_w = tx_fifo_syncfifo_din; +assign tx_fifo_wrport_we = (tx_fifo_syncfifo_we & (tx_fifo_syncfifo_writable | tx_fifo_replace)); +assign tx_fifo_do_read = (tx_fifo_syncfifo_readable & tx_fifo_syncfifo_re); +assign tx_fifo_rdport_adr = tx_fifo_consume; +assign tx_fifo_syncfifo_dout = tx_fifo_rdport_dat_r; +assign tx_fifo_rdport_re = tx_fifo_do_read; +assign tx_fifo_syncfifo_writable = (tx_fifo_level0 != 5'd16); +assign tx_fifo_syncfifo_readable = (tx_fifo_level0 != 1'd0); +assign rx_fifo_syncfifo_din = {rx_fifo_fifo_in_last, rx_fifo_fifo_in_first, rx_fifo_fifo_in_payload_data}; +assign {rx_fifo_fifo_out_last, rx_fifo_fifo_out_first, rx_fifo_fifo_out_payload_data} = rx_fifo_syncfifo_dout; +assign rx_fifo_sink_ready = rx_fifo_syncfifo_writable; +assign rx_fifo_syncfifo_we = rx_fifo_sink_valid; +assign rx_fifo_fifo_in_first = rx_fifo_sink_first; +assign rx_fifo_fifo_in_last = rx_fifo_sink_last; +assign rx_fifo_fifo_in_payload_data = rx_fifo_sink_payload_data; +assign rx_fifo_source_valid = rx_fifo_readable; +assign rx_fifo_source_first = rx_fifo_fifo_out_first; +assign rx_fifo_source_last = rx_fifo_fifo_out_last; +assign rx_fifo_source_payload_data = rx_fifo_fifo_out_payload_data; +assign rx_fifo_re = rx_fifo_source_ready; +assign rx_fifo_syncfifo_re = (rx_fifo_syncfifo_readable & ((~rx_fifo_readable) | rx_fifo_re)); +assign rx_fifo_level1 = (rx_fifo_level0 + rx_fifo_readable); +always @(*) begin + rx_fifo_wrport_adr <= 4'd0; + if (rx_fifo_replace) begin + rx_fifo_wrport_adr <= (rx_fifo_produce - 1'd1); + end else begin + rx_fifo_wrport_adr <= rx_fifo_produce; + end +end +assign rx_fifo_wrport_dat_w = rx_fifo_syncfifo_din; +assign rx_fifo_wrport_we = (rx_fifo_syncfifo_we & (rx_fifo_syncfifo_writable | rx_fifo_replace)); +assign rx_fifo_do_read = (rx_fifo_syncfifo_readable & rx_fifo_syncfifo_re); +assign rx_fifo_rdport_adr = rx_fifo_consume; +assign rx_fifo_syncfifo_dout = rx_fifo_rdport_dat_r; +assign rx_fifo_rdport_re = rx_fifo_do_read; +assign rx_fifo_syncfifo_writable = (rx_fifo_level0 != 5'd16); +assign rx_fifo_syncfifo_readable = (rx_fifo_level0 != 1'd0); +always @(*) begin + gpio0_pads_gpio0i <= 8'd0; + gpio0_pads_gpio0i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[0]; + gpio0_pads_gpio0i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[1]; + gpio0_pads_gpio0i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[2]; + gpio0_pads_gpio0i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[3]; + gpio0_pads_gpio0i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[4]; + gpio0_pads_gpio0i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[5]; + gpio0_pads_gpio0i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[6]; + gpio0_pads_gpio0i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[7]; +end +always @(*) begin + gpio1_pads_gpio1i <= 8'd0; + gpio1_pads_gpio1i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[8]; + gpio1_pads_gpio1i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[9]; + gpio1_pads_gpio1i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[10]; + gpio1_pads_gpio1i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[11]; + gpio1_pads_gpio1i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[12]; + gpio1_pads_gpio1i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[13]; + gpio1_pads_gpio1i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[14]; + gpio1_pads_gpio1i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[15]; +end +always @(*) begin + libresocsim_libresoc_constraintmanager_gpio_o <= 16'd0; + libresocsim_libresoc_constraintmanager_gpio_o[0] <= gpio0_pads_gpio0o[0]; + libresocsim_libresoc_constraintmanager_gpio_o[1] <= gpio0_pads_gpio0o[1]; + libresocsim_libresoc_constraintmanager_gpio_o[2] <= gpio0_pads_gpio0o[2]; + libresocsim_libresoc_constraintmanager_gpio_o[3] <= gpio0_pads_gpio0o[3]; + libresocsim_libresoc_constraintmanager_gpio_o[4] <= gpio0_pads_gpio0o[4]; + libresocsim_libresoc_constraintmanager_gpio_o[5] <= gpio0_pads_gpio0o[5]; + libresocsim_libresoc_constraintmanager_gpio_o[6] <= gpio0_pads_gpio0o[6]; + libresocsim_libresoc_constraintmanager_gpio_o[7] <= gpio0_pads_gpio0o[7]; + libresocsim_libresoc_constraintmanager_gpio_o[8] <= gpio1_pads_gpio1o[0]; + libresocsim_libresoc_constraintmanager_gpio_o[9] <= gpio1_pads_gpio1o[1]; + libresocsim_libresoc_constraintmanager_gpio_o[10] <= gpio1_pads_gpio1o[2]; + libresocsim_libresoc_constraintmanager_gpio_o[11] <= gpio1_pads_gpio1o[3]; + libresocsim_libresoc_constraintmanager_gpio_o[12] <= gpio1_pads_gpio1o[4]; + libresocsim_libresoc_constraintmanager_gpio_o[13] <= gpio1_pads_gpio1o[5]; + libresocsim_libresoc_constraintmanager_gpio_o[14] <= gpio1_pads_gpio1o[6]; + libresocsim_libresoc_constraintmanager_gpio_o[15] <= gpio1_pads_gpio1o[7]; +end +always @(*) begin + libresocsim_libresoc_constraintmanager_gpio_oe <= 16'd0; + libresocsim_libresoc_constraintmanager_gpio_oe[0] <= gpio0_pads_gpio0oe[0]; + libresocsim_libresoc_constraintmanager_gpio_oe[1] <= gpio0_pads_gpio0oe[1]; + libresocsim_libresoc_constraintmanager_gpio_oe[2] <= gpio0_pads_gpio0oe[2]; + libresocsim_libresoc_constraintmanager_gpio_oe[3] <= gpio0_pads_gpio0oe[3]; + libresocsim_libresoc_constraintmanager_gpio_oe[4] <= gpio0_pads_gpio0oe[4]; + libresocsim_libresoc_constraintmanager_gpio_oe[5] <= gpio0_pads_gpio0oe[5]; + libresocsim_libresoc_constraintmanager_gpio_oe[6] <= gpio0_pads_gpio0oe[6]; + libresocsim_libresoc_constraintmanager_gpio_oe[7] <= gpio0_pads_gpio0oe[7]; + libresocsim_libresoc_constraintmanager_gpio_oe[8] <= gpio1_pads_gpio1oe[0]; + libresocsim_libresoc_constraintmanager_gpio_oe[9] <= gpio1_pads_gpio1oe[1]; + libresocsim_libresoc_constraintmanager_gpio_oe[10] <= gpio1_pads_gpio1oe[2]; + libresocsim_libresoc_constraintmanager_gpio_oe[11] <= gpio1_pads_gpio1oe[3]; + libresocsim_libresoc_constraintmanager_gpio_oe[12] <= gpio1_pads_gpio1oe[4]; + libresocsim_libresoc_constraintmanager_gpio_oe[13] <= gpio1_pads_gpio1oe[5]; + libresocsim_libresoc_constraintmanager_gpio_oe[14] <= gpio1_pads_gpio1oe[6]; + libresocsim_libresoc_constraintmanager_gpio_oe[15] <= gpio1_pads_gpio1oe[7]; +end +assign libresocsim_libresoc_constraintmanager_i2c_scl = i2c_scl_1; +assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe; +assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0; +assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i; +always @(*) begin + libresocsim_next_state <= 2'd0; + libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= 8'd0; + libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd0; + libresocsim_libresocsim_adr_libresocsim_next_value1 <= 13'd0; + libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0; + libresocsim_libresocsim_wishbone_dat_r <= 32'd0; + libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0; + libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0; + libresocsim_libresocsim_wishbone_ack <= 1'd0; + libresocsim_next_state <= libresocsim_state; + case (libresocsim_state) + 1'd1: begin + libresocsim_libresocsim_adr_libresocsim_next_value1 <= 1'd0; + libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1; + libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0; + libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1; + libresocsim_next_state <= 2'd2; + end + 2'd2: begin + libresocsim_libresocsim_wishbone_ack <= 1'd1; + libresocsim_libresocsim_wishbone_dat_r <= libresocsim_libresocsim_dat_r; + libresocsim_next_state <= 1'd0; + end + default: begin + libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= libresocsim_libresocsim_wishbone_dat_w; + libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd1; + if ((libresocsim_libresocsim_wishbone_cyc & libresocsim_libresocsim_wishbone_stb)) begin + libresocsim_libresocsim_adr_libresocsim_next_value1 <= libresocsim_libresocsim_wishbone_adr; + libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1; + libresocsim_libresocsim_we_libresocsim_next_value2 <= (libresocsim_libresocsim_wishbone_we & (libresocsim_libresocsim_wishbone_sel != 1'd0)); + libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1; + libresocsim_next_state <= 1'd1; + end + end + endcase +end +assign libresocsim_shared_adr = rhs_array_muxed24; +assign libresocsim_shared_dat_w = rhs_array_muxed25; +assign libresocsim_shared_sel = rhs_array_muxed26; +assign libresocsim_shared_cyc = rhs_array_muxed27; +assign libresocsim_shared_stb = rhs_array_muxed28; +assign libresocsim_shared_we = rhs_array_muxed29; +assign libresocsim_shared_cti = rhs_array_muxed30; +assign libresocsim_shared_bte = rhs_array_muxed31; +assign libresocsim_interface0_converted_interface_dat_r = libresocsim_shared_dat_r; +assign libresocsim_interface1_converted_interface_dat_r = libresocsim_shared_dat_r; +assign libresocsim_libresoc_jtag_wb_dat_r = libresocsim_shared_dat_r; +assign libresocsim_interface0_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd0)); +assign libresocsim_interface1_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd1)); +assign libresocsim_libresoc_jtag_wb_ack = (libresocsim_shared_ack & (libresocsim_grant == 2'd2)); +assign libresocsim_interface0_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd0)); +assign libresocsim_interface1_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd1)); +assign libresocsim_libresoc_jtag_wb_err = (libresocsim_shared_err & (libresocsim_grant == 2'd2)); +assign libresocsim_request = {libresocsim_libresoc_jtag_wb_cyc, libresocsim_interface1_converted_interface_cyc, libresocsim_interface0_converted_interface_cyc}; +always @(*) begin + libresocsim_slave_sel <= 6'd0; + libresocsim_slave_sel[0] <= (libresocsim_shared_adr[29:7] == 1'd0); + libresocsim_slave_sel[1] <= (libresocsim_shared_adr[29:5] == 4'd14); + libresocsim_slave_sel[2] <= (libresocsim_shared_adr[29:3] == 27'd100665344); + libresocsim_slave_sel[3] <= (libresocsim_shared_adr[29:10] == 20'd786449); + libresocsim_slave_sel[4] <= (libresocsim_shared_adr[29:23] == 7'd72); + libresocsim_slave_sel[5] <= (libresocsim_shared_adr[29:13] == 17'd98304); +end +assign libresocsim_ram_bus_adr = libresocsim_shared_adr; +assign libresocsim_ram_bus_dat_w = libresocsim_shared_dat_w; +assign libresocsim_ram_bus_sel = libresocsim_shared_sel; +assign libresocsim_ram_bus_stb = libresocsim_shared_stb; +assign libresocsim_ram_bus_we = libresocsim_shared_we; +assign libresocsim_ram_bus_cti = libresocsim_shared_cti; +assign libresocsim_ram_bus_bte = libresocsim_shared_bte; +assign ram_bus_ram_bus_adr = libresocsim_shared_adr; +assign ram_bus_ram_bus_dat_w = libresocsim_shared_dat_w; +assign ram_bus_ram_bus_sel = libresocsim_shared_sel; +assign ram_bus_ram_bus_stb = libresocsim_shared_stb; +assign ram_bus_ram_bus_we = libresocsim_shared_we; +assign ram_bus_ram_bus_cti = libresocsim_shared_cti; +assign ram_bus_ram_bus_bte = libresocsim_shared_bte; +assign libresocsim_libresoc_xics_icp_adr = libresocsim_shared_adr; +assign libresocsim_libresoc_xics_icp_dat_w = libresocsim_shared_dat_w; +assign libresocsim_libresoc_xics_icp_sel = libresocsim_shared_sel; +assign libresocsim_libresoc_xics_icp_stb = libresocsim_shared_stb; +assign libresocsim_libresoc_xics_icp_we = libresocsim_shared_we; +assign libresocsim_libresoc_xics_icp_cti = libresocsim_shared_cti; +assign libresocsim_libresoc_xics_icp_bte = libresocsim_shared_bte; +assign libresocsim_libresoc_xics_ics_adr = libresocsim_shared_adr; +assign libresocsim_libresoc_xics_ics_dat_w = libresocsim_shared_dat_w; +assign libresocsim_libresoc_xics_ics_sel = libresocsim_shared_sel; +assign libresocsim_libresoc_xics_ics_stb = libresocsim_shared_stb; +assign libresocsim_libresoc_xics_ics_we = libresocsim_shared_we; +assign libresocsim_libresoc_xics_ics_cti = libresocsim_shared_cti; +assign libresocsim_libresoc_xics_ics_bte = libresocsim_shared_bte; +assign wb_sdram_adr = libresocsim_shared_adr; +assign wb_sdram_dat_w = libresocsim_shared_dat_w; +assign wb_sdram_sel = libresocsim_shared_sel; +assign wb_sdram_stb = libresocsim_shared_stb; +assign wb_sdram_we = libresocsim_shared_we; +assign wb_sdram_cti = libresocsim_shared_cti; +assign wb_sdram_bte = libresocsim_shared_bte; +assign libresocsim_libresocsim_wishbone_adr = libresocsim_shared_adr; +assign libresocsim_libresocsim_wishbone_dat_w = libresocsim_shared_dat_w; +assign libresocsim_libresocsim_wishbone_sel = libresocsim_shared_sel; +assign libresocsim_libresocsim_wishbone_stb = libresocsim_shared_stb; +assign libresocsim_libresocsim_wishbone_we = libresocsim_shared_we; +assign libresocsim_libresocsim_wishbone_cti = libresocsim_shared_cti; +assign libresocsim_libresocsim_wishbone_bte = libresocsim_shared_bte; +assign libresocsim_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[0]); +assign ram_bus_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[1]); +assign libresocsim_libresoc_xics_icp_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[2]); +assign libresocsim_libresoc_xics_ics_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[3]); +assign wb_sdram_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[4]); +assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[5]); +assign libresocsim_shared_err = (((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err); +assign libresocsim_wait = ((libresocsim_shared_stb & libresocsim_shared_cyc) & (~libresocsim_shared_ack)); +always @(*) begin + libresocsim_shared_ack <= 1'd0; + libresocsim_error <= 1'd0; + libresocsim_shared_dat_r <= 32'd0; + libresocsim_shared_ack <= (((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack); + libresocsim_shared_dat_r <= (((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & libresocsim_libresocsim_wishbone_dat_r)); + if (libresocsim_done) begin + libresocsim_shared_dat_r <= 32'd4294967295; + libresocsim_shared_ack <= 1'd1; + libresocsim_error <= 1'd1; + end +end +assign libresocsim_done = (libresocsim_count == 1'd0); +assign libresocsim_csrbank0_sel = (libresocsim_interface0_bank_bus_adr[12:9] == 1'd0); +assign libresocsim_csrbank0_reset0_r = libresocsim_interface0_bank_bus_dat_w[0]; +assign libresocsim_csrbank0_reset0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0)); +assign libresocsim_csrbank0_reset0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0)); +assign libresocsim_csrbank0_scratch3_r = libresocsim_interface0_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank0_scratch3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1)); +assign libresocsim_csrbank0_scratch3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1)); +assign libresocsim_csrbank0_scratch2_r = libresocsim_interface0_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank0_scratch2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2)); +assign libresocsim_csrbank0_scratch2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2)); +assign libresocsim_csrbank0_scratch1_r = libresocsim_interface0_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank0_scratch1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3)); +assign libresocsim_csrbank0_scratch1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3)); +assign libresocsim_csrbank0_scratch0_r = libresocsim_interface0_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank0_scratch0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4)); +assign libresocsim_csrbank0_scratch0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4)); +assign libresocsim_csrbank0_bus_errors3_r = libresocsim_interface0_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank0_bus_errors3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5)); +assign libresocsim_csrbank0_bus_errors3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5)); +assign libresocsim_csrbank0_bus_errors2_r = libresocsim_interface0_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank0_bus_errors2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6)); +assign libresocsim_csrbank0_bus_errors2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6)); +assign libresocsim_csrbank0_bus_errors1_r = libresocsim_interface0_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank0_bus_errors1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7)); +assign libresocsim_csrbank0_bus_errors1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7)); +assign libresocsim_csrbank0_bus_errors0_r = libresocsim_interface0_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank0_bus_errors0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8)); +assign libresocsim_csrbank0_bus_errors0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8)); +assign libresocsim_csrbank0_reset0_w = libresocsim_reset_storage; +assign libresocsim_csrbank0_scratch3_w = libresocsim_scratch_storage[31:24]; +assign libresocsim_csrbank0_scratch2_w = libresocsim_scratch_storage[23:16]; +assign libresocsim_csrbank0_scratch1_w = libresocsim_scratch_storage[15:8]; +assign libresocsim_csrbank0_scratch0_w = libresocsim_scratch_storage[7:0]; +assign libresocsim_csrbank0_bus_errors3_w = libresocsim_bus_errors_status[31:24]; +assign libresocsim_csrbank0_bus_errors2_w = libresocsim_bus_errors_status[23:16]; +assign libresocsim_csrbank0_bus_errors1_w = libresocsim_bus_errors_status[15:8]; +assign libresocsim_csrbank0_bus_errors0_w = libresocsim_bus_errors_status[7:0]; +assign libresocsim_bus_errors_we = libresocsim_csrbank0_bus_errors0_we; +assign libresocsim_csrbank1_sel = (libresocsim_interface1_bank_bus_adr[12:9] == 3'd6); +assign libresocsim_csrbank1_oe0_r = libresocsim_interface1_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank1_oe0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0)); +assign libresocsim_csrbank1_oe0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0)); +assign libresocsim_csrbank1_in_r = libresocsim_interface1_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank1_in_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1)); +assign libresocsim_csrbank1_in_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1)); +assign libresocsim_csrbank1_out0_r = libresocsim_interface1_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank1_out0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2)); +assign libresocsim_csrbank1_out0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2)); +assign libresocsim_csrbank1_oe0_w = gpio0_oe_storage[7:0]; +assign libresocsim_csrbank1_in_w = gpio0_status[7:0]; +assign gpio0_we = libresocsim_csrbank1_in_we; +assign libresocsim_csrbank1_out0_w = gpio0_out_storage[7:0]; +assign libresocsim_csrbank2_sel = (libresocsim_interface2_bank_bus_adr[12:9] == 3'd7); +assign libresocsim_csrbank2_oe0_r = libresocsim_interface2_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank2_oe0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0)); +assign libresocsim_csrbank2_oe0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0)); +assign libresocsim_csrbank2_in_r = libresocsim_interface2_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank2_in_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1)); +assign libresocsim_csrbank2_in_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1)); +assign libresocsim_csrbank2_out0_r = libresocsim_interface2_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank2_out0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2)); +assign libresocsim_csrbank2_out0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2)); +assign libresocsim_csrbank2_oe0_w = gpio1_oe_storage[7:0]; +assign libresocsim_csrbank2_in_w = gpio1_status[7:0]; +assign gpio1_we = libresocsim_csrbank2_in_we; +assign libresocsim_csrbank2_out0_w = gpio1_out_storage[7:0]; +assign libresocsim_csrbank3_sel = (libresocsim_interface3_bank_bus_adr[12:9] == 4'd8); +assign libresocsim_csrbank3_w0_r = libresocsim_interface3_bank_bus_dat_w[2:0]; +assign libresocsim_csrbank3_w0_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0)); +assign libresocsim_csrbank3_w0_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0)); +assign libresocsim_csrbank3_r_r = libresocsim_interface3_bank_bus_dat_w[0]; +assign libresocsim_csrbank3_r_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1)); +assign libresocsim_csrbank3_r_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1)); +assign i2c_scl_1 = i2c_storage[0]; +assign i2c_oe = i2c_storage[1]; +assign i2c_sda0 = i2c_storage[2]; +assign libresocsim_csrbank3_w0_w = i2c_storage[2:0]; +assign i2c_status = i2c_sda1; +assign libresocsim_csrbank3_r_w = i2c_status; +assign i2c_we = libresocsim_csrbank3_r_we; +assign libresocsim_csrbank4_sel = (libresocsim_interface4_bank_bus_adr[12:9] == 2'd3); +assign libresocsim_csrbank4_dfii_control0_r = libresocsim_interface4_bank_bus_dat_w[3:0]; +assign libresocsim_csrbank4_dfii_control0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0)); +assign libresocsim_csrbank4_dfii_control0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0)); +assign libresocsim_csrbank4_dfii_pi0_command0_r = libresocsim_interface4_bank_bus_dat_w[5:0]; +assign libresocsim_csrbank4_dfii_pi0_command0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1)); +assign libresocsim_csrbank4_dfii_pi0_command0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1)); +assign sdram_command_issue_r = libresocsim_interface4_bank_bus_dat_w[0]; +assign sdram_command_issue_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2)); +assign sdram_command_issue_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2)); +assign libresocsim_csrbank4_dfii_pi0_address1_r = libresocsim_interface4_bank_bus_dat_w[4:0]; +assign libresocsim_csrbank4_dfii_pi0_address1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3)); +assign libresocsim_csrbank4_dfii_pi0_address1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3)); +assign libresocsim_csrbank4_dfii_pi0_address0_r = libresocsim_interface4_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank4_dfii_pi0_address0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4)); +assign libresocsim_csrbank4_dfii_pi0_address0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4)); +assign libresocsim_csrbank4_dfii_pi0_baddress0_r = libresocsim_interface4_bank_bus_dat_w[1:0]; +assign libresocsim_csrbank4_dfii_pi0_baddress0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5)); +assign libresocsim_csrbank4_dfii_pi0_baddress0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5)); +assign libresocsim_csrbank4_dfii_pi0_wrdata1_r = libresocsim_interface4_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank4_dfii_pi0_wrdata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6)); +assign libresocsim_csrbank4_dfii_pi0_wrdata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6)); +assign libresocsim_csrbank4_dfii_pi0_wrdata0_r = libresocsim_interface4_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank4_dfii_pi0_wrdata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7)); +assign libresocsim_csrbank4_dfii_pi0_wrdata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7)); +assign libresocsim_csrbank4_dfii_pi0_rddata1_r = libresocsim_interface4_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank4_dfii_pi0_rddata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8)); +assign libresocsim_csrbank4_dfii_pi0_rddata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8)); +assign libresocsim_csrbank4_dfii_pi0_rddata0_r = libresocsim_interface4_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank4_dfii_pi0_rddata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9)); +assign libresocsim_csrbank4_dfii_pi0_rddata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9)); +assign sdram_sel = sdram_storage[0]; +assign sdram_cke_1 = sdram_storage[1]; +assign sdram_odt = sdram_storage[2]; +assign sdram_reset_n = sdram_storage[3]; +assign libresocsim_csrbank4_dfii_control0_w = sdram_storage[3:0]; +assign libresocsim_csrbank4_dfii_pi0_command0_w = sdram_command_storage[5:0]; +assign libresocsim_csrbank4_dfii_pi0_address1_w = sdram_address_storage[12:8]; +assign libresocsim_csrbank4_dfii_pi0_address0_w = sdram_address_storage[7:0]; +assign libresocsim_csrbank4_dfii_pi0_baddress0_w = sdram_baddress_storage[1:0]; +assign libresocsim_csrbank4_dfii_pi0_wrdata1_w = sdram_wrdata_storage[15:8]; +assign libresocsim_csrbank4_dfii_pi0_wrdata0_w = sdram_wrdata_storage[7:0]; +assign libresocsim_csrbank4_dfii_pi0_rddata1_w = sdram_status[15:8]; +assign libresocsim_csrbank4_dfii_pi0_rddata0_w = sdram_status[7:0]; +assign sdram_we = libresocsim_csrbank4_dfii_pi0_rddata0_we; +assign libresocsim_csrbank5_sel = (libresocsim_interface5_bank_bus_adr[12:9] == 2'd2); +assign libresocsim_csrbank5_load3_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_load3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0)); +assign libresocsim_csrbank5_load3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0)); +assign libresocsim_csrbank5_load2_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_load2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1)); +assign libresocsim_csrbank5_load2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1)); +assign libresocsim_csrbank5_load1_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_load1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2)); +assign libresocsim_csrbank5_load1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2)); +assign libresocsim_csrbank5_load0_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_load0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3)); +assign libresocsim_csrbank5_load0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3)); +assign libresocsim_csrbank5_reload3_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_reload3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4)); +assign libresocsim_csrbank5_reload3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4)); +assign libresocsim_csrbank5_reload2_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_reload2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5)); +assign libresocsim_csrbank5_reload2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5)); +assign libresocsim_csrbank5_reload1_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_reload1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6)); +assign libresocsim_csrbank5_reload1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6)); +assign libresocsim_csrbank5_reload0_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_reload0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7)); +assign libresocsim_csrbank5_reload0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7)); +assign libresocsim_csrbank5_en0_r = libresocsim_interface5_bank_bus_dat_w[0]; +assign libresocsim_csrbank5_en0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8)); +assign libresocsim_csrbank5_en0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8)); +assign libresocsim_csrbank5_update_value0_r = libresocsim_interface5_bank_bus_dat_w[0]; +assign libresocsim_csrbank5_update_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9)); +assign libresocsim_csrbank5_update_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9)); +assign libresocsim_csrbank5_value3_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_value3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10)); +assign libresocsim_csrbank5_value3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10)); +assign libresocsim_csrbank5_value2_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_value2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11)); +assign libresocsim_csrbank5_value2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11)); +assign libresocsim_csrbank5_value1_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_value1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12)); +assign libresocsim_csrbank5_value1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12)); +assign libresocsim_csrbank5_value0_r = libresocsim_interface5_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank5_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13)); +assign libresocsim_csrbank5_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13)); +assign libresocsim_eventmanager_status_r = libresocsim_interface5_bank_bus_dat_w[0]; +assign libresocsim_eventmanager_status_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14)); +assign libresocsim_eventmanager_status_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14)); +assign libresocsim_eventmanager_pending_r = libresocsim_interface5_bank_bus_dat_w[0]; +assign libresocsim_eventmanager_pending_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15)); +assign libresocsim_eventmanager_pending_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15)); +assign libresocsim_csrbank5_ev_enable0_r = libresocsim_interface5_bank_bus_dat_w[0]; +assign libresocsim_csrbank5_ev_enable0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16)); +assign libresocsim_csrbank5_ev_enable0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16)); +assign libresocsim_csrbank5_load3_w = libresocsim_load_storage[31:24]; +assign libresocsim_csrbank5_load2_w = libresocsim_load_storage[23:16]; +assign libresocsim_csrbank5_load1_w = libresocsim_load_storage[15:8]; +assign libresocsim_csrbank5_load0_w = libresocsim_load_storage[7:0]; +assign libresocsim_csrbank5_reload3_w = libresocsim_reload_storage[31:24]; +assign libresocsim_csrbank5_reload2_w = libresocsim_reload_storage[23:16]; +assign libresocsim_csrbank5_reload1_w = libresocsim_reload_storage[15:8]; +assign libresocsim_csrbank5_reload0_w = libresocsim_reload_storage[7:0]; +assign libresocsim_csrbank5_en0_w = libresocsim_en_storage; +assign libresocsim_csrbank5_update_value0_w = libresocsim_update_value_storage; +assign libresocsim_csrbank5_value3_w = libresocsim_value_status[31:24]; +assign libresocsim_csrbank5_value2_w = libresocsim_value_status[23:16]; +assign libresocsim_csrbank5_value1_w = libresocsim_value_status[15:8]; +assign libresocsim_csrbank5_value0_w = libresocsim_value_status[7:0]; +assign libresocsim_value_we = libresocsim_csrbank5_value0_we; +assign libresocsim_csrbank5_ev_enable0_w = libresocsim_eventmanager_storage; +assign libresocsim_csrbank6_sel = (libresocsim_interface6_bank_bus_adr[12:9] == 3'd5); +assign rxtx_r = libresocsim_interface6_bank_bus_dat_w[7:0]; +assign rxtx_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0)); +assign rxtx_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0)); +assign libresocsim_csrbank6_txfull_r = libresocsim_interface6_bank_bus_dat_w[0]; +assign libresocsim_csrbank6_txfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1)); +assign libresocsim_csrbank6_txfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1)); +assign libresocsim_csrbank6_rxempty_r = libresocsim_interface6_bank_bus_dat_w[0]; +assign libresocsim_csrbank6_rxempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2)); +assign libresocsim_csrbank6_rxempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2)); +assign eventmanager_status_r = libresocsim_interface6_bank_bus_dat_w[1:0]; +assign eventmanager_status_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3)); +assign eventmanager_status_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3)); +assign eventmanager_pending_r = libresocsim_interface6_bank_bus_dat_w[1:0]; +assign eventmanager_pending_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4)); +assign eventmanager_pending_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4)); +assign libresocsim_csrbank6_ev_enable0_r = libresocsim_interface6_bank_bus_dat_w[1:0]; +assign libresocsim_csrbank6_ev_enable0_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5)); +assign libresocsim_csrbank6_ev_enable0_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5)); +assign libresocsim_csrbank6_txempty_r = libresocsim_interface6_bank_bus_dat_w[0]; +assign libresocsim_csrbank6_txempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6)); +assign libresocsim_csrbank6_txempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6)); +assign libresocsim_csrbank6_rxfull_r = libresocsim_interface6_bank_bus_dat_w[0]; +assign libresocsim_csrbank6_rxfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7)); +assign libresocsim_csrbank6_rxfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7)); +assign libresocsim_csrbank6_txfull_w = txfull_status; +assign txfull_we = libresocsim_csrbank6_txfull_we; +assign libresocsim_csrbank6_rxempty_w = rxempty_status; +assign rxempty_we = libresocsim_csrbank6_rxempty_we; +assign libresocsim_csrbank6_ev_enable0_w = eventmanager_storage[1:0]; +assign libresocsim_csrbank6_txempty_w = txempty_status; +assign txempty_we = libresocsim_csrbank6_txempty_we; +assign libresocsim_csrbank6_rxfull_w = rxfull_status; +assign rxfull_we = libresocsim_csrbank6_rxfull_we; +assign libresocsim_csrbank7_sel = (libresocsim_interface7_bank_bus_adr[12:9] == 3'd4); +assign libresocsim_csrbank7_tuning_word3_r = libresocsim_interface7_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank7_tuning_word3_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0)); +assign libresocsim_csrbank7_tuning_word3_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0)); +assign libresocsim_csrbank7_tuning_word2_r = libresocsim_interface7_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank7_tuning_word2_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1)); +assign libresocsim_csrbank7_tuning_word2_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1)); +assign libresocsim_csrbank7_tuning_word1_r = libresocsim_interface7_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank7_tuning_word1_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2)); +assign libresocsim_csrbank7_tuning_word1_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2)); +assign libresocsim_csrbank7_tuning_word0_r = libresocsim_interface7_bank_bus_dat_w[7:0]; +assign libresocsim_csrbank7_tuning_word0_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3)); +assign libresocsim_csrbank7_tuning_word0_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3)); +assign libresocsim_csrbank7_tuning_word3_w = uart_phy_storage[31:24]; +assign libresocsim_csrbank7_tuning_word2_w = uart_phy_storage[23:16]; +assign libresocsim_csrbank7_tuning_word1_w = uart_phy_storage[15:8]; +assign libresocsim_csrbank7_tuning_word0_w = uart_phy_storage[7:0]; +assign libresocsim_csr_interconnect_adr = libresocsim_libresocsim_adr; +assign libresocsim_csr_interconnect_we = libresocsim_libresocsim_we; +assign libresocsim_csr_interconnect_dat_w = libresocsim_libresocsim_dat_w; +assign libresocsim_libresocsim_dat_r = libresocsim_csr_interconnect_dat_r; +assign libresocsim_interface0_bank_bus_adr = libresocsim_csr_interconnect_adr; +assign libresocsim_interface1_bank_bus_adr = libresocsim_csr_interconnect_adr; +assign libresocsim_interface2_bank_bus_adr = libresocsim_csr_interconnect_adr; +assign libresocsim_interface3_bank_bus_adr = libresocsim_csr_interconnect_adr; +assign libresocsim_interface4_bank_bus_adr = libresocsim_csr_interconnect_adr; +assign libresocsim_interface5_bank_bus_adr = libresocsim_csr_interconnect_adr; +assign libresocsim_interface6_bank_bus_adr = libresocsim_csr_interconnect_adr; +assign libresocsim_interface7_bank_bus_adr = libresocsim_csr_interconnect_adr; +assign libresocsim_interface0_bank_bus_we = libresocsim_csr_interconnect_we; +assign libresocsim_interface1_bank_bus_we = libresocsim_csr_interconnect_we; +assign libresocsim_interface2_bank_bus_we = libresocsim_csr_interconnect_we; +assign libresocsim_interface3_bank_bus_we = libresocsim_csr_interconnect_we; +assign libresocsim_interface4_bank_bus_we = libresocsim_csr_interconnect_we; +assign libresocsim_interface5_bank_bus_we = libresocsim_csr_interconnect_we; +assign libresocsim_interface6_bank_bus_we = libresocsim_csr_interconnect_we; +assign libresocsim_interface7_bank_bus_we = libresocsim_csr_interconnect_we; +assign libresocsim_interface0_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; +assign libresocsim_interface1_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; +assign libresocsim_interface2_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; +assign libresocsim_interface3_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; +assign libresocsim_interface4_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; +assign libresocsim_interface5_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; +assign libresocsim_interface6_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; +assign libresocsim_interface7_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; +assign libresocsim_csr_interconnect_dat_r = (((((((libresocsim_interface0_bank_bus_dat_r | libresocsim_interface1_bank_bus_dat_r) | libresocsim_interface2_bank_bus_dat_r) | libresocsim_interface3_bank_bus_dat_r) | libresocsim_interface4_bank_bus_dat_r) | libresocsim_interface5_bank_bus_dat_r) | libresocsim_interface6_bank_bus_dat_r) | libresocsim_interface7_bank_bus_dat_r); +always @(*) begin + rhs_array_muxed0 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[2]; + end + default: begin + rhs_array_muxed0 <= sdram_choose_cmd_valids[3]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 13'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= sdram_bankmachine2_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= sdram_bankmachine3_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 2'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= sdram_bankmachine2_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= sdram_bankmachine3_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= sdram_bankmachine2_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= sdram_bankmachine3_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= sdram_bankmachine2_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= sdram_bankmachine3_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= sdram_bankmachine2_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= sdram_bankmachine3_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= sdram_bankmachine2_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= sdram_bankmachine3_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= sdram_bankmachine2_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= sdram_bankmachine3_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (sdram_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= sdram_bankmachine2_cmd_payload_we; + end + default: begin + t_array_muxed2 <= sdram_bankmachine3_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= sdram_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= sdram_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= sdram_choose_req_valids[2]; + end + default: begin + rhs_array_muxed6 <= sdram_choose_req_valids[3]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 13'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= sdram_bankmachine2_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= sdram_bankmachine3_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 2'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= sdram_bankmachine2_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= sdram_bankmachine3_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= sdram_bankmachine2_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= sdram_bankmachine3_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= sdram_bankmachine2_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= sdram_bankmachine3_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= sdram_bankmachine2_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= sdram_bankmachine3_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= sdram_bankmachine2_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= sdram_bankmachine3_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= sdram_bankmachine2_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= sdram_bankmachine3_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (sdram_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= sdram_bankmachine2_cmd_payload_we; + end + default: begin + t_array_muxed5 <= sdram_bankmachine3_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 22'd0; + case (subfragments_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (subfragments_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (subfragments_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 22'd0; + case (subfragments_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (subfragments_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (subfragments_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 22'd0; + case (subfragments_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (subfragments_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (subfragments_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 22'd0; + case (subfragments_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (subfragments_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (subfragments_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed24 <= 30'd0; + case (libresocsim_grant) + 1'd0: begin + rhs_array_muxed24 <= libresocsim_interface0_converted_interface_adr; + end + 1'd1: begin + rhs_array_muxed24 <= libresocsim_interface1_converted_interface_adr; + end + default: begin + rhs_array_muxed24 <= libresocsim_libresoc_jtag_wb_adr; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 32'd0; + case (libresocsim_grant) + 1'd0: begin + rhs_array_muxed25 <= libresocsim_interface0_converted_interface_dat_w; + end + 1'd1: begin + rhs_array_muxed25 <= libresocsim_interface1_converted_interface_dat_w; + end + default: begin + rhs_array_muxed25 <= libresocsim_libresoc_jtag_wb_dat_w; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 4'd0; + case (libresocsim_grant) + 1'd0: begin + rhs_array_muxed26 <= libresocsim_interface0_converted_interface_sel; + end + 1'd1: begin + rhs_array_muxed26 <= libresocsim_interface1_converted_interface_sel; + end + default: begin + rhs_array_muxed26 <= libresocsim_libresoc_jtag_wb_sel; + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 1'd0; + case (libresocsim_grant) + 1'd0: begin + rhs_array_muxed27 <= libresocsim_interface0_converted_interface_cyc; + end + 1'd1: begin + rhs_array_muxed27 <= libresocsim_interface1_converted_interface_cyc; + end + default: begin + rhs_array_muxed27 <= libresocsim_libresoc_jtag_wb_cyc; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (libresocsim_grant) + 1'd0: begin + rhs_array_muxed28 <= libresocsim_interface0_converted_interface_stb; + end + 1'd1: begin + rhs_array_muxed28 <= libresocsim_interface1_converted_interface_stb; + end + default: begin + rhs_array_muxed28 <= libresocsim_libresoc_jtag_wb_stb; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (libresocsim_grant) + 1'd0: begin + rhs_array_muxed29 <= libresocsim_interface0_converted_interface_we; + end + 1'd1: begin + rhs_array_muxed29 <= libresocsim_interface1_converted_interface_we; + end + default: begin + rhs_array_muxed29 <= libresocsim_libresoc_jtag_wb_we; + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 3'd0; + case (libresocsim_grant) + 1'd0: begin + rhs_array_muxed30 <= libresocsim_interface0_converted_interface_cti; + end + 1'd1: begin + rhs_array_muxed30 <= libresocsim_interface1_converted_interface_cti; + end + default: begin + rhs_array_muxed30 <= libresocsim_libresoc_jtag_wb_cti; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 2'd0; + case (libresocsim_grant) + 1'd0: begin + rhs_array_muxed31 <= libresocsim_interface0_converted_interface_bte; + end + 1'd1: begin + rhs_array_muxed31 <= libresocsim_interface1_converted_interface_bte; + end + default: begin + rhs_array_muxed31 <= libresocsim_libresoc_jtag_wb_bte; + end + endcase +end +always @(*) begin + array_muxed0 <= 2'd0; + case (sdram_steerer_sel) + 1'd0: begin + array_muxed0 <= sdram_nop_ba[1:0]; + end + 1'd1: begin + array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0]; + end + 2'd2: begin + array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0]; + end + default: begin + array_muxed0 <= sdram_cmd_payload_ba[1:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 13'd0; + case (sdram_steerer_sel) + 1'd0: begin + array_muxed1 <= sdram_nop_a; + end + 1'd1: begin + array_muxed1 <= sdram_choose_req_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= sdram_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (sdram_steerer_sel) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (sdram_steerer_sel) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (sdram_steerer_sel) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (sdram_steerer_sel) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (sdram_steerer_sel) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); + end + endcase +end +assign sdrio_clk = sys_clk_1; +assign sdrio_clk_1 = sys_clk_1; +assign sdrio_clk_2 = sys_clk_1; +assign sdrio_clk_3 = sys_clk_1; +assign sdrio_clk_4 = sys_clk_1; +assign sdrio_clk_5 = sys_clk_1; +assign sdrio_clk_6 = sys_clk_1; +assign sdrio_clk_7 = sys_clk_1; +assign sdrio_clk_8 = sys_clk_1; +assign sdrio_clk_9 = sys_clk_1; +assign sdrio_clk_10 = sys_clk_1; +assign sdrio_clk_11 = sys_clk_1; +assign sdrio_clk_12 = sys_clk_1; +assign sdrio_clk_13 = sys_clk_1; +assign sdrio_clk_14 = sys_clk_1; +assign sdrio_clk_15 = sys_clk_1; +assign sdrio_clk_16 = sys_clk_1; +assign sdrio_clk_17 = sys_clk_1; +assign sdrio_clk_18 = sys_clk_1; +assign sdrio_clk_19 = sys_clk_1; +assign sdrio_clk_20 = sys_clk_1; +assign sdrio_clk_21 = sys_clk_1; +assign sdrio_clk_22 = sys_clk_1; +assign sdrio_clk_23 = sys_clk_1; +assign sdrio_clk_24 = sys_clk_1; +assign sdrio_clk_25 = sys_clk_1; +assign sdrio_clk_26 = sys_clk_1; +assign sdrio_clk_27 = sys_clk_1; +assign sdrio_clk_28 = sys_clk_1; +assign sdrio_clk_29 = sys_clk_1; +assign sdrio_clk_30 = sys_clk_1; +assign sdrio_clk_31 = sys_clk_1; +assign sdrio_clk_32 = sys_clk_1; +assign sdrio_clk_33 = sys_clk_1; +assign sdrio_clk_34 = sys_clk_1; +assign sdrio_clk_35 = sys_clk_1; +assign sdrio_clk_36 = sys_clk_1; +assign sdrio_clk_37 = sys_clk_1; +assign sdrio_clk_38 = sys_clk_1; +assign sdrio_clk_39 = sys_clk_1; +assign sdrio_clk_40 = sys_clk_1; +assign sdrio_clk_41 = sys_clk_1; +assign sdrio_clk_42 = sys_clk_1; +assign sdrio_clk_43 = sys_clk_1; +assign sdrio_clk_44 = sys_clk_1; +assign sdrio_clk_45 = sys_clk_1; +assign sdrio_clk_46 = sys_clk_1; +assign sdrio_clk_47 = sys_clk_1; +assign sdrio_clk_48 = sys_clk_1; +assign sdrio_clk_49 = sys_clk_1; +assign sdrio_clk_50 = sys_clk_1; +assign sdrio_clk_51 = sys_clk_1; +assign sdrio_clk_52 = sys_clk_1; +assign sdrio_clk_53 = sys_clk_1; +assign sdrio_clk_54 = sys_clk_1; +assign sdrio_clk_55 = sys_clk_1; +assign sdrio_clk_56 = sys_clk_1; +assign sdrio_clk_57 = sys_clk_1; +assign sdrio_clk_58 = sys_clk_1; +assign sdrio_clk_59 = sys_clk_1; +assign sdrio_clk_60 = sys_clk_1; +assign sdrio_clk_61 = sys_clk_1; +assign sdrio_clk_62 = sys_clk_1; +assign sdrio_clk_63 = sys_clk_1; +assign sdrio_clk_64 = sys_clk_1; +assign sdrio_clk_65 = sys_clk_1; +assign sdrio_clk_66 = sys_clk_1; +assign sdrio_clk_67 = sys_clk_1; +assign sdrio_clk_68 = sys_clk_1; +assign sdrio_clk_69 = sys_clk_1; +assign sdrio_clk_70 = sys_clk_1; +assign uart_phy_rx = regs1; +assign sdrio_clk_71 = sys_clk_1; +assign sdrio_clk_72 = sys_clk_1; +assign sdrio_clk_73 = sys_clk_1; +assign sdrio_clk_74 = sys_clk_1; +assign sdrio_clk_75 = sys_clk_1; +assign sdrio_clk_76 = sys_clk_1; +assign sdrio_clk_77 = sys_clk_1; +assign sdrio_clk_78 = sys_clk_1; +assign sdrio_clk_79 = sys_clk_1; +assign sdrio_clk_80 = sys_clk_1; +assign sdrio_clk_81 = sys_clk_1; +assign sdrio_clk_82 = sys_clk_1; +assign sdrio_clk_83 = sys_clk_1; +assign sdrio_clk_84 = sys_clk_1; +assign sdrio_clk_85 = sys_clk_1; +assign sdrio_clk_86 = sys_clk_1; +assign sdrio_clk_87 = sys_clk_1; +assign sdrio_clk_88 = sys_clk_1; +assign sdrio_clk_89 = sys_clk_1; +assign sdrio_clk_90 = sys_clk_1; +assign sdrio_clk_91 = sys_clk_1; +assign sdrio_clk_92 = sys_clk_1; +assign sdrio_clk_93 = sys_clk_1; +assign sdrio_clk_94 = sys_clk_1; +assign sdrio_clk_95 = sys_clk_1; +assign sdrio_clk_96 = sys_clk_1; +assign sdrio_clk_97 = sys_clk_1; +assign sdrio_clk_98 = sys_clk_1; +assign sdrio_clk_99 = sys_clk_1; +assign sdrio_clk_100 = sys_clk_1; +assign sdrio_clk_101 = sys_clk_1; +assign sdrio_clk_102 = sys_clk_1; +assign sdrio_clk_103 = sys_clk_1; +assign sdrio_clk_104 = sys_clk_1; +assign sdrio_clk_105 = sys_clk_1; +assign sdrio_clk_106 = sys_clk_1; +assign sdrio_clk_107 = sys_clk_1; +assign sdrio_clk_108 = sys_clk_1; +assign sdrio_clk_109 = sys_clk_1; +assign sdrio_clk_110 = sys_clk_1; +assign sdrio_clk_111 = sys_clk_1; +assign sdrio_clk_112 = sys_clk_1; +assign sdrio_clk_113 = sys_clk_1; +assign sdrio_clk_114 = sys_clk_1; +assign sdrio_clk_115 = sys_clk_1; +assign sdrio_clk_116 = sys_clk_1; +assign sdrio_clk_117 = sys_clk_1; +assign sdrio_clk_118 = sys_clk_1; + +always @(posedge por_clk) begin + int_rst <= sys_rst; +end + +always @(posedge sdrio_clk) begin + libresocsim_libresoc_constraintmanager_sdram_a[0] <= dfi_p0_address[0]; + libresocsim_libresoc_constraintmanager_sdram_a[1] <= dfi_p0_address[1]; + libresocsim_libresoc_constraintmanager_sdram_a[2] <= dfi_p0_address[2]; + libresocsim_libresoc_constraintmanager_sdram_a[3] <= dfi_p0_address[3]; + libresocsim_libresoc_constraintmanager_sdram_a[4] <= dfi_p0_address[4]; + libresocsim_libresoc_constraintmanager_sdram_a[5] <= dfi_p0_address[5]; + libresocsim_libresoc_constraintmanager_sdram_a[6] <= dfi_p0_address[6]; + libresocsim_libresoc_constraintmanager_sdram_a[7] <= dfi_p0_address[7]; + libresocsim_libresoc_constraintmanager_sdram_a[8] <= dfi_p0_address[8]; + libresocsim_libresoc_constraintmanager_sdram_a[9] <= dfi_p0_address[9]; + libresocsim_libresoc_constraintmanager_sdram_a[10] <= dfi_p0_address[10]; + libresocsim_libresoc_constraintmanager_sdram_a[11] <= dfi_p0_address[11]; + libresocsim_libresoc_constraintmanager_sdram_a[12] <= dfi_p0_address[12]; + libresocsim_libresoc_constraintmanager_sdram_ba[0] <= dfi_p0_bank[0]; + libresocsim_libresoc_constraintmanager_sdram_ba[1] <= dfi_p0_bank[1]; + libresocsim_libresoc_constraintmanager_sdram_cas_n <= dfi_p0_cas_n; + libresocsim_libresoc_constraintmanager_sdram_ras_n <= dfi_p0_ras_n; + libresocsim_libresoc_constraintmanager_sdram_we_n <= dfi_p0_we_n; + libresocsim_libresoc_constraintmanager_sdram_cke <= dfi_p0_cke; + libresocsim_libresoc_constraintmanager_sdram_cs_n <= dfi_p0_cs_n; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[0] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[0] <= dfi_p0_wrdata[0]; + dfi_p0_rddata[0] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[0]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[1] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[1] <= dfi_p0_wrdata[1]; + dfi_p0_rddata[1] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[1]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[2] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[2] <= dfi_p0_wrdata[2]; + dfi_p0_rddata[2] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[2]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[3] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[3] <= dfi_p0_wrdata[3]; + dfi_p0_rddata[3] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[3]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[4] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[4] <= dfi_p0_wrdata[4]; + dfi_p0_rddata[4] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[4]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[5] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[5] <= dfi_p0_wrdata[5]; + dfi_p0_rddata[5] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[5]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[6] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[6] <= dfi_p0_wrdata[6]; + dfi_p0_rddata[6] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[6]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[7] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[7] <= dfi_p0_wrdata[7]; + dfi_p0_rddata[7] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[7]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[8] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[8] <= dfi_p0_wrdata[8]; + dfi_p0_rddata[8] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[8]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[9] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[9] <= dfi_p0_wrdata[9]; + dfi_p0_rddata[9] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[9]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[10] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[10] <= dfi_p0_wrdata[10]; + dfi_p0_rddata[10] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[10]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[11] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[11] <= dfi_p0_wrdata[11]; + dfi_p0_rddata[11] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[11]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[12] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[12] <= dfi_p0_wrdata[12]; + dfi_p0_rddata[12] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[12]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[13] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[13] <= dfi_p0_wrdata[13]; + dfi_p0_rddata[13] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[13]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[14] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[14] <= dfi_p0_wrdata[14]; + dfi_p0_rddata[14] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[14]; + libresocsim_libresoc_constraintmanager_sdram_dq_oe[15] <= dfi_p0_wrdata_en; + libresocsim_libresoc_constraintmanager_sdram_dq_o[15] <= dfi_p0_wrdata[15]; + dfi_p0_rddata[15] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[15]; + libresocsim_libresoc_constraintmanager_sdram_dm[0] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[0]); + libresocsim_libresoc_constraintmanager_sdram_dm[1] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[1]); + libresocsim_libresoc_constraintmanager_sdram_clock <= sys_clk_1; + gpio0_pads_gpio0oe[0] <= gpio0_oe_storage[0]; + gpio0_pads_gpio0o[0] <= gpio0_out_storage[0]; + gpio0_status[0] <= gpio0_pads_gpio0i[0]; + gpio0_pads_gpio0oe[1] <= gpio0_oe_storage[1]; + gpio0_pads_gpio0o[1] <= gpio0_out_storage[1]; + gpio0_status[1] <= gpio0_pads_gpio0i[1]; + gpio0_pads_gpio0oe[2] <= gpio0_oe_storage[2]; + gpio0_pads_gpio0o[2] <= gpio0_out_storage[2]; + gpio0_status[2] <= gpio0_pads_gpio0i[2]; + gpio0_pads_gpio0oe[3] <= gpio0_oe_storage[3]; + gpio0_pads_gpio0o[3] <= gpio0_out_storage[3]; + gpio0_status[3] <= gpio0_pads_gpio0i[3]; + gpio0_pads_gpio0oe[4] <= gpio0_oe_storage[4]; + gpio0_pads_gpio0o[4] <= gpio0_out_storage[4]; + gpio0_status[4] <= gpio0_pads_gpio0i[4]; + gpio0_pads_gpio0oe[5] <= gpio0_oe_storage[5]; + gpio0_pads_gpio0o[5] <= gpio0_out_storage[5]; + gpio0_status[5] <= gpio0_pads_gpio0i[5]; + gpio0_pads_gpio0oe[6] <= gpio0_oe_storage[6]; + gpio0_pads_gpio0o[6] <= gpio0_out_storage[6]; + gpio0_status[6] <= gpio0_pads_gpio0i[6]; + gpio0_pads_gpio0oe[7] <= gpio0_oe_storage[7]; + gpio0_pads_gpio0o[7] <= gpio0_out_storage[7]; + gpio0_status[7] <= gpio0_pads_gpio0i[7]; + gpio1_pads_gpio1oe[0] <= gpio1_oe_storage[0]; + gpio1_pads_gpio1o[0] <= gpio1_out_storage[0]; + gpio1_status[0] <= gpio1_pads_gpio1i[0]; + gpio1_pads_gpio1oe[1] <= gpio1_oe_storage[1]; + gpio1_pads_gpio1o[1] <= gpio1_out_storage[1]; + gpio1_status[1] <= gpio1_pads_gpio1i[1]; + gpio1_pads_gpio1oe[2] <= gpio1_oe_storage[2]; + gpio1_pads_gpio1o[2] <= gpio1_out_storage[2]; + gpio1_status[2] <= gpio1_pads_gpio1i[2]; + gpio1_pads_gpio1oe[3] <= gpio1_oe_storage[3]; + gpio1_pads_gpio1o[3] <= gpio1_out_storage[3]; + gpio1_status[3] <= gpio1_pads_gpio1i[3]; + gpio1_pads_gpio1oe[4] <= gpio1_oe_storage[4]; + gpio1_pads_gpio1o[4] <= gpio1_out_storage[4]; + gpio1_status[4] <= gpio1_pads_gpio1i[4]; + gpio1_pads_gpio1oe[5] <= gpio1_oe_storage[5]; + gpio1_pads_gpio1o[5] <= gpio1_out_storage[5]; + gpio1_status[5] <= gpio1_pads_gpio1i[5]; + gpio1_pads_gpio1oe[6] <= gpio1_oe_storage[6]; + gpio1_pads_gpio1o[6] <= gpio1_out_storage[6]; + gpio1_status[6] <= gpio1_pads_gpio1i[6]; + gpio1_pads_gpio1oe[7] <= gpio1_oe_storage[7]; + gpio1_pads_gpio1o[7] <= gpio1_out_storage[7]; + gpio1_status[7] <= gpio1_pads_gpio1i[7]; +end + +always @(posedge sys_clk_1) begin + dummy[0] <= (nc_1[0] | libresocsim_libresoc_interrupt[0]); + dummy[1] <= (nc_1[1] | libresocsim_libresoc_interrupt[0]); + dummy[2] <= (nc_1[2] | libresocsim_libresoc_interrupt[0]); + dummy[3] <= (nc_1[3] | libresocsim_libresoc_interrupt[0]); + dummy[4] <= (nc_1[4] | libresocsim_libresoc_interrupt[0]); + dummy[5] <= (nc_1[5] | libresocsim_libresoc_interrupt[0]); + dummy[6] <= (nc_1[6] | libresocsim_libresoc_interrupt[0]); + dummy[7] <= (nc_1[7] | libresocsim_libresoc_interrupt[0]); + dummy[8] <= (nc_1[8] | libresocsim_libresoc_interrupt[0]); + dummy[9] <= (nc_1[9] | libresocsim_libresoc_interrupt[0]); + dummy[10] <= (nc_1[10] | libresocsim_libresoc_interrupt[0]); + dummy[11] <= (nc_1[11] | libresocsim_libresoc_interrupt[0]); + dummy[12] <= (nc_1[12] | libresocsim_libresoc_interrupt[0]); + dummy[13] <= (nc_1[13] | libresocsim_libresoc_interrupt[0]); + dummy[14] <= (nc_1[14] | libresocsim_libresoc_interrupt[0]); + dummy[15] <= (nc_1[15] | libresocsim_libresoc_interrupt[0]); + dummy[16] <= (nc_1[16] | libresocsim_libresoc_interrupt[0]); + dummy[17] <= (nc_1[17] | libresocsim_libresoc_interrupt[0]); + dummy[18] <= (nc_1[18] | libresocsim_libresoc_interrupt[0]); + dummy[19] <= (nc_1[19] | libresocsim_libresoc_interrupt[0]); + dummy[20] <= (nc_1[20] | libresocsim_libresoc_interrupt[0]); + dummy[21] <= (nc_1[21] | libresocsim_libresoc_interrupt[0]); + dummy[22] <= (nc_1[22] | libresocsim_libresoc_interrupt[0]); + dummy[23] <= (nc_1[23] | libresocsim_libresoc_interrupt[0]); + dummy[24] <= (nc_1[24] | libresocsim_libresoc_interrupt[0]); + dummy[25] <= (nc_1[25] | libresocsim_libresoc_interrupt[0]); + dummy[26] <= (nc_1[26] | libresocsim_libresoc_interrupt[0]); + dummy[27] <= (nc_1[27] | libresocsim_libresoc_interrupt[0]); + dummy[28] <= (nc_1[28] | libresocsim_libresoc_interrupt[0]); + dummy[29] <= (nc_1[29] | libresocsim_libresoc_interrupt[0]); + dummy[30] <= (nc_1[30] | libresocsim_libresoc_interrupt[0]); + dummy[31] <= (nc_1[31] | libresocsim_libresoc_interrupt[0]); + dummy[32] <= (nc_1[32] | libresocsim_libresoc_interrupt[0]); + dummy[33] <= (nc_1[33] | libresocsim_libresoc_interrupt[0]); + dummy[34] <= (nc_1[34] | libresocsim_libresoc_interrupt[0]); + dummy[35] <= (nc_1[35] | libresocsim_libresoc_interrupt[0]); + dummy[36] <= (nc_1[36] | libresocsim_libresoc_interrupt[0]); + dummy[37] <= (nc_1[37] | libresocsim_libresoc_interrupt[0]); + dummy[38] <= (nc_1[38] | libresocsim_libresoc_interrupt[0]); + dummy[39] <= (nc_1[39] | libresocsim_libresoc_interrupt[0]); + if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin + libresocsim_converter0_dat_r <= libresocsim_libresoc_ibus_dat_r; + end + subfragments_converter0_state <= subfragments_converter0_next_state; + if (libresocsim_converter0_counter_subfragments_converter0_next_value_ce) begin + libresocsim_converter0_counter <= libresocsim_converter0_counter_subfragments_converter0_next_value; + end + if (libresocsim_converter0_reset) begin + libresocsim_converter0_counter <= 1'd0; + subfragments_converter0_state <= 1'd0; + end + if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin + libresocsim_converter1_dat_r <= libresocsim_libresoc_dbus_dat_r; + end + subfragments_converter1_state <= subfragments_converter1_next_state; + if (libresocsim_converter1_counter_subfragments_converter1_next_value_ce) begin + libresocsim_converter1_counter <= libresocsim_converter1_counter_subfragments_converter1_next_value; + end + if (libresocsim_converter1_reset) begin + libresocsim_converter1_counter <= 1'd0; + subfragments_converter1_state <= 1'd0; + end + if ((libresocsim_bus_errors != 32'd4294967295)) begin + if (libresocsim_bus_error) begin + libresocsim_bus_errors <= (libresocsim_bus_errors + 1'd1); + end + end + libresocsim_ram_bus_ack <= 1'd0; + if (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & (~libresocsim_ram_bus_ack))) begin + libresocsim_ram_bus_ack <= 1'd1; + end + if (libresocsim_en_storage) begin + if ((libresocsim_value == 1'd0)) begin + libresocsim_value <= libresocsim_reload_storage; + end else begin + libresocsim_value <= (libresocsim_value - 1'd1); + end + end else begin + libresocsim_value <= libresocsim_load_storage; + end + if (libresocsim_update_value_re) begin + libresocsim_value_status <= libresocsim_value; + end + if (libresocsim_zero_clear) begin + libresocsim_zero_pending <= 1'd0; + end + libresocsim_zero_old_trigger <= libresocsim_zero_trigger; + if (((~libresocsim_zero_trigger) & libresocsim_zero_old_trigger)) begin + libresocsim_zero_pending <= 1'd1; + end + ram_bus_ram_bus_ack <= 1'd0; + if (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & (~ram_bus_ram_bus_ack))) begin + ram_bus_ram_bus_ack <= 1'd1; + end + rddata_en <= {rddata_en, dfi_p0_rddata_en}; + dfi_p0_rddata_valid <= rddata_en[2]; + if (sdram_inti_p0_rddata_valid) begin + sdram_status <= sdram_inti_p0_rddata; + end + if ((sdram_timer_wait & (~sdram_timer_done0))) begin + sdram_timer_count1 <= (sdram_timer_count1 - 1'd1); + end else begin + sdram_timer_count1 <= 10'd781; + end + sdram_postponer_req_o <= 1'd0; + if (sdram_postponer_req_i) begin + sdram_postponer_count <= (sdram_postponer_count - 1'd1); + if ((sdram_postponer_count == 1'd0)) begin + sdram_postponer_count <= 1'd0; + sdram_postponer_req_o <= 1'd1; + end + end + if (sdram_sequencer_start0) begin + sdram_sequencer_count <= 1'd0; + end else begin + if (sdram_sequencer_done1) begin + if ((sdram_sequencer_count != 1'd0)) begin + sdram_sequencer_count <= (sdram_sequencer_count - 1'd1); + end + end + end + sdram_cmd_payload_a <= 1'd0; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd0; + sdram_cmd_payload_we <= 1'd0; + sdram_sequencer_done1 <= 1'd0; + if ((sdram_sequencer_start1 & (sdram_sequencer_counter == 1'd0))) begin + sdram_cmd_payload_a <= 11'd1024; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd1; + sdram_cmd_payload_we <= 1'd1; + end + if ((sdram_sequencer_counter == 2'd2)) begin + sdram_cmd_payload_a <= 1'd0; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd1; + sdram_cmd_payload_ras <= 1'd1; + sdram_cmd_payload_we <= 1'd0; + end + if ((sdram_sequencer_counter == 4'd8)) begin + sdram_cmd_payload_a <= 1'd0; + sdram_cmd_payload_ba <= 1'd0; + sdram_cmd_payload_cas <= 1'd0; + sdram_cmd_payload_ras <= 1'd0; + sdram_cmd_payload_we <= 1'd0; + sdram_sequencer_done1 <= 1'd1; + end + if ((sdram_sequencer_counter == 4'd8)) begin + sdram_sequencer_counter <= 1'd0; + end else begin + if ((sdram_sequencer_counter != 1'd0)) begin + sdram_sequencer_counter <= (sdram_sequencer_counter + 1'd1); + end else begin + if (sdram_sequencer_start1) begin + sdram_sequencer_counter <= 1'd1; + end + end + end + subfragments_refresher_state <= subfragments_refresher_next_state; + if (sdram_bankmachine0_row_close) begin + sdram_bankmachine0_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine0_row_open) begin + sdram_bankmachine0_row_opened <= 1'd1; + sdram_bankmachine0_row <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]; + end + end + if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine0_cmd_buffer_lookahead_produce <= (sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine0_cmd_buffer_lookahead_consume <= (sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready)) begin + sdram_bankmachine0_cmd_buffer_source_valid <= sdram_bankmachine0_cmd_buffer_sink_valid; + sdram_bankmachine0_cmd_buffer_source_first <= sdram_bankmachine0_cmd_buffer_sink_first; + sdram_bankmachine0_cmd_buffer_source_last <= sdram_bankmachine0_cmd_buffer_sink_last; + sdram_bankmachine0_cmd_buffer_source_payload_we <= sdram_bankmachine0_cmd_buffer_sink_payload_we; + sdram_bankmachine0_cmd_buffer_source_payload_addr <= sdram_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine0_twtpcon_valid) begin + sdram_bankmachine0_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine0_twtpcon_ready)) begin + sdram_bankmachine0_twtpcon_count <= (sdram_bankmachine0_twtpcon_count - 1'd1); + if ((sdram_bankmachine0_twtpcon_count == 1'd1)) begin + sdram_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + subfragments_bankmachine0_state <= subfragments_bankmachine0_next_state; + if (sdram_bankmachine1_row_close) begin + sdram_bankmachine1_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine1_row_open) begin + sdram_bankmachine1_row_opened <= 1'd1; + sdram_bankmachine1_row <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]; + end + end + if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine1_cmd_buffer_lookahead_produce <= (sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine1_cmd_buffer_lookahead_consume <= (sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready)) begin + sdram_bankmachine1_cmd_buffer_source_valid <= sdram_bankmachine1_cmd_buffer_sink_valid; + sdram_bankmachine1_cmd_buffer_source_first <= sdram_bankmachine1_cmd_buffer_sink_first; + sdram_bankmachine1_cmd_buffer_source_last <= sdram_bankmachine1_cmd_buffer_sink_last; + sdram_bankmachine1_cmd_buffer_source_payload_we <= sdram_bankmachine1_cmd_buffer_sink_payload_we; + sdram_bankmachine1_cmd_buffer_source_payload_addr <= sdram_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine1_twtpcon_valid) begin + sdram_bankmachine1_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine1_twtpcon_ready)) begin + sdram_bankmachine1_twtpcon_count <= (sdram_bankmachine1_twtpcon_count - 1'd1); + if ((sdram_bankmachine1_twtpcon_count == 1'd1)) begin + sdram_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + subfragments_bankmachine1_state <= subfragments_bankmachine1_next_state; + if (sdram_bankmachine2_row_close) begin + sdram_bankmachine2_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine2_row_open) begin + sdram_bankmachine2_row_opened <= 1'd1; + sdram_bankmachine2_row <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]; + end + end + if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine2_cmd_buffer_lookahead_produce <= (sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine2_cmd_buffer_lookahead_consume <= (sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready)) begin + sdram_bankmachine2_cmd_buffer_source_valid <= sdram_bankmachine2_cmd_buffer_sink_valid; + sdram_bankmachine2_cmd_buffer_source_first <= sdram_bankmachine2_cmd_buffer_sink_first; + sdram_bankmachine2_cmd_buffer_source_last <= sdram_bankmachine2_cmd_buffer_sink_last; + sdram_bankmachine2_cmd_buffer_source_payload_we <= sdram_bankmachine2_cmd_buffer_sink_payload_we; + sdram_bankmachine2_cmd_buffer_source_payload_addr <= sdram_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine2_twtpcon_valid) begin + sdram_bankmachine2_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine2_twtpcon_ready)) begin + sdram_bankmachine2_twtpcon_count <= (sdram_bankmachine2_twtpcon_count - 1'd1); + if ((sdram_bankmachine2_twtpcon_count == 1'd1)) begin + sdram_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + subfragments_bankmachine2_state <= subfragments_bankmachine2_next_state; + if (sdram_bankmachine3_row_close) begin + sdram_bankmachine3_row_opened <= 1'd0; + end else begin + if (sdram_bankmachine3_row_open) begin + sdram_bankmachine3_row_opened <= 1'd1; + sdram_bankmachine3_row <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]; + end + end + if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + sdram_bankmachine3_cmd_buffer_lookahead_produce <= (sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine3_cmd_buffer_lookahead_consume <= (sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin + sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready)) begin + sdram_bankmachine3_cmd_buffer_source_valid <= sdram_bankmachine3_cmd_buffer_sink_valid; + sdram_bankmachine3_cmd_buffer_source_first <= sdram_bankmachine3_cmd_buffer_sink_first; + sdram_bankmachine3_cmd_buffer_source_last <= sdram_bankmachine3_cmd_buffer_sink_last; + sdram_bankmachine3_cmd_buffer_source_payload_we <= sdram_bankmachine3_cmd_buffer_sink_payload_we; + sdram_bankmachine3_cmd_buffer_source_payload_addr <= sdram_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (sdram_bankmachine3_twtpcon_valid) begin + sdram_bankmachine3_twtpcon_count <= 3'd4; + if (1'd0) begin + sdram_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + sdram_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~sdram_bankmachine3_twtpcon_ready)) begin + sdram_bankmachine3_twtpcon_count <= (sdram_bankmachine3_twtpcon_count - 1'd1); + if ((sdram_bankmachine3_twtpcon_count == 1'd1)) begin + sdram_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + subfragments_bankmachine3_state <= subfragments_bankmachine3_next_state; + if ((~sdram_en0)) begin + sdram_time0 <= 5'd31; + end else begin + if ((~sdram_max_time0)) begin + sdram_time0 <= (sdram_time0 - 1'd1); + end + end + if ((~sdram_en1)) begin + sdram_time1 <= 4'd15; + end else begin + if ((~sdram_max_time1)) begin + sdram_time1 <= (sdram_time1 - 1'd1); + end + end + if (sdram_choose_cmd_ce) begin + case (sdram_choose_cmd_grant) + 1'd0: begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end else begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end else begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end + end + end + end + 1'd1: begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end else begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end else begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end + end + end + end + 2'd2: begin + if (sdram_choose_cmd_request[3]) begin + sdram_choose_cmd_grant <= 2'd3; + end else begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end else begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end + end + end + end + 2'd3: begin + if (sdram_choose_cmd_request[0]) begin + sdram_choose_cmd_grant <= 1'd0; + end else begin + if (sdram_choose_cmd_request[1]) begin + sdram_choose_cmd_grant <= 1'd1; + end else begin + if (sdram_choose_cmd_request[2]) begin + sdram_choose_cmd_grant <= 2'd2; + end + end + end + end + endcase + end + if (sdram_choose_req_ce) begin + case (sdram_choose_req_grant) + 1'd0: begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end else begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end else begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end + end + end + end + 1'd1: begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end else begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end else begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end + end + end + end + 2'd2: begin + if (sdram_choose_req_request[3]) begin + sdram_choose_req_grant <= 2'd3; + end else begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end else begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end + end + end + end + 2'd3: begin + if (sdram_choose_req_request[0]) begin + sdram_choose_req_grant <= 1'd0; + end else begin + if (sdram_choose_req_request[1]) begin + sdram_choose_req_grant <= 1'd1; + end else begin + if (sdram_choose_req_request[2]) begin + sdram_choose_req_grant <= 2'd2; + end + end + end + end + endcase + end + sdram_dfi_p0_cs_n <= 1'd0; + sdram_dfi_p0_bank <= array_muxed0; + sdram_dfi_p0_address <= array_muxed1; + sdram_dfi_p0_cas_n <= (~array_muxed2); + sdram_dfi_p0_ras_n <= (~array_muxed3); + sdram_dfi_p0_we_n <= (~array_muxed4); + sdram_dfi_p0_rddata_en <= array_muxed5; + sdram_dfi_p0_wrdata_en <= array_muxed6; + if (sdram_tccdcon_valid) begin + sdram_tccdcon_count <= 1'd0; + if (1'd1) begin + sdram_tccdcon_ready <= 1'd1; + end else begin + sdram_tccdcon_ready <= 1'd0; + end + end else begin + if ((~sdram_tccdcon_ready)) begin + sdram_tccdcon_count <= (sdram_tccdcon_count - 1'd1); + if ((sdram_tccdcon_count == 1'd1)) begin + sdram_tccdcon_ready <= 1'd1; + end + end + end + if (sdram_twtrcon_valid) begin + sdram_twtrcon_count <= 3'd4; + if (1'd0) begin + sdram_twtrcon_ready <= 1'd1; + end else begin + sdram_twtrcon_ready <= 1'd0; + end + end else begin + if ((~sdram_twtrcon_ready)) begin + sdram_twtrcon_count <= (sdram_twtrcon_count - 1'd1); + if ((sdram_twtrcon_count == 1'd1)) begin + sdram_twtrcon_ready <= 1'd1; + end + end + end + subfragments_multiplexer_state <= subfragments_multiplexer_next_state; + subfragments_new_master_wdata_ready <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_wdata_ready)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_wdata_ready)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_wdata_ready)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_wdata_ready)); + subfragments_new_master_rdata_valid0 <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_rdata_valid)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_rdata_valid)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_rdata_valid)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_rdata_valid)); + subfragments_new_master_rdata_valid1 <= subfragments_new_master_rdata_valid0; + subfragments_new_master_rdata_valid2 <= subfragments_new_master_rdata_valid1; + subfragments_new_master_rdata_valid3 <= subfragments_new_master_rdata_valid2; + if ((litedram_wb_ack | converter_skip)) begin + converter_dat_r <= wb_sdram_dat_r; + end + subfragments_state <= subfragments_next_state; + if (converter_counter_subfragments_next_value_ce) begin + converter_counter <= converter_counter_subfragments_next_value; + end + if (converter_reset) begin + converter_counter <= 1'd0; + subfragments_state <= 1'd0; + end + if (litedram_wb_ack) begin + cmd_consumed <= 1'd0; + wdata_consumed <= 1'd0; + end else begin + if ((port_cmd_valid & port_cmd_ready)) begin + cmd_consumed <= 1'd1; + end + if ((port_wdata_valid & port_wdata_ready)) begin + wdata_consumed <= 1'd1; + end + end + uart_phy_sink_ready <= 1'd0; + if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin + uart_phy_tx_reg <= uart_phy_sink_payload_data; + uart_phy_tx_bitcount <= 1'd0; + uart_phy_tx_busy <= 1'd1; + libresocsim_libresoc_constraintmanager_uart_tx <= 1'd0; + end else begin + if ((uart_phy_uart_clk_txen & uart_phy_tx_busy)) begin + uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1); + if ((uart_phy_tx_bitcount == 4'd8)) begin + libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1; + end else begin + if ((uart_phy_tx_bitcount == 4'd9)) begin + libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1; + uart_phy_tx_busy <= 1'd0; + uart_phy_sink_ready <= 1'd1; + end else begin + libresocsim_libresoc_constraintmanager_uart_tx <= uart_phy_tx_reg[0]; + uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]}; + end + end + end + end + if (uart_phy_tx_busy) begin + {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= (uart_phy_phase_accumulator_tx + uart_phy_storage); + end else begin + {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= uart_phy_storage; + end + uart_phy_source_valid <= 1'd0; + uart_phy_rx_r <= uart_phy_rx; + if ((~uart_phy_rx_busy)) begin + if (((~uart_phy_rx) & uart_phy_rx_r)) begin + uart_phy_rx_busy <= 1'd1; + uart_phy_rx_bitcount <= 1'd0; + end + end else begin + if (uart_phy_uart_clk_rxen) begin + uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1); + if ((uart_phy_rx_bitcount == 1'd0)) begin + if (uart_phy_rx) begin + uart_phy_rx_busy <= 1'd0; + end + end else begin + if ((uart_phy_rx_bitcount == 4'd9)) begin + uart_phy_rx_busy <= 1'd0; + if (uart_phy_rx) begin + uart_phy_source_payload_data <= uart_phy_rx_reg; + uart_phy_source_valid <= 1'd1; + end + end else begin + uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]}; + end + end + end + end + if (uart_phy_rx_busy) begin + {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= (uart_phy_phase_accumulator_rx + uart_phy_storage); + end else begin + {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= 32'd2147483648; + end + if (tx_clear) begin + tx_pending <= 1'd0; + end + tx_old_trigger <= tx_trigger; + if (((~tx_trigger) & tx_old_trigger)) begin + tx_pending <= 1'd1; + end + if (rx_clear) begin + rx_pending <= 1'd0; + end + rx_old_trigger <= rx_trigger; + if (((~rx_trigger) & rx_old_trigger)) begin + rx_pending <= 1'd1; + end + if (tx_fifo_syncfifo_re) begin + tx_fifo_readable <= 1'd1; + end else begin + if (tx_fifo_re) begin + tx_fifo_readable <= 1'd0; + end + end + if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin + tx_fifo_produce <= (tx_fifo_produce + 1'd1); + end + if (tx_fifo_do_read) begin + tx_fifo_consume <= (tx_fifo_consume + 1'd1); + end + if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin + if ((~tx_fifo_do_read)) begin + tx_fifo_level0 <= (tx_fifo_level0 + 1'd1); + end + end else begin + if (tx_fifo_do_read) begin + tx_fifo_level0 <= (tx_fifo_level0 - 1'd1); + end + end + if (rx_fifo_syncfifo_re) begin + rx_fifo_readable <= 1'd1; + end else begin + if (rx_fifo_re) begin + rx_fifo_readable <= 1'd0; + end + end + if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin + rx_fifo_produce <= (rx_fifo_produce + 1'd1); + end + if (rx_fifo_do_read) begin + rx_fifo_consume <= (rx_fifo_consume + 1'd1); + end + if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin + if ((~rx_fifo_do_read)) begin + rx_fifo_level0 <= (rx_fifo_level0 + 1'd1); + end + end else begin + if (rx_fifo_do_read) begin + rx_fifo_level0 <= (rx_fifo_level0 - 1'd1); + end + end + if (reset) begin + tx_pending <= 1'd0; + tx_old_trigger <= 1'd0; + rx_pending <= 1'd0; + rx_old_trigger <= 1'd0; + tx_fifo_readable <= 1'd0; + tx_fifo_level0 <= 5'd0; + tx_fifo_produce <= 4'd0; + tx_fifo_consume <= 4'd0; + rx_fifo_readable <= 1'd0; + rx_fifo_level0 <= 5'd0; + rx_fifo_produce <= 4'd0; + rx_fifo_consume <= 4'd0; + end + libresocsim_state <= libresocsim_next_state; + if (libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0) begin + libresocsim_libresocsim_dat_w <= libresocsim_libresocsim_dat_w_libresocsim_next_value0; + end + if (libresocsim_libresocsim_adr_libresocsim_next_value_ce1) begin + libresocsim_libresocsim_adr <= libresocsim_libresocsim_adr_libresocsim_next_value1; + end + if (libresocsim_libresocsim_we_libresocsim_next_value_ce2) begin + libresocsim_libresocsim_we <= libresocsim_libresocsim_we_libresocsim_next_value2; + end + case (libresocsim_grant) + 1'd0: begin + if ((~libresocsim_request[0])) begin + if (libresocsim_request[1]) begin + libresocsim_grant <= 1'd1; + end else begin + if (libresocsim_request[2]) begin + libresocsim_grant <= 2'd2; + end + end + end + end + 1'd1: begin + if ((~libresocsim_request[1])) begin + if (libresocsim_request[2]) begin + libresocsim_grant <= 2'd2; + end else begin + if (libresocsim_request[0]) begin + libresocsim_grant <= 1'd0; + end + end + end + end + 2'd2: begin + if ((~libresocsim_request[2])) begin + if (libresocsim_request[0]) begin + libresocsim_grant <= 1'd0; + end else begin + if (libresocsim_request[1]) begin + libresocsim_grant <= 1'd1; + end + end + end + end + endcase + libresocsim_slave_sel_r <= libresocsim_slave_sel; + if (libresocsim_wait) begin + if ((~libresocsim_done)) begin + libresocsim_count <= (libresocsim_count - 1'd1); + end + end else begin + libresocsim_count <= 20'd1000000; + end + libresocsim_interface0_bank_bus_dat_r <= 1'd0; + if (libresocsim_csrbank0_sel) begin + case (libresocsim_interface0_bank_bus_adr[3:0]) + 1'd0: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_reset0_w; + end + 1'd1: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch3_w; + end + 2'd2: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch2_w; + end + 2'd3: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch1_w; + end + 3'd4: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch0_w; + end + 3'd5: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors3_w; + end + 3'd6: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors2_w; + end + 3'd7: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors1_w; + end + 4'd8: begin + libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors0_w; + end + endcase + end + if (libresocsim_csrbank0_reset0_re) begin + libresocsim_reset_storage <= libresocsim_csrbank0_reset0_r; + end + libresocsim_reset_re <= libresocsim_csrbank0_reset0_re; + if (libresocsim_csrbank0_scratch3_re) begin + libresocsim_scratch_storage[31:24] <= libresocsim_csrbank0_scratch3_r; + end + if (libresocsim_csrbank0_scratch2_re) begin + libresocsim_scratch_storage[23:16] <= libresocsim_csrbank0_scratch2_r; + end + if (libresocsim_csrbank0_scratch1_re) begin + libresocsim_scratch_storage[15:8] <= libresocsim_csrbank0_scratch1_r; + end + if (libresocsim_csrbank0_scratch0_re) begin + libresocsim_scratch_storage[7:0] <= libresocsim_csrbank0_scratch0_r; + end + libresocsim_scratch_re <= libresocsim_csrbank0_scratch0_re; + libresocsim_interface1_bank_bus_dat_r <= 1'd0; + if (libresocsim_csrbank1_sel) begin + case (libresocsim_interface1_bank_bus_adr[1:0]) + 1'd0: begin + libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_oe0_w; + end + 1'd1: begin + libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_in_w; + end + 2'd2: begin + libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_out0_w; + end + endcase + end + if (libresocsim_csrbank1_oe0_re) begin + gpio0_oe_storage[7:0] <= libresocsim_csrbank1_oe0_r; + end + gpio0_oe_re <= libresocsim_csrbank1_oe0_re; + if (libresocsim_csrbank1_out0_re) begin + gpio0_out_storage[7:0] <= libresocsim_csrbank1_out0_r; + end + gpio0_out_re <= libresocsim_csrbank1_out0_re; + libresocsim_interface2_bank_bus_dat_r <= 1'd0; + if (libresocsim_csrbank2_sel) begin + case (libresocsim_interface2_bank_bus_adr[1:0]) + 1'd0: begin + libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_oe0_w; + end + 1'd1: begin + libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_in_w; + end + 2'd2: begin + libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_out0_w; + end + endcase + end + if (libresocsim_csrbank2_oe0_re) begin + gpio1_oe_storage[7:0] <= libresocsim_csrbank2_oe0_r; + end + gpio1_oe_re <= libresocsim_csrbank2_oe0_re; + if (libresocsim_csrbank2_out0_re) begin + gpio1_out_storage[7:0] <= libresocsim_csrbank2_out0_r; + end + gpio1_out_re <= libresocsim_csrbank2_out0_re; + libresocsim_interface3_bank_bus_dat_r <= 1'd0; + if (libresocsim_csrbank3_sel) begin + case (libresocsim_interface3_bank_bus_adr[0]) + 1'd0: begin + libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_w0_w; + end + 1'd1: begin + libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_r_w; + end + endcase + end + if (libresocsim_csrbank3_w0_re) begin + i2c_storage[2:0] <= libresocsim_csrbank3_w0_r; + end + i2c_re <= libresocsim_csrbank3_w0_re; + libresocsim_interface4_bank_bus_dat_r <= 1'd0; + if (libresocsim_csrbank4_sel) begin + case (libresocsim_interface4_bank_bus_adr[3:0]) + 1'd0: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_control0_w; + end + 1'd1: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_command0_w; + end + 2'd2: begin + libresocsim_interface4_bank_bus_dat_r <= sdram_command_issue_w; + end + 2'd3: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address1_w; + end + 3'd4: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address0_w; + end + 3'd5: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_baddress0_w; + end + 3'd6: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata1_w; + end + 3'd7: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata0_w; + end + 4'd8: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata1_w; + end + 4'd9: begin + libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata0_w; + end + endcase + end + if (libresocsim_csrbank4_dfii_control0_re) begin + sdram_storage[3:0] <= libresocsim_csrbank4_dfii_control0_r; + end + sdram_re <= libresocsim_csrbank4_dfii_control0_re; + if (libresocsim_csrbank4_dfii_pi0_command0_re) begin + sdram_command_storage[5:0] <= libresocsim_csrbank4_dfii_pi0_command0_r; + end + sdram_command_re <= libresocsim_csrbank4_dfii_pi0_command0_re; + if (libresocsim_csrbank4_dfii_pi0_address1_re) begin + sdram_address_storage[12:8] <= libresocsim_csrbank4_dfii_pi0_address1_r; + end + if (libresocsim_csrbank4_dfii_pi0_address0_re) begin + sdram_address_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_address0_r; + end + sdram_address_re <= libresocsim_csrbank4_dfii_pi0_address0_re; + if (libresocsim_csrbank4_dfii_pi0_baddress0_re) begin + sdram_baddress_storage[1:0] <= libresocsim_csrbank4_dfii_pi0_baddress0_r; + end + sdram_baddress_re <= libresocsim_csrbank4_dfii_pi0_baddress0_re; + if (libresocsim_csrbank4_dfii_pi0_wrdata1_re) begin + sdram_wrdata_storage[15:8] <= libresocsim_csrbank4_dfii_pi0_wrdata1_r; + end + if (libresocsim_csrbank4_dfii_pi0_wrdata0_re) begin + sdram_wrdata_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_wrdata0_r; + end + sdram_wrdata_re <= libresocsim_csrbank4_dfii_pi0_wrdata0_re; + libresocsim_interface5_bank_bus_dat_r <= 1'd0; + if (libresocsim_csrbank5_sel) begin + case (libresocsim_interface5_bank_bus_adr[4:0]) + 1'd0: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load3_w; + end + 1'd1: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load2_w; + end + 2'd2: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load1_w; + end + 2'd3: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load0_w; + end + 3'd4: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload3_w; + end + 3'd5: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload2_w; + end + 3'd6: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload1_w; + end + 3'd7: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload0_w; + end + 4'd8: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_en0_w; + end + 4'd9: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_update_value0_w; + end + 4'd10: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value3_w; + end + 4'd11: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value2_w; + end + 4'd12: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value1_w; + end + 4'd13: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value0_w; + end + 4'd14: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_status_w; + end + 4'd15: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_pending_w; + end + 5'd16: begin + libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_ev_enable0_w; + end + endcase + end + if (libresocsim_csrbank5_load3_re) begin + libresocsim_load_storage[31:24] <= libresocsim_csrbank5_load3_r; + end + if (libresocsim_csrbank5_load2_re) begin + libresocsim_load_storage[23:16] <= libresocsim_csrbank5_load2_r; + end + if (libresocsim_csrbank5_load1_re) begin + libresocsim_load_storage[15:8] <= libresocsim_csrbank5_load1_r; + end + if (libresocsim_csrbank5_load0_re) begin + libresocsim_load_storage[7:0] <= libresocsim_csrbank5_load0_r; + end + libresocsim_load_re <= libresocsim_csrbank5_load0_re; + if (libresocsim_csrbank5_reload3_re) begin + libresocsim_reload_storage[31:24] <= libresocsim_csrbank5_reload3_r; + end + if (libresocsim_csrbank5_reload2_re) begin + libresocsim_reload_storage[23:16] <= libresocsim_csrbank5_reload2_r; + end + if (libresocsim_csrbank5_reload1_re) begin + libresocsim_reload_storage[15:8] <= libresocsim_csrbank5_reload1_r; + end + if (libresocsim_csrbank5_reload0_re) begin + libresocsim_reload_storage[7:0] <= libresocsim_csrbank5_reload0_r; + end + libresocsim_reload_re <= libresocsim_csrbank5_reload0_re; + if (libresocsim_csrbank5_en0_re) begin + libresocsim_en_storage <= libresocsim_csrbank5_en0_r; + end + libresocsim_en_re <= libresocsim_csrbank5_en0_re; + if (libresocsim_csrbank5_update_value0_re) begin + libresocsim_update_value_storage <= libresocsim_csrbank5_update_value0_r; + end + libresocsim_update_value_re <= libresocsim_csrbank5_update_value0_re; + if (libresocsim_csrbank5_ev_enable0_re) begin + libresocsim_eventmanager_storage <= libresocsim_csrbank5_ev_enable0_r; + end + libresocsim_eventmanager_re <= libresocsim_csrbank5_ev_enable0_re; + libresocsim_interface6_bank_bus_dat_r <= 1'd0; + if (libresocsim_csrbank6_sel) begin + case (libresocsim_interface6_bank_bus_adr[2:0]) + 1'd0: begin + libresocsim_interface6_bank_bus_dat_r <= rxtx_w; + end + 1'd1: begin + libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txfull_w; + end + 2'd2: begin + libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxempty_w; + end + 2'd3: begin + libresocsim_interface6_bank_bus_dat_r <= eventmanager_status_w; + end + 3'd4: begin + libresocsim_interface6_bank_bus_dat_r <= eventmanager_pending_w; + end + 3'd5: begin + libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_ev_enable0_w; + end + 3'd6: begin + libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txempty_w; + end + 3'd7: begin + libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxfull_w; + end + endcase + end + if (libresocsim_csrbank6_ev_enable0_re) begin + eventmanager_storage[1:0] <= libresocsim_csrbank6_ev_enable0_r; + end + eventmanager_re <= libresocsim_csrbank6_ev_enable0_re; + libresocsim_interface7_bank_bus_dat_r <= 1'd0; + if (libresocsim_csrbank7_sel) begin + case (libresocsim_interface7_bank_bus_adr[1:0]) + 1'd0: begin + libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word3_w; + end + 1'd1: begin + libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word2_w; + end + 2'd2: begin + libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word1_w; + end + 2'd3: begin + libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word0_w; + end + endcase + end + if (libresocsim_csrbank7_tuning_word3_re) begin + uart_phy_storage[31:24] <= libresocsim_csrbank7_tuning_word3_r; + end + if (libresocsim_csrbank7_tuning_word2_re) begin + uart_phy_storage[23:16] <= libresocsim_csrbank7_tuning_word2_r; + end + if (libresocsim_csrbank7_tuning_word1_re) begin + uart_phy_storage[15:8] <= libresocsim_csrbank7_tuning_word1_r; + end + if (libresocsim_csrbank7_tuning_word0_re) begin + uart_phy_storage[7:0] <= libresocsim_csrbank7_tuning_word0_r; + end + uart_phy_re <= libresocsim_csrbank7_tuning_word0_re; + if (sys_rst_1) begin + libresocsim_reset_storage <= 1'd0; + libresocsim_reset_re <= 1'd0; + libresocsim_scratch_storage <= 32'd305419896; + libresocsim_scratch_re <= 1'd0; + libresocsim_bus_errors <= 32'd0; + libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1; + libresocsim_converter0_counter <= 1'd0; + libresocsim_converter1_counter <= 1'd0; + libresocsim_ram_bus_ack <= 1'd0; + libresocsim_load_storage <= 32'd0; + libresocsim_load_re <= 1'd0; + libresocsim_reload_storage <= 32'd0; + libresocsim_reload_re <= 1'd0; + libresocsim_en_storage <= 1'd0; + libresocsim_en_re <= 1'd0; + libresocsim_update_value_storage <= 1'd0; + libresocsim_update_value_re <= 1'd0; + libresocsim_value_status <= 32'd0; + libresocsim_zero_pending <= 1'd0; + libresocsim_zero_old_trigger <= 1'd0; + libresocsim_eventmanager_storage <= 1'd0; + libresocsim_eventmanager_re <= 1'd0; + libresocsim_value <= 32'd0; + ram_bus_ram_bus_ack <= 1'd0; + dfi_p0_rddata_valid <= 1'd0; + rddata_en <= 3'd0; + sdram_storage <= 4'd1; + sdram_re <= 1'd0; + sdram_command_storage <= 6'd0; + sdram_command_re <= 1'd0; + sdram_address_re <= 1'd0; + sdram_baddress_re <= 1'd0; + sdram_wrdata_re <= 1'd0; + sdram_status <= 16'd0; + sdram_dfi_p0_address <= 13'd0; + sdram_dfi_p0_bank <= 2'd0; + sdram_dfi_p0_cas_n <= 1'd1; + sdram_dfi_p0_cs_n <= 1'd1; + sdram_dfi_p0_ras_n <= 1'd1; + sdram_dfi_p0_we_n <= 1'd1; + sdram_dfi_p0_wrdata_en <= 1'd0; + sdram_dfi_p0_rddata_en <= 1'd0; + sdram_timer_count1 <= 10'd781; + sdram_postponer_req_o <= 1'd0; + sdram_postponer_count <= 1'd0; + sdram_sequencer_done1 <= 1'd0; + sdram_sequencer_counter <= 4'd0; + sdram_sequencer_count <= 1'd0; + sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine0_row <= 13'd0; + sdram_bankmachine0_row_opened <= 1'd0; + sdram_bankmachine0_twtpcon_ready <= 1'd0; + sdram_bankmachine0_twtpcon_count <= 3'd0; + sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine1_row <= 13'd0; + sdram_bankmachine1_row_opened <= 1'd0; + sdram_bankmachine1_twtpcon_ready <= 1'd0; + sdram_bankmachine1_twtpcon_count <= 3'd0; + sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine2_row <= 13'd0; + sdram_bankmachine2_row_opened <= 1'd0; + sdram_bankmachine2_twtpcon_ready <= 1'd0; + sdram_bankmachine2_twtpcon_count <= 3'd0; + sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0; + sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0; + sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0; + sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; + sdram_bankmachine3_row <= 13'd0; + sdram_bankmachine3_row_opened <= 1'd0; + sdram_bankmachine3_twtpcon_ready <= 1'd0; + sdram_bankmachine3_twtpcon_count <= 3'd0; + sdram_choose_cmd_grant <= 2'd0; + sdram_choose_req_grant <= 2'd0; + sdram_tccdcon_ready <= 1'd0; + sdram_tccdcon_count <= 1'd0; + sdram_twtrcon_ready <= 1'd0; + sdram_twtrcon_count <= 3'd0; + sdram_time0 <= 5'd0; + sdram_time1 <= 4'd0; + converter_counter <= 1'd0; + cmd_consumed <= 1'd0; + wdata_consumed <= 1'd0; + uart_phy_storage <= 32'd9895604; + uart_phy_re <= 1'd0; + uart_phy_sink_ready <= 1'd0; + uart_phy_uart_clk_txen <= 1'd0; + uart_phy_tx_busy <= 1'd0; + uart_phy_source_valid <= 1'd0; + uart_phy_uart_clk_rxen <= 1'd0; + uart_phy_rx_r <= 1'd0; + uart_phy_rx_busy <= 1'd0; + tx_pending <= 1'd0; + tx_old_trigger <= 1'd0; + rx_pending <= 1'd0; + rx_old_trigger <= 1'd0; + eventmanager_storage <= 2'd0; + eventmanager_re <= 1'd0; + tx_fifo_readable <= 1'd0; + tx_fifo_level0 <= 5'd0; + tx_fifo_produce <= 4'd0; + tx_fifo_consume <= 4'd0; + rx_fifo_readable <= 1'd0; + rx_fifo_level0 <= 5'd0; + rx_fifo_produce <= 4'd0; + rx_fifo_consume <= 4'd0; + gpio0_oe_storage <= 8'd0; + gpio0_oe_re <= 1'd0; + gpio0_out_storage <= 8'd0; + gpio0_out_re <= 1'd0; + gpio1_oe_storage <= 8'd0; + gpio1_oe_re <= 1'd0; + gpio1_out_storage <= 8'd0; + gpio1_out_re <= 1'd0; + dummy <= 40'd0; + i2c_storage <= 3'd0; + i2c_re <= 1'd0; + subfragments_converter0_state <= 1'd0; + subfragments_converter1_state <= 1'd0; + subfragments_refresher_state <= 2'd0; + subfragments_bankmachine0_state <= 3'd0; + subfragments_bankmachine1_state <= 3'd0; + subfragments_bankmachine2_state <= 3'd0; + subfragments_bankmachine3_state <= 3'd0; + subfragments_multiplexer_state <= 3'd0; + subfragments_new_master_wdata_ready <= 1'd0; + subfragments_new_master_rdata_valid0 <= 1'd0; + subfragments_new_master_rdata_valid1 <= 1'd0; + subfragments_new_master_rdata_valid2 <= 1'd0; + subfragments_new_master_rdata_valid3 <= 1'd0; + subfragments_state <= 1'd0; + libresocsim_libresocsim_we <= 1'd0; + libresocsim_grant <= 2'd0; + libresocsim_slave_sel_r <= 6'd0; + libresocsim_count <= 20'd1000000; + libresocsim_state <= 2'd0; + end + regs0 <= libresocsim_libresoc_constraintmanager_uart_rx; + regs1 <= regs0; +end + +reg [31:0] mem[0:127]; +reg [6:0] memadr; +always @(posedge sys_clk_1) begin + if (libresocsim_we[0]) + mem[libresocsim_adr][7:0] <= libresocsim_dat_w[7:0]; + if (libresocsim_we[1]) + mem[libresocsim_adr][15:8] <= libresocsim_dat_w[15:8]; + if (libresocsim_we[2]) + mem[libresocsim_adr][23:16] <= libresocsim_dat_w[23:16]; + if (libresocsim_we[3]) + mem[libresocsim_adr][31:24] <= libresocsim_dat_w[31:24]; + memadr <= libresocsim_adr; +end + +assign libresocsim_dat_r = mem[memadr]; + +initial begin + $readmemh("mem.init", mem); +end + +reg [31:0] mem_1[0:31]; +reg [4:0] memadr_1; +always @(posedge sys_clk_1) begin + if (ram_we[0]) + mem_1[ram_adr][7:0] <= ram_dat_w[7:0]; + if (ram_we[1]) + mem_1[ram_adr][15:8] <= ram_dat_w[15:8]; + if (ram_we[2]) + mem_1[ram_adr][23:16] <= ram_dat_w[23:16]; + if (ram_we[3]) + mem_1[ram_adr][31:24] <= ram_dat_w[31:24]; + memadr_1 <= ram_adr; +end + +assign ram_dat_r = mem_1[memadr_1]; + +initial begin + $readmemh("mem_1.init", mem_1); +end + +reg [24:0] storage[0:7]; +reg [24:0] memdat; +always @(posedge sys_clk_1) begin + if (sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk_1) begin +end + +assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_1[0:7]; +reg [24:0] memdat_1; +always @(posedge sys_clk_1) begin + if (sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk_1) begin +end + +assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_2[0:7]; +reg [24:0] memdat_2; +always @(posedge sys_clk_1) begin + if (sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk_1) begin +end + +assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_3[0:7]; +reg [24:0] memdat_3; +always @(posedge sys_clk_1) begin + if (sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk_1) begin +end + +assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [9:0] storage_4[0:15]; +reg [9:0] memdat_4; +reg [9:0] memdat_5; +always @(posedge sys_clk_1) begin + if (tx_fifo_wrport_we) + storage_4[tx_fifo_wrport_adr] <= tx_fifo_wrport_dat_w; + memdat_4 <= storage_4[tx_fifo_wrport_adr]; +end + +always @(posedge sys_clk_1) begin + if (tx_fifo_rdport_re) + memdat_5 <= storage_4[tx_fifo_rdport_adr]; +end + +assign tx_fifo_wrport_dat_r = memdat_4; +assign tx_fifo_rdport_dat_r = memdat_5; + +reg [9:0] storage_5[0:15]; +reg [9:0] memdat_6; +reg [9:0] memdat_7; +always @(posedge sys_clk_1) begin + if (rx_fifo_wrport_we) + storage_5[rx_fifo_wrport_adr] <= rx_fifo_wrport_dat_w; + memdat_6 <= storage_5[rx_fifo_wrport_adr]; +end + +always @(posedge sys_clk_1) begin + if (rx_fifo_rdport_re) + memdat_7 <= storage_5[rx_fifo_rdport_adr]; +end + +assign rx_fifo_wrport_dat_r = memdat_6; +assign rx_fifo_rdport_dat_r = memdat_7; + +test_issuer test_issuer( + .TAP_bus__tck(libresocsim_libresoc_jtag_tck), + .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi), + .TAP_bus__tms(libresocsim_libresoc_jtag_tms), + .clk(sys_clk_1), + .core_bigendian_i(1'd0), + .dbus__ack(libresocsim_libresoc_dbus_ack), + .dbus__bte(1'd0), + .dbus__cti(1'd0), + .dbus__dat_r(libresocsim_libresoc_dbus_dat_r), + .dbus__err(libresocsim_libresoc_dbus_err), + .eint_0__pad__i(eint_0), + .eint_1__pad__i(eint_1), + .eint_2__pad__i(eint_2), + .gpio_e10__core__o(libresocsim_libresoc_constraintmanager_gpio_o[10]), + .gpio_e10__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[10]), + .gpio_e10__pad__i(gpio_i[10]), + .gpio_e11__core__o(libresocsim_libresoc_constraintmanager_gpio_o[11]), + .gpio_e11__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[11]), + .gpio_e11__pad__i(gpio_i[11]), + .gpio_e12__core__o(libresocsim_libresoc_constraintmanager_gpio_o[12]), + .gpio_e12__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[12]), + .gpio_e12__pad__i(gpio_i[12]), + .gpio_e13__core__o(libresocsim_libresoc_constraintmanager_gpio_o[13]), + .gpio_e13__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[13]), + .gpio_e13__pad__i(gpio_i[13]), + .gpio_e14__core__o(libresocsim_libresoc_constraintmanager_gpio_o[14]), + .gpio_e14__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[14]), + .gpio_e14__pad__i(gpio_i[14]), + .gpio_e15__core__o(libresocsim_libresoc_constraintmanager_gpio_o[15]), + .gpio_e15__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[15]), + .gpio_e15__pad__i(gpio_i[15]), + .gpio_e8__core__o(libresocsim_libresoc_constraintmanager_gpio_o[8]), + .gpio_e8__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[8]), + .gpio_e8__pad__i(gpio_i[8]), + .gpio_e9__core__o(libresocsim_libresoc_constraintmanager_gpio_o[9]), + .gpio_e9__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[9]), + .gpio_e9__pad__i(gpio_i[9]), + .gpio_s0__core__o(libresocsim_libresoc_constraintmanager_gpio_o[0]), + .gpio_s0__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[0]), + .gpio_s0__pad__i(gpio_i[0]), + .gpio_s1__core__o(libresocsim_libresoc_constraintmanager_gpio_o[1]), + .gpio_s1__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[1]), + .gpio_s1__pad__i(gpio_i[1]), + .gpio_s2__core__o(libresocsim_libresoc_constraintmanager_gpio_o[2]), + .gpio_s2__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[2]), + .gpio_s2__pad__i(gpio_i[2]), + .gpio_s3__core__o(libresocsim_libresoc_constraintmanager_gpio_o[3]), + .gpio_s3__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[3]), + .gpio_s3__pad__i(gpio_i[3]), + .gpio_s4__core__o(libresocsim_libresoc_constraintmanager_gpio_o[4]), + .gpio_s4__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[4]), + .gpio_s4__pad__i(gpio_i[4]), + .gpio_s5__core__o(libresocsim_libresoc_constraintmanager_gpio_o[5]), + .gpio_s5__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[5]), + .gpio_s5__pad__i(gpio_i[5]), + .gpio_s6__core__o(libresocsim_libresoc_constraintmanager_gpio_o[6]), + .gpio_s6__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[6]), + .gpio_s6__pad__i(gpio_i[6]), + .gpio_s7__core__o(libresocsim_libresoc_constraintmanager_gpio_o[7]), + .gpio_s7__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[7]), + .gpio_s7__pad__i(gpio_i[7]), + .ibus__ack(libresocsim_libresoc_ibus_ack), + .ibus__bte(1'd0), + .ibus__cti(1'd0), + .ibus__dat_r(libresocsim_libresoc_ibus_dat_r), + .ibus__err(libresocsim_libresoc_ibus_err), + .icp_wb__adr(libresocsim_libresoc_xics_icp_adr), + .icp_wb__cyc(libresocsim_libresoc_xics_icp_cyc), + .icp_wb__dat_w(libresocsim_libresoc_xics_icp_dat_w), + .icp_wb__sel(libresocsim_libresoc_xics_icp_sel), + .icp_wb__stb(libresocsim_libresoc_xics_icp_stb), + .icp_wb__we(libresocsim_libresoc_xics_icp_we), + .ics_wb__adr(libresocsim_libresoc_xics_ics_adr), + .ics_wb__cyc(libresocsim_libresoc_xics_ics_cyc), + .ics_wb__dat_w(libresocsim_libresoc_xics_ics_dat_w), + .ics_wb__sel(libresocsim_libresoc_xics_ics_sel), + .ics_wb__stb(libresocsim_libresoc_xics_ics_stb), + .ics_wb__we(libresocsim_libresoc_xics_ics_we), + .int_level_i(libresocsim_libresoc_interrupt), + .jtag_wb__ack(libresocsim_libresoc_jtag_wb_ack), + .jtag_wb__dat_r(libresocsim_libresoc_jtag_wb_dat_r), + .jtag_wb__err(libresocsim_libresoc_jtag_wb_err), + .mspi0_clk__core__o(libresocsim_libresoc_constraintmanager_spimaster_clk), + .mspi0_cs_n__core__o(libresocsim_libresoc_constraintmanager_spimaster_cs_n), + .mspi0_miso__pad__i(spimaster_miso), + .mspi0_mosi__core__o(libresocsim_libresoc_constraintmanager_spimaster_mosi), + .mtwi_scl__core__o(libresocsim_libresoc_constraintmanager_i2c_scl), + .mtwi_sda__core__o(libresocsim_libresoc_constraintmanager_i2c_sda_o), + .mtwi_sda__core__oe(libresocsim_libresoc_constraintmanager_i2c_sda_oe), + .mtwi_sda__pad__i(i2c_sda_i), + .pc_i(libresocsim_libresoc0), + .pc_i_ok(1'd0), + .rst((sys_rst_1 | libresocsim_libresoc_reset)), + .sdr_a_0__core__o(libresocsim_libresoc_constraintmanager_sdram_a[0]), + .sdr_a_10__core__o(libresocsim_libresoc_constraintmanager_sdram_a[10]), + .sdr_a_11__core__o(libresocsim_libresoc_constraintmanager_sdram_a[11]), + .sdr_a_12__core__o(libresocsim_libresoc_constraintmanager_sdram_a[12]), + .sdr_a_1__core__o(libresocsim_libresoc_constraintmanager_sdram_a[1]), + .sdr_a_2__core__o(libresocsim_libresoc_constraintmanager_sdram_a[2]), + .sdr_a_3__core__o(libresocsim_libresoc_constraintmanager_sdram_a[3]), + .sdr_a_4__core__o(libresocsim_libresoc_constraintmanager_sdram_a[4]), + .sdr_a_5__core__o(libresocsim_libresoc_constraintmanager_sdram_a[5]), + .sdr_a_6__core__o(libresocsim_libresoc_constraintmanager_sdram_a[6]), + .sdr_a_7__core__o(libresocsim_libresoc_constraintmanager_sdram_a[7]), + .sdr_a_8__core__o(libresocsim_libresoc_constraintmanager_sdram_a[8]), + .sdr_a_9__core__o(libresocsim_libresoc_constraintmanager_sdram_a[9]), + .sdr_ba_0__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[0]), + .sdr_ba_1__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[1]), + .sdr_cas_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cas_n), + .sdr_cke__core__o(libresocsim_libresoc_constraintmanager_sdram_cke), + .sdr_clock__core__o(libresocsim_libresoc_constraintmanager_sdram_clock), + .sdr_cs_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cs_n), + .sdr_dm_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[0]), + .sdr_dm_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[1]), + .sdr_dq_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[0]), + .sdr_dq_0__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[0]), + .sdr_dq_0__pad__i(sdram_dq_i[0]), + .sdr_dq_10__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[10]), + .sdr_dq_10__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[10]), + .sdr_dq_10__pad__i(sdram_dq_i[10]), + .sdr_dq_11__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[11]), + .sdr_dq_11__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[11]), + .sdr_dq_11__pad__i(sdram_dq_i[11]), + .sdr_dq_12__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[12]), + .sdr_dq_12__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[12]), + .sdr_dq_12__pad__i(sdram_dq_i[12]), + .sdr_dq_13__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[13]), + .sdr_dq_13__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[13]), + .sdr_dq_13__pad__i(sdram_dq_i[13]), + .sdr_dq_14__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[14]), + .sdr_dq_14__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[14]), + .sdr_dq_14__pad__i(sdram_dq_i[14]), + .sdr_dq_15__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[15]), + .sdr_dq_15__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[15]), + .sdr_dq_15__pad__i(sdram_dq_i[15]), + .sdr_dq_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[1]), + .sdr_dq_1__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[1]), + .sdr_dq_1__pad__i(sdram_dq_i[1]), + .sdr_dq_2__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[2]), + .sdr_dq_2__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[2]), + .sdr_dq_2__pad__i(sdram_dq_i[2]), + .sdr_dq_3__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[3]), + .sdr_dq_3__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[3]), + .sdr_dq_3__pad__i(sdram_dq_i[3]), + .sdr_dq_4__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[4]), + .sdr_dq_4__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[4]), + .sdr_dq_4__pad__i(sdram_dq_i[4]), + .sdr_dq_5__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[5]), + .sdr_dq_5__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[5]), + .sdr_dq_5__pad__i(sdram_dq_i[5]), + .sdr_dq_6__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[6]), + .sdr_dq_6__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[6]), + .sdr_dq_6__pad__i(sdram_dq_i[6]), + .sdr_dq_7__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[7]), + .sdr_dq_7__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[7]), + .sdr_dq_7__pad__i(sdram_dq_i[7]), + .sdr_dq_8__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[8]), + .sdr_dq_8__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[8]), + .sdr_dq_8__pad__i(sdram_dq_i[8]), + .sdr_dq_9__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[9]), + .sdr_dq_9__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[9]), + .sdr_dq_9__pad__i(sdram_dq_i[9]), + .sdr_ras_n__core__o(libresocsim_libresoc_constraintmanager_sdram_ras_n), + .sdr_we_n__core__o(libresocsim_libresoc_constraintmanager_sdram_we_n), + .TAP_bus__tdo(libresocsim_libresoc_jtag_tdo), + .busy_o(libresocsim_libresoc1), + .dbus__adr(libresocsim_libresoc_dbus_adr), + .dbus__cyc(libresocsim_libresoc_dbus_cyc), + .dbus__dat_w(libresocsim_libresoc_dbus_dat_w), + .dbus__sel(libresocsim_libresoc_dbus_sel), + .dbus__stb(libresocsim_libresoc_dbus_stb), + .dbus__we(libresocsim_libresoc_dbus_we), + .eint_0__core__i(libresocsim_libresoc_constraintmanager_eint_0), + .eint_1__core__i(libresocsim_libresoc_constraintmanager_eint_1), + .eint_2__core__i(libresocsim_libresoc_constraintmanager_eint_2), + .gpio_e10__core__i(libresocsim_libresoc_constraintmanager_gpio_i[10]), + .gpio_e10__pad__o(gpio_o[10]), + .gpio_e10__pad__oe(gpio_oe[10]), + .gpio_e11__core__i(libresocsim_libresoc_constraintmanager_gpio_i[11]), + .gpio_e11__pad__o(gpio_o[11]), + .gpio_e11__pad__oe(gpio_oe[11]), + .gpio_e12__core__i(libresocsim_libresoc_constraintmanager_gpio_i[12]), + .gpio_e12__pad__o(gpio_o[12]), + .gpio_e12__pad__oe(gpio_oe[12]), + .gpio_e13__core__i(libresocsim_libresoc_constraintmanager_gpio_i[13]), + .gpio_e13__pad__o(gpio_o[13]), + .gpio_e13__pad__oe(gpio_oe[13]), + .gpio_e14__core__i(libresocsim_libresoc_constraintmanager_gpio_i[14]), + .gpio_e14__pad__o(gpio_o[14]), + .gpio_e14__pad__oe(gpio_oe[14]), + .gpio_e15__core__i(libresocsim_libresoc_constraintmanager_gpio_i[15]), + .gpio_e15__pad__o(gpio_o[15]), + .gpio_e15__pad__oe(gpio_oe[15]), + .gpio_e8__core__i(libresocsim_libresoc_constraintmanager_gpio_i[8]), + .gpio_e8__pad__o(gpio_o[8]), + .gpio_e8__pad__oe(gpio_oe[8]), + .gpio_e9__core__i(libresocsim_libresoc_constraintmanager_gpio_i[9]), + .gpio_e9__pad__o(gpio_o[9]), + .gpio_e9__pad__oe(gpio_oe[9]), + .gpio_s0__core__i(libresocsim_libresoc_constraintmanager_gpio_i[0]), + .gpio_s0__pad__o(gpio_o[0]), + .gpio_s0__pad__oe(gpio_oe[0]), + .gpio_s1__core__i(libresocsim_libresoc_constraintmanager_gpio_i[1]), + .gpio_s1__pad__o(gpio_o[1]), + .gpio_s1__pad__oe(gpio_oe[1]), + .gpio_s2__core__i(libresocsim_libresoc_constraintmanager_gpio_i[2]), + .gpio_s2__pad__o(gpio_o[2]), + .gpio_s2__pad__oe(gpio_oe[2]), + .gpio_s3__core__i(libresocsim_libresoc_constraintmanager_gpio_i[3]), + .gpio_s3__pad__o(gpio_o[3]), + .gpio_s3__pad__oe(gpio_oe[3]), + .gpio_s4__core__i(libresocsim_libresoc_constraintmanager_gpio_i[4]), + .gpio_s4__pad__o(gpio_o[4]), + .gpio_s4__pad__oe(gpio_oe[4]), + .gpio_s5__core__i(libresocsim_libresoc_constraintmanager_gpio_i[5]), + .gpio_s5__pad__o(gpio_o[5]), + .gpio_s5__pad__oe(gpio_oe[5]), + .gpio_s6__core__i(libresocsim_libresoc_constraintmanager_gpio_i[6]), + .gpio_s6__pad__o(gpio_o[6]), + .gpio_s6__pad__oe(gpio_oe[6]), + .gpio_s7__core__i(libresocsim_libresoc_constraintmanager_gpio_i[7]), + .gpio_s7__pad__o(gpio_o[7]), + .gpio_s7__pad__oe(gpio_oe[7]), + .ibus__adr(libresocsim_libresoc_ibus_adr), + .ibus__cyc(libresocsim_libresoc_ibus_cyc), + .ibus__dat_w(libresocsim_libresoc_ibus_dat_w), + .ibus__sel(libresocsim_libresoc_ibus_sel), + .ibus__stb(libresocsim_libresoc_ibus_stb), + .ibus__we(libresocsim_libresoc_ibus_we), + .icp_wb__ack(libresocsim_libresoc_xics_icp_ack), + .icp_wb__dat_r(libresocsim_libresoc_xics_icp_dat_r), + .icp_wb__err(libresocsim_libresoc_xics_icp_err), + .ics_wb__ack(libresocsim_libresoc_xics_ics_ack), + .ics_wb__dat_r(libresocsim_libresoc_xics_ics_dat_r), + .ics_wb__err(libresocsim_libresoc_xics_ics_err), + .jtag_wb__adr(libresocsim_libresoc_jtag_wb_adr), + .jtag_wb__cyc(libresocsim_libresoc_jtag_wb_cyc), + .jtag_wb__dat_w(libresocsim_libresoc_jtag_wb_dat_w), + .jtag_wb__sel(libresocsim_libresoc_jtag_wb_sel), + .jtag_wb__stb(libresocsim_libresoc_jtag_wb_stb), + .jtag_wb__we(libresocsim_libresoc_jtag_wb_we), + .memerr_o(libresocsim_libresoc2), + .mspi0_clk__pad__o(spimaster_clk), + .mspi0_cs_n__pad__o(spimaster_cs_n), + .mspi0_miso__core__i(libresocsim_libresoc_constraintmanager_spimaster_miso), + .mspi0_mosi__pad__o(spimaster_mosi), + .mtwi_scl__pad__o(i2c_scl), + .mtwi_sda__core__i(libresocsim_libresoc_constraintmanager_i2c_sda_i), + .mtwi_sda__pad__o(i2c_sda_o), + .mtwi_sda__pad__oe(i2c_sda_oe), + .pc_o(libresocsim_libresoc3), + .sdr_a_0__pad__o(sdram_a[0]), + .sdr_a_10__pad__o(sdram_a[10]), + .sdr_a_11__pad__o(sdram_a[11]), + .sdr_a_12__pad__o(sdram_a[12]), + .sdr_a_1__pad__o(sdram_a[1]), + .sdr_a_2__pad__o(sdram_a[2]), + .sdr_a_3__pad__o(sdram_a[3]), + .sdr_a_4__pad__o(sdram_a[4]), + .sdr_a_5__pad__o(sdram_a[5]), + .sdr_a_6__pad__o(sdram_a[6]), + .sdr_a_7__pad__o(sdram_a[7]), + .sdr_a_8__pad__o(sdram_a[8]), + .sdr_a_9__pad__o(sdram_a[9]), + .sdr_ba_0__pad__o(sdram_ba[0]), + .sdr_ba_1__pad__o(sdram_ba[1]), + .sdr_cas_n__pad__o(sdram_cas_n), + .sdr_cke__pad__o(sdram_cke), + .sdr_clock__pad__o(sdram_clock), + .sdr_cs_n__pad__o(sdram_cs_n), + .sdr_dm_0__pad__o(sdram_dm[0]), + .sdr_dm_1__pad__o(sdram_dm[1]), + .sdr_dq_0__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[0]), + .sdr_dq_0__pad__o(sdram_dq_o[0]), + .sdr_dq_0__pad__oe(sdram_dq_oe[0]), + .sdr_dq_10__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[10]), + .sdr_dq_10__pad__o(sdram_dq_o[10]), + .sdr_dq_10__pad__oe(sdram_dq_oe[10]), + .sdr_dq_11__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[11]), + .sdr_dq_11__pad__o(sdram_dq_o[11]), + .sdr_dq_11__pad__oe(sdram_dq_oe[11]), + .sdr_dq_12__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[12]), + .sdr_dq_12__pad__o(sdram_dq_o[12]), + .sdr_dq_12__pad__oe(sdram_dq_oe[12]), + .sdr_dq_13__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[13]), + .sdr_dq_13__pad__o(sdram_dq_o[13]), + .sdr_dq_13__pad__oe(sdram_dq_oe[13]), + .sdr_dq_14__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[14]), + .sdr_dq_14__pad__o(sdram_dq_o[14]), + .sdr_dq_14__pad__oe(sdram_dq_oe[14]), + .sdr_dq_15__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[15]), + .sdr_dq_15__pad__o(sdram_dq_o[15]), + .sdr_dq_15__pad__oe(sdram_dq_oe[15]), + .sdr_dq_1__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[1]), + .sdr_dq_1__pad__o(sdram_dq_o[1]), + .sdr_dq_1__pad__oe(sdram_dq_oe[1]), + .sdr_dq_2__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[2]), + .sdr_dq_2__pad__o(sdram_dq_o[2]), + .sdr_dq_2__pad__oe(sdram_dq_oe[2]), + .sdr_dq_3__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[3]), + .sdr_dq_3__pad__o(sdram_dq_o[3]), + .sdr_dq_3__pad__oe(sdram_dq_oe[3]), + .sdr_dq_4__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[4]), + .sdr_dq_4__pad__o(sdram_dq_o[4]), + .sdr_dq_4__pad__oe(sdram_dq_oe[4]), + .sdr_dq_5__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[5]), + .sdr_dq_5__pad__o(sdram_dq_o[5]), + .sdr_dq_5__pad__oe(sdram_dq_oe[5]), + .sdr_dq_6__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[6]), + .sdr_dq_6__pad__o(sdram_dq_o[6]), + .sdr_dq_6__pad__oe(sdram_dq_oe[6]), + .sdr_dq_7__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[7]), + .sdr_dq_7__pad__o(sdram_dq_o[7]), + .sdr_dq_7__pad__oe(sdram_dq_oe[7]), + .sdr_dq_8__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[8]), + .sdr_dq_8__pad__o(sdram_dq_o[8]), + .sdr_dq_8__pad__oe(sdram_dq_oe[8]), + .sdr_dq_9__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[9]), + .sdr_dq_9__pad__o(sdram_dq_o[9]), + .sdr_dq_9__pad__oe(sdram_dq_oe[9]), + .sdr_ras_n__pad__o(sdram_ras_n), + .sdr_we_n__pad__o(sdram_we_n) +); + +endmodule -- 2.30.2