From c0296ab34fe33beed2a9a31d5bd62ee9f426c1f9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 27 Oct 2023 11:55:38 +0100 Subject: [PATCH] missing brackets in lhbrx --- openpower/isa/fixedloadshift.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn index ba0b5d1e..504ba839 100644 --- a/openpower/isa/fixedloadshift.mdwn +++ b/openpower/isa/fixedloadshift.mdwn @@ -357,7 +357,7 @@ Description: register RB shifted by (SH+1), and (RA|0). Bits 0:7 of the halfword in storage addressed by EA are - loaded into RT 56:63. Bits 8:15 of the halfword in storage + loaded into RT[56:63]. Bits 8:15 of the halfword in storage addressed by EA are loaded into RT[48:55]. RT[0:47] are set to 0. -- 2.30.2