From c030176faf54e1941c75fc6a4bfb6ecc6a280440 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 27 Dec 2021 18:52:05 +0000 Subject: [PATCH] found bug in mmu with calculating addrsh, should have been a right shift --- src/soc/experiment/mmu.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index 5787f110..a245ddbd 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -522,7 +522,7 @@ class MMU(Elaboratable): # Shift address bits 61--12 right by 0--47 bits and # supply the least significant 16 bits of the result. - comb += addrsh.eq(r.addr[12:62] << r.shift) + comb += addrsh.eq(r.addr[12:62] >> r.shift) with m.If(r.state != State.IDLE): sync += Display("MMU state %d %016x", r.state, data) -- 2.30.2