From c055003a59b527bec0aa2ba4bf35078639c40b24 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 22 Sep 2022 20:00:52 -0700 Subject: [PATCH] fix 'write reg ' log call --- src/openpower/decoder/isa/caller.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 5f54a01e..0edca8ad 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1884,7 +1884,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): if self.is_svp64_mode and self.pred_dst_zero: log('zeroing reg %d %s' % (regnum, str(output)), is_vec) output = SelectableInt(0, 256) - log("write reg %s%d %0xx" % (reg_prefix, regnum, output.value)) + log("write reg %s%d 0x%x" % (reg_prefix, regnum, output.value), + kind=LogKind.InstrInOuts) # zero-extend tov64 bit begore storing (should use EXT oh well) if output.bits > 64: output = SelectableInt(output.value, 64) -- 2.30.2