From c093821cee2d8c132aab2861764603ad0e09d23c Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 4 Aug 2017 03:26:38 +0200 Subject: [PATCH] radeonsi: rename shader_userdata -> shader_pointers where appropriate MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Tested-by: Dieter Nützel Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_compute.c | 2 +- src/gallium/drivers/radeonsi/si_descriptors.c | 24 +++++++++---------- src/gallium/drivers/radeonsi/si_pipe.h | 2 +- src/gallium/drivers/radeonsi/si_state.h | 6 ++--- src/gallium/drivers/radeonsi/si_state_draw.c | 6 ++--- 5 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index fba02faeb5a..5efdd3919d2 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -811,7 +811,7 @@ static void si_launch_grid( return; si_upload_compute_shader_descriptors(sctx); - si_emit_compute_shader_userdata(sctx); + si_emit_compute_shader_pointers(sctx); if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) { sctx->atoms.s.render_cond->emit(&sctx->b, diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 43f1792eddd..5a7f5d911a0 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -1175,7 +1175,7 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx) * on performance (confirmed by testing). New descriptors are always * uploaded to a fresh new buffer, so I don't think flushing the const * cache is needed. */ - si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom); + si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom); sctx->vertex_buffers_dirty = false; sctx->vertex_buffer_pointer_dirty = true; sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS; @@ -2097,14 +2097,14 @@ static void si_mark_shader_pointers_dirty(struct si_context *sctx, if (shader == PIPE_SHADER_VERTEX) sctx->vertex_buffer_pointer_dirty = sctx->vertex_buffers.buffer != NULL; - si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom); + si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom); } -static void si_shader_userdata_begin_new_cs(struct si_context *sctx) +static void si_shader_pointers_begin_new_cs(struct si_context *sctx) { sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS); sctx->vertex_buffer_pointer_dirty = sctx->vertex_buffers.buffer != NULL; - si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom); + si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom); } /* Set a base register address for user data constants in the given shader. @@ -2113,7 +2113,7 @@ static void si_shader_userdata_begin_new_cs(struct si_context *sctx) static void si_set_user_data_base(struct si_context *sctx, unsigned shader, uint32_t new_base) { - uint32_t *base = &sctx->shader_userdata.sh_base[shader]; + uint32_t *base = &sctx->shader_pointers.sh_base[shader]; if (*base != new_base) { *base = new_base; @@ -2184,11 +2184,11 @@ static void si_emit_shader_pointer(struct si_context *sctx, radeon_emit(cs, va >> 32); } -void si_emit_graphics_shader_userdata(struct si_context *sctx, +void si_emit_graphics_shader_pointers(struct si_context *sctx, struct r600_atom *atom) { unsigned mask; - uint32_t *sh_base = sctx->shader_userdata.sh_base; + uint32_t *sh_base = sctx->shader_pointers.sh_base; struct si_descriptors *descs; descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS]; @@ -2242,7 +2242,7 @@ void si_emit_graphics_shader_userdata(struct si_context *sctx, } } -void si_emit_compute_shader_userdata(struct si_context *sctx) +void si_emit_compute_shader_pointers(struct si_context *sctx) { unsigned base = R_00B900_COMPUTE_USER_DATA_0; struct si_descriptors *descs = sctx->descriptors; @@ -2883,8 +2883,8 @@ void si_init_all_descriptors(struct si_context *sctx) sctx->b.rebind_buffer = si_rebind_buffer; /* Shader user data. */ - si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata, - si_emit_graphics_shader_userdata); + si_init_atom(sctx, &sctx->shader_pointers.atom, &sctx->atoms.s.shader_pointers, + si_emit_graphics_shader_pointers); /* Set default and immutable mappings. */ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0); @@ -2915,7 +2915,7 @@ bool si_upload_graphics_shader_descriptors(struct si_context *sctx) unsigned i = u_bit_scan(&dirty); if (!si_upload_descriptors(sctx, &sctx->descriptors[i], - &sctx->shader_userdata.atom)) + &sctx->shader_pointers.atom)) return false; } @@ -2989,7 +2989,7 @@ void si_all_descriptors_begin_new_cs(struct si_context *sctx) for (i = 0; i < SI_NUM_DESCS; ++i) si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]); - si_shader_userdata_begin_new_cs(sctx); + si_shader_pointers_begin_new_cs(sctx); } void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx, diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 62b64e16879..ee0ab1b37b9 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -312,7 +312,7 @@ struct si_context { struct si_blend_color blend_color; struct r600_atom clip_regs; struct si_clip_state clip_state; - struct si_shader_data shader_userdata; + struct si_shader_data shader_pointers; struct si_stencil_ref stencil_ref; struct r600_atom spi_map; diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 48e88afe1b8..bce40663085 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -153,7 +153,7 @@ union si_state_atoms { struct r600_atom *blend_color; struct r600_atom *clip_regs; struct r600_atom *clip_state; - struct r600_atom *shader_userdata; + struct r600_atom *shader_pointers; struct r600_atom *scissors; struct r600_atom *viewports; struct r600_atom *stencil_ref; @@ -339,9 +339,9 @@ void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuf void si_update_all_texture_descriptors(struct si_context *sctx); void si_shader_change_notify(struct si_context *sctx); void si_update_needs_color_decompress_masks(struct si_context *sctx); -void si_emit_graphics_shader_userdata(struct si_context *sctx, +void si_emit_graphics_shader_pointers(struct si_context *sctx, struct r600_atom *atom); -void si_emit_compute_shader_userdata(struct si_context *sctx); +void si_emit_compute_shader_pointers(struct si_context *sctx); void si_set_rw_buffer(struct si_context *sctx, uint slot, const struct pipe_constant_buffer *input); void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx, diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index c78450c2ce3..605dfdbd0a4 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -105,7 +105,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id; bool has_primid_instancing_bug = sctx->b.chip_class == SI && sctx->b.screen->info.max_se == 1; - unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL]; + unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; unsigned num_tcs_input_cp = info->vertices_per_patch; unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs; unsigned num_tcs_patch_outputs; @@ -567,7 +567,7 @@ static void si_emit_vs_state(struct si_context *sctx, struct radeon_winsys_cs *cs = sctx->b.gfx.cs; radeon_set_sh_reg(cs, - sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] + + sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_STATE_BITS * 4, sctx->current_vs_state); @@ -640,7 +640,7 @@ static void si_emit_draw_packets(struct si_context *sctx, { struct pipe_draw_indirect_info *indirect = info->indirect; struct radeon_winsys_cs *cs = sctx->b.gfx.cs; - unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX]; + unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX]; bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off; uint32_t index_max_size = 0; uint64_t index_va = 0; -- 2.30.2