From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:32:28 +0200 Subject: [PATCH] Removed RTLIL::SigSpec::optimize() --- backends/blif/blif.cc | 1 - backends/edif/edif.cc | 1 - backends/intersynth/intersynth.cc | 2 - backends/verilog/verilog_backend.cc | 3 - frontends/ast/genrtlil.cc | 11 --- kernel/bitpattern.h | 3 - kernel/rtlil.cc | 114 +++------------------------- kernel/rtlil.h | 7 -- passes/abc/blifparse.cc | 3 - passes/cmds/setundef.cc | 1 - passes/cmds/show.cc | 3 - passes/cmds/splice.cc | 2 - passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_map.cc | 5 -- passes/memory/memory_collect.cc | 7 -- passes/memory/memory_dff.cc | 1 - passes/memory/memory_share.cc | 2 - passes/opt/opt_clean.cc | 2 - passes/opt/opt_const.cc | 2 - passes/proc/proc_dff.cc | 4 - passes/proc/proc_init.cc | 2 - passes/sat/eval.cc | 3 - passes/sat/freduce.cc | 10 +-- passes/sat/sat.cc | 5 -- 24 files changed, 15 insertions(+), 181 deletions(-) diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index a240d2a26..d0c250790 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -70,7 +70,6 @@ struct BlifDumper const char *cstr(RTLIL::SigSpec sig) { - sig.optimize(); log_assert(sig.size() == 1); if (sig.chunks().at(0).wire == NULL) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 3b9a43370..8f36f4090 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -315,7 +315,6 @@ struct EdifBackend : public Backend { } for (auto &it : net_join_db) { RTLIL::SigSpec sig = it.first; - sig.optimize(); log_assert(sig.size() == 1); if (sig.chunks().at(0).wire == NULL) { if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1) diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 832922def..a4cad5add 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -28,8 +28,6 @@ static std::string netname(std::set &conntypes_code, std::set &celltypes_code, std::set &constcells_code, RTLIL::SigSpec sig) { - sig.optimize(); - if (sig.chunks().size() != 1) error: log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig)); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 160835087..1dcc3003a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -133,7 +133,6 @@ std::string id(std::string internal_id, bool may_rename = true) bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) { - sig.optimize(); if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL) return false; if (reg_wires.count(sig.chunks()[0].wire->name) == 0) @@ -303,7 +302,6 @@ std::string cellname(RTLIL::Cell *cell) if (sig.size() != 1 || sig.is_fully_const()) goto no_special_reg_name; - sig.optimize(); RTLIL::Wire *wire = sig.chunks()[0].wire; if (wire->name[0] != '\\') @@ -909,7 +907,6 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) continue; RTLIL::SigSpec sig = cell->connections["\\Q"]; - sig.optimize(); if (sig.chunks().size() == 1 && sig.chunks()[0].wire) for (int i = 0; i < sig.chunks()[0].width; i++) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 18ae008cb..3d848e823 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -292,8 +292,6 @@ struct AST_INTERNAL::ProcessGenerator proc->syncs.push_back(sync); assert(init_lvalue.size() == init_rvalue.size()); - init_lvalue.optimize(); - init_rvalue.optimize(); int offset = 0; for (size_t i = 0; i < init_lvalue.chunks().size(); i++) { @@ -308,7 +306,6 @@ struct AST_INTERNAL::ProcessGenerator // create new temporary signals RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig) { - sig.optimize(); std::vector chunks = sig.chunks(); for (int i = 0; i < SIZE(chunks); i++) @@ -399,8 +396,6 @@ struct AST_INTERNAL::ProcessGenerator lvalue.remove2(initSyncSignals, &rvalue); } assert(lvalue.size() == rvalue.size()); - lvalue.optimize(); - rvalue.optimize(); int offset = 0; for (size_t i = 0; i < lvalue.chunks().size(); i++) { @@ -433,9 +428,7 @@ struct AST_INTERNAL::ProcessGenerator if (ast->type == AST_ASSIGN_EQ) { subst_rvalue_from.remove2(unmapped_lvalue, &subst_rvalue_to); subst_rvalue_from.append(unmapped_lvalue); - subst_rvalue_from.optimize(); subst_rvalue_to.append(rvalue); - subst_rvalue_to.optimize(); } removeSignalFromCaseTree(lvalue, current_case); @@ -486,9 +479,7 @@ struct AST_INTERNAL::ProcessGenerator subst_lvalue_from.remove2(this_case_eq_lvalue, &subst_lvalue_to); subst_lvalue_from.append(this_case_eq_lvalue); - subst_lvalue_from.optimize(); subst_lvalue_to.append(this_case_eq_ltemp); - subst_lvalue_to.optimize(); RTLIL::CaseRule *backup_case = current_case; current_case = new RTLIL::CaseRule; @@ -527,9 +518,7 @@ struct AST_INTERNAL::ProcessGenerator subst_rvalue_from.remove2(this_case_eq_lvalue, &subst_rvalue_to); subst_rvalue_from.append(this_case_eq_lvalue); - subst_rvalue_from.optimize(); subst_rvalue_to.append(this_case_eq_ltemp); - subst_rvalue_to.optimize(); this_case_eq_lvalue.replace(subst_lvalue_from, subst_lvalue_to); removeSignalFromCaseTree(this_case_eq_lvalue, current_case); diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 934796d24..4f4bc37a0 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -34,10 +34,8 @@ struct BitPatternPool width = sig.size(); if (width > 0) { std::vector pattern(width); - sig.optimize(); for (int i = 0; i < width; i++) { RTLIL::SigSpec s = sig.extract(i, 1); - s.optimize(); assert(s.chunks().size() == 1); if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1) pattern[i] = s.chunks()[0].data.bits[0]; @@ -61,7 +59,6 @@ struct BitPatternPool bits_t sig2bits(RTLIL::SigSpec sig) { - sig.optimize(); assert(sig.is_fully_const()); assert(sig.chunks().size() == 1); bits_t bits = sig.chunks()[0].data.bits; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 32a6b2775..7d031e174 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -768,14 +768,6 @@ void RTLIL::Module::check() void RTLIL::Module::optimize() { - for (auto &it : cells) - it.second->optimize(); - for (auto &it : processes) - it.second->optimize(); - for (auto &it : connections) { - it.first.optimize(); - it.second.optimize(); - } } void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const @@ -1297,12 +1289,6 @@ RTLIL::Memory::Memory() size = 0; } -void RTLIL::Cell::optimize() -{ - for (auto &it : connections) - it.second.optimize(); -} - void RTLIL::Cell::check() { InternalCellChecker checker(NULL, this); @@ -1548,40 +1534,6 @@ bool RTLIL::SigSpec::packed() const return bits_.empty(); } -void RTLIL::SigSpec::optimize() -{ -#if 0 - pack(); - std::vector new_chunks; - for (auto &c : chunks_) - if (new_chunks.size() == 0) { - new_chunks.push_back(c); - } else { - RTLIL::SigChunk &cc = new_chunks.back(); - if (c.wire == NULL && cc.wire == NULL) - cc.data.bits.insert(cc.data.bits.end(), c.data.bits.begin(), c.data.bits.end()); - if (c.wire == cc.wire && (c.wire == NULL || cc.offset + cc.width == c.offset)) - cc.width += c.width; - else - new_chunks.push_back(c); - } - chunks_.swap(new_chunks); - check(); -#endif -} - -RTLIL::SigSpec RTLIL::SigSpec::optimized() const -{ -#if 0 - pack(); - RTLIL::SigSpec ret = *this; - ret.optimize(); - return ret; -#else - return *this; -#endif -} - void RTLIL::SigSpec::sort() { unpack(); @@ -1825,8 +1777,6 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) while (width_ < width) append(padding); } - - optimize(); } void RTLIL::SigSpec::extend_u0(int width, bool is_signed) @@ -1844,7 +1794,6 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) append(padding); } - optimize(); } void RTLIL::SigSpec::check() const @@ -1888,8 +1837,6 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const return width_ < other.width_; RTLIL::SigSpec a = *this, b = other; - a.optimize(); - b.optimize(); if (a.chunks_.size() != b.chunks_.size()) return a.chunks_.size() < b.chunks_.size(); @@ -1910,8 +1857,6 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const return false; RTLIL::SigSpec a = *this, b = other; - a.optimize(); - b.optimize(); if (a.chunks_.size() != b.chunks_.size()) return false; @@ -1973,22 +1918,18 @@ bool RTLIL::SigSpec::has_marked_bits() const bool RTLIL::SigSpec::as_bool() const { pack(); - assert(is_fully_const()); - SigSpec sig = *this; - sig.optimize(); - if (sig.width_) - return sig.chunks_[0].data.as_bool(); + assert(is_fully_const() && SIZE(chunks_) <= 1); + if (width_) + return chunks_[0].data.as_bool(); return false; } int RTLIL::SigSpec::as_int() const { pack(); - assert(is_fully_const()); - SigSpec sig = *this; - sig.optimize(); - if (sig.width_) - return sig.chunks_[0].data.as_int(); + assert(is_fully_const() && SIZE(chunks_) <= 1); + if (width_) + return chunks_[0].data.as_int(); return 0; } @@ -2010,11 +1951,9 @@ std::string RTLIL::SigSpec::as_string() const RTLIL::Const RTLIL::SigSpec::as_const() const { pack(); - assert(is_fully_const()); - SigSpec sig = *this; - sig.optimize(); - if (sig.width_) - return sig.chunks_[0].data; + assert(is_fully_const() && SIZE(chunks_) <= 1); + if (width_) + return chunks_[0].data; return RTLIL::Const(); } @@ -2200,18 +2139,6 @@ RTLIL::CaseRule::~CaseRule() delete *it; } -void RTLIL::CaseRule::optimize() -{ - for (auto it : switches) - it->optimize(); - for (auto &it : compare) - it.optimize(); - for (auto &it : actions) { - it.first.optimize(); - it.second.optimize(); - } -} - RTLIL::CaseRule *RTLIL::CaseRule::clone() const { RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule; @@ -2228,13 +2155,6 @@ RTLIL::SwitchRule::~SwitchRule() delete *it; } -void RTLIL::SwitchRule::optimize() -{ - signal.optimize(); - for (auto it : cases) - it->optimize(); -} - RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const { RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule; @@ -2246,15 +2166,6 @@ RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const } -void RTLIL::SyncRule::optimize() -{ - signal.optimize(); - for (auto &it : actions) { - it.first.optimize(); - it.second.optimize(); - } -} - RTLIL::SyncRule *RTLIL::SyncRule::clone() const { RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule; @@ -2270,13 +2181,6 @@ RTLIL::Process::~Process() delete *it; } -void RTLIL::Process::optimize() -{ - root_case.optimize(); - for (auto it : syncs) - it->optimize(); -} - RTLIL::Process *RTLIL::Process::clone() const { RTLIL::Process *new_proc = new RTLIL::Process; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6c0a7b66f..a13164c37 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -450,7 +450,6 @@ struct RTLIL::Cell { std::map connections; std::map parameters; RTLIL_ATTRIBUTE_MEMBERS - void optimize(); void check(); template void rewrite_sigspecs(T functor); @@ -544,9 +543,6 @@ public: inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } - void optimize(); - RTLIL::SigSpec optimized() const; - void sort(); void sort_and_unify(); @@ -624,7 +620,6 @@ struct RTLIL::SwitchRule { RTLIL_ATTRIBUTE_MEMBERS std::vector cases; ~SwitchRule(); - void optimize(); template void rewrite_sigspecs(T functor); RTLIL::SwitchRule *clone() const; @@ -634,7 +629,6 @@ struct RTLIL::SyncRule { RTLIL::SyncType type; RTLIL::SigSpec signal; std::vector actions; - void optimize(); template void rewrite_sigspecs(T functor); RTLIL::SyncRule *clone() const; @@ -646,7 +640,6 @@ struct RTLIL::Process { RTLIL::CaseRule root_case; std::vector syncs; ~Process(); - void optimize(); template void rewrite_sigspecs(T functor); RTLIL::Process *clone() const; diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 47fa0f821..04977b369 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -212,9 +212,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) goto continue_without_read; } - input_sig.optimize(); - output_sig.optimize(); - RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$lut"; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 63d5bb9af..6c4bb16c0 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -144,7 +144,6 @@ struct SetundefPass : public Pass { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); - bits.optimize(); module->connections.push_back(RTLIL::SigSig(c, bits)); } } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 37fe44047..6b37b7bb1 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -171,8 +171,6 @@ struct ShowWorker std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true) { - sig.optimize(); - if (sig.chunks().size() == 0) { fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count); return stringf("v%d", single_idx_count++); @@ -199,7 +197,6 @@ struct ShowWorker if (net.empty()) { std::string label_string; - sig.optimize(); int pos = sig.size()-1; int idx = single_idx_count++; for (int i = int(sig.chunks().size())-1; i >= 0; i--) { diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index aed9c076e..68e8951ff 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -82,7 +82,6 @@ struct SpliceWorker module->add(cell); } - new_sig.optimize(); sliced_signals_cache[sig] = new_sig; return new_sig; @@ -143,7 +142,6 @@ struct SpliceWorker module->add(cell); } - new_sig.optimize(); spliced_signals_cache[sig] = new_sig; log(" Created spliced signal: %s -> %s\n", log_signal(sig), log_signal(new_sig)); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index c40ff2c4a..c65b6a5f8 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -141,7 +141,7 @@ struct SplitnetsPass : public Pass { if (!ct.cell_output(c.second->type, p.first)) continue; - RTLIL::SigSpec sig = p.second.optimized(); + RTLIL::SigSpec sig = p.second; for (auto &chunk : sig.chunks()) { if (chunk.wire == NULL) continue; diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 9dda2ba89..cee267629 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -42,13 +42,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapparameters["\\SIZE"] = RTLIL::Const(memory->size); mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits); - sig_wr_clk_enable.optimize(); - sig_wr_clk_polarity.optimize(); - assert(sig_wr_clk.size() == wr_ports); assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); @@ -158,10 +155,6 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->connections["\\WR_DATA"] = sig_wr_data; mem->connections["\\WR_EN"] = sig_wr_en; - sig_rd_clk_enable.optimize(); - sig_rd_clk_polarity.optimize(); - sig_rd_transparent.optimize(); - assert(sig_rd_clk.size() == rd_ports); assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index b1f1e22b5..56915776e 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -69,7 +69,6 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI replaced_this_bit:; } - sig.optimize(); return true; } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 38eff9961..dd2a32cad 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -439,8 +439,6 @@ struct MemoryShareWorker merged_en.replace(k, cell_en.extract(k, 1)); merged_data.replace(k, cell_data.extract(k, 1)); } - merged_en.optimize(); - merged_data.optimize(); } // Connect the new EN and DATA signals and remove the old write port. diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 0be36606d..ba0aadc6b 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -241,8 +241,6 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool new_conn.second.append_bit(s2[i]); } if (new_conn.first.size() > 0) { - new_conn.first.optimize(); - new_conn.second.optimize(); used_signals.add(new_conn.first); used_signals.add(new_conn.second); module->connections.push_back(new_conn); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index ff139854f..800fbf109 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -481,8 +481,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() < a.size() || new_b.size() < b.size()) { - new_a.optimize(); - new_b.optimize(); cell->connections["\\A"] = new_a; cell->connections["\\B"] = new_b; cell->parameters["\\A_WIDTH"] = new_a.size(); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 8e5fbe8f4..a8aba903a 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -352,10 +352,6 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) ce.assign_map.apply(rstval); ce.assign_map.apply(sig); - insig.optimize(); - rstval.optimize(); - sig.optimize(); - if (rstval == sig) { rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index ba1fb5ab9..4c9b6bcd2 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -28,7 +28,6 @@ static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) assert(rule.compare.size() == 0); while (1) { - sig.optimize(); RTLIL::SigSpec tmp = sig; for (auto &it : rule.actions) tmp.replace(it.first, it.second); @@ -53,7 +52,6 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) RTLIL::SigSpec lhs = action.first; RTLIL::SigSpec rhs = action.second; - lhs.optimize(); proc_get_const(rhs, proc->root_case); if (!rhs.is_fully_const()) diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 9b8c35361..6949b76db 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -53,8 +53,6 @@ struct BruteForceEquivChecker return; } - inputs.optimize(); - ConstEval ce1(mod1), ce2(mod2); ce1.set(mod1_inputs, inputs.as_const()); ce2.set(mod2_inputs, inputs.as_const()); @@ -482,7 +480,6 @@ struct EvalPass : public Pass { RTLIL::SigSpec signal, value, undef; if (!RTLIL::SigSpec::parse_sel(signal, design, module, it)) log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); - signal.optimize(); value = signal; if (set_undef) { while (!ce.eval(value, undef)) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 1e47e7de2..ba01bc322 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -349,7 +349,7 @@ struct PerformReduction std::vector bucket_sigbits; for (int idx : bucket) bucket_sigbits.push_back(out_bits[idx]); - log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(RTLIL::SigSpec(bucket_sigbits).optimized())); + log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(bucket_sigbits)); } std::vector sat_set_list, sat_clr_list; @@ -494,7 +494,7 @@ struct PerformReduction std::vector r_sigbits; for (int idx : r) r_sigbits.push_back(out_bits[idx]); - log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(RTLIL::SigSpec(r_sigbits).optimized())); + log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(r_sigbits)); } std::vector undef_slaves; @@ -640,7 +640,7 @@ struct FreduceWorker found_selected_wire: log(" Finding reduced input cone for signal batch %s%c\n", - log_signal(RTLIL::SigSpec(std::vector(batch.begin(), batch.end())).optimized()), verbose_level ? ':' : '.'); + log_signal(batch), verbose_level ? ':' : '.'); FindReducedInputs infinder(sigmap, drivers); for (auto &bit : batch) { @@ -663,12 +663,12 @@ struct FreduceWorker continue; if (bucket.first.size() == 0) { - log(" Finding const values for bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.'); + log(" Finding const values for bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.'); PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size()); for (size_t idx = 0; idx < bucket.second.size(); idx++) worker.analyze_const(equiv, idx); } else { - log(" Trying to shatter bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.'); + log(" Trying to shatter bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.'); PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size()); worker.analyze(equiv, 100 * bucket_count / (buckets.size() + 1)); } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 34becaee8..4b6b1b719 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -114,10 +114,6 @@ struct SatHelper } } - lhs.optimize(); - rhs.optimize(); - removed_bits.optimize(); - if (removed_bits.size()) log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); @@ -152,7 +148,6 @@ struct SatHelper if (!satgen.initial_state.check_all(big_lhs)) { RTLIL::SigSpec rem = satgen.initial_state.remove(big_lhs); - rem.optimize(); log_cmd_error("Found -set-init bits that are not part of the initial_state: %s\n", log_signal(rem)); } -- 2.30.2