From c096a329934deeb33448adae4f286813895c8101 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Thu, 3 Nov 2016 12:08:26 +0000 Subject: [PATCH] [rtlanal] Fix WORD_REGISTER_OPERATIONS condition in nonzero_bits * rtlanal.c (nonzero_bits1): Fix WORD_REGISTER_OPERATIONS condition. Move comments into more natural position. From-SVN: r241815 --- gcc/ChangeLog | 5 +++++ gcc/rtlanal.c | 14 +++++++------- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f0eb5f9e29..22b16c5afa4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-11-03 Kyrylo Tkachov + + * rtlanal.c (nonzero_bits1): Fix WORD_REGISTER_OPERATIONS condition. + Move comments into more natural position. + 2016-11-03 Vineet Gupta * config/arc/arc.h (SIZE_TYPE): Define as unsigned int. diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 508c66384d6..4ebb314013b 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -4568,18 +4568,18 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, known_x, known_mode, known_ret); #ifdef LOAD_EXTEND_OP - /* If this is a typical RISC machine, we only have to worry - about the way loads are extended. */ - if (WORD_REGISTER_OPERATIONS - && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND + /* On many CISC machines, accessing an object in a wider mode + causes the high-order bits to become undefined. So they are + not known to be zero. */ + if (!WORD_REGISTER_OPERATIONS + /* If this is a typical RISC machine, we only have to worry + about the way loads are extended. */ + || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND ? val_signbit_known_set_p (inner_mode, nonzero) : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) || !MEM_P (SUBREG_REG (x)))) #endif { - /* On many CISC machines, accessing an object in a wider mode - causes the high-order bits to become undefined. So they are - not known to be zero. */ if (GET_MODE_PRECISION (GET_MODE (x)) > GET_MODE_PRECISION (inner_mode)) nonzero |= (GET_MODE_MASK (GET_MODE (x)) -- 2.30.2