From c0bb47beca2fb78670ab14515047a88a677cc608 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 12:11:17 +0100 Subject: [PATCH] sv: Fix memories of typedefs Signed-off-by: David Shah --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e0a654b76..516fa4138 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1350,7 +1350,7 @@ wire_name: if ($2 != NULL) { if (node->is_input || node->is_output) frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions."); - if (!astbuf2) { + if (!astbuf2 && !node->is_custom_type) { AstNode *rng = new AstNode(AST_RANGE); rng->children.push_back(AstNode::mkconst_int(0, true)); rng->children.push_back(AstNode::mkconst_int(0, true)); -- 2.30.2