From c0c17030fd6ded41135f14e5ece38c305bc873ce Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 3 Sep 2014 18:37:04 +0200
Subject: [PATCH] spi_flash: simplify usage by removing cmd, cmd_width,
 addr_width parameters

---
 misoclib/spiflash/__init__.py | 35 +++++++++++++++++++++++++++--------
 targets/kc705.py              |  3 +--
 targets/ppro.py               |  3 +--
 3 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/misoclib/spiflash/__init__.py b/misoclib/spiflash/__init__.py
index 006ad08f..8f836731 100644
--- a/misoclib/spiflash/__init__.py
+++ b/misoclib/spiflash/__init__.py
@@ -4,20 +4,31 @@ from migen.bus import wishbone
 from migen.genlib.misc import timeline
 from migen.genlib.record import Record
 
+_FAST_READ = 0x0b
+_DIOFR = 0xbb
+_QIOFR = 0xeb
+
+def _format_cmd(cmd, spi_width):
+	"""
+	`cmd` is the read instruction. Since everything is transmitted on all
+	dq lines (cmd, adr and data), extend/interleave cmd to full pads.dq
+	width even if dq1-dq3 are don't care during the command phase:
+	For example, for N25Q128, 0xeb is the quad i/o fast read, and
+	extended to 4 bits (dq1,dq2,dq3 high) is: 0xfffefeff
+	"""
+	c = 2**(8*spi_width)-1
+	for b in range(8):
+		if not (cmd>>b)%2:
+			c &= ~(1<<(b*spi_width))
+	return c
+
 class SpiFlash(Module):
-	def __init__(self, pads, cmd=0xfffefeff, cmd_width=32, addr_width=24,
-			dummy=15, div=2):
+	def __init__(self, pads, dummy=15, div=2):
 		"""
 		Simple read-only SPI flash, e.g. N25Q128 on the LX9 Microboard.
 
 		Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
 		Read). Only supports mode0 (cpol=0, cpha=0).
-
-		`cmd` is the read instruction. Since everything is transmitted on all
-		dq lines (cmd, adr and data), extend/interleave cmd to full pads.dq
-		width even if dq1-dq3 are don't care during the command phase:
-		For example, for N25Q128, 0xeb is the quad i/o fast read, and
-		extended to 4 bits (dq1,dq2,dq3 high) is: 0xfffefeff
 		"""
 		self.bus = bus = wishbone.Interface()
 
@@ -26,6 +37,14 @@ class SpiFlash(Module):
 		wbone_width = flen(bus.dat_r)
 		spi_width = flen(pads.dq)
 
+		cmd_params = {
+			4: (_format_cmd(_QIOFR, 4), 4*8),
+			2: (_format_cmd(_DIOFR, 2), 2*8),
+			1: (_format_cmd(_FAST_READ, 1), 1*8)
+		}
+		cmd, cmd_width = cmd_params[spi_width]
+		addr_width = 24
+
 		pads.cs_n.reset = 1
 
 		dq = TSTriple(spi_width)
diff --git a/targets/kc705.py b/targets/kc705.py
index ad3b9e99..8c78ad76 100644
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -100,8 +100,7 @@ class BaseSoC(SDRAMSoC):
 		self.specials += Instance("STARTUPE2",
 			i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
 			i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
-		self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads,
-			cmd=0xfffefeff, cmd_width=32, addr_width=24, dummy=11, div=2)
+		self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
 		self.flash_boot_address = 0xb00000
 		self.register_rom(self.spiflash.bus)
 
diff --git a/targets/ppro.py b/targets/ppro.py
index 97034231..05bfea3b 100644
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -87,8 +87,7 @@ class BaseSoC(SDRAMSoC):
 		self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing)
 
 		# BIOS is in SPI flash
-		self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"),
-			cmd=0xefef, cmd_width=16, addr_width=24, dummy=4, div=6)
+		self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
 		self.flash_boot_address = 0x70000
 		self.register_rom(self.spiflash.bus)
 
-- 
2.30.2