From c0c40dc26616117b7454440fc894eb6456efed5b Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Thu, 9 Dec 2021 20:23:22 +0000 Subject: [PATCH] Tried using other jtag_ commands, still need some extra config to fill shift reg --- src/spec/testing_stage1.py | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py index 88beb06..7386f9d 100644 --- a/src/spec/testing_stage1.py +++ b/src/spec/testing_stage1.py @@ -26,7 +26,11 @@ from nmutil.util import wrap # jtag_set_ir, jtag_set_get_dr) from soc.debug.test.test_jtag_tap import (jtag_read_write_reg, - jtag_set_reset) + jtag_set_reset, + jtag_set_shift_ir, + jtag_set_shift_dr, + jtag_set_run, + jtag_set_idle) from c4m.nmigen.jtag.tap import TAP, IOType from c4m.nmigen.jtag.bus import Interface as JTAGInterface @@ -720,11 +724,25 @@ def test_jtag_bs_chain(): top.jtag.stop = True - - #----------------------------------------- # Start of my basic test, toggling not working #----------------------------------------- + print("JTAG BS Reset") + yield from jtag_set_reset(top.jtag) + + # Trying to fill the shift register with 1's (to at least see propagation) + top.jtag.bus.tdi.eq(1) + yield + + #yield from jtag_set_run(top.jtag) + #yield from jtag_set_shift_dr(top.jtag) + yield from jtag_set_shift_ir(top.jtag) + for _ in range(0, 10): + yield from jtag_set_shift_ir(top.jtag) + #yield + #yield from jtag_set_idle(top.jtag) + + # Doesn't work for i in range(0, 10): top.jtag.ios['uart_0__rx'].core.i.eq(1) top.jtag.ios['uart_0__rx'].pad.i.eq(0) -- 2.30.2