From c0c549dbb052e8ee34a874008c79c2752e3af749 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 28 Sep 2020 12:25:17 +0100 Subject: [PATCH] switch off internal gpio (testing) --- src/soc/simple/issuer_verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 394913c2..820e5fd3 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -28,7 +28,7 @@ if __name__ == '__main__': # set to 32 to make data wishbone bus 32-bit #wb_data_wid=32, xics=True, - gpio=True, # for test purposes + gpio=False, # for test purposes debug="jtag", # set to jtag or dmi units=units) -- 2.30.2