From c0df9e08236697bad334b47dc8d6589420e37125 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 18 Jun 2019 09:44:09 +0200 Subject: [PATCH] cpu/rocket: update submodule --- litex/soc/cores/cpu/rocket/verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog index bcb12b02..b17b6984 160000 --- a/litex/soc/cores/cpu/rocket/verilog +++ b/litex/soc/cores/cpu/rocket/verilog @@ -1 +1 @@ -Subproject commit bcb12b0233b050dddef8d9c69bbf590d10428647 +Subproject commit b17b6984b9b7b0d0c259306ba94187abae7f37f5 -- 2.30.2