From c0edfa878833f8c6a2a90c3466448783eae3fa28 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 29 Oct 2021 13:31:41 +0200
Subject: [PATCH] Add missing items in CHANGELOG

---
 CHANGELOG | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/CHANGELOG b/CHANGELOG
index b980c5a1a..6feea4162 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,6 +16,12 @@ Yosys 0.10 .. Yosys 0.10-dev
     - Fixed an issue where connecting a slice covering the entirety of a signed
       signal to a cell input would cause a failed assertion
 
+ * Verific support
+    - Importer support for {PRIM,WIDE_OPER}_DFF
+    - Importer support for PRIM_BUFIF1
+    - Option to use Verific without VHDL support
+    - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
+
 Yosys 0.9 .. Yosys 0.10
 --------------------------
 
-- 
2.30.2