From c0eea387a37e90292e4a65d775ee1f3f2797b93f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 6 Nov 2018 11:36:43 +0000 Subject: [PATCH] convert rv_sl to same extra bitwidth arg --- riscv/insns/slli.h | 2 +- riscv/insns/slliw.h | 2 +- riscv/insns/sllw.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h index b196afa..515c221 100644 --- a/riscv/insns/slli.h +++ b/riscv/insns/slli.h @@ -1,2 +1,2 @@ require(rv_lt(SHAMT, sv_reg_t(xlen))); -WRITE_RD(sext_xlen(rv_sl(RS1, SHAMT))); +WRITE_RD(sext_xlen(rv_sl(RS1, SHAMT, 64))); diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h index c9495ab..87d65b7 100644 --- a/riscv/insns/slliw.h +++ b/riscv/insns/slliw.h @@ -1,2 +1,2 @@ require_rv64; -WRITE_RD(sext32(rv_sl(RS1, SHAMT))); +WRITE_RD(sext32(rv_sl(RS1, SHAMT, 64))); diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h index 276e285..3a764a9 100644 --- a/riscv/insns/sllw.h +++ b/riscv/insns/sllw.h @@ -1,2 +1,2 @@ require_rv64; -WRITE_RD(sext32(rv_sl(RS1, rv_and(RS2, sv_reg_t(0x1FU))))); +WRITE_RD(sext32(rv_sl(RS1, RS2, 32U))); -- 2.30.2