From c0f8084d728b80fa8f1f005b4d42c68129e753a0 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 10:41:11 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 83ff38bf4..c42f3df89 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -119,18 +119,32 @@ Pseudocode for Horizontal-First Mode:
    else
        cond_ok = not SVRMmode.ALL
        for i in range(VL):
+           # select predicate bit or zero/one
            if predicate[i]:
                testbit = CR[BI+32+srcstep*4]
            else if not SVRMmode.sz:
                continue
-           else testbit = SVRMmode.SNZ
+           else
+               testbit = SVRMmode.SNZ
+           # actual element test herr
            el_cond_ok <- ¬(testbit ^ BO[1])
+           # merge in the test
+           if SVRMmode.ALL:
+               cond_ok &= el_cond_ok
+           else
+               cond_ok |= el_cond_ok
+           # test for VL to be set (and exit)
+           if ~el_cond_ok and VLSET
+               if SVRMmode.VLI
+                   SVSTATE.VL = i+1
+               else
+                   SVSTATE.VL = i
+               break
+           # early exit? 
            if SVRMmode.ALL:
                if ~el_cond_ok:
                    break
-               cond_ok &= el_cond_ok
            else
                if el_cond_ok:
                    break
-               cond_ok |= el_cond_ok
 ```
-- 
2.30.2