From c10622f5e295ec69e7e687a6bc65db0cd8afbb96 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 27 Feb 2013 18:10:04 +0100 Subject: [PATCH] fhdl/verilog: insert reset before listing signals --- migen/fhdl/tools.py | 2 +- migen/fhdl/verilog.py | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py index 62e1183e..f9cb67c7 100644 --- a/migen/fhdl/tools.py +++ b/migen/fhdl/tools.py @@ -86,7 +86,7 @@ def is_variable(node): def insert_reset(rst, sl): targets = list_targets(sl) resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)] - return If(rst, *resetcode).Else(*sl) + return [If(rst, *resetcode).Else(*sl)] def value_bits_sign(v): if isinstance(v, bool): diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 502d4d14..bc0a19c4 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -200,11 +200,17 @@ def _printcomb(f, ns, display_run): r += "\n" return r +def _insert_resets(f, clock_domains): + newsync = dict() + for k, v in f.sync.items(): + newsync[k] = insert_reset(clock_domains[k].rst, v) + f.sync = newsync + def _printsync(f, ns, clock_domains): r = "" for k, v in sorted(f.sync.items(), key=itemgetter(0)): r += "always @(posedge " + ns.get_name(clock_domains[k].clk) + ") begin\n" - r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(clock_domains[k].rst, v)) + r += _printnode(ns, _AT_SIGNAL, 1, v) r += "end\n\n" return r @@ -267,6 +273,7 @@ def convert(f, ios=None, name="top", f = lower_arrays(f) fs, lowered_specials = _lower_specials(special_overrides, f.specials) f += fs + _insert_resets(f, clock_domains) ns = build_namespace(list_signals(f) \ | list_special_ios(f, True, True, True) \ -- 2.30.2