From c114508fc43f5ebd72d4ab25f4e2c1443d11acdb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 13 Sep 2019 04:44:08 +0100 Subject: [PATCH] update VL format --- simple_v_extension/vblock_format_table.mdwn | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn index 4143f9c0d..a0c258eb7 100644 --- a/simple_v_extension/vblock_format_table.mdwn +++ b/simple_v_extension/vblock_format_table.mdwn @@ -14,13 +14,15 @@ of the RISC-V ISA, is as follows: The VL/MAXVL/SubVL Block format, when 16xil != 0b111, is: [[!table data=""" -31:30 | 29:28 | 27:22 | 21 | 20:19 | 18:16 | comment................ | -0b00 | SubVL | imm[5:0] |rsvd| rd[4:0] || sv.setvl rd, x0, imm | -0b01 | SubVL | imm[5:0] | rs1[2:0] || rd[2:0] | RVC format, sv.setvl rd, rs, imm | -0b10 | SubVL | imm[5:0] |rsvd| rs1[4:0] || sv.setvl x0, rs1, imm | -0b11 | rsvd | rsvd |rsvd| rsvd || reserved, all 0s | +31:30 | 29:28 | 27:22 | 21 | 20:19 | 18:16 | comment.................. | +0b00 | SubVL | imm[5:0] |rsvd| rd[4:0] || sv.setvl rd, x0, imm | +0b01 | SubVL | imm[5:0] | rs1[2:0] || rd[2:0] | sv.setvl rd, rs1, imm (1) | +0b10 | SubVL | imm[5:0] |rsvd| rs1[4:0] || sv.setvl x0, rs1, imm | +0b11 | rsvd | rsvd |rsvd| rsvd || reserved, all 0s | """]] +Note (1) - Registers are in RVC format (x8-x15) + When 16xil is 0b111, this is the "Extended" Format, using the >= 192-bit RISC-V ISA format. Note that the length is 96+16\*nnnnn, not 192+ -- 2.30.2