From c12327f15c903c3562821d591c68125ef59db2cc Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 5 Aug 2010 17:59:34 -0700 Subject: [PATCH] [sim,xcc] Added first few Hauser FP insns (sign-injection) Also updated FPmove test case to test negation and moving between FP regs --- riscv/decode.h | 1 + riscv/execute.h | 100 ++++++++++++++++------------ riscv/insns/{abs_fmt.h => add_d.h} | 0 riscv/insns/{add_fmt.h => add_s.h} | 0 riscv/insns/{div_fmt.h => div_d.h} | 0 riscv/insns/{mul_fmt.h => div_s.h} | 0 riscv/insns/mov_fmt.h | 2 - riscv/insns/movn.h | 1 - riscv/insns/movz.h | 1 - riscv/insns/{neg_fmt.h => mul_d.h} | 0 riscv/insns/{sqrt_fmt.h => mul_s.h} | 0 riscv/insns/sgninj_d.h | 2 + riscv/insns/sgninj_s.h | 2 + riscv/insns/sgninjn_d.h | 2 + riscv/insns/sgninjn_s.h | 2 + riscv/insns/sgnmul_d.h | 2 + riscv/insns/sgnmul_s.h | 2 + riscv/insns/{sub_fmt.h => sqrt_d.h} | 0 riscv/insns/sqrt_s.h | 0 riscv/insns/sub_d.h | 0 riscv/insns/sub_s.h | 0 21 files changed, 69 insertions(+), 48 deletions(-) rename riscv/insns/{abs_fmt.h => add_d.h} (100%) rename riscv/insns/{add_fmt.h => add_s.h} (100%) rename riscv/insns/{div_fmt.h => div_d.h} (100%) rename riscv/insns/{mul_fmt.h => div_s.h} (100%) delete mode 100644 riscv/insns/mov_fmt.h delete mode 100644 riscv/insns/movn.h delete mode 100644 riscv/insns/movz.h rename riscv/insns/{neg_fmt.h => mul_d.h} (100%) rename riscv/insns/{sqrt_fmt.h => mul_s.h} (100%) create mode 100644 riscv/insns/sgninj_d.h create mode 100644 riscv/insns/sgninj_s.h create mode 100644 riscv/insns/sgninjn_d.h create mode 100644 riscv/insns/sgninjn_s.h create mode 100644 riscv/insns/sgnmul_d.h create mode 100644 riscv/insns/sgnmul_s.h rename riscv/insns/{sub_fmt.h => sqrt_d.h} (100%) create mode 100644 riscv/insns/sqrt_s.h create mode 100644 riscv/insns/sub_d.h create mode 100644 riscv/insns/sub_s.h diff --git a/riscv/decode.h b/riscv/decode.h index 1357b37..7bdfb18 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1,6 +1,7 @@ #ifndef _RISCV_DECODE_H #define _RISCV_DECODE_H +#define __STDC_LIMIT_MACROS #include typedef int int128_t __attribute__((mode(TI))); typedef unsigned int uint128_t __attribute__((mode(TI))); diff --git a/riscv/execute.h b/riscv/execute.h index 8c8ae90..ad655ac 100644 --- a/riscv/execute.h +++ b/riscv/execute.h @@ -67,72 +67,84 @@ switch((insn.bits >> 0x19) & 0x7f) { case 0x0: { - if((insn.bits & 0xfe007c00) == 0xd0000000) + if((insn.bits & 0xfe007fe0) == 0xd0000ca0) { - #include "insns/add_fmt.h" + #include "insns/sgninj_d.h" break; } - #include "insns/unimp.h" - } - case 0x1: - { - if((insn.bits & 0xfe007c00) == 0xd0001000) + if((insn.bits & 0xfe007fe0) == 0xd00000a0) { - #include "insns/sub_fmt.h" + #include "insns/sgninj_s.h" break; } - #include "insns/unimp.h" - } - case 0x2: - { - if((insn.bits & 0xfe007c00) == 0xd0002000) + if((insn.bits & 0xfe007fe0) == 0xd0000000) { - #include "insns/mul_fmt.h" + #include "insns/add_s.h" break; } - #include "insns/unimp.h" - } - case 0x3: - { - if((insn.bits & 0xfe007c00) == 0xd0003000) + if((insn.bits & 0xfe007fe0) == 0xd0000c00) { - #include "insns/div_fmt.h" + #include "insns/add_d.h" break; } - #include "insns/unimp.h" - } - case 0x4: - { - if((insn.bits & 0xfe0ffc00) == 0xd0004000) + if((insn.bits & 0xfe007fe0) == 0xd0000ce0) { - #include "insns/sqrt_fmt.h" + #include "insns/sgnmul_d.h" break; } - #include "insns/unimp.h" - } - case 0x5: - { - if((insn.bits & 0xfe0ffc00) == 0xd0005000) + if((insn.bits & 0xfe007fe0) == 0xd0000cc0) { - #include "insns/abs_fmt.h" + #include "insns/sgninjn_d.h" break; } - #include "insns/unimp.h" - } - case 0x6: - { - if((insn.bits & 0xfe0ffc00) == 0xd0006000) + if((insn.bits & 0xfe007fe0) == 0xd00000c0) { - #include "insns/mov_fmt.h" + #include "insns/sgninjn_s.h" break; } - #include "insns/unimp.h" - } - case 0x7: - { - if((insn.bits & 0xfe0ffc00) == 0xd0007000) + if((insn.bits & 0xfe007fe0) == 0xd0000c40) + { + #include "insns/mul_d.h" + break; + } + if((insn.bits & 0xfe007fe0) == 0xd0000020) + { + #include "insns/sub_s.h" + break; + } + if((insn.bits & 0xfe007fe0) == 0xd0000c20) + { + #include "insns/sub_d.h" + break; + } + if((insn.bits & 0xfe0fffe0) == 0xd0000080) + { + #include "insns/sqrt_s.h" + break; + } + if((insn.bits & 0xfe0fffe0) == 0xd0000c80) + { + #include "insns/sqrt_d.h" + break; + } + if((insn.bits & 0xfe007fe0) == 0xd00000e0) + { + #include "insns/sgnmul_s.h" + break; + } + if((insn.bits & 0xfe007fe0) == 0xd0000c60) + { + #include "insns/div_d.h" + break; + } + if((insn.bits & 0xfe007fe0) == 0xd0000060) + { + #include "insns/div_s.h" + break; + } + if((insn.bits & 0xfe007fe0) == 0xd0000040) { - #include "insns/neg_fmt.h" + #include "insns/mul_s.h" break; } #include "insns/unimp.h" diff --git a/riscv/insns/abs_fmt.h b/riscv/insns/add_d.h similarity index 100% rename from riscv/insns/abs_fmt.h rename to riscv/insns/add_d.h diff --git a/riscv/insns/add_fmt.h b/riscv/insns/add_s.h similarity index 100% rename from riscv/insns/add_fmt.h rename to riscv/insns/add_s.h diff --git a/riscv/insns/div_fmt.h b/riscv/insns/div_d.h similarity index 100% rename from riscv/insns/div_fmt.h rename to riscv/insns/div_d.h diff --git a/riscv/insns/mul_fmt.h b/riscv/insns/div_s.h similarity index 100% rename from riscv/insns/mul_fmt.h rename to riscv/insns/div_s.h diff --git a/riscv/insns/mov_fmt.h b/riscv/insns/mov_fmt.h deleted file mode 100644 index 9bbde8a..0000000 --- a/riscv/insns/mov_fmt.h +++ /dev/null @@ -1,2 +0,0 @@ -require_fp; -FRC = FRA; diff --git a/riscv/insns/movn.h b/riscv/insns/movn.h deleted file mode 100644 index bdf6e5f..0000000 --- a/riscv/insns/movn.h +++ /dev/null @@ -1 +0,0 @@ -if(RB) RC = RA; diff --git a/riscv/insns/movz.h b/riscv/insns/movz.h deleted file mode 100644 index 45f4f07..0000000 --- a/riscv/insns/movz.h +++ /dev/null @@ -1 +0,0 @@ -if(!RB) RC = RA; diff --git a/riscv/insns/neg_fmt.h b/riscv/insns/mul_d.h similarity index 100% rename from riscv/insns/neg_fmt.h rename to riscv/insns/mul_d.h diff --git a/riscv/insns/sqrt_fmt.h b/riscv/insns/mul_s.h similarity index 100% rename from riscv/insns/sqrt_fmt.h rename to riscv/insns/mul_s.h diff --git a/riscv/insns/sgninj_d.h b/riscv/insns/sgninj_d.h new file mode 100644 index 0000000..a87ca63 --- /dev/null +++ b/riscv/insns/sgninj_d.h @@ -0,0 +1,2 @@ +require_fp; +FRC.bits = (FRA.bits &~ INT64_MIN) | (FRB.bits & INT64_MIN); diff --git a/riscv/insns/sgninj_s.h b/riscv/insns/sgninj_s.h new file mode 100644 index 0000000..db56f49 --- /dev/null +++ b/riscv/insns/sgninj_s.h @@ -0,0 +1,2 @@ +require_fp; +FRC.bits = (FRA.bits &~ (uint32_t)INT32_MIN) | (FRB.bits & (uint32_t)INT32_MIN); diff --git a/riscv/insns/sgninjn_d.h b/riscv/insns/sgninjn_d.h new file mode 100644 index 0000000..5fad072 --- /dev/null +++ b/riscv/insns/sgninjn_d.h @@ -0,0 +1,2 @@ +require_fp; +FRC.bits = (FRA.bits &~ INT64_MIN) | ((~FRB.bits) & INT64_MIN); diff --git a/riscv/insns/sgninjn_s.h b/riscv/insns/sgninjn_s.h new file mode 100644 index 0000000..c50967b --- /dev/null +++ b/riscv/insns/sgninjn_s.h @@ -0,0 +1,2 @@ +require_fp; +FRC.bits = (FRA.bits &~ (uint32_t)INT32_MIN) | ((~FRB.bits) & (uint32_t)INT32_MIN); diff --git a/riscv/insns/sgnmul_d.h b/riscv/insns/sgnmul_d.h new file mode 100644 index 0000000..47d950f --- /dev/null +++ b/riscv/insns/sgnmul_d.h @@ -0,0 +1,2 @@ +require_fp; +FRC.bits = FRA.bits ^ (FRB.bits & INT64_MIN); diff --git a/riscv/insns/sgnmul_s.h b/riscv/insns/sgnmul_s.h new file mode 100644 index 0000000..2a9ae11 --- /dev/null +++ b/riscv/insns/sgnmul_s.h @@ -0,0 +1,2 @@ +require_fp; +FRC.bits = FRA.bits ^ (FRB.bits & (uint32_t)INT32_MIN); diff --git a/riscv/insns/sub_fmt.h b/riscv/insns/sqrt_d.h similarity index 100% rename from riscv/insns/sub_fmt.h rename to riscv/insns/sqrt_d.h diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/sqrt_s.h new file mode 100644 index 0000000..e69de29 diff --git a/riscv/insns/sub_d.h b/riscv/insns/sub_d.h new file mode 100644 index 0000000..e69de29 diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h new file mode 100644 index 0000000..e69de29 -- 2.30.2