From c12cb3f95c4c27a7320773fc0bacefea31fb0cd9 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 7 Jun 2022 01:30:27 +0100 Subject: [PATCH] --- openpower/sv/remap.mdwn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn index dec09925a..198877b22 100644 --- a/openpower/sv/remap.mdwn +++ b/openpower/sv/remap.mdwn @@ -204,6 +204,8 @@ Fields: Examples showing how all of these Modes operate exists in the online [SVP64 unit tests](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD) +and the full pseudocode setting up all SPRs +is in the [[openpower/isa/simplev]] page. In Indexed Mode, there are only 5 bits available to specify the GPR to use, out of 128 GPRs (7 bit numbering). Therefore, only the top -- 2.30.2