From c14491c0c10e1806840fb4b1328bc3af982a2a70 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 20 Dec 2020 16:24:03 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 7bc8da50f..26e9ec854 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -190,6 +190,10 @@ These are the modes: note that reduce mode only applies to 2 src operations. * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element (CR0) however is still stored in the CR regfile. This scheme does not apply to crops (crand, cror). +Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however independent and may easily be parallelised to give high performance, regardless of the value of VL. + +The Mode table is laid out as follows: + | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | | 00 | 0 | sz dz | normal mode | -- 2.30.2