From c16477158b53e192e4232ab610706da245b48348 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 21 Jun 2022 20:43:09 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 54514b7c5..64c58f8ac 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -72,9 +72,8 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations: | 6 | 7 | 19-20 | 21 | 22 23 | description | | - | - | ----- | --- |---------|----------------- | |sz |SNZ| 0 RG | 0 | dz / | normal mode | -|sz |SNZ| 0 RG | 1 | 0 / | scalar reduce mode (mapreduce), SUBVL=1 | -|zz |SNZ| 0 RG | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | -|sz |SNZ| 0 RG | 1 | SVM / | subvector reduce mode, SUBVL>1 | +|sz |SNZ| 0 RG | 1 | 0 / | scalar reduce mode (mapreduce) | +|zz |SNZ| 0 RG | 1 | 1 / | parallel reduce mode (mapreduce) | |sz |SNZ| 1 VLI | inv | CR-bit | Ffirst 3-bit mode | |sz |SNZ| 1 VLI | inv | dz / | Ffirst 5-bit mode | @@ -87,7 +86,6 @@ Fields: * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) * **RG** inverts the Vector Loop order (VL-1 downto 0) rather than the normal 0..VL-1 -* **SVM** sets "subvector" reduce mode * **VLi** VL inclusive: in fail-first mode, the truncation of VL *includes* the current element at the failure point rather than excludes it from the count. -- 2.30.2