From c16a42a9bae4855b3ffe8d219a78613c6373a311 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 29 Feb 2020 15:37:35 -0500 Subject: [PATCH] Correct cry in field from a single bit to an enum --- src/decoder/major.csv | 70 ++++++++++---------- src/decoder/power_major_decoder.py | 11 ++- src/decoder/test/test_power_major_decoder.py | 5 +- 3 files changed, 49 insertions(+), 37 deletions(-) diff --git a/src/decoder/major.csv b/src/decoder/major.csv index f9f7cfce..f58784a6 100644 --- a/src/decoder/major.csv +++ b/src/decoder/major.csv @@ -1,35 +1,35 @@ -opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe, -12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,0,0,0,1,NONE,0,0,0,0,0,0,NONE,0,0,addic -13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,0,0,0,1,NONE,0,0,0,0,0,0,ONE,0,0,addic. -14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,addi -15,ALU,OP_ADD,RA_OR_ZERO,CONST_SI_HI,NONE,RT,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,addis -28,ALU,OP_AND,NONE,CONST_UI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,ONE,0,0,andi. -29,ALU,OP_AND,NONE,CONST_UI_HI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,ONE,0,0,andis. -18,ALU,OP_B,NONE,CONST_LI,NONE,NONE,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,1,0,b -16,ALU,OP_BC,SPR,CONST_BD,NONE,SPR,1,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,1,0,bc -11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,0,1,1,0,1,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi -10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,0,1,1,0,1,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli -34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz -35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu -42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is2B,0,1,0,0,0,0,NONE,0,1,lha -43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau -40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz -41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu -32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz -33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu -7,ALU,OP_MUL_L64,RA,CONST_SI,NONE,RT,0,1,0,0,0,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli -24,ALU,OP_OR,NONE,CONST_UI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,ori -25,ALU,OP_OR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,oris -20,ALU,OP_RLC,RA,CONST_SH32,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi -21,ALU,OP_RLC,NONE,CONST_SH32,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm -23,ALU,OP_RLC,NONE,RB,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm -38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is1B,0,0,0,0,0,0,RC,0,1,stb -39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is1B,0,0,1,0,0,0,RC,0,1,stbu -44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is2B,0,0,0,0,0,0,NONE,0,1,sth -45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu -36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is4B,0,0,0,0,0,0,NONE,0,1,stw -37,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu -8,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,1,0,1,1,NONE,0,0,0,0,0,0,NONE,0,0,subfic -2,ALU,OP_TDI,RA,CONST_SI,NONE,NONE,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,1,tdi -26,ALU,OP_XOR,NONE,CONST_UI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,xori -27,ALU,OP_XOR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,xoris +opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe +12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,0,NONE,0,0,addic +13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,0,ONE,0,0,addic. +14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addi +15,ALU,OP_ADD,RA_OR_ZERO,CONST_SI_HI,NONE,RT,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addis +28,ALU,OP_AND,NONE,CONST_UI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andi. +29,ALU,OP_AND,NONE,CONST_UI_HI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andis. +18,ALU,OP_B,NONE,CONST_LI,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,b +16,ALU,OP_BC,SPR,CONST_BD,NONE,SPR,1,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bc +11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,0,1,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi +10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,0,1,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli +34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz +35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu +42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha +43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau +40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz +41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu +32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz +33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu +7,ALU,OP_MUL_L64,RA,CONST_SI,NONE,RT,0,1,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli +24,ALU,OP_OR,NONE,CONST_UI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori +25,ALU,OP_OR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris +20,ALU,OP_RLC,RA,CONST_SH32,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi +21,ALU,OP_RLC,NONE,CONST_SH32,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm +23,ALU,OP_RLC,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm +38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,1,stb +39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbu +44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth +45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu +36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw +37,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu +8,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,1,0,ONE,1,NONE,0,0,0,0,0,0,NONE,0,0,subfic +2,ALU,OP_TDI,RA,CONST_SI,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,tdi +26,ALU,OP_XOR,NONE,CONST_UI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xori +27,ALU,OP_XOR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xoris diff --git a/src/decoder/power_major_decoder.py b/src/decoder/power_major_decoder.py index d3078444..2f1e5297 100644 --- a/src/decoder/power_major_decoder.py +++ b/src/decoder/power_major_decoder.py @@ -75,8 +75,15 @@ class RC(Enum): RC = 2 +@unique +class CryIn(Enum): + ZERO = 0 + ONE = 1 + CA = 2 + + # names of the fields in major.csv that don't correspond to an enum -single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out', 'cry in', +single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out', 'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b', 'sgn', 'lk', 'sgl pipe'] @@ -107,6 +114,7 @@ class PowerMajorDecoder(Elaboratable): self.out_sel = Signal(OutSel, reset_less=True) self.ldst_len = Signal(LdstLen, reset_less=True) self.rc_sel = Signal(RC, reset_less=True) + self.cry_in = Signal(CryIn, reset_less=True) for bit in single_bit_flags: name = get_signal_name(bit) setattr(self, name, @@ -128,6 +136,7 @@ class PowerMajorDecoder(Elaboratable): comb += self.out_sel.eq(OutSel[row['out']]) comb += self.ldst_len.eq(LdstLen[row['ldst len']]) comb += self.rc_sel.eq(RC[row['rc']]) + comb += self.cry_in.eq(CryIn[row['cry in']]) for bit in single_bit_flags: sig = getattr(self, get_signal_name(bit)) comb += sig.eq(int(row[bit])) diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py index 1d0d6b17..1f8374d1 100644 --- a/src/decoder/test/test_power_major_decoder.py +++ b/src/decoder/test/test_power_major_decoder.py @@ -7,7 +7,7 @@ import unittest sys.path.append("../") from power_major_decoder import (PowerMajorDecoder, Function, In1Sel, In2Sel, In3Sel, OutSel, - LdstLen, RC, + LdstLen, RC, CryIn, single_bit_flags, get_signal_name, InternalOp, major_opcodes) @@ -25,6 +25,7 @@ class DecoderTestCase(FHDLTestCase): out_sel = Signal(OutSel) rc_sel = Signal(RC) ldst_len = Signal(LdstLen) + cry_in = Signal(CryIn) m.submodules.dut = dut = PowerMajorDecoder() comb += [dut.opcode_in.eq(opcode), @@ -35,6 +36,7 @@ class DecoderTestCase(FHDLTestCase): out_sel.eq(dut.out_sel), rc_sel.eq(dut.rc_sel), ldst_len.eq(dut.ldst_len), + cry_in.eq(dut.cry_in), internal_op.eq(dut.internal_op)] sim = Simulator(m) @@ -50,6 +52,7 @@ class DecoderTestCase(FHDLTestCase): (in3_sel, In3Sel, 'in3'), (out_sel, OutSel, 'out'), (rc_sel, RC, 'rc'), + (cry_in, CryIn, 'cry in'), (ldst_len, LdstLen, 'ldst len')] for sig, enm, name in signals: result = yield sig -- 2.30.2