From c17a6e01de9756d9cbeec83f2e7152e440f0f24e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 26 Feb 2020 17:31:01 +0000 Subject: [PATCH] tiny code-shuffle on GatedBitReverse --- src/ieee754/part_shift/bitrev.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/ieee754/part_shift/bitrev.py b/src/ieee754/part_shift/bitrev.py index 47523b10..7f1c1bbb 100644 --- a/src/ieee754/part_shift/bitrev.py +++ b/src/ieee754/part_shift/bitrev.py @@ -1,20 +1,26 @@ from nmigen import Signal, Module, Elaboratable, Cat, Mux class GatedBitReverse(Elaboratable): + def __init__(self, width): self.width = width self.data = Signal(width, reset_less=True) self.reverse_en = Signal(reset_less=True) self.output = Signal(width, reset_less=True) + def elaborate(self, platform): m = Module() comb = m.d.comb width = self.width + l, r = [], [] for i in range(width): - with m.If(self.reverse_en): - comb += self.output[i].eq(self.data[width-i-1]) - with m.Else(): - comb += self.output[i].eq(self.data[i]) + l.append(self.data[i]) + r.append(self.data[width-i-1]) + + with m.If(self.reverse_en): + comb += self.output.eq(Cat(*r)) + with m.Else(): + comb += self.output.eq(Cat(*l)) return m -- 2.30.2