From c17cf3e6e8dd4496a7b0e944bab89b835495d2ba Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Nov 2018 03:15:58 +0000
Subject: [PATCH] more cpu logic

---
 README.txt |  2 ++
 cpu.py     | 28 +++++++++++++++++++++-------
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/README.txt b/README.txt
index 611dc57..c357623 100644
--- a/README.txt
+++ b/README.txt
@@ -1,6 +1,8 @@
 # Limitations
 
 * there is no << or >> operator, only <<< and >>> (arithmetic shift)
+  _Operator("<<", [lhs, rhs]) will generate verilog however simulation
+  will fail, and value_bits_sign will not correctly recognise it
 * it is not possible to declare parameters
 * an input of [31:2] is not possible, only a parameter of [N:0]
 
diff --git a/cpu.py b/cpu.py
index 20da637..7dbf77d 100644
--- a/cpu.py
+++ b/cpu.py
@@ -28,6 +28,7 @@
 
 from migen import *
 from migen.fhdl import verilog
+from migen.fhdl.structure import _Operator
 
 from riscvdefs import *
 from cpudefs import *
@@ -58,6 +59,13 @@ class CPU(Module):
                   "default": ls.eq(Constant(1))
                 })
 
+    def get_lsbm(self, decoder_funct3):
+        return Cat(Constant(1),
+                   Mux((decoder_funct3[1] | decoder_funct3[0]),
+                       Constant(1), Constant(0)),
+                   Mux((decoder_funct3[1]),
+                       Constant(0b11, 2), Constant(0, 2)))
+
     def __init__(self):
         #self.clk = ClockSignal()
         #self.reset = ResetSignal()
@@ -82,9 +90,6 @@ class CPU(Module):
             l.append(Signal(32, name="register%d" % i))
         registers = Array(l)
 
-        #self.sync += self.registers[0].eq(0)
-        #self.sync += self.registers[1].eq(0)
-
         mi = MemoryInterface()
 
         mii = Instance("cpu_memory_interface", name="memory_instance",
@@ -181,6 +186,19 @@ class CPU(Module):
                                      load_store_address_low_2)
         self.comb += lsa
 
+        # XXX rwaddr not 31:2 any more
+        self.comb += mi.rw_address.eq(load_store_address[2:])
+
+        unshifted_load_store_byte_mask = Signal(4)
+
+        self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(
+                                                       decoder_funct3))
+
+        # XXX yuck.  this will cause migen simulation to fail
+        # (however conversion to verilog works)
+        self.comb += mi.rw_byte_mask.eq(
+                _Operator("<<", [unshifted_load_store_byte_mask,
+                                        load_store_address_low_2]))
 
 if __name__ == "__main__":
     example = CPU()
@@ -197,10 +215,6 @@ if __name__ == "__main__":
 
 """
 
-    assign memory_interface_rw_address = load_store_address[31:2];
-
-    wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
-
     assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
 
     assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
-- 
2.30.2