From c18c81edc68d2d84bcce7f24129414a175806477 Mon Sep 17 00:00:00 2001 From: Erik Faye-Lund Date: Thu, 31 Oct 2019 13:02:06 +0100 Subject: [PATCH] zink/spirv: implement bany_fnequal[2-4] --- src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index 47d93efc910..e502da7d045 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -1028,6 +1028,18 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) result = emit_select(ctx, dest_type, src[0], src[1], src[2]); break; + case nir_op_bany_fnequal2: + case nir_op_bany_fnequal3: + case nir_op_bany_fnequal4: + assert(nir_op_infos[alu->op].num_inputs == 2); + assert(alu_instr_src_components(alu, 0) == + alu_instr_src_components(alu, 1)); + result = emit_binop(ctx, SpvOpFOrdNotEqual, + get_bvec_type(ctx, alu_instr_src_components(alu, 0)), + src[0], src[1]); + result = emit_unop(ctx, SpvOpAny, dest_type, result); + break; + case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: { -- 2.30.2