From c18d53f534d25eb9728480b62e3fa0f0be13f96f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 16 Apr 2022 13:33:33 +0100 Subject: [PATCH] blegh. * add in a new PRE_IDLE state into issue FSM (to allow pc_at_reset to get a word in edgeways) * set nia to pc_at_reset on core_rst (not 0x0) * add in a terrible hack where the STATE regfile entry for PC is shifted down by one. absolutely no frickin idea why that is needed --- Makefile | 2 +- src/soc/simple/core.py | 2 +- src/soc/simple/issuer.py | 16 +++++++++++----- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 736cd7b1..8d379590 100644 --- a/Makefile +++ b/Makefile @@ -72,7 +72,7 @@ microwatt_external_core_spi: microwatt_external_core_bram: python3 src/soc/simple/issuer_verilog.py --microwatt-compat \ --enable-mmu \ - --pc-reset 0xFFF00000 \ + --pc-reset 0xFF000000 \ external_core_top.v # build the litex libresoc SoC without 4k SRAMs diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 9a4abacc..10fe1f86 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -168,7 +168,7 @@ class NonProductionCore(ControlBase): self.msr_at_reset = pspec.msr_reset if hasattr(pspec, "pc_reset") and isinstance(pspec.pc_reset, int): self.pc_at_reset = pspec.pc_reset - state_resets = [self.pc_at_reset, # PC at reset + state_resets = [self.pc_at_reset>>1, # PC at reset self.msr_at_reset, # MSR at reset 0x0, # SVSTATE at reset 0x0, # DEC at reset diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index a80941db..7ea8ff33 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -626,6 +626,7 @@ class TestIssuerBase(Elaboratable): with m.If(core_rst): m.d.sync += self.cur_state.eq(0) # and, sigh, set configured values, which are also done in regfile + # XXX ??? what the hell is the shift for?? m.d.sync += self.cur_state.pc.eq(self.core.pc_at_reset) m.d.sync += self.cur_state.msr.eq(self.core.msr_at_reset) @@ -805,7 +806,7 @@ class TestIssuerInternal(TestIssuerBase): easy understanding) come later. """ - def fetch_fsm(self, m, dbg, core, nia, is_svp64_mode, + def fetch_fsm(self, m, dbg, core, core_rst, nia, is_svp64_mode, fetch_pc_o_ready, fetch_pc_i_valid, fetch_insn_o_valid, fetch_insn_i_ready): """fetch FSM @@ -839,7 +840,7 @@ class TestIssuerInternal(TestIssuerBase): # allow fetch to not run at startup due to I-Cache reset not # having time to settle. power-on-reset holds dbg.core_stopped_i with m.State("PRE_IDLE"): - with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o): + with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o & ~core_rst): m.next = "IDLE" # waiting (zzz) @@ -1188,6 +1189,10 @@ class TestIssuerInternal(TestIssuerBase): with m.FSM(name="issue_fsm"): + with m.State("PRE_IDLE"): + with m.If(~dbg.core_stop_o & ~core_rst): + m.next = "ISSUE_START" + # sync with the "fetch" phase which is reading the instruction # at this point, there is no instruction running, that # could inadvertently update the PC. @@ -1597,7 +1602,7 @@ class TestIssuerInternal(TestIssuerBase): # Issue is where the VL for-loop # lives. the ready/valid # signalling is used to communicate between the four. - self.fetch_fsm(m, dbg, core, nia, is_svp64_mode, + self.fetch_fsm(m, dbg, core, core_rst, nia, is_svp64_mode, fetch_pc_o_ready, fetch_pc_i_valid, fetch_insn_o_valid, fetch_insn_i_ready) @@ -1619,9 +1624,10 @@ class TestIssuerInternal(TestIssuerBase): exec_insn_i_valid, exec_insn_o_ready, exec_pc_o_valid, exec_pc_i_ready) - # whatever was done above, over-ride it if core reset is held + # whatever was done above, over-ride it if core reset is held. + # set NIA to pc_at_reset with m.If(core_rst): - sync += nia.eq(0) + sync += nia.eq(self.core.pc_at_reset) return m -- 2.30.2