From c18ddbcd822410095d28c4be1c3ac3c6358622d2 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 4 Mar 2021 15:08:16 -0500
Subject: [PATCH] verilog: impose limit on maximum expression width

Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
---
 frontends/ast/genrtlil.cc           |  6 ++++++
 tests/verilog/absurd_width.ys       | 17 +++++++++++++++++
 tests/verilog/absurd_width_const.ys | 16 ++++++++++++++++
 3 files changed, 39 insertions(+)
 create mode 100644 tests/verilog/absurd_width.ys
 create mode 100644 tests/verilog/absurd_width_const.ys

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d4299bf69..e0a522430 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1000,6 +1000,12 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real
 	if (found_real)
 		*found_real = false;
 	detectSignWidthWorker(width_hint, sign_hint, found_real);
+
+	constexpr int kWidthLimit = 1 << 24;
+	if (width_hint >= kWidthLimit)
+		log_file_error(filename, location.first_line,
+			"Expression width %d exceeds implementation limit of %d!\n",
+			width_hint, kWidthLimit);
 }
 
 static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
diff --git a/tests/verilog/absurd_width.ys b/tests/verilog/absurd_width.ys
new file mode 100644
index 000000000..c0d2af4c2
--- /dev/null
+++ b/tests/verilog/absurd_width.ys
@@ -0,0 +1,17 @@
+logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
+read_verilog <<EOF
+module top(
+    input inp,
+    output out
+);
+    assign out =
+        {1024 {
+        {1024 {
+        {1024 {
+        inp
+        }}
+        }}
+        }}
+        ;
+endmodule
+EOF
diff --git a/tests/verilog/absurd_width_const.ys b/tests/verilog/absurd_width_const.ys
new file mode 100644
index 000000000..b7191fd0d
--- /dev/null
+++ b/tests/verilog/absurd_width_const.ys
@@ -0,0 +1,16 @@
+logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
+read_verilog <<EOF
+module top(
+    output out
+);
+    assign out =
+        {1024 {
+        {1024 {
+        {1024 {
+        1'b1
+        }}
+        }}
+        }}
+        ;
+endmodule
+EOF
-- 
2.30.2