From c19b5b8cc7470c68243ceed6339f831747c0be40 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 20:27:15 +1000 Subject: [PATCH] litedram: Update to new LiteX/LiteDRAM version Things have changed a bit in upstream LiteX. LiteDRAM now exposes a wishbone for the CSRs for example. Signed-off-by: Benjamin Herrenschmidt --- fpga/top-arty.vhdl | 6 +- fpga/top-nexys-video.vhdl | 6 +- include/console.h | 3 + include/microwatt_soc.h | 3 + lib/console.c | 2 + litedram/gen-src/arty.yml | 4 +- litedram/gen-src/generate.py | 3 +- litedram/gen-src/nexys-video.yml | 3 +- litedram/gen-src/sdram_init/Makefile | 4 +- litedram/gen-src/sdram_init/include/system.h | 30 +- litedram/gen-src/sdram_init/main.c | 105 +- litedram/gen-src/wrapper-mw-init.vhdl | 119 +- litedram/gen-src/wrapper-self-init.vhdl | 8 +- litedram/generated/arty/litedram-wrapper.vhdl | 130 +- litedram/generated/arty/litedram_core.init | 1551 +++---- litedram/generated/arty/litedram_core.v | 2875 +++++++----- .../nexys-video/litedram-wrapper.vhdl | 130 +- .../generated/nexys-video/litedram_core.init | 920 ++-- .../generated/nexys-video/litedram_core.v | 4011 ++++++++++------- soc.vhdl | 14 +- 20 files changed, 5523 insertions(+), 4404 deletions(-) diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index fbea534..9150f82 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -68,7 +68,7 @@ architecture behaviour of toplevel is -- DRAM wishbone connection signal wb_dram_in : wishbone_master_out; signal wb_dram_out : wishbone_slave_out; - signal wb_dram_csr : std_ulogic; + signal wb_dram_ctrl : std_ulogic; signal wb_dram_init : std_ulogic; -- Control/status @@ -104,7 +104,7 @@ begin uart0_rxd => uart_main_rx, wb_dram_in => wb_dram_in, wb_dram_out => wb_dram_out, - wb_dram_csr => wb_dram_csr, + wb_dram_ctrl => wb_dram_ctrl, wb_dram_init => wb_dram_init, alt_reset => core_alt_reset ); @@ -194,7 +194,7 @@ begin wb_in => wb_dram_in, wb_out => wb_dram_out, - wb_is_csr => wb_dram_csr, + wb_is_ctrl => wb_dram_ctrl, wb_is_init => wb_dram_init, serial_tx => uart_pmod_tx, diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index c0e3659..7cabfa6 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -60,7 +60,7 @@ architecture behaviour of toplevel is -- DRAM wishbone connection signal wb_dram_in : wishbone_master_out; signal wb_dram_out : wishbone_slave_out; - signal wb_dram_csr : std_ulogic; + signal wb_dram_ctrl : std_ulogic; signal wb_dram_init : std_ulogic; -- Control/status @@ -87,7 +87,7 @@ begin uart0_rxd => uart_main_rx, wb_dram_in => wb_dram_in, wb_dram_out => wb_dram_out, - wb_dram_csr => wb_dram_csr, + wb_dram_ctrl => wb_dram_ctrl, wb_dram_init => wb_dram_init, alt_reset => core_alt_reset ); @@ -175,7 +175,7 @@ begin wb_in => wb_dram_in, wb_out => wb_dram_out, - wb_is_csr => wb_dram_csr, + wb_is_ctrl => wb_dram_ctrl, wb_is_init => wb_dram_init, serial_tx => open, diff --git a/include/console.h b/include/console.h index cfd9dc1..e871c67 100644 --- a/include/console.h +++ b/include/console.h @@ -6,4 +6,7 @@ void potato_uart_irq_dis(void); int getchar(void); int putchar(int c); int puts(const char *str); + +#ifndef __USE_LIBC size_t strlen(const char *s); +#endif diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index 35add6b..16871a4 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -31,4 +31,7 @@ #define POTATO_CONSOLE_CLOCK_DIV 0x18 #define POTATO_CONSOLE_IRQ_EN 0x20 +/* Definition for the LiteDRAM control registers */ +#define DRAM_CTRL_BASE 0xc0100000 + #endif /* __MICROWATT_SOC_H */ diff --git a/lib/console.c b/lib/console.c index fa2ade3..a75d9a0 100644 --- a/lib/console.c +++ b/lib/console.c @@ -120,6 +120,7 @@ int puts(const char *str) return 0; } +#ifndef __USE_LIBC size_t strlen(const char *s) { size_t len = 0; @@ -129,3 +130,4 @@ size_t strlen(const char *s) return len; } +#endif diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml index a84f964..a4c982b 100644 --- a/litedram/gen-src/arty.yml +++ b/litedram/gen-src/arty.yml @@ -37,7 +37,5 @@ }, # CSR Port ----------------------------------------------------------------- - "csr_expose": "False", # expose access to CSR (I/O) ports - "csr_align" : 32, # CSR alignment - "csr_base" : 0xc0100000 # For cpu=None only + "csr_base" : 0xc0100000, # For cpu=None only } diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 4c24cae..3ec8690 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -104,8 +104,7 @@ def generate_one(t, mw_init): # Override values for mw_init if mw_init: core_config["cpu"] = None - core_config["csr_expose"] = True - core_config["csr_align"] = 64 + core_config["csr_alignment"] = 64 # Generate core if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml index 640ccab..23c1ce4 100644 --- a/litedram/gen-src/nexys-video.yml +++ b/litedram/gen-src/nexys-video.yml @@ -37,6 +37,5 @@ }, # CSR Port ----------------------------------------------------------------- - "csr_expose": "False", # expose access to CSR (I/O) ports - "csr_align" : 32, # 64-bit alignment + "csr_base" : 0xc0100000, # For cpu=None only } diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index 367b89d..4bc3e7b 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -21,7 +21,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy #### Flags -CPPFLAGS = -nostdinc +CPPFLAGS = -nostdinc -D__USE_LIBC CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks @@ -36,7 +36,7 @@ define Q endef else define Q - @echo " [$1] $(3)" + @echo " [$1] " $(shell basename $3) @$(2) endef endif diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h index 879f4ca..ded9b10 100644 --- a/litedram/gen-src/sdram_init/include/system.h +++ b/litedram/gen-src/sdram_init/include/system.h @@ -1,9 +1,18 @@ -static inline void flush_cpu_dcache(void) { } -static inline void flush_l2_cache(void) { } +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#include "microwatt_soc.h" +#include "io.h" + +#define CSR_ACCESSORS_DEFINED +#define CSR_BASE DRAM_CTRL_BASE +#define CONFIG_CPU_NOP "nop" -#define CONFIG_CPU_NOP "nop" -#define CONFIG_CLOCK_FREQUENCY 100000000 +extern void flush_cpu_dcache(void); +extern void flush_cpu_icache(void); +static inline void flush_l2_cache(void) { } +/* Fake timer stuff. LiteX should abstract this */ static inline void timer0_en_write(int e) { } static inline void timer0_reload_write(int r) { } static inline void timer0_load_write(int l) { } @@ -15,3 +24,16 @@ static inline uint64_t timer0_value_read(void) __asm__ volatile ("mfdec %0" : "=r" (val)); return val; } + +static inline void csr_write_simple(unsigned long v, unsigned long a) +{ + return writel(v, a); +} + +static inline unsigned long csr_read_simple(unsigned long a) +{ + return readl(a); +} + +#endif /* __SYSTEM_H */ + diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index e36b1da..b40c4df 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -10,89 +10,7 @@ #include "microwatt_soc.h" #include "io.h" #include "sdram.h" - -/* - * Core UART functions to implement for a port - */ - -static uint64_t potato_uart_base; - -#define PROC_FREQ 100000000 -#define UART_FREQ 115200 - -static uint8_t potato_uart_reg_read(int offset) -{ - return readb(potato_uart_base + offset); -} - -static void potato_uart_reg_write(int offset, uint8_t val) -{ - writeb(val, potato_uart_base + offset); -} - -static bool potato_uart_rx_empty(void) -{ - uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS); - - return (val & POTATO_CONSOLE_STATUS_RX_EMPTY) != 0; -} - -static int potato_uart_tx_full(void) -{ - uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS); - - return (val & POTATO_CONSOLE_STATUS_TX_FULL) != 0; -} - -static char potato_uart_read(void) -{ - return potato_uart_reg_read(POTATO_CONSOLE_RX); -} - -static void potato_uart_write(char c) -{ - potato_uart_reg_write(POTATO_CONSOLE_TX, c); -} - -static unsigned long potato_uart_divisor(unsigned long proc_freq, - unsigned long uart_freq) -{ - return proc_freq / (uart_freq * 16) - 1; -} - -void potato_uart_init(void) -{ - potato_uart_base = UART_BASE; - - potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, - potato_uart_divisor(PROC_FREQ, UART_FREQ)); -} - -int getchar(void) -{ - while (potato_uart_rx_empty()) - /* Do nothing */ ; - - return potato_uart_read(); -} - -int putchar(int c) -{ - while (potato_uart_tx_full()) - /* Do Nothing */; - - potato_uart_write(c); - return c; -} - -void putstr(const char *str, unsigned long len) -{ - for (unsigned long i = 0; i < len; i++) { - if (str[i] == '\n') - putchar('\r'); - putchar(str[i]); - } -} +#include "console.h" int _printf(const char *fmt, ...) { @@ -103,26 +21,33 @@ int _printf(const char *fmt, ...) va_start(ap, fmt); count = vsnprintf(buffer, sizeof(buffer), fmt, ap); va_end(ap); - putstr(buffer, count); + puts(buffer); return count; } -void flush_cpu_dcache(void) { } -void flush_cpu_icache(void) { } -void flush_l2_cache(void) { } +void flush_cpu_dcache(void) +{ +} + +void flush_cpu_icache(void) +{ + __asm__ volatile ("icbi 0,0; isync" : : : "memory"); +} void main(void) { unsigned long long ftr, val; int i; + /* Init the UART */ + potato_uart_init(); + /* * Let things settle ... not sure why but the UART is * not happy otherwise. The PLL might need to settle ? */ - potato_uart_init(); - for (i = 0; i < 100000; i++) - potato_uart_reg_read(POTATO_CONSOLE_STATUS); + for (i = 0; i < 10000; i++) + readb(UART_BASE + POTATO_CONSOLE_STATUS); printf("\n\nWelcome to Microwatt !\n\n"); /* TODO: Add core version information somewhere in syscon, possibly diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl index 46ae4b1..f13edeb 100644 --- a/litedram/gen-src/wrapper-mw-init.vhdl +++ b/litedram/gen-src/wrapper-mw-init.vhdl @@ -25,7 +25,7 @@ entity litedram_wrapper is -- Wishbone ports: wb_in : in wishbone_master_out; wb_out : out wishbone_slave_out; - wb_is_csr : in std_ulogic; + wb_is_ctrl : in std_ulogic; wb_is_init : in std_ulogic; -- Init core serial debug @@ -58,32 +58,39 @@ end entity litedram_wrapper; architecture behaviour of litedram_wrapper is component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - csr_port0_adr : in std_ulogic_vector(13 downto 0); - csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(31 downto 0); - csr_port0_dat_r : out std_ulogic_vector(31 downto 0); + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -114,18 +121,19 @@ architecture behaviour of litedram_wrapper is signal dram_user_reset : std_ulogic; - signal csr_port0_adr : std_ulogic_vector(13 downto 0); - signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); - signal csr_port_read_comb : std_ulogic_vector(63 downto 0); - signal csr_valid : std_ulogic; - signal csr_write_valid : std_ulogic; + signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); + signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); + signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); + signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); + signal wb_ctrl_cyc : std_ulogic; + signal wb_ctrl_stb : std_ulogic; + signal wb_ctrl_ack : std_ulogic; + signal wb_ctrl_we : std_ulogic; signal wb_init_in : wishbone_master_out; signal wb_init_out : wishbone_slave_out; - type state_t is (CMD, MWRITE, MREAD, CSR); + type state_t is (CMD, MWRITE, MREAD); signal state : state_t; constant INIT_RAM_SIZE : integer := 16384; @@ -192,7 +200,7 @@ begin ad3 <= wb_in.adr(3); -- DRAM data interface signals - user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; user_port0_wdata_valid <= '1' when state = MWRITE else '0'; @@ -202,21 +210,21 @@ begin user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else "00000000" & wb_in.sel; - -- DRAM CSR interface signals. We only support access to the bottom byte - csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; - csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(31 downto 0); - csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + -- DRAM ctrl interface signals + wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2); + wb_ctrl_dat_w <= wb_in.dat(31 downto 0); + wb_ctrl_sel <= wb_in.sel(3 downto 0); + wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl; + wb_ctrl_stb <= wb_in.stb and wb_is_ctrl; + wb_ctrl_we <= wb_in.we; -- Wishbone out signals - wb_out.ack <= '1' when state = CSR else + wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else wb_init_out.ack when wb_is_init = '1' else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000" & csr_port0_dat_r; - wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); @@ -239,9 +247,7 @@ begin else case state is when CMD => - if csr_valid = '1' then - state <= CSR; - elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then state <= MWRITE when wb_in.we = '1' else MREAD; end if; when MWRITE => @@ -252,8 +258,6 @@ begin if user_port0_rdata_valid = '1' then state <= CMD; end if; - when CSR => - state <= CMD; end case; end if; end if; @@ -283,10 +287,17 @@ begin init_error => init_error, user_clk => system_clk, user_rst => dram_user_reset, - csr_port0_adr => csr_port0_adr, - csr_port0_we => csr_port0_we, - csr_port0_dat_w => csr_port0_dat_w, - csr_port0_dat_r => csr_port0_dat_r, + wb_ctrl_adr => wb_ctrl_adr, + wb_ctrl_dat_w => wb_ctrl_dat_w, + wb_ctrl_dat_r => wb_ctrl_dat_r, + wb_ctrl_sel => wb_ctrl_sel, + wb_ctrl_cyc => wb_ctrl_cyc, + wb_ctrl_stb => wb_ctrl_stb, + wb_ctrl_ack => wb_ctrl_ack, + wb_ctrl_we => wb_ctrl_we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, user_port_native_0_cmd_valid => user_port0_cmd_valid, user_port_native_0_cmd_ready => user_port0_cmd_ready, user_port_native_0_cmd_we => user_port0_cmd_we, diff --git a/litedram/gen-src/wrapper-self-init.vhdl b/litedram/gen-src/wrapper-self-init.vhdl index 0664866..34e69e3 100644 --- a/litedram/gen-src/wrapper-self-init.vhdl +++ b/litedram/gen-src/wrapper-self-init.vhdl @@ -25,7 +25,7 @@ entity litedram_wrapper is -- Wishbone ports: wb_in : in wishbone_master_out; wb_out : out wishbone_slave_out; - wb_is_csr : in std_ulogic; + wb_is_ctrl : in std_ulogic; wb_is_init : in std_ulogic; -- Init core serial debug @@ -123,7 +123,7 @@ begin ad3 <= wb_in.adr(3); -- DRAM interface signals - user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; user_port0_wdata_valid <= '1' when state = MWRITE else '0'; @@ -134,10 +134,10 @@ begin "00000000" & wb_in.sel; -- Wishbone out signals. CSR and init memory do nothing, just ack - wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else + wb_out.ack <= '1' when (wb_is_ctrl = '1' or wb_is_init = '1') else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else + wb_out.dat <= (others => '0') when (wb_is_ctrl = '1' or wb_is_init = '1') else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl index 46ae4b1..fd9f3bd 100644 --- a/litedram/generated/arty/litedram-wrapper.vhdl +++ b/litedram/generated/arty/litedram-wrapper.vhdl @@ -25,7 +25,7 @@ entity litedram_wrapper is -- Wishbone ports: wb_in : in wishbone_master_out; wb_out : out wishbone_slave_out; - wb_is_csr : in std_ulogic; + wb_is_ctrl : in std_ulogic; wb_is_init : in std_ulogic; -- Init core serial debug @@ -58,32 +58,39 @@ end entity litedram_wrapper; architecture behaviour of litedram_wrapper is component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - csr_port0_adr : in std_ulogic_vector(13 downto 0); - csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(31 downto 0); - csr_port0_dat_r : out std_ulogic_vector(31 downto 0); + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -112,20 +119,19 @@ architecture behaviour of litedram_wrapper is signal ad3 : std_ulogic; - signal dram_user_reset : std_ulogic; - - signal csr_port0_adr : std_ulogic_vector(13 downto 0); - signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); - signal csr_port_read_comb : std_ulogic_vector(63 downto 0); - signal csr_valid : std_ulogic; - signal csr_write_valid : std_ulogic; + signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); + signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); + signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); + signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); + signal wb_ctrl_cyc : std_ulogic; + signal wb_ctrl_stb : std_ulogic; + signal wb_ctrl_ack : std_ulogic; + signal wb_ctrl_we : std_ulogic; signal wb_init_in : wishbone_master_out; signal wb_init_out : wishbone_slave_out; - type state_t is (CMD, MWRITE, MREAD, CSR); + type state_t is (CMD, MWRITE, MREAD); signal state : state_t; constant INIT_RAM_SIZE : integer := 16384; @@ -192,7 +198,7 @@ begin ad3 <= wb_in.adr(3); -- DRAM data interface signals - user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; user_port0_wdata_valid <= '1' when state = MWRITE else '0'; @@ -202,31 +208,28 @@ begin user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else "00000000" & wb_in.sel; - -- DRAM CSR interface signals. We only support access to the bottom byte - csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; - csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(31 downto 0); - csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + -- DRAM ctrl interface signals + wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2); + wb_ctrl_dat_w <= wb_in.dat(31 downto 0); + wb_ctrl_sel <= wb_in.sel(3 downto 0); + wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl; + wb_ctrl_stb <= wb_in.stb and wb_is_ctrl; + wb_ctrl_we <= wb_in.we; -- Wishbone out signals - wb_out.ack <= '1' when state = CSR else + wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else wb_init_out.ack when wb_is_init = '1' else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000" & csr_port0_dat_r; - wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); -- We don't do pipelining yet. wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - -- Reset ignored, the reset controller use the pll lock signal, - -- and alternate core reset address set when DRAM is not initialized. - -- - system_reset <= '0'; + -- Use alternate core reset address set when DRAM is not initialized. core_alt_reset <= not init_done; -- State machine @@ -234,14 +237,12 @@ begin begin if rising_edge(system_clk) then - if dram_user_reset = '1' then + if system_reset = '1' then state <= CMD; else case state is when CMD => - if csr_valid = '1' then - state <= CSR; - elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then state <= MWRITE when wb_in.we = '1' else MREAD; end if; when MWRITE => @@ -252,8 +253,6 @@ begin if user_port0_rdata_valid = '1' then state <= CMD; end if; - when CSR => - state <= CMD; end case; end if; end if; @@ -282,11 +281,18 @@ begin init_done => init_done, init_error => init_error, user_clk => system_clk, - user_rst => dram_user_reset, - csr_port0_adr => csr_port0_adr, - csr_port0_we => csr_port0_we, - csr_port0_dat_w => csr_port0_dat_w, - csr_port0_dat_r => csr_port0_dat_r, + user_rst => system_reset, + wb_ctrl_adr => wb_ctrl_adr, + wb_ctrl_dat_w => wb_ctrl_dat_w, + wb_ctrl_dat_r => wb_ctrl_dat_r, + wb_ctrl_sel => wb_ctrl_sel, + wb_ctrl_cyc => wb_ctrl_cyc, + wb_ctrl_stb => wb_ctrl_stb, + wb_ctrl_ack => wb_ctrl_ack, + wb_ctrl_we => wb_ctrl_we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, user_port_native_0_cmd_valid => user_port0_cmd_valid, user_port_native_0_cmd_ready => user_port0_cmd_ready, user_port_native_0_cmd_we => user_port0_cmd_we, diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 4f7ad0f..508f707 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ffff782107c6 3d80000060213f00 798c07c6618c0000 -618c1168658cffff +618c108c658cffff 4e8004217d8903a6 0000000048000002 0000000000000000 @@ -510,124 +510,113 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429e003c4c0001 -600000003d20c000 -7929002061292000 -3d40c000f92280a8 -614a201839200035 -7c0004ac794a0020 -4e8000207d2057aa -0000000000000000 -3c4c000100000000 -6000000038429dbc -39290010e92280a8 -7d204eaa7c0004ac -4082ffe871290008 -e92280a860000000 -7c604faa7c0004ac -000000004e800020 -0000000000000000 -38429d783c4c0001 +38429f003c4c0001 fbc1fff07c0802a6 -7fc32214fbe1fff8 -f80100107c7f1b78 -7fbff040f821ffd1 -38210030409e000c -893f000048001ab4 -409e000c2f89000a -4bffff813860000d -3bff0001887f0000 -4bffffd04bffff75 +f8010010fbe1fff8 +3be10020f821fe91 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-0020642562202c64 +6432302562202c64 +0000000000000020 0000000078323025 6f6e204d41524453 207265646e752077 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 18cb7f1..991adbd 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:11 +// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:26 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -22,10 +22,17 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [13:0] csr_port0_adr, - input wire csr_port0_we, - input wire [31:0] csr_port0_dat_w, - output wire [31:0] csr_port0_dat_r, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -41,6 +48,21 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +wire [31:0] litedramcore_dat_w; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +wire [31:0] litedramcore_wishbone_dat_r; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -185,8 +207,8 @@ wire a7ddrphy_dq_t0; wire [7:0] a7ddrphy_dq_i_data0; wire [7:0] a7ddrphy_bitslip0_i; reg [7:0] a7ddrphy_bitslip0_o = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value = 3'd0; -reg [15:0] a7ddrphy_bitslip0_r = 16'd0; +reg [3:0] a7ddrphy_bitslip0_value = 4'd0; +reg [23:0] a7ddrphy_bitslip0_r = 24'd0; wire a7ddrphy_dq_o_nodelay1; wire a7ddrphy_dq_i_nodelay1; wire a7ddrphy_dq_i_delayed1; @@ -194,8 +216,8 @@ wire a7ddrphy_dq_t1; wire [7:0] a7ddrphy_dq_i_data1; wire [7:0] a7ddrphy_bitslip1_i; reg [7:0] a7ddrphy_bitslip1_o = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value = 3'd0; -reg [15:0] a7ddrphy_bitslip1_r = 16'd0; +reg [3:0] a7ddrphy_bitslip1_value = 4'd0; +reg [23:0] a7ddrphy_bitslip1_r = 24'd0; wire a7ddrphy_dq_o_nodelay2; wire a7ddrphy_dq_i_nodelay2; wire a7ddrphy_dq_i_delayed2; @@ -203,8 +225,8 @@ wire a7ddrphy_dq_t2; wire [7:0] a7ddrphy_dq_i_data2; wire [7:0] a7ddrphy_bitslip2_i; reg [7:0] a7ddrphy_bitslip2_o = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value = 3'd0; -reg [15:0] a7ddrphy_bitslip2_r = 16'd0; +reg [3:0] a7ddrphy_bitslip2_value = 4'd0; +reg [23:0] a7ddrphy_bitslip2_r = 24'd0; wire a7ddrphy_dq_o_nodelay3; wire a7ddrphy_dq_i_nodelay3; wire a7ddrphy_dq_i_delayed3; @@ -212,8 +234,8 @@ wire a7ddrphy_dq_t3; wire [7:0] a7ddrphy_dq_i_data3; wire [7:0] a7ddrphy_bitslip3_i; reg [7:0] a7ddrphy_bitslip3_o = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value = 3'd0; -reg [15:0] a7ddrphy_bitslip3_r = 16'd0; +reg [3:0] a7ddrphy_bitslip3_value = 4'd0; +reg [23:0] a7ddrphy_bitslip3_r = 24'd0; wire a7ddrphy_dq_o_nodelay4; wire a7ddrphy_dq_i_nodelay4; wire a7ddrphy_dq_i_delayed4; @@ -221,8 +243,8 @@ wire a7ddrphy_dq_t4; wire [7:0] a7ddrphy_dq_i_data4; wire [7:0] a7ddrphy_bitslip4_i; reg [7:0] a7ddrphy_bitslip4_o = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value = 3'd0; -reg [15:0] a7ddrphy_bitslip4_r = 16'd0; +reg [3:0] a7ddrphy_bitslip4_value = 4'd0; +reg [23:0] a7ddrphy_bitslip4_r = 24'd0; wire a7ddrphy_dq_o_nodelay5; wire a7ddrphy_dq_i_nodelay5; wire a7ddrphy_dq_i_delayed5; @@ -230,8 +252,8 @@ wire a7ddrphy_dq_t5; wire [7:0] a7ddrphy_dq_i_data5; wire [7:0] a7ddrphy_bitslip5_i; reg [7:0] a7ddrphy_bitslip5_o = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value = 3'd0; -reg [15:0] a7ddrphy_bitslip5_r = 16'd0; +reg [3:0] a7ddrphy_bitslip5_value = 4'd0; +reg [23:0] a7ddrphy_bitslip5_r = 24'd0; wire a7ddrphy_dq_o_nodelay6; wire a7ddrphy_dq_i_nodelay6; wire a7ddrphy_dq_i_delayed6; @@ -239,8 +261,8 @@ wire a7ddrphy_dq_t6; wire [7:0] a7ddrphy_dq_i_data6; wire [7:0] a7ddrphy_bitslip6_i; reg [7:0] a7ddrphy_bitslip6_o = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value = 3'd0; -reg [15:0] a7ddrphy_bitslip6_r = 16'd0; +reg [3:0] a7ddrphy_bitslip6_value = 4'd0; +reg [23:0] a7ddrphy_bitslip6_r = 24'd0; wire a7ddrphy_dq_o_nodelay7; wire a7ddrphy_dq_i_nodelay7; wire a7ddrphy_dq_i_delayed7; @@ -248,8 +270,8 @@ wire a7ddrphy_dq_t7; wire [7:0] a7ddrphy_dq_i_data7; wire [7:0] a7ddrphy_bitslip7_i; reg [7:0] a7ddrphy_bitslip7_o = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value = 3'd0; -reg [15:0] a7ddrphy_bitslip7_r = 16'd0; +reg [3:0] a7ddrphy_bitslip7_value = 4'd0; +reg [23:0] a7ddrphy_bitslip7_r = 24'd0; wire a7ddrphy_dq_o_nodelay8; wire a7ddrphy_dq_i_nodelay8; wire a7ddrphy_dq_i_delayed8; @@ -257,8 +279,8 @@ wire a7ddrphy_dq_t8; wire [7:0] a7ddrphy_dq_i_data8; wire [7:0] a7ddrphy_bitslip8_i; reg [7:0] a7ddrphy_bitslip8_o = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value = 3'd0; -reg [15:0] a7ddrphy_bitslip8_r = 16'd0; +reg [3:0] a7ddrphy_bitslip8_value = 4'd0; +reg [23:0] a7ddrphy_bitslip8_r = 24'd0; wire a7ddrphy_dq_o_nodelay9; wire a7ddrphy_dq_i_nodelay9; wire a7ddrphy_dq_i_delayed9; @@ -266,8 +288,8 @@ wire a7ddrphy_dq_t9; wire [7:0] a7ddrphy_dq_i_data9; wire [7:0] a7ddrphy_bitslip9_i; reg [7:0] a7ddrphy_bitslip9_o = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value = 3'd0; -reg [15:0] a7ddrphy_bitslip9_r = 16'd0; +reg [3:0] a7ddrphy_bitslip9_value = 4'd0; +reg [23:0] a7ddrphy_bitslip9_r = 24'd0; wire a7ddrphy_dq_o_nodelay10; wire a7ddrphy_dq_i_nodelay10; wire a7ddrphy_dq_i_delayed10; @@ -275,8 +297,8 @@ wire a7ddrphy_dq_t10; wire [7:0] a7ddrphy_dq_i_data10; wire [7:0] a7ddrphy_bitslip10_i; reg [7:0] a7ddrphy_bitslip10_o = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value = 3'd0; -reg [15:0] a7ddrphy_bitslip10_r = 16'd0; +reg [3:0] a7ddrphy_bitslip10_value = 4'd0; +reg [23:0] a7ddrphy_bitslip10_r = 24'd0; wire a7ddrphy_dq_o_nodelay11; wire a7ddrphy_dq_i_nodelay11; wire a7ddrphy_dq_i_delayed11; @@ -284,8 +306,8 @@ wire a7ddrphy_dq_t11; wire [7:0] a7ddrphy_dq_i_data11; wire [7:0] a7ddrphy_bitslip11_i; reg [7:0] a7ddrphy_bitslip11_o = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value = 3'd0; -reg [15:0] a7ddrphy_bitslip11_r = 16'd0; +reg [3:0] a7ddrphy_bitslip11_value = 4'd0; +reg [23:0] a7ddrphy_bitslip11_r = 24'd0; wire a7ddrphy_dq_o_nodelay12; wire a7ddrphy_dq_i_nodelay12; wire a7ddrphy_dq_i_delayed12; @@ -293,8 +315,8 @@ wire a7ddrphy_dq_t12; wire [7:0] a7ddrphy_dq_i_data12; wire [7:0] a7ddrphy_bitslip12_i; reg [7:0] a7ddrphy_bitslip12_o = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value = 3'd0; -reg [15:0] a7ddrphy_bitslip12_r = 16'd0; +reg [3:0] a7ddrphy_bitslip12_value = 4'd0; +reg [23:0] a7ddrphy_bitslip12_r = 24'd0; wire a7ddrphy_dq_o_nodelay13; wire a7ddrphy_dq_i_nodelay13; wire a7ddrphy_dq_i_delayed13; @@ -302,8 +324,8 @@ wire a7ddrphy_dq_t13; wire [7:0] a7ddrphy_dq_i_data13; wire [7:0] a7ddrphy_bitslip13_i; reg [7:0] a7ddrphy_bitslip13_o = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value = 3'd0; -reg [15:0] a7ddrphy_bitslip13_r = 16'd0; +reg [3:0] a7ddrphy_bitslip13_value = 4'd0; +reg [23:0] a7ddrphy_bitslip13_r = 24'd0; wire a7ddrphy_dq_o_nodelay14; wire a7ddrphy_dq_i_nodelay14; wire a7ddrphy_dq_i_delayed14; @@ -311,8 +333,8 @@ wire a7ddrphy_dq_t14; wire [7:0] a7ddrphy_dq_i_data14; wire [7:0] a7ddrphy_bitslip14_i; reg [7:0] a7ddrphy_bitslip14_o = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value = 3'd0; -reg [15:0] a7ddrphy_bitslip14_r = 16'd0; +reg [3:0] a7ddrphy_bitslip14_value = 4'd0; +reg [23:0] a7ddrphy_bitslip14_r = 24'd0; wire a7ddrphy_dq_o_nodelay15; wire a7ddrphy_dq_i_nodelay15; wire a7ddrphy_dq_i_delayed15; @@ -320,8 +342,8 @@ wire a7ddrphy_dq_t15; wire [7:0] a7ddrphy_dq_i_data15; wire [7:0] a7ddrphy_bitslip15_i; reg [7:0] a7ddrphy_bitslip15_o = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value = 3'd0; -reg [15:0] a7ddrphy_bitslip15_r = 16'd0; +reg [3:0] a7ddrphy_bitslip15_value = 4'd0; +reg [23:0] a7ddrphy_bitslip15_r = 24'd0; wire [7:0] a7ddrphy_rddata_en; reg [7:0] a7ddrphy_rddata_en_last = 8'd0; wire [3:0] a7ddrphy_wrdata_en; @@ -1483,10 +1505,17 @@ reg init_done_storage = 1'd0; reg init_done_re = 1'd0; reg init_error_storage = 1'd0; reg init_error_re = 1'd0; -wire [13:0] csr_port_adr; -wire csr_port_we; -wire [31:0] csr_port_dat_w; -wire [31:0] csr_port_dat_r; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1498,6 +1527,8 @@ wire [15:0] user_port_wdata_payload_we; wire user_port_rdata_valid; wire user_port_rdata_ready; wire [127:0] user_port_rdata_payload_data; +reg state = 1'd0; +reg next_state = 1'd0; wire pll_fb0; wire pll_fb1; reg [1:0] refresher_state = 2'd0; @@ -1774,10 +1805,17 @@ initial dummy_s <= 1'd0; // synthesis translate_on assign init_done = init_done_storage; assign init_error = init_error_storage; -assign csr_port_adr = csr_port0_adr; -assign csr_port_we = csr_port0_we; -assign csr_port_dat_w = csr_port0_dat_w; -assign csr_port0_dat_r = csr_port_dat_r; +assign wb_bus_adr = wb_ctrl_adr; +assign wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wb_ctrl_sel; +assign wb_bus_cyc = wb_ctrl_cyc; +assign wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = wb_bus_ack; +assign wb_bus_we = wb_ctrl_we; +assign wb_bus_cti = wb_ctrl_cti; +assign wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; assign user_port_cmd_valid = user_port_native_0_cmd_valid; @@ -1791,6 +1829,84 @@ assign user_port_wdata_payload_data = user_port_native_0_wdata_data; assign user_port_native_0_rdata_valid = user_port_rdata_valid; assign user_port_rdata_ready = user_port_native_0_rdata_ready; assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign litedramcore_dat_w = litedramcore_wishbone_dat_w; +assign litedramcore_wishbone_dat_r = litedramcore_dat_r; + +// synthesis translate_off +reg dummy_d; +// synthesis translate_on +always @(*) begin + next_state <= 1'd0; + next_state <= state; + case (state) + 1'd1: begin + next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_1; +// synthesis translate_on +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (state) + 1'd1: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_1 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_2; +// synthesis translate_on +always @(*) begin + litedramcore_adr <= 14'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr <= litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_2 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_3; +// synthesis translate_on +always @(*) begin + litedramcore_we <= 1'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we <= litedramcore_wishbone_we; + end + end + endcase +// synthesis translate_off + dummy_d_3 = dummy_s; +// synthesis translate_on +end assign sys_pll_reset = rst; assign pll_locked = sys_pll_locked; assign iodelay_pll_reset = rst; @@ -1803,7 +1919,7 @@ assign iodelay_clk = s7pll1_clkout_buf; assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0; // synthesis translate_off -reg dummy_d; +reg dummy_d_4; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p0_rddata <= 32'd0; @@ -1840,12 +1956,12 @@ always @(*) begin a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0]; a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1]; // synthesis translate_off - dummy_d = dummy_s; + dummy_d_4 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_1; +reg dummy_d_5; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p1_rddata <= 32'd0; @@ -1882,12 +1998,12 @@ always @(*) begin a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2]; a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3]; // synthesis translate_off - dummy_d_1 = dummy_s; + dummy_d_5 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_2; +reg dummy_d_6; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p2_rddata <= 32'd0; @@ -1924,12 +2040,12 @@ always @(*) begin a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4]; a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5]; // synthesis translate_off - dummy_d_2 = dummy_s; + dummy_d_6 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_3; +reg dummy_d_7; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p3_rddata <= 32'd0; @@ -1966,7 +2082,7 @@ always @(*) begin a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6]; a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7]; // synthesis translate_off - dummy_d_3 = dummy_s; + dummy_d_7 = dummy_s; // synthesis translate_on end assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1; @@ -1989,7 +2105,7 @@ assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en} assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2]; // synthesis translate_off -reg dummy_d_4; +reg dummy_d_8; // synthesis translate_on always @(*) begin a7ddrphy_dqs_oe <= 1'd0; @@ -1999,14 +2115,14 @@ always @(*) begin a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; end // synthesis translate_off - dummy_d_4 = dummy_s; + dummy_d_8 = dummy_s; // synthesis translate_on end assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2])); assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2])); // synthesis translate_off -reg dummy_d_5; +reg dummy_d_9; // synthesis translate_on always @(*) begin a7ddrphy_dqspattern_o0 <= 8'd0; @@ -2024,12 +2140,12 @@ always @(*) begin end end // synthesis translate_off - dummy_d_5 = dummy_s; + dummy_d_9 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_6; +reg dummy_d_10; // synthesis translate_on always @(*) begin a7ddrphy_bitslip0_o <= 8'd0; @@ -2058,14 +2174,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15]; + end endcase // synthesis translate_off - dummy_d_6 = dummy_s; + dummy_d_10 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_7; +reg dummy_d_11; // synthesis translate_on always @(*) begin a7ddrphy_bitslip1_o <= 8'd0; @@ -2094,14 +2234,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15]; + end endcase // synthesis translate_off - dummy_d_7 = dummy_s; + dummy_d_11 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_8; +reg dummy_d_12; // synthesis translate_on always @(*) begin a7ddrphy_bitslip2_o <= 8'd0; @@ -2130,14 +2294,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15]; + end endcase // synthesis translate_off - dummy_d_8 = dummy_s; + dummy_d_12 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_9; +reg dummy_d_13; // synthesis translate_on always @(*) begin a7ddrphy_bitslip3_o <= 8'd0; @@ -2166,14 +2354,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15]; + end endcase // synthesis translate_off - dummy_d_9 = dummy_s; + dummy_d_13 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_10; +reg dummy_d_14; // synthesis translate_on always @(*) begin a7ddrphy_bitslip4_o <= 8'd0; @@ -2202,14 +2414,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15]; + end endcase // synthesis translate_off - dummy_d_10 = dummy_s; + dummy_d_14 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_11; +reg dummy_d_15; // synthesis translate_on always @(*) begin a7ddrphy_bitslip5_o <= 8'd0; @@ -2238,14 +2474,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15]; + end endcase // synthesis translate_off - dummy_d_11 = dummy_s; + dummy_d_15 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_12; +reg dummy_d_16; // synthesis translate_on always @(*) begin a7ddrphy_bitslip6_o <= 8'd0; @@ -2274,14 +2534,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15]; + end endcase // synthesis translate_off - dummy_d_12 = dummy_s; + dummy_d_16 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_13; +reg dummy_d_17; // synthesis translate_on always @(*) begin a7ddrphy_bitslip7_o <= 8'd0; @@ -2310,14 +2594,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15]; + end endcase // synthesis translate_off - dummy_d_13 = dummy_s; + dummy_d_17 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_14; +reg dummy_d_18; // synthesis translate_on always @(*) begin a7ddrphy_bitslip8_o <= 8'd0; @@ -2346,14 +2654,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15]; + end endcase // synthesis translate_off - dummy_d_14 = dummy_s; + dummy_d_18 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_15; +reg dummy_d_19; // synthesis translate_on always @(*) begin a7ddrphy_bitslip9_o <= 8'd0; @@ -2382,14 +2714,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15]; + end endcase // synthesis translate_off - dummy_d_15 = dummy_s; + dummy_d_19 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_16; +reg dummy_d_20; // synthesis translate_on always @(*) begin a7ddrphy_bitslip10_o <= 8'd0; @@ -2418,14 +2774,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15]; + end endcase // synthesis translate_off - dummy_d_16 = dummy_s; + dummy_d_20 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_17; +reg dummy_d_21; // synthesis translate_on always @(*) begin a7ddrphy_bitslip11_o <= 8'd0; @@ -2454,14 +2834,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7]; end - endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on -end - + 4'd8: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15]; + end + endcase // synthesis translate_off -reg dummy_d_18; + dummy_d_21 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_22; // synthesis translate_on always @(*) begin a7ddrphy_bitslip12_o <= 8'd0; @@ -2490,14 +2894,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15]; + end endcase // synthesis translate_off - dummy_d_18 = dummy_s; + dummy_d_22 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_19; +reg dummy_d_23; // synthesis translate_on always @(*) begin a7ddrphy_bitslip13_o <= 8'd0; @@ -2526,14 +2954,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15]; + end endcase // synthesis translate_off - dummy_d_19 = dummy_s; + dummy_d_23 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_20; +reg dummy_d_24; // synthesis translate_on always @(*) begin a7ddrphy_bitslip14_o <= 8'd0; @@ -2562,14 +3014,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15]; + end endcase // synthesis translate_off - dummy_d_20 = dummy_s; + dummy_d_24 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_21; +reg dummy_d_25; // synthesis translate_on always @(*) begin a7ddrphy_bitslip15_o <= 8'd0; @@ -2598,9 +3074,33 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15]; + end endcase // synthesis translate_off - dummy_d_21 = dummy_s; + dummy_d_25 = dummy_s; // synthesis translate_on end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; @@ -2732,75 +3232,15 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on -always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; - end else begin - litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; - end -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on -always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; - end else begin - litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; - end -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on -always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; - end else begin - litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; - end -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on -always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; - end else begin - litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; - end -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on -end - // synthesis translate_off reg dummy_d_26; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; + litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_26 = dummy_s; @@ -2811,10 +3251,11 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata <= 32'd0; + litedramcore_master_p2_odt <= 1'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin - litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_27 = dummy_s; @@ -2825,11 +3266,11 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; + litedramcore_master_p2_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_28 = dummy_s; @@ -2840,10 +3281,11 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata_valid <= 1'd0; + litedramcore_master_p2_act_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_29 = dummy_s; @@ -2854,11 +3296,11 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; + litedramcore_master_p2_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_30 = dummy_s; @@ -2869,11 +3311,10 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; + litedramcore_inti_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_31 = dummy_s; @@ -2884,11 +3325,11 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - litedramcore_master_p0_address <= 14'd0; + litedramcore_master_p2_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p0_address <= litedramcore_inti_p0_address; + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_32 = dummy_s; @@ -2899,11 +3340,10 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - litedramcore_master_p0_bank <= 3'd0; + litedramcore_inti_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin - litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_33 = dummy_s; @@ -2914,11 +3354,11 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; + litedramcore_master_p2_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_34 = dummy_s; @@ -2929,11 +3369,11 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; + litedramcore_master_p2_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_35 = dummy_s; @@ -2944,10 +3384,11 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; + litedramcore_master_p3_address <= 14'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_master_p3_address <= litedramcore_slave_p3_address; end else begin + litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_36 = dummy_s; @@ -2958,11 +3399,11 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; + litedramcore_master_p3_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_37 = dummy_s; @@ -2973,10 +3414,11 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_master_p3_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end else begin + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_38 = dummy_s; @@ -2987,11 +3429,11 @@ end reg dummy_d_39; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_master_p3_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_39 = dummy_s; @@ -3002,11 +3444,11 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cke <= 1'd0; + litedramcore_master_p3_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_40 = dummy_s; @@ -3017,11 +3459,10 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - litedramcore_master_p0_odt <= 1'd0; + litedramcore_slave_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end else begin - litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_41 = dummy_s; @@ -3032,11 +3473,11 @@ end reg dummy_d_42; // synthesis translate_on always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; + litedramcore_master_p3_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3047,11 +3488,10 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; + litedramcore_slave_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin - litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_43 = dummy_s; @@ -3062,11 +3502,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; + litedramcore_master_p3_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3077,10 +3517,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata <= 32'd0; + litedramcore_master_p3_odt <= 1'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3091,11 +3532,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; + litedramcore_master_p3_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3106,10 +3547,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata_valid <= 1'd0; + litedramcore_master_p3_act_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3120,11 +3562,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; + litedramcore_master_p3_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3135,11 +3577,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; + litedramcore_inti_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3150,11 +3591,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - litedramcore_master_p1_address <= 14'd0; + litedramcore_master_p3_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p1_address <= litedramcore_inti_p1_address; + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3165,11 +3606,10 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - litedramcore_master_p1_bank <= 3'd0; + litedramcore_inti_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3180,11 +3620,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; + litedramcore_master_p3_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3195,11 +3635,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; + litedramcore_master_p3_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3210,11 +3650,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; + litedramcore_master_p0_address <= 14'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + litedramcore_master_p0_address <= litedramcore_slave_p0_address; end else begin - litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; + litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3225,10 +3665,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; + litedramcore_master_p0_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3239,11 +3680,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; + litedramcore_master_p0_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3254,10 +3695,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; + litedramcore_master_p0_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end else begin + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3268,11 +3710,10 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cke <= 1'd0; + litedramcore_slave_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end else begin - litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3283,11 +3724,11 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - litedramcore_master_p1_odt <= 1'd0; + litedramcore_master_p0_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end else begin - litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -3298,11 +3739,10 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3313,11 +3753,11 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -3328,11 +3768,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; + litedramcore_master_p0_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3343,10 +3783,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; + litedramcore_master_p0_odt <= 1'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3357,11 +3798,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; + litedramcore_master_p0_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3372,10 +3813,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; + litedramcore_master_p0_act_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3386,11 +3828,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; + litedramcore_master_p0_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3401,11 +3843,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; + litedramcore_inti_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3416,10 +3857,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; + litedramcore_master_p0_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3430,11 +3872,10 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - litedramcore_master_p2_address <= 14'd0; + litedramcore_inti_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p2_address <= litedramcore_inti_p2_address; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3445,11 +3886,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - litedramcore_master_p2_bank <= 3'd0; + litedramcore_master_p0_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3460,11 +3901,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; + litedramcore_master_p0_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3475,11 +3916,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; + litedramcore_master_p1_address <= 14'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3490,10 +3931,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; + litedramcore_master_p1_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3504,11 +3946,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; + litedramcore_master_p1_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3533,11 +3975,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; + litedramcore_master_p1_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3548,10 +3990,11 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_master_p1_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -3562,11 +4005,10 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cke <= 1'd0; + litedramcore_slave_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin - litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -3577,11 +4019,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - litedramcore_master_p2_odt <= 1'd0; + litedramcore_master_p1_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -3592,11 +4034,10 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; + litedramcore_slave_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin - litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -3607,11 +4048,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; + litedramcore_master_p1_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -3622,11 +4063,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; + litedramcore_master_p1_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin - litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -3637,10 +4078,10 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata <= 32'd0; + litedramcore_slave_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin - litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -3651,11 +4092,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; + litedramcore_master_p1_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -3666,10 +4107,11 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata_valid <= 1'd0; + litedramcore_master_p1_act_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; end else begin - litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -3680,11 +4122,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; + litedramcore_master_p1_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -3695,11 +4137,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; + litedramcore_inti_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -3710,11 +4151,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - litedramcore_master_p3_address <= 14'd0; + litedramcore_master_p1_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p3_address <= litedramcore_inti_p3_address; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -3725,11 +4166,10 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - litedramcore_master_p3_bank <= 3'd0; + litedramcore_inti_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -3740,11 +4180,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; + litedramcore_master_p1_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -3755,11 +4195,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; + litedramcore_master_p1_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -3770,11 +4210,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; + litedramcore_master_p2_address <= 14'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -3785,16 +4225,76 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; + litedramcore_master_p2_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_93 = dummy_s; // synthesis translate_on end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + end +// synthesis translate_off + dummy_d_97 = dummy_s; +// synthesis translate_on +end assign litedramcore_inti_p0_cke = litedramcore_storage[1]; assign litedramcore_inti_p1_cke = litedramcore_storage[1]; assign litedramcore_inti_p2_cke = litedramcore_storage[1]; @@ -3809,7 +4309,7 @@ assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; // synthesis translate_off -reg dummy_d_94; +reg dummy_d_98; // synthesis translate_on always @(*) begin litedramcore_inti_p0_cas_n <= 1'd1; @@ -3819,12 +4319,12 @@ always @(*) begin litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_94 = dummy_s; + dummy_d_98 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_95; +reg dummy_d_99; // synthesis translate_on always @(*) begin litedramcore_inti_p0_cs_n <= 1'd1; @@ -3834,12 +4334,12 @@ always @(*) begin litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_95 = dummy_s; + dummy_d_99 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_96; +reg dummy_d_100; // synthesis translate_on always @(*) begin litedramcore_inti_p0_ras_n <= 1'd1; @@ -3849,12 +4349,12 @@ always @(*) begin litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_96 = dummy_s; + dummy_d_100 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_97; +reg dummy_d_101; // synthesis translate_on always @(*) begin litedramcore_inti_p0_we_n <= 1'd1; @@ -3864,7 +4364,7 @@ always @(*) begin litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off - dummy_d_97 = dummy_s; + dummy_d_101 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; @@ -3875,7 +4375,7 @@ assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_98; +reg dummy_d_102; // synthesis translate_on always @(*) begin litedramcore_inti_p1_cas_n <= 1'd1; @@ -3885,12 +4385,12 @@ always @(*) begin litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_98 = dummy_s; + dummy_d_102 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_99; +reg dummy_d_103; // synthesis translate_on always @(*) begin litedramcore_inti_p1_cs_n <= 1'd1; @@ -3900,12 +4400,12 @@ always @(*) begin litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_99 = dummy_s; + dummy_d_103 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_100; +reg dummy_d_104; // synthesis translate_on always @(*) begin litedramcore_inti_p1_ras_n <= 1'd1; @@ -3915,12 +4415,12 @@ always @(*) begin litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_100 = dummy_s; + dummy_d_104 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_101; +reg dummy_d_105; // synthesis translate_on always @(*) begin litedramcore_inti_p1_we_n <= 1'd1; @@ -3930,7 +4430,7 @@ always @(*) begin litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off - dummy_d_101 = dummy_s; + dummy_d_105 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; @@ -3941,7 +4441,7 @@ assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_102; +reg dummy_d_106; // synthesis translate_on always @(*) begin litedramcore_inti_p2_cas_n <= 1'd1; @@ -3951,12 +4451,12 @@ always @(*) begin litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_102 = dummy_s; + dummy_d_106 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_103; +reg dummy_d_107; // synthesis translate_on always @(*) begin litedramcore_inti_p2_cs_n <= 1'd1; @@ -3966,12 +4466,12 @@ always @(*) begin litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_103 = dummy_s; + dummy_d_107 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_104; +reg dummy_d_108; // synthesis translate_on always @(*) begin litedramcore_inti_p2_ras_n <= 1'd1; @@ -3981,12 +4481,12 @@ always @(*) begin litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_104 = dummy_s; + dummy_d_108 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_105; +reg dummy_d_109; // synthesis translate_on always @(*) begin litedramcore_inti_p2_we_n <= 1'd1; @@ -3996,7 +4496,7 @@ always @(*) begin litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off - dummy_d_105 = dummy_s; + dummy_d_109 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; @@ -4007,7 +4507,7 @@ assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_106; +reg dummy_d_110; // synthesis translate_on always @(*) begin litedramcore_inti_p3_cas_n <= 1'd1; @@ -4017,12 +4517,12 @@ always @(*) begin litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_106 = dummy_s; + dummy_d_110 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_107; +reg dummy_d_111; // synthesis translate_on always @(*) begin litedramcore_inti_p3_cs_n <= 1'd1; @@ -4032,12 +4532,12 @@ always @(*) begin litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_107 = dummy_s; + dummy_d_111 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_108; +reg dummy_d_112; // synthesis translate_on always @(*) begin litedramcore_inti_p3_ras_n <= 1'd1; @@ -4047,12 +4547,12 @@ always @(*) begin litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_108 = dummy_s; + dummy_d_112 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_109; +reg dummy_d_113; // synthesis translate_on always @(*) begin litedramcore_inti_p3_we_n <= 1'd1; @@ -4062,7 +4562,7 @@ always @(*) begin litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off - dummy_d_109 = dummy_s; + dummy_d_113 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; @@ -4142,7 +4642,7 @@ assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; // synthesis translate_off -reg dummy_d_110; +reg dummy_d_114; // synthesis translate_on always @(*) begin refresher_next_state <= 2'd0; @@ -4176,12 +4676,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_110 = dummy_s; + dummy_d_114 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_111; +reg dummy_d_115; // synthesis translate_on always @(*) begin litedramcore_cmd_valid <= 1'd0; @@ -4208,12 +4708,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_111 = dummy_s; + dummy_d_115 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_112; +reg dummy_d_116; // synthesis translate_on always @(*) begin litedramcore_zqcs_executer_start <= 1'd0; @@ -4234,12 +4734,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_112 = dummy_s; + dummy_d_116 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_113; +reg dummy_d_117; // synthesis translate_on always @(*) begin litedramcore_cmd_last <= 1'd0; @@ -4263,12 +4763,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_113 = dummy_s; + dummy_d_117 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_114; +reg dummy_d_118; // synthesis translate_on always @(*) begin litedramcore_sequencer_start0 <= 1'd0; @@ -4286,7 +4786,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_114 = dummy_s; + dummy_d_118 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; @@ -4305,7 +4805,7 @@ assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == lit assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off -reg dummy_d_115; +reg dummy_d_119; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= 14'd0; @@ -4315,7 +4815,7 @@ always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_115 = dummy_s; + dummy_d_119 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); @@ -4323,7 +4823,7 @@ assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_ assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); // synthesis translate_off -reg dummy_d_116; +reg dummy_d_120; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_auto_precharge <= 1'd0; @@ -4333,7 +4833,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_116 = dummy_s; + dummy_d_120 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -4355,7 +4855,7 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_117; +reg dummy_d_121; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -4365,7 +4865,7 @@ always @(*) begin litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_117 = dummy_s; + dummy_d_121 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; @@ -4378,7 +4878,7 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (lite assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_118; +reg dummy_d_122; // synthesis translate_on always @(*) begin bankmachine0_next_state <= 4'd0; @@ -4441,12 +4941,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_118 = dummy_s; + dummy_d_122 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_119; +reg dummy_d_123; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_req_rdata_valid <= 1'd0; @@ -4486,12 +4986,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_119 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_120; +reg dummy_d_124; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_124 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_125; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; @@ -4519,12 +5052,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_120 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_121; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -4567,12 +5100,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_121 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_122; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_open <= 1'd0; @@ -4600,12 +5133,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_127 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_128; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; @@ -4633,12 +5166,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_128 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_129; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; @@ -4675,12 +5208,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_129 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_130; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; @@ -4711,12 +5244,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_131; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_we <= 1'd0; @@ -4759,45 +5292,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_128; +reg dummy_d_132; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; @@ -4829,12 +5329,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_129; +reg dummy_d_133; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; @@ -4874,12 +5374,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_133 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_134; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; @@ -4919,12 +5419,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_134 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_135; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_req_wdata_ready <= 1'd0; @@ -4964,7 +5464,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_135 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; @@ -4983,7 +5483,7 @@ assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == lit assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_132; +reg dummy_d_136; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= 14'd0; @@ -4993,7 +5493,7 @@ always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_136 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); @@ -5001,7 +5501,7 @@ assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_ assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_133; +reg dummy_d_137; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_auto_precharge <= 1'd0; @@ -5011,7 +5511,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_137 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -5033,7 +5533,7 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_134; +reg dummy_d_138; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -5043,7 +5543,7 @@ always @(*) begin litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; @@ -5056,7 +5556,7 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (lite assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_135; +reg dummy_d_139; // synthesis translate_on always @(*) begin bankmachine1_next_state <= 4'd0; @@ -5119,12 +5619,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_135 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_136; +reg dummy_d_140; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_req_rdata_valid <= 1'd0; @@ -5164,26 +5664,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_136 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_137; +reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5197,26 +5697,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_137 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_138; +reg dummy_d_142; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5227,29 +5730,38 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_139; +reg dummy_d_143; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5263,27 +5775,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_144; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_open <= 1'd0; @@ -5311,12 +5811,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_145; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_close <= 1'd0; @@ -5344,12 +5844,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_146; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; @@ -5386,12 +5886,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_147; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; @@ -5422,12 +5922,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_148; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_we <= 1'd0; @@ -5470,12 +5970,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_149; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; @@ -5507,12 +6007,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_150; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; @@ -5552,12 +6052,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_151; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; @@ -5597,12 +6097,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_151 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_152; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_req_wdata_ready <= 1'd0; @@ -5642,7 +6142,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_152 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; @@ -5661,7 +6161,7 @@ assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == lit assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_149; +reg dummy_d_153; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= 14'd0; @@ -5671,7 +6171,7 @@ always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_153 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); @@ -5679,7 +6179,7 @@ assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_ assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); // synthesis translate_off -reg dummy_d_150; +reg dummy_d_154; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_auto_precharge <= 1'd0; @@ -5689,7 +6189,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_154 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -5711,7 +6211,7 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_151; +reg dummy_d_155; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -5721,7 +6221,7 @@ always @(*) begin litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; @@ -5734,7 +6234,7 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (lite assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_152; +reg dummy_d_156; // synthesis translate_on always @(*) begin bankmachine2_next_state <= 4'd0; @@ -5797,12 +6297,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; + dummy_d_156 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_153; +reg dummy_d_157; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_req_rdata_valid <= 1'd0; @@ -5842,12 +6342,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_153 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_154; +reg dummy_d_158; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_refresh_gnt <= 1'd0; @@ -5875,12 +6375,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_154 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_155; +reg dummy_d_159; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_valid <= 1'd0; @@ -5923,15 +6423,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_155 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_156; +reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -5939,7 +6439,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -5956,26 +6456,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -5989,26 +6489,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_158; +reg dummy_d_162; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6019,24 +6516,39 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_163; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6049,27 +6561,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_164; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; @@ -6100,12 +6600,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_165; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_we <= 1'd0; @@ -6148,12 +6648,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_162; +reg dummy_d_166; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; @@ -6185,12 +6685,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_167; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; @@ -6230,12 +6730,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_168; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; @@ -6275,12 +6775,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_169; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_req_wdata_ready <= 1'd0; @@ -6320,7 +6820,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_169 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; @@ -6339,7 +6839,7 @@ assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == lit assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_166; +reg dummy_d_170; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= 14'd0; @@ -6349,7 +6849,7 @@ always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_170 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); @@ -6357,7 +6857,7 @@ assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_ assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); // synthesis translate_off -reg dummy_d_167; +reg dummy_d_171; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_auto_precharge <= 1'd0; @@ -6367,7 +6867,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_171 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -6389,7 +6889,7 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_168; +reg dummy_d_172; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -6399,7 +6899,7 @@ always @(*) begin litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; @@ -6412,7 +6912,7 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (lite assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_169; +reg dummy_d_173; // synthesis translate_on always @(*) begin bankmachine3_next_state <= 4'd0; @@ -6475,12 +6975,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_169 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_170; +reg dummy_d_174; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_rdata_valid <= 1'd0; @@ -6520,12 +7020,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_170 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_171; +reg dummy_d_175; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_refresh_gnt <= 1'd0; @@ -6553,12 +7053,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_171 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_172; +reg dummy_d_176; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_valid <= 1'd0; @@ -6601,12 +7101,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_177; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_open <= 1'd0; @@ -6634,12 +7134,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_178; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_close <= 1'd0; @@ -6667,12 +7167,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_179; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; @@ -6709,45 +7209,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_176; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_180; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; @@ -6778,12 +7245,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_181; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_we <= 1'd0; @@ -6826,12 +7293,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_179; +reg dummy_d_182; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; @@ -6863,12 +7330,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_183; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; @@ -6908,12 +7375,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_184; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_184 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_185; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; @@ -6953,12 +7453,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_185 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_186; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_wdata_ready <= 1'd0; @@ -6998,7 +7498,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; @@ -7017,7 +7517,7 @@ assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == lit assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_183; +reg dummy_d_187; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= 14'd0; @@ -7027,7 +7527,7 @@ always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); @@ -7035,7 +7535,7 @@ assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_ assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); // synthesis translate_off -reg dummy_d_184; +reg dummy_d_188; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_auto_precharge <= 1'd0; @@ -7045,7 +7545,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_188 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -7067,7 +7567,7 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_185; +reg dummy_d_189; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -7077,7 +7577,7 @@ always @(*) begin litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; @@ -7090,7 +7590,7 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (lite assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_186; +reg dummy_d_190; // synthesis translate_on always @(*) begin bankmachine4_next_state <= 4'd0; @@ -7153,12 +7653,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_186 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_187; +reg dummy_d_191; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_req_rdata_valid <= 1'd0; @@ -7198,26 +7698,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_187 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_188; +reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7231,12 +7731,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_188 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_189; +reg dummy_d_193; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_valid <= 1'd0; @@ -7279,12 +7779,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_190; +reg dummy_d_194; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_194 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_195; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_row_open <= 1'd0; @@ -7312,12 +7845,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_196; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_row_close <= 1'd0; @@ -7345,12 +7878,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_197; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; @@ -7387,12 +7920,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_198; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; @@ -7423,12 +7956,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_199; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_we <= 1'd0; @@ -7471,12 +8004,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_200; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; @@ -7508,12 +8041,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_201; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; @@ -7553,45 +8086,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_196 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_197; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_202; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; @@ -7631,12 +8131,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_203; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_req_wdata_ready <= 1'd0; @@ -7676,7 +8176,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; @@ -7695,7 +8195,7 @@ assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == lit assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_200; +reg dummy_d_204; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= 14'd0; @@ -7705,7 +8205,7 @@ always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_204 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); @@ -7713,7 +8213,7 @@ assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_ assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); // synthesis translate_off -reg dummy_d_201; +reg dummy_d_205; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_auto_precharge <= 1'd0; @@ -7723,7 +8223,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_205 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -7745,7 +8245,7 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_202; +reg dummy_d_206; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -7755,7 +8255,7 @@ always @(*) begin litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; @@ -7768,7 +8268,7 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (lite assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_203; +reg dummy_d_207; // synthesis translate_on always @(*) begin bankmachine5_next_state <= 4'd0; @@ -7831,12 +8331,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_203 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_204; +reg dummy_d_208; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_req_rdata_valid <= 1'd0; @@ -7876,26 +8376,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_205; +reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7909,26 +8409,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_205 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_206; +reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7939,29 +8442,38 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_207; +reg dummy_d_211; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7975,27 +8487,15 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_212; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_open <= 1'd0; @@ -8023,12 +8523,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_213; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_close <= 1'd0; @@ -8056,12 +8556,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_214; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; @@ -8098,12 +8598,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_215; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; @@ -8134,12 +8634,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_216; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd0; @@ -8182,12 +8682,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_217; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; @@ -8219,12 +8719,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_218; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; @@ -8264,12 +8764,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_219; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; @@ -8309,12 +8809,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_220; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_req_wdata_ready <= 1'd0; @@ -8354,7 +8854,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_220 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; @@ -8373,7 +8873,7 @@ assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == lit assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_217; +reg dummy_d_221; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= 14'd0; @@ -8383,7 +8883,7 @@ always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_221 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); @@ -8391,7 +8891,7 @@ assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_ assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); // synthesis translate_off -reg dummy_d_218; +reg dummy_d_222; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_auto_precharge <= 1'd0; @@ -8401,7 +8901,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_222 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -8423,7 +8923,7 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_219; +reg dummy_d_223; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -8433,7 +8933,7 @@ always @(*) begin litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; @@ -8446,7 +8946,7 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (lite assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_220; +reg dummy_d_224; // synthesis translate_on always @(*) begin bankmachine6_next_state <= 4'd0; @@ -8509,12 +9009,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_220 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_221; +reg dummy_d_225; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_req_rdata_valid <= 1'd0; @@ -8554,12 +9054,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_221 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_222; +reg dummy_d_226; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_refresh_gnt <= 1'd0; @@ -8587,12 +9087,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_222 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_223; +reg dummy_d_227; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_valid <= 1'd0; @@ -8635,45 +9135,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_223 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_224; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_228; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_open <= 1'd0; @@ -8701,12 +9168,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_229; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_close <= 1'd0; @@ -8734,12 +9201,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_230; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; @@ -8776,12 +9243,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_231; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; @@ -8812,12 +9279,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_232; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd0; @@ -8860,12 +9327,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_233; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; @@ -8897,12 +9364,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_234; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_234 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_235; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; @@ -8942,12 +9442,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_236; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; @@ -8987,12 +9487,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_237; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_req_wdata_ready <= 1'd0; @@ -9032,7 +9532,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_237 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; @@ -9051,7 +9551,7 @@ assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == lit assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_234; +reg dummy_d_238; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= 14'd0; @@ -9061,7 +9561,7 @@ always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_238 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); @@ -9069,7 +9569,7 @@ assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_ assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); // synthesis translate_off -reg dummy_d_235; +reg dummy_d_239; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_auto_precharge <= 1'd0; @@ -9079,7 +9579,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_239 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -9101,7 +9601,7 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_236; +reg dummy_d_240; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -9111,7 +9611,7 @@ always @(*) begin litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; @@ -9124,7 +9624,7 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (lite assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_237; +reg dummy_d_241; // synthesis translate_on always @(*) begin bankmachine7_next_state <= 4'd0; @@ -9187,12 +9687,45 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_237 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_238; +reg dummy_d_242; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_242 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_243; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_req_rdata_valid <= 1'd0; @@ -9232,12 +9765,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_239; +reg dummy_d_244; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_refresh_gnt <= 1'd0; @@ -9265,12 +9798,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_239 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_240; +reg dummy_d_245; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_valid <= 1'd0; @@ -9313,12 +9846,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_241; +reg dummy_d_246; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_open <= 1'd0; @@ -9346,12 +9879,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_247; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_close <= 1'd0; @@ -9379,12 +9912,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_248; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; @@ -9421,12 +9954,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_249; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; @@ -9457,12 +9990,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_250; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_we <= 1'd0; @@ -9490,78 +10023,45 @@ always @(*) begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_251; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9575,12 +10075,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_252; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; @@ -9620,12 +10120,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_253; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; @@ -9665,12 +10165,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_254; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_req_wdata_ready <= 1'd0; @@ -9710,7 +10210,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_254 = dummy_s; // synthesis translate_on end assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); @@ -9743,7 +10243,7 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_251; +reg dummy_d_255; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_valids <= 8'd0; @@ -9756,7 +10256,7 @@ always @(*) begin litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_255 = dummy_s; // synthesis translate_on end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; @@ -9768,7 +10268,7 @@ assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; // synthesis translate_off -reg dummy_d_252; +reg dummy_d_256; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; @@ -9776,12 +10276,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; end // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_256 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_257; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; @@ -9789,12 +10289,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; end // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_258; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= 1'd0; @@ -9802,12 +10302,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; end // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_255; +reg dummy_d_259; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd0; @@ -9818,12 +10318,12 @@ always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_256; +reg dummy_d_260; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd0; @@ -9834,12 +10334,12 @@ always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_260 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_257; +reg dummy_d_261; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd0; @@ -9850,12 +10350,12 @@ always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_261 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_262; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd0; @@ -9866,12 +10366,12 @@ always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_263; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd0; @@ -9882,12 +10382,12 @@ always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_264; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd0; @@ -9898,12 +10398,12 @@ always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_265; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd0; @@ -9914,12 +10414,12 @@ always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_266; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd0; @@ -9930,13 +10430,13 @@ always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_263; +reg dummy_d_267; // synthesis translate_on always @(*) begin litedramcore_choose_req_valids <= 8'd0; @@ -9949,7 +10449,7 @@ always @(*) begin litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; @@ -9961,7 +10461,7 @@ assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; // synthesis translate_off -reg dummy_d_264; +reg dummy_d_268; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_cas <= 1'd0; @@ -9969,12 +10469,12 @@ always @(*) begin litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; end // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_268 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_265; +reg dummy_d_269; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_ras <= 1'd0; @@ -9982,12 +10482,12 @@ always @(*) begin litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; end // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_269 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_266; +reg dummy_d_270; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_we <= 1'd0; @@ -9995,7 +10495,7 @@ always @(*) begin litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; end // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_270 = dummy_s; // synthesis translate_on end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); @@ -10014,7 +10514,7 @@ assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_267; +reg dummy_d_271; // synthesis translate_on always @(*) begin multiplexer_next_state <= 4'd0; @@ -10073,17 +10573,18 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_271 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_268; +reg dummy_d_272; // synthesis translate_on always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin end @@ -10104,24 +10605,23 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_272 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_269; +reg dummy_d_273; // synthesis translate_on always @(*) begin - litedramcore_cmd_ready <= 1'd0; + litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10140,26 +10640,24 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_270; +reg dummy_d_274; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10178,24 +10676,24 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end endcase // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_274 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_271; +reg dummy_d_275; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10216,22 +10714,24 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_272; +reg dummy_d_276; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10252,25 +10752,22 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_277; // synthesis translate_on always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10291,26 +10788,25 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end endcase // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_274; +reg dummy_d_278; // synthesis translate_on always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -10331,21 +10827,26 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_279; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; + litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 2'd2; + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10366,16 +10867,15 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_276; +reg dummy_d_280; // synthesis translate_on always @(*) begin litedramcore_steerer_sel0 <= 2'd0; @@ -10407,12 +10907,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_280 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_277; +reg dummy_d_281; // synthesis translate_on always @(*) begin litedramcore_steerer_sel1 <= 2'd0; @@ -10443,12 +10943,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_278; +reg dummy_d_282; // synthesis translate_on always @(*) begin litedramcore_steerer_sel2 <= 2'd0; @@ -10479,12 +10979,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_282 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_283; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_want_activates <= 1'd0; @@ -10521,7 +11021,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_283 = dummy_s; // synthesis translate_on end assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; @@ -10569,7 +11069,7 @@ assign user_port_wdata_ready = new_master_wdata_ready2; assign user_port_rdata_valid = new_master_rdata_valid8; // synthesis translate_off -reg dummy_d_280; +reg dummy_d_284; // synthesis translate_on always @(*) begin litedramcore_interface_wdata_we <= 16'd0; @@ -10582,12 +11082,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_280 = dummy_s; + dummy_d_284 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_281; +reg dummy_d_285; // synthesis translate_on always @(*) begin litedramcore_interface_wdata <= 128'd0; @@ -10600,7 +11100,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_281 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end assign user_port_rdata_payload_data = litedramcore_interface_rdata; @@ -10612,9 +11112,20 @@ assign roundrobin4_grant = 1'd0; assign roundrobin5_grant = 1'd0; assign roundrobin6_grant = 1'd0; assign roundrobin7_grant = 1'd0; +assign litedramcore_wishbone_adr = wb_bus_adr; +assign litedramcore_wishbone_dat_w = wb_bus_dat_w; +assign wb_bus_dat_r = litedramcore_wishbone_dat_r; +assign litedramcore_wishbone_sel = wb_bus_sel; +assign litedramcore_wishbone_cyc = wb_bus_cyc; +assign litedramcore_wishbone_stb = wb_bus_stb; +assign wb_bus_ack = litedramcore_wishbone_ack; +assign litedramcore_wishbone_we = wb_bus_we; +assign litedramcore_wishbone_cti = wb_bus_cti; +assign litedramcore_wishbone_bte = wb_bus_bte; +assign wb_bus_err = litedramcore_wishbone_err; // synthesis translate_off -reg dummy_d_282; +reg dummy_d_286; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; @@ -10623,7 +11134,7 @@ always @(*) begin csrbank0_sel <= 1'd0; end // synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; @@ -10636,7 +11147,7 @@ assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; // synthesis translate_off -reg dummy_d_283; +reg dummy_d_287; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; @@ -10645,7 +11156,7 @@ always @(*) begin csrbank1_sel <= 1'd0; end // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; @@ -10683,7 +11194,7 @@ assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; // synthesis translate_off -reg dummy_d_284; +reg dummy_d_288; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; @@ -10692,7 +11203,7 @@ always @(*) begin csrbank2_sel <= 1'd0; end // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; @@ -10795,10 +11306,10 @@ assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_stor assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; -assign adr = csr_port_adr; -assign we = csr_port_we; -assign dat_w = csr_port_dat_w; -assign csr_port_dat_r = dat_r; +assign adr = litedramcore_adr; +assign we = litedramcore_we; +assign dat_w = litedramcore_dat_w; +assign litedramcore_dat_r = dat_r; assign interface0_bank_bus_adr = adr; assign interface1_bank_bus_adr = adr; assign interface2_bank_bus_adr = adr; @@ -10811,7 +11322,7 @@ assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_285; +reg dummy_d_289; // synthesis translate_on always @(*) begin rhs_array_muxed0 <= 1'd0; @@ -10842,12 +11353,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_286; +reg dummy_d_290; // synthesis translate_on always @(*) begin rhs_array_muxed1 <= 14'd0; @@ -10878,12 +11389,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_287; +reg dummy_d_291; // synthesis translate_on always @(*) begin rhs_array_muxed2 <= 3'd0; @@ -10914,12 +11425,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_288; +reg dummy_d_292; // synthesis translate_on always @(*) begin rhs_array_muxed3 <= 1'd0; @@ -10950,12 +11461,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_288 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_289; +reg dummy_d_293; // synthesis translate_on always @(*) begin rhs_array_muxed4 <= 1'd0; @@ -10986,12 +11497,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_294; // synthesis translate_on always @(*) begin rhs_array_muxed5 <= 1'd0; @@ -11022,12 +11533,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_295; // synthesis translate_on always @(*) begin t_array_muxed0 <= 1'd0; @@ -11058,12 +11569,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_296; // synthesis translate_on always @(*) begin t_array_muxed1 <= 1'd0; @@ -11094,12 +11605,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_297; // synthesis translate_on always @(*) begin t_array_muxed2 <= 1'd0; @@ -11130,12 +11641,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_298; // synthesis translate_on always @(*) begin rhs_array_muxed6 <= 1'd0; @@ -11166,12 +11677,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_299; // synthesis translate_on always @(*) begin rhs_array_muxed7 <= 14'd0; @@ -11202,12 +11713,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_300; // synthesis translate_on always @(*) begin rhs_array_muxed8 <= 3'd0; @@ -11238,12 +11749,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_301; // synthesis translate_on always @(*) begin rhs_array_muxed9 <= 1'd0; @@ -11274,12 +11785,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_302; // synthesis translate_on always @(*) begin rhs_array_muxed10 <= 1'd0; @@ -11310,12 +11821,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_303; // synthesis translate_on always @(*) begin rhs_array_muxed11 <= 1'd0; @@ -11346,12 +11857,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_304; // synthesis translate_on always @(*) begin t_array_muxed3 <= 1'd0; @@ -11382,12 +11893,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_305; // synthesis translate_on always @(*) begin t_array_muxed4 <= 1'd0; @@ -11418,12 +11929,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_306; // synthesis translate_on always @(*) begin t_array_muxed5 <= 1'd0; @@ -11454,12 +11965,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_307; // synthesis translate_on always @(*) begin rhs_array_muxed12 <= 21'd0; @@ -11469,12 +11980,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_308; // synthesis translate_on always @(*) begin rhs_array_muxed13 <= 1'd0; @@ -11484,12 +11995,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_309; // synthesis translate_on always @(*) begin rhs_array_muxed14 <= 1'd0; @@ -11499,12 +12010,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_310; // synthesis translate_on always @(*) begin rhs_array_muxed15 <= 21'd0; @@ -11514,12 +12025,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_311; // synthesis translate_on always @(*) begin rhs_array_muxed16 <= 1'd0; @@ -11529,12 +12040,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_312; // synthesis translate_on always @(*) begin rhs_array_muxed17 <= 1'd0; @@ -11544,12 +12055,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_313; // synthesis translate_on always @(*) begin rhs_array_muxed18 <= 21'd0; @@ -11559,12 +12070,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_314; // synthesis translate_on always @(*) begin rhs_array_muxed19 <= 1'd0; @@ -11574,12 +12085,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_315; // synthesis translate_on always @(*) begin rhs_array_muxed20 <= 1'd0; @@ -11589,12 +12100,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_316; // synthesis translate_on always @(*) begin rhs_array_muxed21 <= 21'd0; @@ -11604,12 +12115,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_317; // synthesis translate_on always @(*) begin rhs_array_muxed22 <= 1'd0; @@ -11619,12 +12130,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_318; // synthesis translate_on always @(*) begin rhs_array_muxed23 <= 1'd0; @@ -11634,12 +12145,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_319; // synthesis translate_on always @(*) begin rhs_array_muxed24 <= 21'd0; @@ -11649,12 +12160,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_320; // synthesis translate_on always @(*) begin rhs_array_muxed25 <= 1'd0; @@ -11664,12 +12175,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_321; // synthesis translate_on always @(*) begin rhs_array_muxed26 <= 1'd0; @@ -11679,12 +12190,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_322; // synthesis translate_on always @(*) begin rhs_array_muxed27 <= 21'd0; @@ -11694,12 +12205,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_323; // synthesis translate_on always @(*) begin rhs_array_muxed28 <= 1'd0; @@ -11709,12 +12220,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_324; // synthesis translate_on always @(*) begin rhs_array_muxed29 <= 1'd0; @@ -11724,12 +12235,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_325; // synthesis translate_on always @(*) begin rhs_array_muxed30 <= 21'd0; @@ -11739,12 +12250,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_326; // synthesis translate_on always @(*) begin rhs_array_muxed31 <= 1'd0; @@ -11754,12 +12265,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_327; // synthesis translate_on always @(*) begin rhs_array_muxed32 <= 1'd0; @@ -11769,12 +12280,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_328; // synthesis translate_on always @(*) begin rhs_array_muxed33 <= 21'd0; @@ -11784,12 +12295,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_329; // synthesis translate_on always @(*) begin rhs_array_muxed34 <= 1'd0; @@ -11799,12 +12310,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_330; // synthesis translate_on always @(*) begin rhs_array_muxed35 <= 1'd0; @@ -11814,12 +12325,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_331; // synthesis translate_on always @(*) begin array_muxed0 <= 3'd0; @@ -11838,12 +12349,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_332; // synthesis translate_on always @(*) begin array_muxed1 <= 14'd0; @@ -11862,12 +12373,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_333; // synthesis translate_on always @(*) begin array_muxed2 <= 1'd0; @@ -11886,12 +12397,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_334; // synthesis translate_on always @(*) begin array_muxed3 <= 1'd0; @@ -11910,12 +12421,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_335; // synthesis translate_on always @(*) begin array_muxed4 <= 1'd0; @@ -11934,12 +12445,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_336; // synthesis translate_on always @(*) begin array_muxed5 <= 1'd0; @@ -11958,12 +12469,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_337; // synthesis translate_on always @(*) begin array_muxed6 <= 1'd0; @@ -11982,12 +12493,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_338; // synthesis translate_on always @(*) begin array_muxed7 <= 3'd0; @@ -12006,12 +12517,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_339; // synthesis translate_on always @(*) begin array_muxed8 <= 14'd0; @@ -12030,12 +12541,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_340; // synthesis translate_on always @(*) begin array_muxed9 <= 1'd0; @@ -12054,12 +12565,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_341; // synthesis translate_on always @(*) begin array_muxed10 <= 1'd0; @@ -12078,12 +12589,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_342; // synthesis translate_on always @(*) begin array_muxed11 <= 1'd0; @@ -12102,12 +12613,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_343; // synthesis translate_on always @(*) begin array_muxed12 <= 1'd0; @@ -12126,12 +12637,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_344; // synthesis translate_on always @(*) begin array_muxed13 <= 1'd0; @@ -12150,12 +12661,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_345; // synthesis translate_on always @(*) begin array_muxed14 <= 3'd0; @@ -12174,12 +12685,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_346; // synthesis translate_on always @(*) begin array_muxed15 <= 14'd0; @@ -12198,12 +12709,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_347; // synthesis translate_on always @(*) begin array_muxed16 <= 1'd0; @@ -12222,12 +12733,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_348; // synthesis translate_on always @(*) begin array_muxed17 <= 1'd0; @@ -12246,12 +12757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_349; // synthesis translate_on always @(*) begin array_muxed18 <= 1'd0; @@ -12270,12 +12781,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_350; // synthesis translate_on always @(*) begin array_muxed19 <= 1'd0; @@ -12294,12 +12805,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_351; // synthesis translate_on always @(*) begin array_muxed20 <= 1'd0; @@ -12318,12 +12829,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_352; // synthesis translate_on always @(*) begin array_muxed21 <= 3'd0; @@ -12342,12 +12853,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_353; // synthesis translate_on always @(*) begin array_muxed22 <= 14'd0; @@ -12366,12 +12877,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_354; // synthesis translate_on always @(*) begin array_muxed23 <= 1'd0; @@ -12390,12 +12901,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_354 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_355; // synthesis translate_on always @(*) begin array_muxed24 <= 1'd0; @@ -12414,12 +12925,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_355 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_356; // synthesis translate_on always @(*) begin array_muxed25 <= 1'd0; @@ -12438,12 +12949,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_356 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_357; // synthesis translate_on always @(*) begin array_muxed26 <= 1'd0; @@ -12462,12 +12973,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_357 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_358; // synthesis translate_on always @(*) begin array_muxed27 <= 1'd0; @@ -12486,7 +12997,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_358 = dummy_s; // synthesis translate_on end assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); @@ -12507,6 +13018,7 @@ always @(posedge iodelay_clk) begin end always @(posedge sys_clk) begin + state <= next_state; a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1); a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1); a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en; @@ -12522,112 +13034,112 @@ always @(posedge sys_clk) begin if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip0_value <= 1'd0; end - a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]}; + a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip1_value <= 1'd0; end - a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]}; + a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip2_value <= 1'd0; end - a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]}; + a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip3_value <= 1'd0; end - a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]}; + a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip4_value <= 1'd0; end - a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]}; + a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip5_value <= 1'd0; end - a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]}; + a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip6_value <= 1'd0; end - a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]}; + a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip7_value <= 1'd0; end - a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]}; + a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip8_value <= 1'd0; end - a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]}; + a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip9_value <= 1'd0; end - a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]}; + a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip10_value <= 1'd0; end - a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]}; + a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip11_value <= 1'd0; end - a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]}; + a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip12_value <= 1'd0; end - a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]}; + a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip13_value <= 1'd0; end - a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]}; + a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip14_value <= 1'd0; end - a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]}; + a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip15_value <= 1'd0; end - a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]}; + a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]}; if (litedramcore_inti_p0_rddata_valid) begin litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata; end @@ -14161,22 +14673,22 @@ always @(posedge sys_clk) begin a7ddrphy_dqs_oe_delayed <= 1'd0; a7ddrphy_dqspattern_o1 <= 8'd0; a7ddrphy_dq_oe_delayed <= 1'd0; - a7ddrphy_bitslip0_value <= 3'd0; - a7ddrphy_bitslip1_value <= 3'd0; - a7ddrphy_bitslip2_value <= 3'd0; - a7ddrphy_bitslip3_value <= 3'd0; - a7ddrphy_bitslip4_value <= 3'd0; - a7ddrphy_bitslip5_value <= 3'd0; - a7ddrphy_bitslip6_value <= 3'd0; - a7ddrphy_bitslip7_value <= 3'd0; - a7ddrphy_bitslip8_value <= 3'd0; - a7ddrphy_bitslip9_value <= 3'd0; - a7ddrphy_bitslip10_value <= 3'd0; - a7ddrphy_bitslip11_value <= 3'd0; - a7ddrphy_bitslip12_value <= 3'd0; - a7ddrphy_bitslip13_value <= 3'd0; - a7ddrphy_bitslip14_value <= 3'd0; - a7ddrphy_bitslip15_value <= 3'd0; + a7ddrphy_bitslip0_value <= 4'd0; + a7ddrphy_bitslip1_value <= 4'd0; + a7ddrphy_bitslip2_value <= 4'd0; + a7ddrphy_bitslip3_value <= 4'd0; + a7ddrphy_bitslip4_value <= 4'd0; + a7ddrphy_bitslip5_value <= 4'd0; + a7ddrphy_bitslip6_value <= 4'd0; + a7ddrphy_bitslip7_value <= 4'd0; + a7ddrphy_bitslip8_value <= 4'd0; + a7ddrphy_bitslip9_value <= 4'd0; + a7ddrphy_bitslip10_value <= 4'd0; + a7ddrphy_bitslip11_value <= 4'd0; + a7ddrphy_bitslip12_value <= 4'd0; + a7ddrphy_bitslip13_value <= 4'd0; + a7ddrphy_bitslip14_value <= 4'd0; + a7ddrphy_bitslip15_value <= 4'd0; a7ddrphy_rddata_en_last <= 8'd0; a7ddrphy_wrdata_en_last <= 4'd0; litedramcore_storage <= 4'd0; @@ -14358,6 +14870,7 @@ always @(posedge sys_clk) begin init_done_re <= 1'd0; init_error_storage <= 1'd0; init_error_re <= 1'd0; + state <= 1'd0; refresher_state <= 2'd0; bankmachine0_state <= 4'd0; bankmachine1_state <= 4'd0; diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl index 46ae4b1..fd9f3bd 100644 --- a/litedram/generated/nexys-video/litedram-wrapper.vhdl +++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl @@ -25,7 +25,7 @@ entity litedram_wrapper is -- Wishbone ports: wb_in : in wishbone_master_out; wb_out : out wishbone_slave_out; - wb_is_csr : in std_ulogic; + wb_is_ctrl : in std_ulogic; wb_is_init : in std_ulogic; -- Init core serial debug @@ -58,32 +58,39 @@ end entity litedram_wrapper; architecture behaviour of litedram_wrapper is component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - csr_port0_adr : in std_ulogic_vector(13 downto 0); - csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(31 downto 0); - csr_port0_dat_r : out std_ulogic_vector(31 downto 0); + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -112,20 +119,19 @@ architecture behaviour of litedram_wrapper is signal ad3 : std_ulogic; - signal dram_user_reset : std_ulogic; - - signal csr_port0_adr : std_ulogic_vector(13 downto 0); - signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); - signal csr_port_read_comb : std_ulogic_vector(63 downto 0); - signal csr_valid : std_ulogic; - signal csr_write_valid : std_ulogic; + signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); + signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); + signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); + signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); + signal wb_ctrl_cyc : std_ulogic; + signal wb_ctrl_stb : std_ulogic; + signal wb_ctrl_ack : std_ulogic; + signal wb_ctrl_we : std_ulogic; signal wb_init_in : wishbone_master_out; signal wb_init_out : wishbone_slave_out; - type state_t is (CMD, MWRITE, MREAD, CSR); + type state_t is (CMD, MWRITE, MREAD); signal state : state_t; constant INIT_RAM_SIZE : integer := 16384; @@ -192,7 +198,7 @@ begin ad3 <= wb_in.adr(3); -- DRAM data interface signals - user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; user_port0_wdata_valid <= '1' when state = MWRITE else '0'; @@ -202,31 +208,28 @@ begin user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else "00000000" & wb_in.sel; - -- DRAM CSR interface signals. We only support access to the bottom byte - csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; - csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(31 downto 0); - csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + -- DRAM ctrl interface signals + wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2); + wb_ctrl_dat_w <= wb_in.dat(31 downto 0); + wb_ctrl_sel <= wb_in.sel(3 downto 0); + wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl; + wb_ctrl_stb <= wb_in.stb and wb_is_ctrl; + wb_ctrl_we <= wb_in.we; -- Wishbone out signals - wb_out.ack <= '1' when state = CSR else + wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else wb_init_out.ack when wb_is_init = '1' else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000" & csr_port0_dat_r; - wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); -- We don't do pipelining yet. wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - -- Reset ignored, the reset controller use the pll lock signal, - -- and alternate core reset address set when DRAM is not initialized. - -- - system_reset <= '0'; + -- Use alternate core reset address set when DRAM is not initialized. core_alt_reset <= not init_done; -- State machine @@ -234,14 +237,12 @@ begin begin if rising_edge(system_clk) then - if dram_user_reset = '1' then + if system_reset = '1' then state <= CMD; else case state is when CMD => - if csr_valid = '1' then - state <= CSR; - elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then state <= MWRITE when wb_in.we = '1' else MREAD; end if; when MWRITE => @@ -252,8 +253,6 @@ begin if user_port0_rdata_valid = '1' then state <= CMD; end if; - when CSR => - state <= CMD; end case; end if; end if; @@ -282,11 +281,18 @@ begin init_done => init_done, init_error => init_error, user_clk => system_clk, - user_rst => dram_user_reset, - csr_port0_adr => csr_port0_adr, - csr_port0_we => csr_port0_we, - csr_port0_dat_w => csr_port0_dat_w, - csr_port0_dat_r => csr_port0_dat_r, + user_rst => system_reset, + wb_ctrl_adr => wb_ctrl_adr, + wb_ctrl_dat_w => wb_ctrl_dat_w, + wb_ctrl_dat_r => wb_ctrl_dat_r, + wb_ctrl_sel => wb_ctrl_sel, + wb_ctrl_cyc => wb_ctrl_cyc, + wb_ctrl_stb => wb_ctrl_stb, + wb_ctrl_ack => wb_ctrl_ack, + wb_ctrl_we => wb_ctrl_we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, user_port_native_0_cmd_valid => user_port0_cmd_valid, user_port_native_0_cmd_ready => user_port0_cmd_ready, user_port_native_0_cmd_we => user_port0_cmd_we, diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 7708f27..508f707 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ffff782107c6 3d80000060213f00 798c07c6618c0000 -618c1168658cffff +618c108c658cffff 4e8004217d8903a6 0000000048000002 0000000000000000 @@ -510,120 +510,113 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429d003c4c0001 -600000003d20c000 -7929002061292000 -3d40c000f9228000 -614a201839200035 -7c0004ac794a0020 -4e8000207d2057aa -0000000000000000 -3c4c000100000000 -6000000038429cbc -39290010e9228000 -7d204eaa7c0004ac -4082ffe871290008 -e922800060000000 -7c604faa7c0004ac -000000004e800020 -0000000000000000 -38429c783c4c0001 +38429f003c4c0001 fbc1fff07c0802a6 -7fc32214fbe1fff8 -f80100107c7f1b78 -7fbff040f821ffd1 -38210030409e000c -893f000048001908 -409e000c2f89000a -4bffff813860000d -3bff0001887f0000 -4bffffd04bffff75 +f8010010fbe1fff8 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480005397c0802a6 7c741b79f821fed1 38600000f8610060 2fa4000041820068 39210040419e0060 -3ac4ffff3e42ffff +3ac4ffff60000000 f92100703b410020 -3ae000003d22ffff -3a527fb039297ff8 +3ae0000060000000 +3a428060392280a8 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1362,9 +1447,9 @@ e8010010ebc1fff0 203a4b4c43202020 7a484d20646c6c25 000000000000000a -6564346264343964 +6138393331393333 0000000000000000 -0036656663396364 +0033306536316430 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1402,10 +1487,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 -0000000000000830 -0000000000000860 -0000000000000890 -00000000000008c0 +00000000c0100830 +00000000c0100860 +00000000c0100890 +00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 @@ -1416,12 +1501,13 @@ e8010010ebc1fff0 00000a2e2e2e4d41 76656c2064616552 000a3a676e696c65 -642562202c64256d -00000000007c203a +302562202c64256d +0000007c203a6432 0000000000006425 000000000000207c 256d203a74736562 -0020642562202c64 +6432302562202c64 +0000000000000020 0000000078323025 6f6e204d41524453 207265646e752077 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index 854f4c6..57ecfd7 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:13 +// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:28 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -22,10 +22,17 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [13:0] csr_port0_adr, - input wire csr_port0_we, - input wire [31:0] csr_port0_dat_w, - output wire [31:0] csr_port0_dat_r, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -41,6 +48,21 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +wire [31:0] litedramcore_dat_w; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +wire [31:0] litedramcore_wishbone_dat_r; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -185,8 +207,8 @@ wire a7ddrphy_dq_t0; wire [7:0] a7ddrphy_dq_i_data0; wire [7:0] a7ddrphy_bitslip0_i; reg [7:0] a7ddrphy_bitslip0_o = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value = 3'd0; -reg [15:0] a7ddrphy_bitslip0_r = 16'd0; +reg [3:0] a7ddrphy_bitslip0_value = 4'd0; +reg [23:0] a7ddrphy_bitslip0_r = 24'd0; wire a7ddrphy_dq_o_nodelay1; wire a7ddrphy_dq_i_nodelay1; wire a7ddrphy_dq_i_delayed1; @@ -194,8 +216,8 @@ wire a7ddrphy_dq_t1; wire [7:0] a7ddrphy_dq_i_data1; wire [7:0] a7ddrphy_bitslip1_i; reg [7:0] a7ddrphy_bitslip1_o = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value = 3'd0; -reg [15:0] a7ddrphy_bitslip1_r = 16'd0; +reg [3:0] a7ddrphy_bitslip1_value = 4'd0; +reg [23:0] a7ddrphy_bitslip1_r = 24'd0; wire a7ddrphy_dq_o_nodelay2; wire a7ddrphy_dq_i_nodelay2; wire a7ddrphy_dq_i_delayed2; @@ -203,8 +225,8 @@ wire a7ddrphy_dq_t2; wire [7:0] a7ddrphy_dq_i_data2; wire [7:0] a7ddrphy_bitslip2_i; reg [7:0] a7ddrphy_bitslip2_o = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value = 3'd0; -reg [15:0] a7ddrphy_bitslip2_r = 16'd0; +reg [3:0] a7ddrphy_bitslip2_value = 4'd0; +reg [23:0] a7ddrphy_bitslip2_r = 24'd0; wire a7ddrphy_dq_o_nodelay3; wire a7ddrphy_dq_i_nodelay3; wire a7ddrphy_dq_i_delayed3; @@ -212,8 +234,8 @@ wire a7ddrphy_dq_t3; wire [7:0] a7ddrphy_dq_i_data3; wire [7:0] a7ddrphy_bitslip3_i; reg [7:0] a7ddrphy_bitslip3_o = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value = 3'd0; -reg [15:0] a7ddrphy_bitslip3_r = 16'd0; +reg [3:0] a7ddrphy_bitslip3_value = 4'd0; +reg [23:0] a7ddrphy_bitslip3_r = 24'd0; wire a7ddrphy_dq_o_nodelay4; wire a7ddrphy_dq_i_nodelay4; wire a7ddrphy_dq_i_delayed4; @@ -221,8 +243,8 @@ wire a7ddrphy_dq_t4; wire [7:0] a7ddrphy_dq_i_data4; wire [7:0] a7ddrphy_bitslip4_i; reg [7:0] a7ddrphy_bitslip4_o = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value = 3'd0; -reg [15:0] a7ddrphy_bitslip4_r = 16'd0; +reg [3:0] a7ddrphy_bitslip4_value = 4'd0; +reg [23:0] a7ddrphy_bitslip4_r = 24'd0; wire a7ddrphy_dq_o_nodelay5; wire a7ddrphy_dq_i_nodelay5; wire a7ddrphy_dq_i_delayed5; @@ -230,8 +252,8 @@ wire a7ddrphy_dq_t5; wire [7:0] a7ddrphy_dq_i_data5; wire [7:0] a7ddrphy_bitslip5_i; reg [7:0] a7ddrphy_bitslip5_o = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value = 3'd0; -reg [15:0] a7ddrphy_bitslip5_r = 16'd0; +reg [3:0] a7ddrphy_bitslip5_value = 4'd0; +reg [23:0] a7ddrphy_bitslip5_r = 24'd0; wire a7ddrphy_dq_o_nodelay6; wire a7ddrphy_dq_i_nodelay6; wire a7ddrphy_dq_i_delayed6; @@ -239,8 +261,8 @@ wire a7ddrphy_dq_t6; wire [7:0] a7ddrphy_dq_i_data6; wire [7:0] a7ddrphy_bitslip6_i; reg [7:0] a7ddrphy_bitslip6_o = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value = 3'd0; -reg [15:0] a7ddrphy_bitslip6_r = 16'd0; +reg [3:0] a7ddrphy_bitslip6_value = 4'd0; +reg [23:0] a7ddrphy_bitslip6_r = 24'd0; wire a7ddrphy_dq_o_nodelay7; wire a7ddrphy_dq_i_nodelay7; wire a7ddrphy_dq_i_delayed7; @@ -248,8 +270,8 @@ wire a7ddrphy_dq_t7; wire [7:0] a7ddrphy_dq_i_data7; wire [7:0] a7ddrphy_bitslip7_i; reg [7:0] a7ddrphy_bitslip7_o = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value = 3'd0; -reg [15:0] a7ddrphy_bitslip7_r = 16'd0; +reg [3:0] a7ddrphy_bitslip7_value = 4'd0; +reg [23:0] a7ddrphy_bitslip7_r = 24'd0; wire a7ddrphy_dq_o_nodelay8; wire a7ddrphy_dq_i_nodelay8; wire a7ddrphy_dq_i_delayed8; @@ -257,8 +279,8 @@ wire a7ddrphy_dq_t8; wire [7:0] a7ddrphy_dq_i_data8; wire [7:0] a7ddrphy_bitslip8_i; reg [7:0] a7ddrphy_bitslip8_o = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value = 3'd0; -reg [15:0] a7ddrphy_bitslip8_r = 16'd0; +reg [3:0] a7ddrphy_bitslip8_value = 4'd0; +reg [23:0] a7ddrphy_bitslip8_r = 24'd0; wire a7ddrphy_dq_o_nodelay9; wire a7ddrphy_dq_i_nodelay9; wire a7ddrphy_dq_i_delayed9; @@ -266,8 +288,8 @@ wire a7ddrphy_dq_t9; wire [7:0] a7ddrphy_dq_i_data9; wire [7:0] a7ddrphy_bitslip9_i; reg [7:0] a7ddrphy_bitslip9_o = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value = 3'd0; -reg [15:0] a7ddrphy_bitslip9_r = 16'd0; +reg [3:0] a7ddrphy_bitslip9_value = 4'd0; +reg [23:0] a7ddrphy_bitslip9_r = 24'd0; wire a7ddrphy_dq_o_nodelay10; wire a7ddrphy_dq_i_nodelay10; wire a7ddrphy_dq_i_delayed10; @@ -275,8 +297,8 @@ wire a7ddrphy_dq_t10; wire [7:0] a7ddrphy_dq_i_data10; wire [7:0] a7ddrphy_bitslip10_i; reg [7:0] a7ddrphy_bitslip10_o = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value = 3'd0; -reg [15:0] a7ddrphy_bitslip10_r = 16'd0; +reg [3:0] a7ddrphy_bitslip10_value = 4'd0; +reg [23:0] a7ddrphy_bitslip10_r = 24'd0; wire a7ddrphy_dq_o_nodelay11; wire a7ddrphy_dq_i_nodelay11; wire a7ddrphy_dq_i_delayed11; @@ -284,8 +306,8 @@ wire a7ddrphy_dq_t11; wire [7:0] a7ddrphy_dq_i_data11; wire [7:0] a7ddrphy_bitslip11_i; reg [7:0] a7ddrphy_bitslip11_o = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value = 3'd0; -reg [15:0] a7ddrphy_bitslip11_r = 16'd0; +reg [3:0] a7ddrphy_bitslip11_value = 4'd0; +reg [23:0] a7ddrphy_bitslip11_r = 24'd0; wire a7ddrphy_dq_o_nodelay12; wire a7ddrphy_dq_i_nodelay12; wire a7ddrphy_dq_i_delayed12; @@ -293,8 +315,8 @@ wire a7ddrphy_dq_t12; wire [7:0] a7ddrphy_dq_i_data12; wire [7:0] a7ddrphy_bitslip12_i; reg [7:0] a7ddrphy_bitslip12_o = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value = 3'd0; -reg [15:0] a7ddrphy_bitslip12_r = 16'd0; +reg [3:0] a7ddrphy_bitslip12_value = 4'd0; +reg [23:0] a7ddrphy_bitslip12_r = 24'd0; wire a7ddrphy_dq_o_nodelay13; wire a7ddrphy_dq_i_nodelay13; wire a7ddrphy_dq_i_delayed13; @@ -302,8 +324,8 @@ wire a7ddrphy_dq_t13; wire [7:0] a7ddrphy_dq_i_data13; wire [7:0] a7ddrphy_bitslip13_i; reg [7:0] a7ddrphy_bitslip13_o = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value = 3'd0; -reg [15:0] a7ddrphy_bitslip13_r = 16'd0; +reg [3:0] a7ddrphy_bitslip13_value = 4'd0; +reg [23:0] a7ddrphy_bitslip13_r = 24'd0; wire a7ddrphy_dq_o_nodelay14; wire a7ddrphy_dq_i_nodelay14; wire a7ddrphy_dq_i_delayed14; @@ -311,8 +333,8 @@ wire a7ddrphy_dq_t14; wire [7:0] a7ddrphy_dq_i_data14; wire [7:0] a7ddrphy_bitslip14_i; reg [7:0] a7ddrphy_bitslip14_o = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value = 3'd0; -reg [15:0] a7ddrphy_bitslip14_r = 16'd0; +reg [3:0] a7ddrphy_bitslip14_value = 4'd0; +reg [23:0] a7ddrphy_bitslip14_r = 24'd0; wire a7ddrphy_dq_o_nodelay15; wire a7ddrphy_dq_i_nodelay15; wire a7ddrphy_dq_i_delayed15; @@ -320,8 +342,8 @@ wire a7ddrphy_dq_t15; wire [7:0] a7ddrphy_dq_i_data15; wire [7:0] a7ddrphy_bitslip15_i; reg [7:0] a7ddrphy_bitslip15_o = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value = 3'd0; -reg [15:0] a7ddrphy_bitslip15_r = 16'd0; +reg [3:0] a7ddrphy_bitslip15_value = 4'd0; +reg [23:0] a7ddrphy_bitslip15_r = 24'd0; wire [7:0] a7ddrphy_rddata_en; reg [7:0] a7ddrphy_rddata_en_last = 8'd0; wire [3:0] a7ddrphy_wrdata_en; @@ -1483,10 +1505,17 @@ reg init_done_storage = 1'd0; reg init_done_re = 1'd0; reg init_error_storage = 1'd0; reg init_error_re = 1'd0; -wire [13:0] csr_port_adr; -wire csr_port_we; -wire [31:0] csr_port_dat_w; -wire [31:0] csr_port_dat_r; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1498,6 +1527,8 @@ wire [15:0] user_port_wdata_payload_we; wire user_port_rdata_valid; wire user_port_rdata_ready; wire [127:0] user_port_rdata_payload_data; +reg state = 1'd0; +reg next_state = 1'd0; wire pll_fb0; wire pll_fb1; reg [1:0] refresher_state = 2'd0; @@ -1774,10 +1805,17 @@ initial dummy_s <= 1'd0; // synthesis translate_on assign init_done = init_done_storage; assign init_error = init_error_storage; -assign csr_port_adr = csr_port0_adr; -assign csr_port_we = csr_port0_we; -assign csr_port_dat_w = csr_port0_dat_w; -assign csr_port0_dat_r = csr_port_dat_r; +assign wb_bus_adr = wb_ctrl_adr; +assign wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wb_ctrl_sel; +assign wb_bus_cyc = wb_ctrl_cyc; +assign wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = wb_bus_ack; +assign wb_bus_we = wb_ctrl_we; +assign wb_bus_cti = wb_ctrl_cti; +assign wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; assign user_port_cmd_valid = user_port_native_0_cmd_valid; @@ -1791,6 +1829,84 @@ assign user_port_wdata_payload_data = user_port_native_0_wdata_data; assign user_port_native_0_rdata_valid = user_port_rdata_valid; assign user_port_rdata_ready = user_port_native_0_rdata_ready; assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign litedramcore_dat_w = litedramcore_wishbone_dat_w; +assign litedramcore_wishbone_dat_r = litedramcore_dat_r; + +// synthesis translate_off +reg dummy_d; +// synthesis translate_on +always @(*) begin + next_state <= 1'd0; + next_state <= state; + case (state) + 1'd1: begin + next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_1; +// synthesis translate_on +always @(*) begin + litedramcore_adr <= 14'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr <= litedramcore_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_1 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_2; +// synthesis translate_on +always @(*) begin + litedramcore_we <= 1'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we <= litedramcore_wishbone_we; + end + end + endcase +// synthesis translate_off + dummy_d_2 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_3; +// synthesis translate_on +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (state) + 1'd1: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_3 = dummy_s; +// synthesis translate_on +end assign sys_pll_reset = rst; assign pll_locked = sys_pll_locked; assign iodelay_pll_reset = rst; @@ -1803,7 +1919,7 @@ assign iodelay_clk = s7pll1_clkout_buf; assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0; // synthesis translate_off -reg dummy_d; +reg dummy_d_4; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p0_rddata <= 32'd0; @@ -1840,12 +1956,12 @@ always @(*) begin a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0]; a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1]; // synthesis translate_off - dummy_d = dummy_s; + dummy_d_4 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_1; +reg dummy_d_5; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p1_rddata <= 32'd0; @@ -1882,12 +1998,12 @@ always @(*) begin a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2]; a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3]; // synthesis translate_off - dummy_d_1 = dummy_s; + dummy_d_5 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_2; +reg dummy_d_6; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p2_rddata <= 32'd0; @@ -1924,12 +2040,12 @@ always @(*) begin a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4]; a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5]; // synthesis translate_off - dummy_d_2 = dummy_s; + dummy_d_6 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_3; +reg dummy_d_7; // synthesis translate_on always @(*) begin a7ddrphy_dfi_p3_rddata <= 32'd0; @@ -1966,7 +2082,7 @@ always @(*) begin a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6]; a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7]; // synthesis translate_off - dummy_d_3 = dummy_s; + dummy_d_7 = dummy_s; // synthesis translate_on end assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1; @@ -1989,7 +2105,7 @@ assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en} assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2]; // synthesis translate_off -reg dummy_d_4; +reg dummy_d_8; // synthesis translate_on always @(*) begin a7ddrphy_dqs_oe <= 1'd0; @@ -1999,14 +2115,14 @@ always @(*) begin a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; end // synthesis translate_off - dummy_d_4 = dummy_s; + dummy_d_8 = dummy_s; // synthesis translate_on end assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2])); assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2])); // synthesis translate_off -reg dummy_d_5; +reg dummy_d_9; // synthesis translate_on always @(*) begin a7ddrphy_dqspattern_o0 <= 8'd0; @@ -2024,12 +2140,12 @@ always @(*) begin end end // synthesis translate_off - dummy_d_5 = dummy_s; + dummy_d_9 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_6; +reg dummy_d_10; // synthesis translate_on always @(*) begin a7ddrphy_bitslip0_o <= 8'd0; @@ -2058,14 +2174,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15]; + end endcase // synthesis translate_off - dummy_d_6 = dummy_s; + dummy_d_10 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_7; +reg dummy_d_11; // synthesis translate_on always @(*) begin a7ddrphy_bitslip1_o <= 8'd0; @@ -2094,14 +2234,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15]; + end endcase // synthesis translate_off - dummy_d_7 = dummy_s; + dummy_d_11 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_8; +reg dummy_d_12; // synthesis translate_on always @(*) begin a7ddrphy_bitslip2_o <= 8'd0; @@ -2130,14 +2294,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15]; + end endcase // synthesis translate_off - dummy_d_8 = dummy_s; + dummy_d_12 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_9; +reg dummy_d_13; // synthesis translate_on always @(*) begin a7ddrphy_bitslip3_o <= 8'd0; @@ -2166,14 +2354,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15]; + end endcase // synthesis translate_off - dummy_d_9 = dummy_s; + dummy_d_13 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_10; +reg dummy_d_14; // synthesis translate_on always @(*) begin a7ddrphy_bitslip4_o <= 8'd0; @@ -2202,14 +2414,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15]; + end endcase // synthesis translate_off - dummy_d_10 = dummy_s; + dummy_d_14 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_11; +reg dummy_d_15; // synthesis translate_on always @(*) begin a7ddrphy_bitslip5_o <= 8'd0; @@ -2238,14 +2474,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15]; + end endcase // synthesis translate_off - dummy_d_11 = dummy_s; + dummy_d_15 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_12; +reg dummy_d_16; // synthesis translate_on always @(*) begin a7ddrphy_bitslip6_o <= 8'd0; @@ -2274,14 +2534,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15]; + end endcase // synthesis translate_off - dummy_d_12 = dummy_s; + dummy_d_16 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_13; +reg dummy_d_17; // synthesis translate_on always @(*) begin a7ddrphy_bitslip7_o <= 8'd0; @@ -2310,14 +2594,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15]; + end endcase // synthesis translate_off - dummy_d_13 = dummy_s; + dummy_d_17 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_14; +reg dummy_d_18; // synthesis translate_on always @(*) begin a7ddrphy_bitslip8_o <= 8'd0; @@ -2346,14 +2654,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15]; + end endcase // synthesis translate_off - dummy_d_14 = dummy_s; + dummy_d_18 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_15; +reg dummy_d_19; // synthesis translate_on always @(*) begin a7ddrphy_bitslip9_o <= 8'd0; @@ -2382,14 +2714,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15]; + end endcase // synthesis translate_off - dummy_d_15 = dummy_s; + dummy_d_19 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_16; +reg dummy_d_20; // synthesis translate_on always @(*) begin a7ddrphy_bitslip10_o <= 8'd0; @@ -2418,14 +2774,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15]; + end endcase // synthesis translate_off - dummy_d_16 = dummy_s; + dummy_d_20 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_17; +reg dummy_d_21; // synthesis translate_on always @(*) begin a7ddrphy_bitslip11_o <= 8'd0; @@ -2454,14 +2834,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7]; end - endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on -end - + 4'd8: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15]; + end + endcase // synthesis translate_off -reg dummy_d_18; + dummy_d_21 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_22; // synthesis translate_on always @(*) begin a7ddrphy_bitslip12_o <= 8'd0; @@ -2490,14 +2894,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15]; + end endcase // synthesis translate_off - dummy_d_18 = dummy_s; + dummy_d_22 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_19; +reg dummy_d_23; // synthesis translate_on always @(*) begin a7ddrphy_bitslip13_o <= 8'd0; @@ -2526,14 +2954,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15]; + end endcase // synthesis translate_off - dummy_d_19 = dummy_s; + dummy_d_23 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_20; +reg dummy_d_24; // synthesis translate_on always @(*) begin a7ddrphy_bitslip14_o <= 8'd0; @@ -2562,14 +3014,38 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15]; + end endcase // synthesis translate_off - dummy_d_20 = dummy_s; + dummy_d_24 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_21; +reg dummy_d_25; // synthesis translate_on always @(*) begin a7ddrphy_bitslip15_o <= 8'd0; @@ -2598,9 +3074,33 @@ always @(*) begin 3'd7: begin a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7]; end + 4'd8: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8]; + end + 4'd9: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9]; + end + 4'd10: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10]; + end + 4'd11: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11]; + end + 4'd12: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12]; + end + 4'd13: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13]; + end + 4'd14: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14]; + end + 4'd15: begin + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15]; + end endcase // synthesis translate_off - dummy_d_21 = dummy_s; + dummy_d_25 = dummy_s; // synthesis translate_on end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; @@ -2732,73 +3232,15 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on -always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; - end else begin - litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; - end -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on -always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; - end else begin - end -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on -always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; - end else begin - litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; - end -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on -always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end else begin - end -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on -end - // synthesis translate_off reg dummy_d_26; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cke <= 1'd0; + litedramcore_master_p1_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_26 = dummy_s; @@ -2809,11 +3251,10 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - litedramcore_master_p1_odt <= 1'd0; + litedramcore_inti_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin - litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_27 = dummy_s; @@ -2824,11 +3265,11 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_master_p1_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_28 = dummy_s; @@ -2839,11 +3280,11 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; + litedramcore_master_p1_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_29 = dummy_s; @@ -2854,11 +3295,11 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; + litedramcore_master_p2_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_30 = dummy_s; @@ -2869,10 +3310,11 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; + litedramcore_master_p2_bank <= 3'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_31 = dummy_s; @@ -2883,11 +3325,11 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; + litedramcore_master_p2_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_32 = dummy_s; @@ -2898,10 +3340,11 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; + litedramcore_master_p2_cs_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_33 = dummy_s; @@ -2912,11 +3355,11 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; + litedramcore_master_p2_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_34 = dummy_s; @@ -2927,11 +3370,10 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; + litedramcore_slave_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_35 = dummy_s; @@ -2942,11 +3384,11 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - litedramcore_master_p2_address <= 15'd0; + litedramcore_master_p2_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; end else begin - litedramcore_master_p2_address <= litedramcore_inti_p2_address; + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_36 = dummy_s; @@ -2957,11 +3399,10 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - litedramcore_master_p2_bank <= 3'd0; + litedramcore_slave_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin - litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_37 = dummy_s; @@ -2972,11 +3413,11 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; + litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_38 = dummy_s; @@ -2987,11 +3428,10 @@ end reg dummy_d_39; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; + litedramcore_inti_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_39 = dummy_s; @@ -3002,11 +3442,11 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; + litedramcore_master_p2_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin - litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_40 = dummy_s; @@ -3017,10 +3457,11 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; + litedramcore_master_p2_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_41 = dummy_s; @@ -3031,11 +3472,11 @@ end reg dummy_d_42; // synthesis translate_on always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; + litedramcore_master_p2_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3046,10 +3487,11 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_master_p2_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_43 = dummy_s; @@ -3060,11 +3502,10 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cke <= 1'd0; + litedramcore_inti_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3075,11 +3516,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - litedramcore_master_p2_odt <= 1'd0; + litedramcore_master_p2_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3090,11 +3531,10 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; + litedramcore_inti_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3105,11 +3545,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; + litedramcore_master_p2_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3120,11 +3560,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; + litedramcore_master_p2_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3135,10 +3575,11 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata <= 32'd0; + litedramcore_master_p3_address <= 15'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; end else begin - litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3149,11 +3590,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; + litedramcore_master_p3_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3164,10 +3605,11 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata_valid <= 1'd0; + litedramcore_master_p3_cas_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end else begin - litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3178,11 +3620,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; + litedramcore_master_p3_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3193,11 +3635,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; + litedramcore_master_p3_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3208,11 +3650,10 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - litedramcore_master_p3_address <= 15'd0; + litedramcore_slave_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end else begin - litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3223,11 +3664,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - litedramcore_master_p3_bank <= 3'd0; + litedramcore_master_p3_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3238,11 +3679,10 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; + litedramcore_slave_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin - litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3253,11 +3693,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; + litedramcore_master_p3_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3268,11 +3708,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; + litedramcore_master_p3_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3283,10 +3723,11 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; + litedramcore_master_p3_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -3297,11 +3738,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; + litedramcore_master_p3_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3312,10 +3753,11 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; + litedramcore_master_p3_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -3326,11 +3768,10 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cke <= 1'd0; + litedramcore_inti_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3341,11 +3782,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_master_p3_odt <= 1'd0; + litedramcore_master_p3_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3356,11 +3797,10 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; + litedramcore_inti_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3371,11 +3811,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; + litedramcore_master_p3_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3386,11 +3826,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; + litedramcore_master_p3_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3401,10 +3841,11 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata <= 32'd0; + litedramcore_master_p0_address <= 15'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; end else begin - litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3415,11 +3856,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; + litedramcore_master_p0_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3430,10 +3871,11 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata_valid <= 1'd0; + litedramcore_master_p0_cas_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end else begin - litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3444,11 +3886,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; + litedramcore_master_p0_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3459,11 +3901,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; + litedramcore_master_p0_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3474,11 +3916,10 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - litedramcore_master_p0_address <= 15'd0; + litedramcore_slave_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end else begin - litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3489,11 +3930,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - litedramcore_master_p0_bank <= 3'd0; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin - litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3504,11 +3945,10 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin - litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3519,11 +3959,11 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; + litedramcore_master_p0_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -3534,11 +3974,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; + litedramcore_master_p0_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end else begin - litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3549,10 +3989,11 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; + litedramcore_master_p0_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -3563,11 +4004,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_master_p0_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -3578,10 +4019,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_master_p0_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end else begin + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -3592,11 +4034,10 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cke <= 1'd0; + litedramcore_inti_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -3607,11 +4048,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - litedramcore_master_p0_odt <= 1'd0; + litedramcore_master_p0_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin - litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -3622,11 +4063,10 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; + litedramcore_inti_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -3637,11 +4077,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; + litedramcore_master_p0_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -3652,11 +4092,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; + litedramcore_master_p0_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -3667,10 +4107,11 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata <= 32'd0; + litedramcore_master_p1_address <= 15'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -3681,11 +4122,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; + litedramcore_master_p1_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -3696,10 +4137,11 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata_valid <= 1'd0; + litedramcore_master_p1_cas_n <= 1'd1; if (litedramcore_storage[0]) begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin - litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -3710,11 +4152,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; + litedramcore_master_p1_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -3725,11 +4167,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; + litedramcore_master_p1_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -3740,11 +4182,10 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - litedramcore_master_p1_address <= 15'd0; + litedramcore_slave_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin - litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -3755,11 +4196,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - litedramcore_master_p1_bank <= 3'd0; + litedramcore_master_p1_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -3770,11 +4211,10 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; + litedramcore_slave_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin - litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -3785,16 +4225,76 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; + litedramcore_master_p1_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_93 = dummy_s; // synthesis translate_on end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + end +// synthesis translate_off + dummy_d_97 = dummy_s; +// synthesis translate_on +end assign litedramcore_inti_p0_cke = litedramcore_storage[1]; assign litedramcore_inti_p1_cke = litedramcore_storage[1]; assign litedramcore_inti_p2_cke = litedramcore_storage[1]; @@ -3809,7 +4309,22 @@ assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; // synthesis translate_off -reg dummy_d_94; +reg dummy_d_98; +// synthesis translate_on +always @(*) begin + litedramcore_inti_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_98 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_99; // synthesis translate_on always @(*) begin litedramcore_inti_p0_ras_n <= 1'd1; @@ -3819,12 +4334,12 @@ always @(*) begin litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_94 = dummy_s; + dummy_d_99 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_95; +reg dummy_d_100; // synthesis translate_on always @(*) begin litedramcore_inti_p0_we_n <= 1'd1; @@ -3834,12 +4349,12 @@ always @(*) begin litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off - dummy_d_95 = dummy_s; + dummy_d_100 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_96; +reg dummy_d_101; // synthesis translate_on always @(*) begin litedramcore_inti_p0_cas_n <= 1'd1; @@ -3849,33 +4364,33 @@ always @(*) begin litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_96 = dummy_s; + dummy_d_101 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); +assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); +assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_97; +reg dummy_d_102; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + litedramcore_inti_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin - litedramcore_inti_p0_cs_n <= {1{1'd1}}; + litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_97 = dummy_s; + dummy_d_102 = dummy_s; // synthesis translate_on end -assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); -assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); -assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_98; +reg dummy_d_103; // synthesis translate_on always @(*) begin litedramcore_inti_p1_ras_n <= 1'd1; @@ -3885,12 +4400,12 @@ always @(*) begin litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_98 = dummy_s; + dummy_d_103 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_99; +reg dummy_d_104; // synthesis translate_on always @(*) begin litedramcore_inti_p1_we_n <= 1'd1; @@ -3900,12 +4415,12 @@ always @(*) begin litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off - dummy_d_99 = dummy_s; + dummy_d_104 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_100; +reg dummy_d_105; // synthesis translate_on always @(*) begin litedramcore_inti_p1_cas_n <= 1'd1; @@ -3915,33 +4430,33 @@ always @(*) begin litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_100 = dummy_s; + dummy_d_105 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); +assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); +assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_101; +reg dummy_d_106; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + litedramcore_inti_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - litedramcore_inti_p1_cs_n <= {1{1'd1}}; + litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_101 = dummy_s; + dummy_d_106 = dummy_s; // synthesis translate_on end -assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); -assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); -assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_102; +reg dummy_d_107; // synthesis translate_on always @(*) begin litedramcore_inti_p2_ras_n <= 1'd1; @@ -3951,12 +4466,12 @@ always @(*) begin litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_102 = dummy_s; + dummy_d_107 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_103; +reg dummy_d_108; // synthesis translate_on always @(*) begin litedramcore_inti_p2_we_n <= 1'd1; @@ -3966,12 +4481,12 @@ always @(*) begin litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off - dummy_d_103 = dummy_s; + dummy_d_108 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_104; +reg dummy_d_109; // synthesis translate_on always @(*) begin litedramcore_inti_p2_cas_n <= 1'd1; @@ -3981,33 +4496,33 @@ always @(*) begin litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_104 = dummy_s; + dummy_d_109 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; +assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; +assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); +assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); +assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; +assign litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_105; +reg dummy_d_110; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; + litedramcore_inti_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; end else begin - litedramcore_inti_p2_cs_n <= {1{1'd1}}; + litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off - dummy_d_105 = dummy_s; + dummy_d_110 = dummy_s; // synthesis translate_on end -assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; -assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; -assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); -assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); -assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; -assign litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off -reg dummy_d_106; +reg dummy_d_111; // synthesis translate_on always @(*) begin litedramcore_inti_p3_ras_n <= 1'd1; @@ -4017,12 +4532,12 @@ always @(*) begin litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off - dummy_d_106 = dummy_s; + dummy_d_111 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_107; +reg dummy_d_112; // synthesis translate_on always @(*) begin litedramcore_inti_p3_we_n <= 1'd1; @@ -4032,12 +4547,12 @@ always @(*) begin litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off - dummy_d_107 = dummy_s; + dummy_d_112 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_108; +reg dummy_d_113; // synthesis translate_on always @(*) begin litedramcore_inti_p3_cas_n <= 1'd1; @@ -4047,22 +4562,7 @@ always @(*) begin litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off - dummy_d_108 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_109; -// synthesis translate_on -always @(*) begin - litedramcore_inti_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; - end else begin - litedramcore_inti_p3_cs_n <= {1{1'd1}}; - end -// synthesis translate_off - dummy_d_109 = dummy_s; + dummy_d_113 = dummy_s; // synthesis translate_on end assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; @@ -4142,7 +4642,7 @@ assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; // synthesis translate_off -reg dummy_d_110; +reg dummy_d_114; // synthesis translate_on always @(*) begin refresher_next_state <= 2'd0; @@ -4176,12 +4676,35 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_110 = dummy_s; + dummy_d_114 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_111; +reg dummy_d_115; +// synthesis translate_on +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_115 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_116; // synthesis translate_on always @(*) begin litedramcore_cmd_valid <= 1'd0; @@ -4208,12 +4731,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_111 = dummy_s; + dummy_d_116 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_112; +reg dummy_d_117; // synthesis translate_on always @(*) begin litedramcore_zqcs_executer_start <= 1'd0; @@ -4234,12 +4757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_112 = dummy_s; + dummy_d_117 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_113; +reg dummy_d_118; // synthesis translate_on always @(*) begin litedramcore_cmd_last <= 1'd0; @@ -4263,30 +4786,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_113 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_114; -// synthesis translate_on -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_114 = dummy_s; + dummy_d_118 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; @@ -4305,7 +4805,7 @@ assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == lit assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off -reg dummy_d_115; +reg dummy_d_119; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= 15'd0; @@ -4315,7 +4815,7 @@ always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_115 = dummy_s; + dummy_d_119 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); @@ -4323,7 +4823,7 @@ assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_ assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); // synthesis translate_off -reg dummy_d_116; +reg dummy_d_120; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_auto_precharge <= 1'd0; @@ -4333,7 +4833,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_116 = dummy_s; + dummy_d_120 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -4355,7 +4855,7 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_117; +reg dummy_d_121; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -4365,7 +4865,7 @@ always @(*) begin litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_117 = dummy_s; + dummy_d_121 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; @@ -4378,7 +4878,7 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (lite assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_118; +reg dummy_d_122; // synthesis translate_on always @(*) begin bankmachine0_next_state <= 4'd0; @@ -4441,21 +4941,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_118 = dummy_s; + dummy_d_122 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_119; +reg dummy_d_123; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine0_row_open <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -4468,41 +4971,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_119 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_120; +reg dummy_d_124; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + litedramcore_bankmachine0_row_close <= 1'd0; case (bankmachine0_state) 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -4513,33 +5004,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_120 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_121; +reg dummy_d_125; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4563,10 +5039,7 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; - end + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -4576,23 +5049,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_121 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_122; +reg dummy_d_126; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -4609,26 +5085,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_127; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -4639,29 +5115,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_127 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_128; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -4675,41 +5163,33 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_128 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_129; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -4723,26 +5203,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_129 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_130; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -4753,18 +5230,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_126 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_127; +reg dummy_d_131; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4788,7 +5280,10 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -4798,56 +5293,62 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_128; +reg dummy_d_132; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end end end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_129; +reg dummy_d_133; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -4870,8 +5371,8 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -4882,30 +5383,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_133 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_134; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -4919,21 +5416,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_134 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_135; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine0_cmd_valid <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -4951,10 +5454,7 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine0_cmd_valid <= 1'd1; end else begin end end else begin @@ -4964,7 +5464,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_135 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; @@ -4983,7 +5483,7 @@ assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == lit assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_132; +reg dummy_d_136; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= 15'd0; @@ -4993,7 +5493,7 @@ always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_136 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); @@ -5001,7 +5501,7 @@ assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_ assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_133; +reg dummy_d_137; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_auto_precharge <= 1'd0; @@ -5011,7 +5511,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_137 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -5033,7 +5533,7 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_134; +reg dummy_d_138; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -5043,7 +5543,7 @@ always @(*) begin litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; @@ -5056,7 +5556,7 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (lite assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_135; +reg dummy_d_139; // synthesis translate_on always @(*) begin bankmachine1_next_state <= 4'd0; @@ -5119,21 +5619,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_135 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_136; +reg dummy_d_140; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine1_row_open <= 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin end @@ -5146,41 +5649,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_136 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_137; +reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + litedramcore_bankmachine1_row_close <= 1'd0; case (bankmachine1_state) 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5191,33 +5682,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_137 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_138; +reg dummy_d_142; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5241,10 +5717,7 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5254,26 +5727,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_139; +reg dummy_d_143; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5287,27 +5763,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_144; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5325,7 +5798,10 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -5335,12 +5811,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_145; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; @@ -5368,26 +5844,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_146; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5401,26 +5881,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_147; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (bankmachine1_state) 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5431,18 +5908,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_148; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5466,7 +5958,10 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -5476,27 +5971,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_149; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -5509,23 +5998,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_150; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5548,8 +6049,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -5560,30 +6061,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_151; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5597,21 +6094,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_151 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_152; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -5629,10 +6132,7 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -5642,7 +6142,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_152 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; @@ -5661,7 +6161,7 @@ assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == lit assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_149; +reg dummy_d_153; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= 15'd0; @@ -5671,7 +6171,7 @@ always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_153 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); @@ -5679,7 +6179,7 @@ assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_ assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); // synthesis translate_off -reg dummy_d_150; +reg dummy_d_154; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_auto_precharge <= 1'd0; @@ -5689,7 +6189,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_154 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -5711,7 +6211,7 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_151; +reg dummy_d_155; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -5721,7 +6221,7 @@ always @(*) begin litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; @@ -5734,7 +6234,7 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (lite assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_152; +reg dummy_d_156; // synthesis translate_on always @(*) begin bankmachine2_next_state <= 4'd0; @@ -5797,21 +6297,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; + dummy_d_156 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_153; +reg dummy_d_157; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin end @@ -5824,41 +6327,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_153 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_154; +reg dummy_d_158; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -5869,33 +6360,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_154 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_155; +reg dummy_d_159; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -5919,10 +6395,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5932,26 +6405,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_155 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_156; +reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5965,27 +6441,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6003,7 +6476,10 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -6013,15 +6489,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_158; +reg dummy_d_162; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6029,7 +6505,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6046,26 +6522,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_163; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6079,15 +6559,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_164; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6111,7 +6591,10 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -6121,24 +6604,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_165; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6151,30 +6631,39 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_162; +reg dummy_d_166; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6187,23 +6676,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_167; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6226,8 +6727,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6238,30 +6739,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_168; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6275,21 +6772,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_169; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine2_cmd_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6307,10 +6810,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6320,7 +6820,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_169 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; @@ -6339,7 +6839,7 @@ assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == lit assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_166; +reg dummy_d_170; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= 15'd0; @@ -6349,7 +6849,7 @@ always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_170 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); @@ -6357,7 +6857,7 @@ assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_ assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); // synthesis translate_off -reg dummy_d_167; +reg dummy_d_171; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_auto_precharge <= 1'd0; @@ -6367,7 +6867,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_171 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -6389,7 +6889,7 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_168; +reg dummy_d_172; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -6399,7 +6899,7 @@ always @(*) begin litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; @@ -6412,7 +6912,7 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (lite assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_169; +reg dummy_d_173; // synthesis translate_on always @(*) begin bankmachine3_next_state <= 4'd0; @@ -6475,21 +6975,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_169 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_170; +reg dummy_d_174; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine3_row_open <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end end 3'd4: begin end @@ -6502,41 +7005,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_170 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_171; +reg dummy_d_175; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + litedramcore_bankmachine3_row_close <= 1'd0; case (bankmachine3_state) 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -6547,42 +7038,24 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_171 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_172; +reg dummy_d_176; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6595,24 +7068,42 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_177; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -6625,44 +7116,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_178; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6673,29 +7149,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_179; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6709,41 +7197,33 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_180; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6757,26 +7237,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_181; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -6787,18 +7264,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_182; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6822,7 +7314,10 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -6832,27 +7327,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_179; +reg dummy_d_183; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6865,23 +7354,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_184; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6904,8 +7405,8 @@ always @(*) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6916,30 +7417,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_185; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6953,21 +7450,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_185 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_186; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine3_cmd_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6985,10 +7488,7 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -6998,7 +7498,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; @@ -7017,7 +7517,7 @@ assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == lit assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_183; +reg dummy_d_187; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= 15'd0; @@ -7027,7 +7527,7 @@ always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); @@ -7035,7 +7535,7 @@ assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_ assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); // synthesis translate_off -reg dummy_d_184; +reg dummy_d_188; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_auto_precharge <= 1'd0; @@ -7045,7 +7545,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_188 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -7067,7 +7567,7 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_185; +reg dummy_d_189; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -7077,7 +7577,7 @@ always @(*) begin litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; @@ -7090,7 +7590,7 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (lite assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_186; +reg dummy_d_190; // synthesis translate_on always @(*) begin bankmachine4_next_state <= 4'd0; @@ -7153,21 +7653,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_186 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_187; +reg dummy_d_191; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine4_row_open <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin end @@ -7180,41 +7683,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_187 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_188; +reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + litedramcore_bankmachine4_row_close <= 1'd0; case (bankmachine4_state) 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7225,33 +7716,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_188 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_189; +reg dummy_d_193; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7275,10 +7751,7 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7288,26 +7761,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_190; +reg dummy_d_194; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7321,24 +7797,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_195; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7351,29 +7827,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_196; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7387,41 +7875,33 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_197; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7435,26 +7915,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_198; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7465,18 +7942,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_199; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7500,7 +7992,10 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -7510,56 +8005,62 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_200; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end end end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end endcase // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_197; +reg dummy_d_201; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7582,8 +8083,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7594,30 +8095,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_202; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7631,21 +8128,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_203; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine4_cmd_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -7663,10 +8166,7 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -7676,7 +8176,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; @@ -7695,7 +8195,7 @@ assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == lit assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_200; +reg dummy_d_204; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= 15'd0; @@ -7705,7 +8205,7 @@ always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_204 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); @@ -7713,7 +8213,7 @@ assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_ assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); // synthesis translate_off -reg dummy_d_201; +reg dummy_d_205; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_auto_precharge <= 1'd0; @@ -7723,7 +8223,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_205 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -7745,7 +8245,7 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_202; +reg dummy_d_206; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -7755,7 +8255,7 @@ always @(*) begin litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; @@ -7768,7 +8268,7 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (lite assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_203; +reg dummy_d_207; // synthesis translate_on always @(*) begin bankmachine5_next_state <= 4'd0; @@ -7831,21 +8331,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_203 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_204; +reg dummy_d_208; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine5_row_open <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end end 3'd4: begin end @@ -7858,41 +8361,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_205; +reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + litedramcore_bankmachine5_row_close <= 1'd0; case (bankmachine5_state) 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -7903,33 +8394,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_205 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_206; +reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7953,10 +8429,7 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7966,26 +8439,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_207; +reg dummy_d_211; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7999,27 +8475,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_212; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8037,7 +8510,10 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -8047,15 +8523,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_213; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8063,7 +8539,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8080,26 +8556,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_214; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8113,26 +8593,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_215; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (bankmachine5_state) 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8143,18 +8620,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_216; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8178,7 +8670,10 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -8188,27 +8683,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_217; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -8221,23 +8710,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_218; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8260,8 +8761,8 @@ always @(*) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -8272,30 +8773,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_219; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8309,21 +8806,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_220; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8341,10 +8844,7 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -8354,7 +8854,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_220 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; @@ -8373,7 +8873,7 @@ assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == lit assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_217; +reg dummy_d_221; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= 15'd0; @@ -8383,7 +8883,7 @@ always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_221 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); @@ -8391,7 +8891,7 @@ assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_ assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); // synthesis translate_off -reg dummy_d_218; +reg dummy_d_222; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_auto_precharge <= 1'd0; @@ -8401,7 +8901,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_222 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -8423,7 +8923,7 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_219; +reg dummy_d_223; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -8433,7 +8933,7 @@ always @(*) begin litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; @@ -8446,7 +8946,7 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (lite assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_220; +reg dummy_d_224; // synthesis translate_on always @(*) begin bankmachine6_next_state <= 4'd0; @@ -8509,21 +9009,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_220 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_221; +reg dummy_d_225; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine6_row_open <= 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin end @@ -8536,41 +9039,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_221 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_222; +reg dummy_d_226; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + litedramcore_bankmachine6_row_close <= 1'd0; case (bankmachine6_state) 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -8581,33 +9072,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_222 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_223; +reg dummy_d_227; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8631,10 +9107,7 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8644,26 +9117,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_223 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_224; +reg dummy_d_228; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8677,27 +9153,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_229; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8715,7 +9188,10 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -8725,15 +9201,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_230; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8741,7 +9217,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8758,26 +9234,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_231; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (bankmachine6_state) 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8791,15 +9271,15 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_232; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8823,7 +9303,10 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -8833,27 +9316,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_233; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -8866,23 +9343,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_234; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8905,7 +9394,7 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -8917,24 +9406,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_235; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -8947,33 +9433,44 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_236; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8987,21 +9484,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_237; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine6_cmd_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9019,10 +9522,7 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -9032,7 +9532,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_237 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; @@ -9051,7 +9551,7 @@ assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == lit assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_234; +reg dummy_d_238; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= 15'd0; @@ -9061,7 +9561,7 @@ always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_238 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); @@ -9069,7 +9569,7 @@ assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_ assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); // synthesis translate_off -reg dummy_d_235; +reg dummy_d_239; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_auto_precharge <= 1'd0; @@ -9079,7 +9579,7 @@ always @(*) begin end end // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_239 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; @@ -9101,7 +9601,7 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = lite assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_236; +reg dummy_d_240; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; @@ -9111,7 +9611,7 @@ always @(*) begin litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; @@ -9124,7 +9624,7 @@ assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (lite assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_237; +reg dummy_d_241; // synthesis translate_on always @(*) begin bankmachine7_next_state <= 4'd0; @@ -9187,21 +9687,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_237 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_238; +reg dummy_d_242; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine7_row_open <= 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin end @@ -9214,41 +9717,29 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_239; +reg dummy_d_243; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + litedramcore_bankmachine7_row_close <= 1'd0; case (bankmachine7_state) 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9259,33 +9750,18 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_239 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_240; +reg dummy_d_244; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9309,10 +9785,7 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9322,23 +9795,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_241; +reg dummy_d_245; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9355,26 +9831,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_246; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9385,29 +9861,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_247; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9421,41 +9909,33 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_248; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9469,26 +9949,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_249; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9499,18 +9976,33 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_250; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9534,7 +10026,10 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end end else begin end end else begin @@ -9544,27 +10039,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_251; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9577,23 +10066,35 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_252; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9616,8 +10117,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9628,30 +10129,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_253; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9665,21 +10162,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_254; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine7_cmd_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9697,10 +10200,7 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end + litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9710,7 +10210,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_254 = dummy_s; // synthesis translate_on end assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); @@ -9743,7 +10243,7 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_251; +reg dummy_d_255; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_valids <= 8'd0; @@ -9756,7 +10256,7 @@ always @(*) begin litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_255 = dummy_s; // synthesis translate_on end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; @@ -9768,7 +10268,7 @@ assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; // synthesis translate_off -reg dummy_d_252; +reg dummy_d_256; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; @@ -9776,12 +10276,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; end // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_256 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_257; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; @@ -9789,12 +10289,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; end // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_258; // synthesis translate_on always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= 1'd0; @@ -9802,12 +10302,12 @@ always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; end // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_255; +reg dummy_d_259; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd0; @@ -9818,12 +10318,12 @@ always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_256; +reg dummy_d_260; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd0; @@ -9834,12 +10334,12 @@ always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_260 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_257; +reg dummy_d_261; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd0; @@ -9850,12 +10350,12 @@ always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_261 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_262; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd0; @@ -9866,12 +10366,12 @@ always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_263; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd0; @@ -9882,12 +10382,12 @@ always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_264; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd0; @@ -9898,12 +10398,12 @@ always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_265; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd0; @@ -9914,12 +10414,12 @@ always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_266; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd0; @@ -9930,13 +10430,13 @@ always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_263; +reg dummy_d_267; // synthesis translate_on always @(*) begin litedramcore_choose_req_valids <= 8'd0; @@ -9949,7 +10449,7 @@ always @(*) begin litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; @@ -9961,7 +10461,7 @@ assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; // synthesis translate_off -reg dummy_d_264; +reg dummy_d_268; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_cas <= 1'd0; @@ -9969,12 +10469,12 @@ always @(*) begin litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; end // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_268 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_265; +reg dummy_d_269; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_ras <= 1'd0; @@ -9982,12 +10482,12 @@ always @(*) begin litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; end // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_269 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_266; +reg dummy_d_270; // synthesis translate_on always @(*) begin litedramcore_choose_req_cmd_payload_we <= 1'd0; @@ -9995,7 +10495,7 @@ always @(*) begin litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; end // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_270 = dummy_s; // synthesis translate_on end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); @@ -10014,7 +10514,7 @@ assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_267; +reg dummy_d_271; // synthesis translate_on always @(*) begin multiplexer_next_state <= 4'd0; @@ -10073,18 +10573,22 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_271 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_268; +reg dummy_d_272; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -10105,25 +10609,26 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 2'd2; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_272 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_269; +reg dummy_d_273; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; + litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10144,27 +10649,24 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end end endcase // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_270; +reg dummy_d_274; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; + litedramcore_steerer_sel0 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 2'd2; + litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10183,21 +10685,22 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; + litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_274 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_271; +reg dummy_d_275; // synthesis translate_on always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_steerer_sel1 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; end 2'd2: begin end @@ -10218,24 +10721,24 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_272; +reg dummy_d_276; // synthesis translate_on always @(*) begin - litedramcore_cmd_ready <= 1'd0; + litedramcore_steerer_sel2 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel2 <= 1'd1; end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10254,23 +10757,24 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_277; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_choose_cmd_want_activates <= 1'd0; case (multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end 2'd2: begin @@ -10294,22 +10798,23 @@ always @(*) begin default: begin if (1'd0) begin end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end endcase // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_274; +reg dummy_d_278; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin end @@ -10330,22 +10835,21 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_279; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10366,27 +10870,24 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_276; +reg dummy_d_280; // synthesis translate_on always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10405,26 +10906,24 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end endcase // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_280 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_277; +reg dummy_d_281; // synthesis translate_on always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10445,24 +10944,26 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_278; +reg dummy_d_282; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10481,22 +10982,22 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_282 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_283; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10517,11 +11018,10 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_283 = dummy_s; // synthesis translate_on end assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; @@ -10569,7 +11069,7 @@ assign user_port_wdata_ready = new_master_wdata_ready2; assign user_port_rdata_valid = new_master_rdata_valid8; // synthesis translate_off -reg dummy_d_280; +reg dummy_d_284; // synthesis translate_on always @(*) begin litedramcore_interface_wdata <= 128'd0; @@ -10582,12 +11082,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_280 = dummy_s; + dummy_d_284 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_281; +reg dummy_d_285; // synthesis translate_on always @(*) begin litedramcore_interface_wdata_we <= 16'd0; @@ -10600,7 +11100,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_281 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end assign user_port_rdata_payload_data = litedramcore_interface_rdata; @@ -10612,9 +11112,20 @@ assign roundrobin4_grant = 1'd0; assign roundrobin5_grant = 1'd0; assign roundrobin6_grant = 1'd0; assign roundrobin7_grant = 1'd0; +assign litedramcore_wishbone_adr = wb_bus_adr; +assign litedramcore_wishbone_dat_w = wb_bus_dat_w; +assign wb_bus_dat_r = litedramcore_wishbone_dat_r; +assign litedramcore_wishbone_sel = wb_bus_sel; +assign litedramcore_wishbone_cyc = wb_bus_cyc; +assign litedramcore_wishbone_stb = wb_bus_stb; +assign wb_bus_ack = litedramcore_wishbone_ack; +assign litedramcore_wishbone_we = wb_bus_we; +assign litedramcore_wishbone_cti = wb_bus_cti; +assign litedramcore_wishbone_bte = wb_bus_bte; +assign wb_bus_err = litedramcore_wishbone_err; // synthesis translate_off -reg dummy_d_282; +reg dummy_d_286; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; @@ -10623,7 +11134,7 @@ always @(*) begin csrbank0_sel <= 1'd0; end // synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; @@ -10636,7 +11147,7 @@ assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; // synthesis translate_off -reg dummy_d_283; +reg dummy_d_287; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; @@ -10645,7 +11156,7 @@ always @(*) begin csrbank1_sel <= 1'd0; end // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; @@ -10683,7 +11194,7 @@ assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; // synthesis translate_off -reg dummy_d_284; +reg dummy_d_288; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; @@ -10692,7 +11203,7 @@ always @(*) begin csrbank2_sel <= 1'd0; end // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; @@ -10795,10 +11306,10 @@ assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_stor assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; -assign adr = csr_port_adr; -assign we = csr_port_we; -assign dat_w = csr_port_dat_w; -assign csr_port_dat_r = dat_r; +assign adr = litedramcore_adr; +assign we = litedramcore_we; +assign dat_w = litedramcore_dat_w; +assign litedramcore_dat_r = dat_r; assign interface0_bank_bus_adr = adr; assign interface1_bank_bus_adr = adr; assign interface2_bank_bus_adr = adr; @@ -10811,7 +11322,7 @@ assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_285; +reg dummy_d_289; // synthesis translate_on always @(*) begin rhs_array_muxed0 <= 1'd0; @@ -10842,12 +11353,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_286; +reg dummy_d_290; // synthesis translate_on always @(*) begin rhs_array_muxed1 <= 15'd0; @@ -10878,12 +11389,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_287; +reg dummy_d_291; // synthesis translate_on always @(*) begin rhs_array_muxed2 <= 3'd0; @@ -10914,12 +11425,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_288; +reg dummy_d_292; // synthesis translate_on always @(*) begin rhs_array_muxed3 <= 1'd0; @@ -10950,12 +11461,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_288 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_289; +reg dummy_d_293; // synthesis translate_on always @(*) begin rhs_array_muxed4 <= 1'd0; @@ -10986,12 +11497,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_294; // synthesis translate_on always @(*) begin rhs_array_muxed5 <= 1'd0; @@ -11022,12 +11533,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_295; // synthesis translate_on always @(*) begin t_array_muxed0 <= 1'd0; @@ -11058,12 +11569,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_296; // synthesis translate_on always @(*) begin t_array_muxed1 <= 1'd0; @@ -11094,12 +11605,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_297; // synthesis translate_on always @(*) begin t_array_muxed2 <= 1'd0; @@ -11130,12 +11641,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_298; // synthesis translate_on always @(*) begin rhs_array_muxed6 <= 1'd0; @@ -11166,12 +11677,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_299; // synthesis translate_on always @(*) begin rhs_array_muxed7 <= 15'd0; @@ -11202,12 +11713,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_300; // synthesis translate_on always @(*) begin rhs_array_muxed8 <= 3'd0; @@ -11238,12 +11749,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_301; // synthesis translate_on always @(*) begin rhs_array_muxed9 <= 1'd0; @@ -11274,12 +11785,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_302; // synthesis translate_on always @(*) begin rhs_array_muxed10 <= 1'd0; @@ -11310,12 +11821,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_303; // synthesis translate_on always @(*) begin rhs_array_muxed11 <= 1'd0; @@ -11346,12 +11857,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_304; // synthesis translate_on always @(*) begin t_array_muxed3 <= 1'd0; @@ -11382,12 +11893,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_305; // synthesis translate_on always @(*) begin t_array_muxed4 <= 1'd0; @@ -11418,12 +11929,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_306; // synthesis translate_on always @(*) begin t_array_muxed5 <= 1'd0; @@ -11454,12 +11965,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_307; // synthesis translate_on always @(*) begin rhs_array_muxed12 <= 22'd0; @@ -11469,12 +11980,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_308; // synthesis translate_on always @(*) begin rhs_array_muxed13 <= 1'd0; @@ -11484,12 +11995,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_309; // synthesis translate_on always @(*) begin rhs_array_muxed14 <= 1'd0; @@ -11499,12 +12010,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_310; // synthesis translate_on always @(*) begin rhs_array_muxed15 <= 22'd0; @@ -11514,12 +12025,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_311; // synthesis translate_on always @(*) begin rhs_array_muxed16 <= 1'd0; @@ -11529,12 +12040,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_312; // synthesis translate_on always @(*) begin rhs_array_muxed17 <= 1'd0; @@ -11544,12 +12055,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_313; // synthesis translate_on always @(*) begin rhs_array_muxed18 <= 22'd0; @@ -11559,12 +12070,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_314; // synthesis translate_on always @(*) begin rhs_array_muxed19 <= 1'd0; @@ -11574,12 +12085,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_315; // synthesis translate_on always @(*) begin rhs_array_muxed20 <= 1'd0; @@ -11589,12 +12100,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_316; // synthesis translate_on always @(*) begin rhs_array_muxed21 <= 22'd0; @@ -11604,12 +12115,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_317; // synthesis translate_on always @(*) begin rhs_array_muxed22 <= 1'd0; @@ -11619,12 +12130,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_318; // synthesis translate_on always @(*) begin rhs_array_muxed23 <= 1'd0; @@ -11634,12 +12145,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_319; // synthesis translate_on always @(*) begin rhs_array_muxed24 <= 22'd0; @@ -11649,12 +12160,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_320; // synthesis translate_on always @(*) begin rhs_array_muxed25 <= 1'd0; @@ -11664,12 +12175,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_321; // synthesis translate_on always @(*) begin rhs_array_muxed26 <= 1'd0; @@ -11679,12 +12190,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_322; // synthesis translate_on always @(*) begin rhs_array_muxed27 <= 22'd0; @@ -11694,12 +12205,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_323; // synthesis translate_on always @(*) begin rhs_array_muxed28 <= 1'd0; @@ -11709,12 +12220,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_324; // synthesis translate_on always @(*) begin rhs_array_muxed29 <= 1'd0; @@ -11724,12 +12235,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_325; // synthesis translate_on always @(*) begin rhs_array_muxed30 <= 22'd0; @@ -11739,12 +12250,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_326; // synthesis translate_on always @(*) begin rhs_array_muxed31 <= 1'd0; @@ -11754,12 +12265,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_327; // synthesis translate_on always @(*) begin rhs_array_muxed32 <= 1'd0; @@ -11769,12 +12280,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_328; // synthesis translate_on always @(*) begin rhs_array_muxed33 <= 22'd0; @@ -11784,12 +12295,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_329; // synthesis translate_on always @(*) begin rhs_array_muxed34 <= 1'd0; @@ -11799,12 +12310,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_330; // synthesis translate_on always @(*) begin rhs_array_muxed35 <= 1'd0; @@ -11814,12 +12325,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_331; // synthesis translate_on always @(*) begin array_muxed0 <= 3'd0; @@ -11838,12 +12349,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_332; // synthesis translate_on always @(*) begin array_muxed1 <= 15'd0; @@ -11862,12 +12373,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_333; // synthesis translate_on always @(*) begin array_muxed2 <= 1'd0; @@ -11886,12 +12397,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_334; // synthesis translate_on always @(*) begin array_muxed3 <= 1'd0; @@ -11910,12 +12421,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_335; // synthesis translate_on always @(*) begin array_muxed4 <= 1'd0; @@ -11934,12 +12445,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_336; // synthesis translate_on always @(*) begin array_muxed5 <= 1'd0; @@ -11958,12 +12469,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_337; // synthesis translate_on always @(*) begin array_muxed6 <= 1'd0; @@ -11982,12 +12493,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_338; // synthesis translate_on always @(*) begin array_muxed7 <= 3'd0; @@ -12006,12 +12517,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_339; // synthesis translate_on always @(*) begin array_muxed8 <= 15'd0; @@ -12030,12 +12541,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_340; // synthesis translate_on always @(*) begin array_muxed9 <= 1'd0; @@ -12054,12 +12565,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_341; // synthesis translate_on always @(*) begin array_muxed10 <= 1'd0; @@ -12078,12 +12589,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_342; // synthesis translate_on always @(*) begin array_muxed11 <= 1'd0; @@ -12102,12 +12613,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_343; // synthesis translate_on always @(*) begin array_muxed12 <= 1'd0; @@ -12126,12 +12637,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_344; // synthesis translate_on always @(*) begin array_muxed13 <= 1'd0; @@ -12150,12 +12661,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_345; // synthesis translate_on always @(*) begin array_muxed14 <= 3'd0; @@ -12174,12 +12685,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_346; // synthesis translate_on always @(*) begin array_muxed15 <= 15'd0; @@ -12198,12 +12709,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_347; // synthesis translate_on always @(*) begin array_muxed16 <= 1'd0; @@ -12222,12 +12733,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_348; // synthesis translate_on always @(*) begin array_muxed17 <= 1'd0; @@ -12246,12 +12757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_349; // synthesis translate_on always @(*) begin array_muxed18 <= 1'd0; @@ -12270,12 +12781,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_350; // synthesis translate_on always @(*) begin array_muxed19 <= 1'd0; @@ -12294,12 +12805,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_351; // synthesis translate_on always @(*) begin array_muxed20 <= 1'd0; @@ -12318,12 +12829,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_352; // synthesis translate_on always @(*) begin array_muxed21 <= 3'd0; @@ -12342,12 +12853,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_353; // synthesis translate_on always @(*) begin array_muxed22 <= 15'd0; @@ -12366,12 +12877,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_354; // synthesis translate_on always @(*) begin array_muxed23 <= 1'd0; @@ -12390,12 +12901,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_354 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_355; // synthesis translate_on always @(*) begin array_muxed24 <= 1'd0; @@ -12414,12 +12925,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_355 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_356; // synthesis translate_on always @(*) begin array_muxed25 <= 1'd0; @@ -12438,12 +12949,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_356 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_357; // synthesis translate_on always @(*) begin array_muxed26 <= 1'd0; @@ -12462,12 +12973,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_357 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_358; // synthesis translate_on always @(*) begin array_muxed27 <= 1'd0; @@ -12486,7 +12997,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_358 = dummy_s; // synthesis translate_on end assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); @@ -12507,6 +13018,7 @@ always @(posedge iodelay_clk) begin end always @(posedge sys_clk) begin + state <= next_state; a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1); a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1); a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en; @@ -12522,112 +13034,112 @@ always @(posedge sys_clk) begin if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip0_value <= 1'd0; end - a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]}; + a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip1_value <= 1'd0; end - a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]}; + a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip2_value <= 1'd0; end - a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]}; + a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip3_value <= 1'd0; end - a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]}; + a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip4_value <= 1'd0; end - a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]}; + a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip5_value <= 1'd0; end - a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]}; + a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip6_value <= 1'd0; end - a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]}; + a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip7_value <= 1'd0; end - a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]}; + a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip8_value <= 1'd0; end - a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]}; + a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip9_value <= 1'd0; end - a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]}; + a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip10_value <= 1'd0; end - a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]}; + a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip11_value <= 1'd0; end - a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]}; + a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip12_value <= 1'd0; end - a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]}; + a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip13_value <= 1'd0; end - a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]}; + a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip14_value <= 1'd0; end - a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]}; + a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1); end if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin a7ddrphy_bitslip15_value <= 1'd0; end - a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]}; + a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]}; if (litedramcore_inti_p0_rddata_valid) begin litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata; end @@ -14161,22 +14673,22 @@ always @(posedge sys_clk) begin a7ddrphy_dqs_oe_delayed <= 1'd0; a7ddrphy_dqspattern_o1 <= 8'd0; a7ddrphy_dq_oe_delayed <= 1'd0; - a7ddrphy_bitslip0_value <= 3'd0; - a7ddrphy_bitslip1_value <= 3'd0; - a7ddrphy_bitslip2_value <= 3'd0; - a7ddrphy_bitslip3_value <= 3'd0; - a7ddrphy_bitslip4_value <= 3'd0; - a7ddrphy_bitslip5_value <= 3'd0; - a7ddrphy_bitslip6_value <= 3'd0; - a7ddrphy_bitslip7_value <= 3'd0; - a7ddrphy_bitslip8_value <= 3'd0; - a7ddrphy_bitslip9_value <= 3'd0; - a7ddrphy_bitslip10_value <= 3'd0; - a7ddrphy_bitslip11_value <= 3'd0; - a7ddrphy_bitslip12_value <= 3'd0; - a7ddrphy_bitslip13_value <= 3'd0; - a7ddrphy_bitslip14_value <= 3'd0; - a7ddrphy_bitslip15_value <= 3'd0; + a7ddrphy_bitslip0_value <= 4'd0; + a7ddrphy_bitslip1_value <= 4'd0; + a7ddrphy_bitslip2_value <= 4'd0; + a7ddrphy_bitslip3_value <= 4'd0; + a7ddrphy_bitslip4_value <= 4'd0; + a7ddrphy_bitslip5_value <= 4'd0; + a7ddrphy_bitslip6_value <= 4'd0; + a7ddrphy_bitslip7_value <= 4'd0; + a7ddrphy_bitslip8_value <= 4'd0; + a7ddrphy_bitslip9_value <= 4'd0; + a7ddrphy_bitslip10_value <= 4'd0; + a7ddrphy_bitslip11_value <= 4'd0; + a7ddrphy_bitslip12_value <= 4'd0; + a7ddrphy_bitslip13_value <= 4'd0; + a7ddrphy_bitslip14_value <= 4'd0; + a7ddrphy_bitslip15_value <= 4'd0; a7ddrphy_rddata_en_last <= 8'd0; a7ddrphy_wrdata_en_last <= 4'd0; litedramcore_storage <= 4'd0; @@ -14358,6 +14870,7 @@ always @(posedge sys_clk) begin init_done_re <= 1'd0; init_error_storage <= 1'd0; init_error_re <= 1'd0; + state <= 1'd0; refresher_state <= 2'd0; bankmachine0_state <= 4'd0; bankmachine1_state <= 4'd0; diff --git a/soc.vhdl b/soc.vhdl index a8ae3c9..212314b 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -17,7 +17,7 @@ use work.wishbone_types.all; -- 0xc0000000: SYSCON -- 0xc0002000: UART0 -- 0xc0004000: XICS ICP --- 0xc0100000: DRAM CSRs +-- 0xc0100000: LiteDRAM control (CSRs) -- 0xf0000000: Block RAM (aliased & repeated) -- 0xffff0000: DRAM init code (if any) @@ -39,7 +39,7 @@ entity soc is -- DRAM controller signals wb_dram_in : out wishbone_master_out; wb_dram_out : in wishbone_slave_out; - wb_dram_csr : out std_ulogic; + wb_dram_ctrl : out std_ulogic; wb_dram_init : out std_ulogic; -- UART0 signals: @@ -162,7 +162,7 @@ begin SLAVE_BRAM, SLAVE_DRAM, SLAVE_DRAM_INIT, - SLAVE_DRAM_CSR, + SLAVE_DRAM_CTRL, SLAVE_ICP_0, SLAVE_NONE); variable slave : slave_type; @@ -185,7 +185,7 @@ begin elsif std_match(wb_master_out.adr, x"C0002---") then slave := SLAVE_UART; elsif std_match(wb_master_out.adr, x"C01-----") then - slave := SLAVE_DRAM_CSR; + slave := SLAVE_DRAM_CTRL; elsif std_match(wb_master_out.adr, x"C0004---") then slave := SLAVE_ICP_0; end if; @@ -204,7 +204,7 @@ begin wb_dram_in <= wb_master_out; wb_dram_in.cyc <= '0'; - wb_dram_csr <= '0'; + wb_dram_ctrl <= '0'; wb_dram_init <= '0'; wb_syscon_in <= wb_master_out; wb_syscon_in.cyc <= '0'; @@ -219,10 +219,10 @@ begin wb_dram_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_dram_out; wb_dram_init <= '1'; - when SLAVE_DRAM_CSR => + when SLAVE_DRAM_CTRL => wb_dram_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_dram_out; - wb_dram_csr <= '1'; + wb_dram_ctrl <= '1'; when SLAVE_SYSCON => wb_syscon_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_syscon_out; -- 2.30.2