From c1cee15d64ec2da29672d0f94610830d12793191 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 23 Feb 2020 10:56:39 +0100 Subject: [PATCH] Add tests for logger pass --- tests/various/logger_error.ys | 6 ++++++ tests/various/logger_nowarning.ys | 6 ++++++ tests/various/logger_warn.ys | 6 ++++++ tests/various/logger_warning.ys | 6 ++++++ 4 files changed, 24 insertions(+) create mode 100644 tests/various/logger_error.ys create mode 100644 tests/various/logger_nowarning.ys create mode 100644 tests/various/logger_warn.ys create mode 100644 tests/various/logger_warning.ys diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys new file mode 100644 index 000000000..46fe7f506 --- /dev/null +++ b/tests/various/logger_error.ys @@ -0,0 +1,6 @@ +logger -werror "is implicitly declared." -expect error "is implicitly declared." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys new file mode 100644 index 000000000..87cbbc644 --- /dev/null +++ b/tests/various/logger_nowarning.ys @@ -0,0 +1,6 @@ +logger -expect-no-warnings -nowarn "is implicitly declared." +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys new file mode 100644 index 000000000..2316ae4c6 --- /dev/null +++ b/tests/various/logger_warn.ys @@ -0,0 +1,6 @@ +logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys new file mode 100644 index 000000000..642b1b97b --- /dev/null +++ b/tests/various/logger_warning.ys @@ -0,0 +1,6 @@ +logger -expect warning "is implicitly declared." 2 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF -- 2.30.2