From c1e2583aa1e416a8f08aacfe36ffd049509c127c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Nov 2021 15:23:40 +0000 Subject: [PATCH] early use of Array unnecessarily (all uses are static references not dynamic indexing: no pmux created or needed) --- src/soc/experiment/alu_hier.py | 14 +++++++------- src/soc/experiment/cscore.py | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 6541e12c..b44c17ba 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -9,7 +9,7 @@ A "real" integer ALU would place the answers onto the output bus after only one cycle (sync) """ -from nmigen import Elaboratable, Signal, Module, Const, Mux, Array +from nmigen import Elaboratable, Signal, Module, Const, Mux from nmigen.hdl.rec import Record, Layout from nmigen.cli import main from nmigen.cli import verilog, rtlil @@ -119,9 +119,9 @@ class DummyALU(Elaboratable): i.append(Signal(width, name="i1")) i.append(Signal(width, name="i2")) i.append(Signal(width, name="i3")) - self.i = Array(i) + self.i = i self.a, self.b, self.c = i[0], i[1], i[2] - self.out = Array([Signal(width, name="alu_o")]) + self.out = tuple([Signal(width, name="alu_o")]) self.o = self.out[0] self.width = width # more "look like nmutil pipeline API" @@ -194,12 +194,12 @@ class ALU(Elaboratable): i = [] i.append(Signal(width, name="i1")) i.append(Signal(width, name="i2")) - self.i = Array(i) + self.i = i self.a, self.b = i[0], i[1] out = [] out.append(Data(width, name="alu_o")) out.append(Data(width, name="alu_cr")) - self.out = Array(out) + self.out = tuple(out) self.o = self.out[0] self.cr = self.out[1] self.width = width @@ -375,9 +375,9 @@ class BranchALU(Elaboratable): i = [] i.append(Signal(width, name="i1")) i.append(Signal(width, name="i2")) - self.i = Array(i) + self.i = i self.a, self.b = i[0], i[1] - self.out = Array([Signal(width)]) + self.out = tuple([Signal(width)]) self.o = self.out[0] self.width = width diff --git a/src/soc/experiment/cscore.py b/src/soc/experiment/cscore.py index b6618478..bb9ff6e0 100644 --- a/src/soc/experiment/cscore.py +++ b/src/soc/experiment/cscore.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Const, Signal, Array, Cat, Elaboratable +from nmigen import Module, Const, Signal, Cat, Elaboratable from regfile.regfile import RegFileArray, treereduce from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit @@ -81,7 +81,7 @@ class Scoreboard(Elaboratable): int_src2_pend_v.append(fu.src2_pend_o) int_rd_pend_v.append(fu.int_rd_pend_o) int_wr_pend_v.append(fu.int_wr_pend_o) - int_fus = Array(if_l) + int_fus = if_l # Count of number of FUs n_int_fus = len(if_l) -- 2.30.2