From c1fe7d54e497462c1c4119043dcc4b8fadf1ad8d Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 16 Jul 2020 20:02:03 -0700 Subject: [PATCH] format div code --- src/soc/fu/div/formal/proof_main_stage.py | 10 ++--- src/soc/fu/div/input_stage.py | 3 +- src/soc/fu/div/output_stage.py | 14 +++---- src/soc/fu/div/pipe_data.py | 11 ++--- src/soc/fu/div/pipeline.py | 2 +- src/soc/fu/div/setup_stage.py | 7 ++-- src/soc/fu/div/test/test_pipe_caller.py | 50 ++++++++++++----------- 7 files changed, 51 insertions(+), 46 deletions(-) diff --git a/src/soc/fu/div/formal/proof_main_stage.py b/src/soc/fu/div/formal/proof_main_stage.py index 469127dd..5a2c0f8b 100644 --- a/src/soc/fu/div/formal/proof_main_stage.py +++ b/src/soc/fu/div/formal/proof_main_stage.py @@ -121,10 +121,10 @@ class Driver(Elaboratable): comb += peo.eq(32) with m.Else(): comb += peo.eq(pe32.o) - with m.If(XO[-1]): # cnttzw + with m.If(XO[-1]): # cnttzw comb += pe32.i.eq(a[0:32]) comb += Assert(dut.o.o == peo) - with m.Else(): # cntlzw + with m.Else(): # cntlzw comb += pe32.i.eq(a[0:32][::-1]) comb += Assert(dut.o.o == peo) with m.Else(): @@ -134,14 +134,13 @@ class Driver(Elaboratable): comb += peo64.eq(64) with m.Else(): comb += peo64.eq(pe64.o) - with m.If(XO[-1]): # cnttzd + with m.If(XO[-1]): # cnttzd comb += pe64.i.eq(a[0:64]) comb += Assert(dut.o.o == peo64) - with m.Else(): # cntlzd + with m.Else(): # cntlzd comb += pe64.i.eq(a[0:64][::-1]) comb += Assert(dut.o.o == peo64) - return m @@ -150,6 +149,7 @@ class LogicalTestCase(FHDLTestCase): module = Driver() self.assertFormal(module, mode="bmc", depth=2) self.assertFormal(module, mode="cover", depth=2) + def test_ilang(self): dut = Driver() vl = rtlil.convert(dut, ports=[]) diff --git a/src/soc/fu/div/input_stage.py b/src/soc/fu/div/input_stage.py index a9ad6652..01888cb2 100644 --- a/src/soc/fu/div/input_stage.py +++ b/src/soc/fu/div/input_stage.py @@ -6,10 +6,11 @@ from soc.fu.alu.input_stage import ALUInputStage from soc.fu.div.pipe_data import DIVInputData # simply over-ride ALUInputStage ispec / ospec + + class DivMulInputStage(ALUInputStage): def __init__(self, pspec): super().__init__(pspec) def ispec(self): return DIVInputData(self.pspec) def ospec(self): return DIVInputData(self.pspec) - diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py index 5da7f6c7..7348538c 100644 --- a/src/soc/fu/div/output_stage.py +++ b/src/soc/fu/div/output_stage.py @@ -23,7 +23,7 @@ class DivOutputStage(PipeModBase): self.fields.create_specs() self.quotient_neg = Signal() self.remainder_neg = Signal() - self.quotient_65 = Signal(65) # one extra spare bit for overflow + self.quotient_65 = Signal(65) # one extra spare bit for overflow self.remainder_64 = Signal(64) def ispec(self): @@ -79,12 +79,12 @@ class DivOutputStage(PipeModBase): ov = Signal(reset_less=True) with m.If(op.is_signed): comb += ov.eq(overflow - | (abs_quotient > sign_bit_mask) - | ((abs_quotient == sign_bit_mask) - & ~self.quotient_neg)) + | (abs_quotient > sign_bit_mask) + | ((abs_quotient == sign_bit_mask) + & ~self.quotient_neg)) with m.Else(): comb += ov.eq(overflow) - comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32 + comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32 # check 32/64 bit version of overflow with m.If(op.is_32bit): @@ -106,14 +106,14 @@ class DivOutputStage(PipeModBase): comb += ov.eq(1) with m.Else(): comb += ov.eq(self.i.dive_abs_ov32) - comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32 + comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32 ########################## # main switch for DIV o = self.o.o.data - with m.If(~ov): # result is valid (no overflow) + with m.If(~ov): # result is valid (no overflow) with m.Switch(op.insn_type): with m.Case(MicrOp.OP_DIVE): with m.If(op.is_32bit): diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index 02f169f9..80a408be 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -8,9 +8,10 @@ from ieee754.div_rem_sqrt_rsqrt.core import ( class DIVInputData(IntegerData): - regspec = [('INT', 'ra', '0:63'), # RA - ('INT', 'rb', '0:63'), # RB/immediate - ('XER', 'xer_so', '32'),] # XER bit 32: SO + regspec = [('INT', 'ra', '0:63'), # RA + ('INT', 'rb', '0:63'), # RB/immediate + ('XER', 'xer_so', '32'), ] # XER bit 32: SO + def __init__(self, pspec): super().__init__(pspec, False) # convenience @@ -21,15 +22,15 @@ class DIVInputData(IntegerData): class DivMulOutputData(IntegerData): regspec = [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), - ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32 + ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32 ('XER', 'xer_so', '32')] + def __init__(self, pspec): super().__init__(pspec, True) # convenience self.cr0 = self.cr_a - class DIVPipeSpec(CommonPipeSpec): regspec = (DIVInputData.regspec, DivMulOutputData.regspec) opsubsetkls = CompLogicalOpSubset diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py index 801cd44a..3fa56350 100644 --- a/src/soc/fu/div/pipeline.py +++ b/src/soc/fu/div/pipeline.py @@ -34,7 +34,7 @@ class DivStagesEnd(PipeModBaseChain): core_final = DivCoreFinalStage(self.pspec) div_out = DivOutputStage(self.pspec) alu_out = DivMulOutputStage(self.pspec) - self.div_out = div_out # debugging - bug #425 + self.div_out = div_out # debugging - bug #425 return [core_final, div_out, alu_out] diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py index 11619fc7..679c9cc6 100644 --- a/src/soc/fu/div/setup_stage.py +++ b/src/soc/fu/div/setup_stage.py @@ -41,14 +41,15 @@ class DivSetupStage(PipeModBase): comb += core_o.operation.eq(int(DivPipeCoreOperation.UDivRem)) # work out if a/b are negative (check 32-bit / signed) - comb += dividend_neg_o.eq(Mux(op.is_32bit, a[31], a[63]) & op.is_signed) + comb += dividend_neg_o.eq(Mux(op.is_32bit, + a[31], a[63]) & op.is_signed) comb += divisor_neg_o.eq(Mux(op.is_32bit, b[31], b[63]) & op.is_signed) # negation of a 64-bit value produces the same lower 32-bit # result as negation of just the lower 32-bits, so we don't # need to do anything special before negating - abs_dor = Signal(64, reset_less=True) # absolute of divisor - abs_dend = Signal(64, reset_less=True) # absolute of dividend + abs_dor = Signal(64, reset_less=True) # absolute of divisor + abs_dend = Signal(64, reset_less=True) # absolute of dividend comb += abs_dor.eq(Mux(divisor_neg_o, -b, b)) comb += abs_dend.eq(Mux(dividend_neg_o, -a, a)) diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 204e4315..35d21182 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -17,25 +17,26 @@ from soc.fu.div.pipeline import DIVBasePipe from soc.fu.div.pipe_data import DIVPipeSpec import random + def log_rand(n, min_val=1): logrange = random.randint(1, n) - return random.randint(min_val, (1<