From c20db46a9eb0a17de2ccb471ea72b669a641b914 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Nov 2021 10:28:46 +0000 Subject: [PATCH] whoops, hazard vectors were depth 1 width N they need to be regwidth 1 (1 bit wide) depth N (one per register) --- src/soc/regfile/regfiles.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 93d94226..8461181a 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -285,9 +285,9 @@ class RegFiles: def make_hazard_vec(self, rf, name): if isinstance(rf, VirtualRegPort): - vec = RegFileArray(rf.bitwidth, 1) + vec = RegFileArray(1, rf.nregs) else: - vec = RegFileArray(rf.depth, 1) + vec = RegFileArray(1, rf.depth) # get read/write port specs and create bitvector ports with same names wr_spec, rd_spec = rf.get_port_specs() create_ports(vec, wr_spec, rd_spec) -- 2.30.2