From c22734d0d99531b84e38950fb8ec461ab0a256b3 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sat, 19 Oct 2019 10:33:31 +1100 Subject: [PATCH] wb_debug: Add wishbone pipelining support Signed-off-by: Benjamin Herrenschmidt --- wishbone_debug_master.vhdl | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/wishbone_debug_master.vhdl b/wishbone_debug_master.vhdl index 3ba6b21..11b9ee3 100644 --- a/wishbone_debug_master.vhdl +++ b/wishbone_debug_master.vhdl @@ -124,7 +124,6 @@ begin -- We always move WB cyc and stb simultaneously (no pipelining yet...) wb_out.cyc <= '1' when state = WB_CYCLE else '0'; - wb_out.stb <= '1' when state = WB_CYCLE else '0'; -- Data latch. WB will take the read data away as soon as the cycle -- terminates but we must maintain it on DMI until req goes down, so @@ -145,14 +144,23 @@ begin if rising_edge(clk) then if (rst) then state <= IDLE; + wb_out.stb <= '0'; else case state is when IDLE => if dmi_req = '1' and dmi_addr = DBG_WB_DATA then state <= WB_CYCLE; + wb_out.stb <= '1'; end if; when WB_CYCLE => + if wb_in.stall = '0' then + wb_out.stb <= '0'; + end if; if wb_in.ack then + -- We shouldn't get the ack if we hadn't already cleared + -- stb above but if this happen, don't leave it dangling. + -- + wb_out.stb <= '0'; state <= DMI_WAIT; end if; when DMI_WAIT => -- 2.30.2