From c24e13b1078fa2d358d6b7f91cfd96905c100769 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Jun 2021 10:23:39 +0000 Subject: [PATCH] set various clocks to use H-Tree --- experiments10_verilog/doDesign.py | 2 ++ experiments9/doDesign.py | 2 ++ 2 files changed, 4 insertions(+) diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py index 33a2ed9..f79a3cc 100644 --- a/experiments10_verilog/doDesign.py +++ b/experiments10_verilog/doDesign.py @@ -81,6 +81,8 @@ def scriptMain ( **kw ): adderConf.chipConf.name = 'chip' #adderConf.chipConf.ioPadGauge = 'LibreSOCIO' adderConf.chipConf.ioPadGauge = 'niolib' + adderConf.useHTree('jtag_tck_from_pad') + adderConf.useHTree('sys_clk_from_pad') adderConf.coreSize = ( l(coreSize), l(coreSize) ) adderConf.chipSize = ( l(coreSize+3500), l(coreSize+3500) ) adderToChip = CoreToChip( adderConf ) diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py index 86b1d12..fd61b7a 100644 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@ -58,6 +58,8 @@ def scriptMain (**kw): ls180Conf.chipConf.ioPadGauge = 'niolib' ls180Conf.coreSize = (l(coreSize ), l(coreSize )) ls180Conf.chipSize = (l(coreSize+3360), l(coreSize+3360)) + ls180Conf.useHTree('core.por_clk') + ls180Conf.useHTree('jtag_tck_from_pad') ls180ToChip = CoreToChip( ls180Conf ) ls180ToChip.buildChip() -- 2.30.2