From c25de31824a64873a9000ce10b90fcf493050a8a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 27 Sep 2017 15:06:09 -0700 Subject: [PATCH] broadcom/vc5: Add proper support for base_vertex and base_instance. I had base_vertex hacked into the shader state setup like in vc4, but it's not correct for big offsets. Using the proper packet is easier and hopefully means we can re-emit shader state setup less frequently. --- src/gallium/drivers/vc5/vc5_context.h | 2 -- src/gallium/drivers/vc5/vc5_draw.c | 40 +++++++++++++++------------ src/gallium/drivers/vc5/vc5_screen.c | 2 +- 3 files changed, 24 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/vc5/vc5_context.h b/src/gallium/drivers/vc5/vc5_context.h index b8f3f784a85..cac623adf26 100644 --- a/src/gallium/drivers/vc5/vc5_context.h +++ b/src/gallium/drivers/vc5/vc5_context.h @@ -304,8 +304,6 @@ struct vc5_context { /** Maximum index buffer valid for the current shader_rec. */ uint32_t max_index; - /** Last index bias baked into the current shader_rec. */ - uint32_t last_index_bias; /** Seqno of the last CL flush's job. */ uint64_t last_emit_seqno; diff --git a/src/gallium/drivers/vc5/vc5_draw.c b/src/gallium/drivers/vc5/vc5_draw.c index d78fa3265fd..f764f41ce15 100644 --- a/src/gallium/drivers/vc5/vc5_draw.c +++ b/src/gallium/drivers/vc5/vc5_draw.c @@ -150,8 +150,7 @@ vc5_get_default_values(struct vc5_context *vc5) static void vc5_emit_gl_shader_state(struct vc5_context *vc5, - const struct pipe_draw_info *info, - uint32_t extra_index_bias) + const struct pipe_draw_info *info) { struct vc5_job *job = vc5->job; /* VC5_DIRTY_VTXSTATE */ @@ -242,9 +241,7 @@ vc5_emit_gl_shader_state(struct vc5_context *vc5, const struct util_format_description *desc = util_format_description(elem->src_format); - uint32_t offset = (vb->buffer_offset + - elem->src_offset + - vb->stride * info->index_bias); + uint32_t offset = vb->buffer_offset + elem->src_offset; cl_emit(&job->indirect, GL_SHADER_STATE_ATTRIBUTE_RECORD, attr) { uint32_t r_size = desc->channel[0].size; @@ -380,22 +377,31 @@ vc5_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) vc5_emit_state(pctx); - if ((vc5->dirty & (VC5_DIRTY_VTXBUF | - VC5_DIRTY_VTXSTATE | - VC5_DIRTY_PRIM_MODE | - VC5_DIRTY_RASTERIZER | - VC5_DIRTY_COMPILED_CS | - VC5_DIRTY_COMPILED_VS | - VC5_DIRTY_COMPILED_FS | - vc5->prog.cs->uniform_dirty_bits | - vc5->prog.vs->uniform_dirty_bits | - vc5->prog.fs->uniform_dirty_bits)) || - vc5->last_index_bias != info->index_bias) { - vc5_emit_gl_shader_state(vc5, info, 0); + if (vc5->dirty & (VC5_DIRTY_VTXBUF | + VC5_DIRTY_VTXSTATE | + VC5_DIRTY_PRIM_MODE | + VC5_DIRTY_RASTERIZER | + VC5_DIRTY_COMPILED_CS | + VC5_DIRTY_COMPILED_VS | + VC5_DIRTY_COMPILED_FS | + vc5->prog.cs->uniform_dirty_bits | + vc5->prog.vs->uniform_dirty_bits | + vc5->prog.fs->uniform_dirty_bits)) { + vc5_emit_gl_shader_state(vc5, info); } vc5->dirty = 0; + /* The Base Vertex/Base Instance packet sets those values to nonzero + * for the next draw call only. + */ + if (info->index_bias || info->start_instance) { + cl_emit(&job->bcl, BASE_VERTEX_BASE_INSTANCE, base) { + base.base_instance = info->start_instance; + base.base_vertex = info->index_bias; + } + } + /* Note that the primitive type fields match with OpenGL/gallium * definitions, up to but not including QUADS. */ diff --git a/src/gallium/drivers/vc5/vc5_screen.c b/src/gallium/drivers/vc5/vc5_screen.c index d3c9f0962e3..792d430722b 100644 --- a/src/gallium/drivers/vc5/vc5_screen.c +++ b/src/gallium/drivers/vc5/vc5_screen.c @@ -97,6 +97,7 @@ vc5_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: + case PIPE_CAP_START_INSTANCE: case PIPE_CAP_TGSI_INSTANCEID: case PIPE_CAP_SM3: case PIPE_CAP_INDEP_BLEND_ENABLE: /* XXX */ @@ -159,7 +160,6 @@ vc5_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_START_INSTANCE: case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: case PIPE_CAP_SHADER_STENCIL_EXPORT: case PIPE_CAP_TGSI_TEXCOORD: -- 2.30.2