From c26f0a1935b2341ccd808a4681f1c411e499928d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jun 2018 03:57:15 +0100
Subject: [PATCH] add example code

---
 simple_v_extension/simple_v_chennai_2018.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index e3a951273..eafc4267b 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -47,7 +47,7 @@
   Where SIMD Goes Wrong:\vspace{10pt}
    \begin{itemize}
    \item See "SIMD instructions considered harmful"
-   https://www.sigarch.org/simd-instructions-considered-harmful
+   https://sigarch.org/simd-instructions-considered-harmful
    \item Corner-cases alone are extremely complex.\\
 	     Hardware is easy, but software is hell.
    \item O($N^{6}$) ISA opcode proliferation!\\
@@ -569,7 +569,7 @@ function op\_mv(rd, rs) # MV not VMV!
 
   \begin{itemize}
    \item See "SIMD Considered Harmful" for SIMD/RVV analysis\\
-	   https://www.sigarch.org/simd-instructions-considered-harmful/
+	   https://sigarch.org/simd-instructions-considered-harmful/
   \end{itemize}
 
 
-- 
2.30.2