From c2948277c0f2b5c9dc1656e41c4bbae54269b010 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 15 May 2019 06:44:50 +0000 Subject: [PATCH] hdl.ir: when adding sync domain to a design, also add it to ports. Otherwise we end up in a situation where the examples don't have clk and rst as ports, which is not nice. Fixes #67. --- nmigen/hdl/ir.py | 16 +++++++++++++--- nmigen/test/test_hdl_ir.py | 8 ++++++-- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py index 21c78b5..7884e1d 100644 --- a/nmigen/hdl/ir.py +++ b/nmigen/hdl/ir.py @@ -327,8 +327,13 @@ class Fragment: def _propagate_domains(self, ensure_sync_exists): self._propagate_domains_up() if ensure_sync_exists and not self.domains: - self.add_domains(ClockDomain("sync")) + cd_sync = ClockDomain() + self.add_domains(cd_sync) + new_domains = (cd_sync,) + else: + new_domains = () self._propagate_domains_down() + return new_domains def _insert_domain_resets(self): from .xfrm import ResetInserter @@ -479,14 +484,19 @@ class Fragment: from .xfrm import SampleLowerer fragment = SampleLowerer()(self) - fragment._propagate_domains(ensure_sync_exists) + new_domains = fragment._propagate_domains(ensure_sync_exists) fragment._resolve_hierarchy_conflicts() fragment = fragment._insert_domain_resets() fragment = fragment._lower_domain_signals() if ports is None: fragment._propagate_ports(ports=(), all_undef_as_ports=True) else: - fragment._propagate_ports(ports=ports, all_undef_as_ports=False) + new_ports = [] + for cd in new_domains: + new_ports.append(cd.clk) + if cd.rst is not None: + new_ports.append(cd.rst) + fragment._propagate_ports(ports=(*ports, *new_ports), all_undef_as_ports=False) return fragment diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py index 0e96662..26ddfd5 100644 --- a/nmigen/test/test_hdl_ir.py +++ b/nmigen/test/test_hdl_ir.py @@ -573,9 +573,9 @@ class InstanceTestCase(FHDLTestCase): def test_prepare(self): self.setUp_cpu() f = self.inst.prepare() - clk = f.domains["sync"].clk + sync_clk = f.domains["sync"].clk self.assertEqual(f.ports, SignalDict([ - (clk, "i"), + (sync_clk, "i"), (self.rst, "i"), (self.pins, "io"), ])) @@ -583,7 +583,11 @@ class InstanceTestCase(FHDLTestCase): def test_prepare_explicit_ports(self): self.setUp_cpu() f = self.inst.prepare(ports=[self.rst, self.stb]) + sync_clk = f.domains["sync"].clk + sync_rst = f.domains["sync"].rst self.assertEqual(f.ports, SignalDict([ + (sync_clk, "i"), + (sync_rst, "i"), (self.rst, "i"), (self.stb, "o"), (self.pins, "io"), -- 2.30.2