From c2a4bf2d6edde8b148421668a4c07c844b994271 Mon Sep 17 00:00:00 2001
From: Andrew Pinski <apinski@marvell.com>
Date: Sat, 8 Feb 2020 15:57:54 +0000
Subject: [PATCH] aarch64: fix strict alignment for vector load/stores (PR
 91927)

Hi,
  The problem here is that the vector mode version of movmisalign<mode>
was only conditionalized on if SIMD was enabled instead of being
also conditionalized on STRICT_ALIGNMENT too.

Applied as pre-approved in the bug report by Richard Sandiford
after a bootstrap/test on aarch64-linux-gnu.

Thanks,
Andrew Pinski

ChangeLog:
PR target/91927
* config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
STRICT_ALIGNMENT also.

testsuite/ChangeLog:
PR target/91927
* gcc.target/aarch64/pr91927.c: New testcase.
---
 gcc/ChangeLog                              |  6 ++++
 gcc/config/aarch64/aarch64-simd.md         |  2 +-
 gcc/testsuite/ChangeLog                    |  5 +++
 gcc/testsuite/gcc.target/aarch64/pr91927.c | 38 ++++++++++++++++++++++
 4 files changed, 50 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/pr91927.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0ae8c5442a0..b46ea4fe149 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-02-08  Andrew Pinski  <apinski@marvell.com>
+
+	PR target/91927
+	* config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
+	STRICT_ALIGNMENT also.
+
 2020-02-08  Jim Wilson  <jimw@sifive.com>
 
 	PR target/93532
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c8e1012bd7f..4c651f45d0c 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -41,7 +41,7 @@
 (define_expand "movmisalign<mode>"
   [(set (match_operand:VALL 0 "nonimmediate_operand")
         (match_operand:VALL 1 "general_operand"))]
-  "TARGET_SIMD"
+  "TARGET_SIMD && !STRICT_ALIGNMENT"
 {
   /* This pattern is not permitted to fail during expansion: if both arguments
      are non-registers (e.g. memory := constant, which can be created by the
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b9548b34f01..c47f3fb98dd 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-08  Andrew Pinski  <apinski@marvel.com>
+
+	PR target/91927
+	* gcc.target/aarch64/pr91927.c: New testcase.
+
 2020-02-08  Peter Bergner <bergner@linux.ibm.com>
 
 	PR target/93136
diff --git a/gcc/testsuite/gcc.target/aarch64/pr91927.c b/gcc/testsuite/gcc.target/aarch64/pr91927.c
new file mode 100644
index 00000000000..f5cde1a5336
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr91927.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-mstrict-align -O3" } */
+
+#define NULL 0
+
+typedef unsigned uint32_t;
+typedef struct __attribute__((__packed__))
+{
+	uint32_t nTagID;
+	uint32_t nValueBufferSize;
+	uint32_t nValueLength;
+	
+}	PropertyTags_t;
+
+typedef struct
+{
+	char *szName;
+	uint32_t nBufferSize;
+	uint32_t nLength;
+	
+}	Something_t;
+
+void SetTag(PropertyTags_t *pTag, uint32_t nBufferSize, uint32_t nLength);
+
+void TestCase(Something_t *pSome, uint32_t nBufferSize, uint32_t nLength)
+{
+	if (pSome != NULL)
+	{
+		PropertyTags_t sTag = { 0 };
+		
+		SetTag(&sTag, nBufferSize, nLength);
+		
+		pSome->nBufferSize = sTag.nValueBufferSize;
+		pSome->nLength = sTag.nValueLength;
+	}
+}
+
+/* { dg-final { scan-assembler-not "ldr\td" } } */
-- 
2.30.2