From c2aa2b676123b583fe2c02b9a9806965b4c4c8eb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 14 Apr 2018 06:48:33 +0100 Subject: [PATCH] add virtual reg illustration --- simple_v_extension.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 6ca79263c..996ec164b 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1037,6 +1037,7 @@ translates effectively to: Register File | Reg Num | Bits | +| ------- | ---- | | r0 | (32..0) | | r1 | (32..0) | | r2 | (32..0) | @@ -1049,11 +1050,13 @@ Register File Vectorised CSR | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +| - | - | - | - | - | - | - | - | | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Vector Length CSR | Reg Num | (3..0) | +| ------- | ---- | | r0 | 2 | | r1 | 0 | | r2 | 1 | @@ -1066,6 +1069,7 @@ Vector Length CSR Virtual Register Reordering: | Reg Num | Bits (0) | Bits (1) | Bits (2) | +| ------- | -------- | -------- | -------- | | r0 | (32..0) | (32..0) | | r2 | (32..0) | | r3 | (32..0) | -- 2.30.2