From c2c1ed206d834a468aed160ea0861858f82ff4af Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 26 Jul 2022 14:48:33 +0100 Subject: [PATCH] --- openpower/sv/int_fp_mv.mdwn | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index 1efde29e2..aff94f83b 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -165,12 +165,9 @@ allowing clearing FPRs. Pseudocode: - bf16 = d0 || d1 || d2 - result <- [0]*64 - result[0] <- bf16[0] # sign - result[1:12] <- bf16[1:12] # exponent - result[12:15] <- bf16[12:15] # mantissa - FRS <- result + bf16 = d0 || d1 || d2 # create BF16 immediate + fp32 = bf16 || [0]*16 # convert BF16 to FP32 + FRS = DOUBLE(fp32) # convert FP32 to FP64 ## Float Replace Lower-Half Single, Immediate @@ -198,9 +195,9 @@ as can be seen in the pseudocode below. Pseudocode: - fp32 = Double_to_Single(FRS) - n = fp32[0:15] || d0 || d1 || d2 - FRS = Single_to_Double(n) + fp32 = DOUBLE2SINGLE(FRS) # convert to FP32 + n = fp32[0:15] || d0 || d1 || d2 # replace mantissa LSBs + FRS = DOUBLE(n) # convert back to FP64 *This instruction performs a Read-Modify-Write. FRS is read, the additional 16 bit immediate inserted, and the result also written to FRS* -- 2.30.2