From c2dd7b1235fef6142b63a1f4bc3e773a7c58bb3e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 30 Jan 2017 18:47:22 +0100 Subject: [PATCH] boards/platforms/kcu105: add user sma clock and HPC connector --- litex/boards/platforms/kcu105.py | 157 ++++++++++++++++++++++++++++++- 1 file changed, 156 insertions(+), 1 deletion(-) diff --git a/litex/boards/platforms/kcu105.py b/litex/boards/platforms/kcu105.py index 9b1797de..6f228ce1 100644 --- a/litex/boards/platforms/kcu105.py +++ b/litex/boards/platforms/kcu105.py @@ -24,14 +24,169 @@ _io = [ Subsignal("rx", Pins("G25")), IOStandard("LVCMOS18") ), + + ("user_sma_clock", 0, + Subsignal("p", Pins("D23"), IOStandard("LVDS")), + Subsignal("n", Pins("C23"), IOStandard("LVDS")) + ), +] + +_connectors = [ + ("HPC", { + "DP1_M2C_P": "D2", + "DP1_M2C_N": "D1", + "DP2_M2C_P": "B2", + "DP2_M2C_N": "B1", + "DP3_M2C_P": "A4", + "DP3_M2C_N": "A3", + "DP1_C2M_P": "D6", + "DP1_C2M_N": "D5", + "DP2_C2M_P": "C4", + "DP2_C2M_N": "C3", + "DP3_C2M_P": "B6", + "DP3_C2M_N": "B5", + "DP0_C2M_P": "F6", + "DP0_C2M_N": "F5", + "DP0_M2C_P": "E4", + "DP0_M2C_N": "E3", + "LA06_P": "D13", + "LA06_N": "C13", + "LA10_P": "L8", + "LA10_N": "K8", + "LA14_P": "B10", + "LA14_N": "A10", + "LA18_CC_P": "E22", + "LA18_CC_N": "E23", + "LA27_P": "H21", + "LA27_N": "G21", + "HA01_CC_P": "E16", + "HA01_CC_N": "D16", + "HA05_P": "J15", + "HA05_N": "J14", + "HA09_P": "F18", + "HA09_N": "F17", + "HA13_P": "B14", + "HA13_N": "A14", + "HA16_P": "A19", + "HA16_N": "A18", + "HA20_P": "C19", + "HA20_N": "B19", + "CLK1_M2C_P": "E25", + "CLK1_M2C_N": "D25", + "LA00_CC_P": "H11", + "LA00_CC_N": "G11", + "LA03_P": "A13", + "LA03_N": "A12", + "LA08_P": "J8", + "LA08_N": "H8", + "LA12_P": "E10", + "LA12_N": "D10", + "LA16_P": "B9", + "LA16_N": "A9", + "LA20_P": "B24", + "LA20_N": "A24", + "LA22_P": "G24", + "LA22_N": "F25", + "LA25_P": "D20", + "LA25_N": "D21", + "LA29_P": "B20", + "LA29_N": "A20", + "LA31_P": "B25", + "LA31_N": "A25", + "LA33_P": "A27", + "LA33_N": "A28", + "HA03_P": "G15", + "HA03_N": "G14", + "HA07_P": "L19", + "HA07_N": "L18", + "HA11_P": "J19", + "HA11_N": "J18", + "HA14_P": "F15", + "HA14_N": "F14", + "HA18_P": "B17", + "HA18_N": "B16", + "HA22_P": "C18", + "HA22_N": "C17", + "GBTCLK1_M2C_P": "E25", + "GBTCLK1_M2C_N": "D25", + "GBTCLK0_M2C_P": "H12", + "GBTCLK0_M2C_N": "G12", + "LA01_CC_P": "G9", + "LA01_CC_N": "F9", + "LA05_P": "L13", + "LA05_N": "K13", + "LA09_P": "J9", + "LA09_N": "H9", + "LA13_P": "D9", + "LA13_N": "C9", + "LA17_CC_P": "D24", + "LA17_CC_N": "C24", + "LA23_P": "G22", + "LA23_N": "F22", + "LA26_P": "G20", + "LA26_N": "F20", + "PG_M2C": "L27", + "HA00_CC_P": "G17", + "HA00_CC_N": "G16", + "HA04_P": "G19", + "HA04_N": "F19", + "HA08_P": "K18", + "HA08_N": "K17", + "HA12_P": "K16", + "HA12_N": "J16", + "HA15_P": "D14", + "HA15_N": "C14", + "HA19_P": "D19", + "HA19_N": "D18", + "PRSNT_M2C_B": "H24", + "CLK0_M2C_P": "H12", + "CLK0_M2C_N": "G12", + "LA02_P": "K10", + "LA02_N": "J10", + "LA04_P": "L12", + "LA04_N": "K12", + "LA07_P": "F8", + "LA07_N": "E8", + "LA11_P": "K11", + "LA11_N": "J11", + "LA15_P": "D8", + "LA15_N": "C8", + "LA19_P": "C21", + "LA19_N": "C22", + "LA21_P": "F23", + "LA21_N": "F24", + "LA24_P": "E20", + "LA24_N": "E21", + "LA28_P": "B21", + "LA28_N": "B22", + "LA30_P": "C26", + "LA30_N": "B26", + "LA32_P": "E26", + "LA32_N": "D26", + "HA02_P": "H19", + "HA02_N": "H18", + "HA06_P": "L15", + "HA06_N": "K15", + "HA10_P": "H17", + "HA10_N": "H16", + "HA17_CC_P": "E18", + "HA17_CC_N": "E17", + "HA21_P": "E15", + "HA21_N": "D15", + "HA23_P": "B15", + "HA23_N": "A15", + } + ), ] + class Platform(XilinxPlatform): default_clk_name = "clk125" default_clk_period = 8.0 def __init__(self): - XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain="vivado") + XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, + toolchain="vivado") def create_programmer(self): return VivadoProgrammer() -- 2.30.2