From c2ffdaa0c8d98c9afcab2ca5b8825cb527405c51 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 10 Dec 2020 03:13:38 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 173236967..92df77ca8 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -48,7 +48,7 @@ For 2 op (dest/src1/src2) the tag may be 3 bits: total 9 bits. for 3 op (dest/s # Notes about rounding, clamp and saturate -One of the issues with vector ops is that in integer DSP ops for example in Audio the operation must clamp or saturate rather than overflow or ignore the upper bits and become a modulo operation. This for Audio is extremely important, also to provide an indicator as to whether saturation occurred. +One of the issues with vector ops is that in integer DSP ops for example in Audio the operation must clamp or saturate rather than overflow or ignore the upper bits and become a modulo operation. This for Audio is extremely important, also to provide an indicator as to whether saturation occurred. see [[av_opcodes]]. If there are spare bits it would be very good to look at using some of thrm to specify the mide, because otherwise a SPR has to be used which will need to be set and unset. This can get costly. -- 2.30.2