From c3207e6ea70076278957eff0b61dcca3df89f881 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 22 Mar 2023 14:42:27 -0700 Subject: [PATCH] partially fix FPCSR in "Special Registers altered" sections didn't yet fill in "TODO: which bits?" --- openpower/sv/rfc/ls006.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn index 026474a9e..50d0dccae 100644 --- a/openpower/sv/rfc/ls006.mdwn +++ b/openpower/sv/rfc/ls006.mdwn @@ -271,7 +271,7 @@ operations. Special Registers altered: CR1 (if Rc=1) - FPCSR (TODO: which bits?) + FPCSR (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0) ### Assembly Aliases @@ -574,6 +574,7 @@ Special Registers altered: CR0 (if Rc=1) XER SO, OV, OV32 (if OE=1) + FPCSR (TODO: which bits?) ---------- -- 2.30.2