From c320abc3f490b09b21804581c2b386c30d186a1e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 15 Aug 2019 12:34:11 -0700 Subject: [PATCH] xilinx_dsp to be sensitive to keep attribute --- passes/pmgen/xilinx_dsp.pmg | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 1a3dcdcbb..7f1958d5d 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -29,8 +29,13 @@ match ffA endmatch code clock - if (ffA) + if (ffA) { clock = port(ffA, \CLK).as_bit(); + + for (auto b : port(ffA, \Q)) + if (b.wire->get_bool_attribute(\keep)) + reject; + } endcode match ffB @@ -45,6 +50,10 @@ endmatch code clock if (ffB) { + for (auto b : port(ffB, \Q)) + if (b.wire->get_bool_attribute(\keep)) + reject; + SigBit c = port(ffB, \CLK).as_bit(); if (clock != SigBit() && c != clock) @@ -156,6 +165,10 @@ code ffP clock // ffP = ffY; if (ffP) { + for (auto b : port(ffP, \Q)) + if (b.wire->get_bool_attribute(\keep)) + reject; + SigBit c = port(ffP, \CLK).as_bit(); if (clock != SigBit() && c != clock) -- 2.30.2