From c34d57de2e204653cd5b550de671376f9607773b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 Apr 2020 12:08:45 -0700 Subject: [PATCH] Update CHANGELOG and manual for departure from upstream --- CHANGELOG | 4 ++-- manual/CHAPTER_Auxprogs.tex | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index df8e14b26..3b36c3182 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -8,7 +8,7 @@ Yosys 0.9 .. Yosys 0.9-dev * Various - Added "write_xaiger" backend - - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) @@ -58,7 +58,6 @@ Yosys 0.9 .. Yosys 0.9-dev - Added support for SystemVerilog wildcard port connections (.*) - Added "xilinx_dffopt" pass - Added "scratchpad" pass - - Added "abc9 -dff" - Added "synth_xilinx -dff" - Improved support of $readmem[hb] Memory Content File inclusion - Added "opt_lut_ins" pass @@ -66,6 +65,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Removed "dffsr2dff" (use opt_rmdff instead) - Added "design -delete" - Added "select -unset" + - Use YosysHQ/abc instead of upstream berkeley-abc/abc Yosys 0.8 .. Yosys 0.9 ---------------------- diff --git a/manual/CHAPTER_Auxprogs.tex b/manual/CHAPTER_Auxprogs.tex index 724d37f0b..f09b18f76 100644 --- a/manual/CHAPTER_Auxprogs.tex +++ b/manual/CHAPTER_Auxprogs.tex @@ -19,7 +19,8 @@ for details. \section{yosys-abc} -This is a unmodified copy of ABC \citeweblink{ABC}. Not all versions of Yosys -work with all versions of ABC. So Yosys comes with its own yosys-abc to avoid +This is a fork of ABC \citeweblink{ABC} with a small set of custom modifications +that have not yet been accepted upstream. Not all versions of Yosys work with +all versions of ABC. So Yosys comes with its own yosys-abc to avoid compatibility issues between the two. -- 2.30.2