From c35433591d902d6f487b7d9a298925e2475c96db Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 3 Jan 2022 22:10:17 +0000 Subject: [PATCH] give module appropriate top-level name in microwatt compat mode --- src/soc/simple/issuer_verilog.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 6fead5ee..0ff83d69 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -140,9 +140,11 @@ if __name__ == '__main__': if args.mwcompat: dut = TestIssuerInternal(pspec) + name = "external_core_top" else: dut = TestIssuer(pspec) + name = "test_issuer" - vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer") + vl = verilog.convert(dut, ports=dut.external_ports(), name=name) with open(args.output_filename, "w") as f: f.write(vl) -- 2.30.2