From c383db0df8603568e6013103495fb18933ea29b1 Mon Sep 17 00:00:00 2001 From: Lauri Kasanen Date: Mon, 16 Mar 2020 09:14:20 +0200 Subject: [PATCH] Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility --- 4b/5848b576ad1f2d199a9b85a0050f5b3df006ae | 101 ++++++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 4b/5848b576ad1f2d199a9b85a0050f5b3df006ae diff --git a/4b/5848b576ad1f2d199a9b85a0050f5b3df006ae b/4b/5848b576ad1f2d199a9b85a0050f5b3df006ae new file mode 100644 index 0000000..b4f334d --- /dev/null +++ b/4b/5848b576ad1f2d199a9b85a0050f5b3df006ae @@ -0,0 +1,101 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Mon, 16 Mar 2020 07:13:45 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jDjwW-0006px-0N; Mon, 16 Mar 2020 07:13:44 +0000 +Received: from mout.gmx.net ([212.227.17.21]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jDjwU-0006pr-3B + for libre-riscv-dev@lists.libre-riscv.org; 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