From c3908a3a4de6c8c7a9d6cf0c71c4c2968f001ad1 Mon Sep 17 00:00:00 2001 From: Darrell Harmon Date: Fri, 20 Sep 2019 09:13:27 -0600 Subject: [PATCH] vendor.xilinx_{7series,spartan3_6}: specialize MultiReg. Vivado/ISE would otherwise infer an SRL16 from a MultiReg in some cases. --- nmigen/vendor/xilinx_7series.py | 8 ++++++++ nmigen/vendor/xilinx_spartan_3_6.py | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index 6e7d227..d78581c 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -360,3 +360,11 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): io_IO=p_port[bit], io_IOB=n_port[bit] ) return m + + def get_multi_reg(self, multireg): + m = Module() + for i, o in zip((multireg.i, *multireg._regs), multireg._regs): + o.attrs["ASYNC_REG"] = "TRUE" + m.d[multireg._o_domain] += o.eq(i) + m.d.comb += multireg.o.eq(multireg._regs[-1]) + return m diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py index 00d6831..25b2a59 100644 --- a/nmigen/vendor/xilinx_spartan_3_6.py +++ b/nmigen/vendor/xilinx_spartan_3_6.py @@ -411,6 +411,14 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform): ) return m + def get_multi_reg(self, multireg): + m = Module() + for i, o in zip((multireg.i, *multireg._regs), multireg._regs): + o.attrs["ASYNC_REG"] = "TRUE" + m.d[multireg._o_domain] += o.eq(i) + m.d.comb += multireg.o.eq(multireg._regs[-1]) + return m + XilinxSpartan3APlatform = XilinxSpartan3Or6Platform XilinxSpartan6Platform = XilinxSpartan3Or6Platform -- 2.30.2