From c3c7cad4698dd56d71002e12c2fad10746d684b3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 24 May 2020 12:51:56 +0100 Subject: [PATCH] add RA to trap pipeline, for OP_MTMSR/OP_MFMSR --- src/soc/fu/trap/pipe_data.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index de930da3..0bc11897 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -32,19 +32,22 @@ class TrapInputData(IntegerData): class TrapOutputData(IntegerData): - regspec = [('SPR', 'srr0', '0:63'), + regspec = [('INT', 'o', '0:63'), + ('SPR', 'srr0', '0:63'), ('SPR', 'srr1', '0:63'), ('PC', 'nia', '0:63'), ('MSR', 'msr', '0:63')] def __init__(self, pspec): super().__init__(pspec) + self.o = Data(64, name="o") # RA self.srr0 = Data(64, name="srr0") # SRR0 SPR self.srr1 = Data(64, name="srr1") # SRR1 SPR self.nia = Data(64, name="nia") # NIA (Next PC) - self.msr = Signal(64, reset_less=True) # MSR + self.msr = Data(64, name="msr") # MSR def __iter__(self): yield from super().__iter__() + yield self.o yield self.nia yield self.msr yield self.srr0 @@ -52,7 +55,7 @@ class TrapOutputData(IntegerData): def eq(self, i): lst = super().eq(i) - return lst + [ self.nia.eq(i.nia), self.msr.eq(i.msr), + return lst + [ self.o.eq(i.o), self.nia.eq(i.nia), self.msr.eq(i.msr), self.srr0.eq(i.srr0), self.srr1.eq(i.srr1)] -- 2.30.2