From c3e9f0712fa2a35cf3e4a638164aed7ab8d8ff4a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 3 Jan 2014 12:34:18 +0100 Subject: [PATCH] Another small freduce cleanup/bugfix --- passes/sat/freduce.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index cc3739fe4..4db11436e 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -482,7 +482,8 @@ struct FreduceWorker RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID); for (auto &port : drv->connections) - sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); + if (ct.cell_output(drv->type, port.first)) + sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); if (grp[i].inverted) { -- 2.30.2